1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/slab.h> 32 #include <linux/sort.h> 33 #include <linux/string_helpers.h> 34 #include <linux/timekeeping.h> 35 #include <linux/types.h> 36 37 #include <asm/byteorder.h> 38 39 #include <drm/display/drm_dp_helper.h> 40 #include <drm/display/drm_dp_tunnel.h> 41 #include <drm/display/drm_dsc_helper.h> 42 #include <drm/display/drm_hdmi_helper.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_crtc.h> 45 #include <drm/drm_edid.h> 46 #include <drm/drm_fixed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "g4x_dp.h" 50 #include "i915_drv.h" 51 #include "i915_irq.h" 52 #include "i915_reg.h" 53 #include "intel_alpm.h" 54 #include "intel_atomic.h" 55 #include "intel_audio.h" 56 #include "intel_backlight.h" 57 #include "intel_combo_phy_regs.h" 58 #include "intel_connector.h" 59 #include "intel_crtc.h" 60 #include "intel_cx0_phy.h" 61 #include "intel_ddi.h" 62 #include "intel_de.h" 63 #include "intel_display_driver.h" 64 #include "intel_display_types.h" 65 #include "intel_dp.h" 66 #include "intel_dp_aux.h" 67 #include "intel_dp_hdcp.h" 68 #include "intel_dp_link_training.h" 69 #include "intel_dp_mst.h" 70 #include "intel_dp_tunnel.h" 71 #include "intel_dpio_phy.h" 72 #include "intel_dpll.h" 73 #include "intel_drrs.h" 74 #include "intel_encoder.h" 75 #include "intel_fifo_underrun.h" 76 #include "intel_hdcp.h" 77 #include "intel_hdmi.h" 78 #include "intel_hotplug.h" 79 #include "intel_hotplug_irq.h" 80 #include "intel_lspcon.h" 81 #include "intel_lvds.h" 82 #include "intel_modeset_lock.h" 83 #include "intel_panel.h" 84 #include "intel_pch_display.h" 85 #include "intel_pps.h" 86 #include "intel_psr.h" 87 #include "intel_quirks.h" 88 #include "intel_tc.h" 89 #include "intel_vdsc.h" 90 #include "intel_vrr.h" 91 #include "intel_crtc_state_dump.h" 92 93 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev) 94 95 /* DP DSC throughput values used for slice count calculations KPixels/s */ 96 #define DP_DSC_PEAK_PIXEL_RATE 2720000 97 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 98 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 99 100 /* Max DSC line buffer depth supported by HW. */ 101 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 102 103 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ 104 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 105 106 /* Compliance test status bits */ 107 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 108 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 109 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 110 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 111 112 113 /* Constants for DP DSC configurations */ 114 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 115 116 /* With Single pipe configuration, HW is capable of supporting maximum 117 * of 4 slices per line. 118 */ 119 static const u8 valid_dsc_slicecount[] = {1, 2, 4}; 120 121 /** 122 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 123 * @intel_dp: DP struct 124 * 125 * If a CPU or PCH DP output is attached to an eDP panel, this function 126 * will return true, and false otherwise. 127 * 128 * This function is not safe to use prior to encoder type being set. 129 */ 130 bool intel_dp_is_edp(struct intel_dp *intel_dp) 131 { 132 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 133 134 return dig_port->base.type == INTEL_OUTPUT_EDP; 135 } 136 137 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 138 139 /* Is link rate UHBR and thus 128b/132b? */ 140 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 141 { 142 return drm_dp_is_uhbr_rate(crtc_state->port_clock); 143 } 144 145 /** 146 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 147 * @rate: link rate in 10kbit/s units 148 * 149 * Returns the link symbol size in bits/symbol units depending on the link 150 * rate -> channel coding. 151 */ 152 int intel_dp_link_symbol_size(int rate) 153 { 154 return drm_dp_is_uhbr_rate(rate) ? 32 : 10; 155 } 156 157 /** 158 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 159 * @rate: link rate in 10kbit/s units 160 * 161 * Returns the link symbol clock frequency in kHz units depending on the 162 * link rate and channel coding. 163 */ 164 int intel_dp_link_symbol_clock(int rate) 165 { 166 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); 167 } 168 169 static int max_dprx_rate(struct intel_dp *intel_dp) 170 { 171 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 172 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); 173 174 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 175 } 176 177 static int max_dprx_lane_count(struct intel_dp *intel_dp) 178 { 179 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 180 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); 181 182 return drm_dp_max_lane_count(intel_dp->dpcd); 183 } 184 185 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 186 { 187 intel_dp->sink_rates[0] = 162000; 188 intel_dp->num_sink_rates = 1; 189 } 190 191 /* update sink rates from dpcd */ 192 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 193 { 194 static const int dp_rates[] = { 195 162000, 270000, 540000, 810000 196 }; 197 int i, max_rate; 198 int max_lttpr_rate; 199 200 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 201 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 202 static const int quirk_rates[] = { 162000, 270000, 324000 }; 203 204 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 205 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 206 207 return; 208 } 209 210 /* 211 * Sink rates for 8b/10b. 212 */ 213 max_rate = max_dprx_rate(intel_dp); 214 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 215 if (max_lttpr_rate) 216 max_rate = min(max_rate, max_lttpr_rate); 217 218 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 219 if (dp_rates[i] > max_rate) 220 break; 221 intel_dp->sink_rates[i] = dp_rates[i]; 222 } 223 224 /* 225 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 226 * rates and 10 Gbps. 227 */ 228 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { 229 u8 uhbr_rates = 0; 230 231 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 232 233 drm_dp_dpcd_readb(&intel_dp->aux, 234 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 235 236 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 237 /* We have a repeater */ 238 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 239 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 240 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 241 DP_PHY_REPEATER_128B132B_SUPPORTED) { 242 /* Repeater supports 128b/132b, valid UHBR rates */ 243 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 244 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 245 } else { 246 /* Does not support 128b/132b */ 247 uhbr_rates = 0; 248 } 249 } 250 251 if (uhbr_rates & DP_UHBR10) 252 intel_dp->sink_rates[i++] = 1000000; 253 if (uhbr_rates & DP_UHBR13_5) 254 intel_dp->sink_rates[i++] = 1350000; 255 if (uhbr_rates & DP_UHBR20) 256 intel_dp->sink_rates[i++] = 2000000; 257 } 258 259 intel_dp->num_sink_rates = i; 260 } 261 262 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 263 { 264 struct intel_connector *connector = intel_dp->attached_connector; 265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 266 struct intel_encoder *encoder = &intel_dig_port->base; 267 268 intel_dp_set_dpcd_sink_rates(intel_dp); 269 270 if (intel_dp->num_sink_rates) 271 return; 272 273 drm_err(&dp_to_i915(intel_dp)->drm, 274 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 275 connector->base.base.id, connector->base.name, 276 encoder->base.base.id, encoder->base.name); 277 278 intel_dp_set_default_sink_rates(intel_dp); 279 } 280 281 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 282 { 283 intel_dp->max_sink_lane_count = 1; 284 } 285 286 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 287 { 288 struct intel_connector *connector = intel_dp->attached_connector; 289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 290 struct intel_encoder *encoder = &intel_dig_port->base; 291 292 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); 293 294 switch (intel_dp->max_sink_lane_count) { 295 case 1: 296 case 2: 297 case 4: 298 return; 299 } 300 301 drm_err(&dp_to_i915(intel_dp)->drm, 302 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 303 connector->base.base.id, connector->base.name, 304 encoder->base.base.id, encoder->base.name, 305 intel_dp->max_sink_lane_count); 306 307 intel_dp_set_default_max_sink_lane_count(intel_dp); 308 } 309 310 /* Get length of rates array potentially limited by max_rate. */ 311 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 312 { 313 int i; 314 315 /* Limit results by potentially reduced max rate */ 316 for (i = 0; i < len; i++) { 317 if (rates[len - i - 1] <= max_rate) 318 return len - i; 319 } 320 321 return 0; 322 } 323 324 /* Get length of common rates array potentially limited by max_rate. */ 325 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 326 int max_rate) 327 { 328 return intel_dp_rate_limit_len(intel_dp->common_rates, 329 intel_dp->num_common_rates, max_rate); 330 } 331 332 int intel_dp_common_rate(struct intel_dp *intel_dp, int index) 333 { 334 if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, 335 index < 0 || index >= intel_dp->num_common_rates)) 336 return 162000; 337 338 return intel_dp->common_rates[index]; 339 } 340 341 /* Theoretical max between source and sink */ 342 int intel_dp_max_common_rate(struct intel_dp *intel_dp) 343 { 344 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); 345 } 346 347 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 348 { 349 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 350 int max_lanes = dig_port->max_lanes; 351 352 if (vbt_max_lanes) 353 max_lanes = min(max_lanes, vbt_max_lanes); 354 355 return max_lanes; 356 } 357 358 /* Theoretical max between source and sink */ 359 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 360 { 361 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 362 int source_max = intel_dp_max_source_lane_count(dig_port); 363 int sink_max = intel_dp->max_sink_lane_count; 364 int lane_max = intel_tc_port_max_lane_count(dig_port); 365 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 366 367 if (lttpr_max) 368 sink_max = min(sink_max, lttpr_max); 369 370 return min3(source_max, sink_max, lane_max); 371 } 372 373 static int forced_lane_count(struct intel_dp *intel_dp) 374 { 375 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); 376 } 377 378 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 379 { 380 int lane_count; 381 382 if (intel_dp->link.force_lane_count) 383 lane_count = forced_lane_count(intel_dp); 384 else 385 lane_count = intel_dp->link.max_lane_count; 386 387 switch (lane_count) { 388 case 1: 389 case 2: 390 case 4: 391 return lane_count; 392 default: 393 MISSING_CASE(lane_count); 394 return 1; 395 } 396 } 397 398 static int intel_dp_min_lane_count(struct intel_dp *intel_dp) 399 { 400 if (intel_dp->link.force_lane_count) 401 return forced_lane_count(intel_dp); 402 403 return 1; 404 } 405 406 /* 407 * The required data bandwidth for a mode with given pixel clock and bpp. This 408 * is the required net bandwidth independent of the data bandwidth efficiency. 409 * 410 * TODO: check if callers of this functions should use 411 * intel_dp_effective_data_rate() instead. 412 */ 413 int 414 intel_dp_link_required(int pixel_clock, int bpp) 415 { 416 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 417 return DIV_ROUND_UP(pixel_clock * bpp, 8); 418 } 419 420 /** 421 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead 422 * @pixel_clock: pixel clock in kHz 423 * @bpp_x16: bits per pixel .4 fixed point format 424 * @bw_overhead: BW allocation overhead in 1ppm units 425 * 426 * Return the effective pixel data rate in kB/sec units taking into account 427 * the provided SSC, FEC, DSC BW allocation overhead. 428 */ 429 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 430 int bw_overhead) 431 { 432 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 433 1000000 * 16 * 8); 434 } 435 436 /** 437 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params 438 * @intel_dp: Intel DP object 439 * @max_dprx_rate: Maximum data rate of the DPRX 440 * @max_dprx_lanes: Maximum lane count of the DPRX 441 * 442 * Calculate the maximum data rate for the provided link parameters taking into 443 * account any BW limitations by a DP tunnel attached to @intel_dp. 444 * 445 * Returns the maximum data rate in kBps units. 446 */ 447 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 448 int max_dprx_rate, int max_dprx_lanes) 449 { 450 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); 451 452 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 453 max_rate = min(max_rate, 454 drm_dp_tunnel_available_bw(intel_dp->tunnel)); 455 456 return max_rate; 457 } 458 459 bool intel_dp_has_joiner(struct intel_dp *intel_dp) 460 { 461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 462 struct intel_encoder *encoder = &intel_dig_port->base; 463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 464 465 /* eDP MSO is not compatible with joiner */ 466 if (intel_dp->mso_link_count) 467 return false; 468 469 return DISPLAY_VER(dev_priv) >= 12 || 470 (DISPLAY_VER(dev_priv) == 11 && 471 encoder->port != PORT_A); 472 } 473 474 static int dg2_max_source_rate(struct intel_dp *intel_dp) 475 { 476 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 477 } 478 479 static int icl_max_source_rate(struct intel_dp *intel_dp) 480 { 481 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 482 483 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) 484 return 540000; 485 486 return 810000; 487 } 488 489 static int ehl_max_source_rate(struct intel_dp *intel_dp) 490 { 491 if (intel_dp_is_edp(intel_dp)) 492 return 540000; 493 494 return 810000; 495 } 496 497 static int mtl_max_source_rate(struct intel_dp *intel_dp) 498 { 499 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 500 501 if (intel_encoder_is_c10phy(encoder)) 502 return 810000; 503 504 if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1)) 505 return 1350000; 506 507 return 2000000; 508 } 509 510 static int vbt_max_link_rate(struct intel_dp *intel_dp) 511 { 512 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 513 int max_rate; 514 515 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 516 517 if (intel_dp_is_edp(intel_dp)) { 518 struct intel_connector *connector = intel_dp->attached_connector; 519 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 520 521 if (max_rate && edp_max_rate) 522 max_rate = min(max_rate, edp_max_rate); 523 else if (edp_max_rate) 524 max_rate = edp_max_rate; 525 } 526 527 return max_rate; 528 } 529 530 static void 531 intel_dp_set_source_rates(struct intel_dp *intel_dp) 532 { 533 /* The values must be in increasing order */ 534 static const int mtl_rates[] = { 535 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 536 810000, 1000000, 2000000, 537 }; 538 static const int icl_rates[] = { 539 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 540 1000000, 1350000, 541 }; 542 static const int bxt_rates[] = { 543 162000, 216000, 243000, 270000, 324000, 432000, 540000 544 }; 545 static const int skl_rates[] = { 546 162000, 216000, 270000, 324000, 432000, 540000 547 }; 548 static const int hsw_rates[] = { 549 162000, 270000, 540000 550 }; 551 static const int g4x_rates[] = { 552 162000, 270000 553 }; 554 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 555 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 556 const int *source_rates; 557 int size, max_rate = 0, vbt_max_rate; 558 559 /* This should only be done once */ 560 drm_WARN_ON(&dev_priv->drm, 561 intel_dp->source_rates || intel_dp->num_source_rates); 562 563 if (DISPLAY_VER(dev_priv) >= 14) { 564 source_rates = mtl_rates; 565 size = ARRAY_SIZE(mtl_rates); 566 max_rate = mtl_max_source_rate(intel_dp); 567 } else if (DISPLAY_VER(dev_priv) >= 11) { 568 source_rates = icl_rates; 569 size = ARRAY_SIZE(icl_rates); 570 if (IS_DG2(dev_priv)) 571 max_rate = dg2_max_source_rate(intel_dp); 572 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) || 573 IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) 574 max_rate = 810000; 575 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 576 max_rate = ehl_max_source_rate(intel_dp); 577 else 578 max_rate = icl_max_source_rate(intel_dp); 579 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 580 source_rates = bxt_rates; 581 size = ARRAY_SIZE(bxt_rates); 582 } else if (DISPLAY_VER(dev_priv) == 9) { 583 source_rates = skl_rates; 584 size = ARRAY_SIZE(skl_rates); 585 } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) || 586 IS_BROADWELL(dev_priv)) { 587 source_rates = hsw_rates; 588 size = ARRAY_SIZE(hsw_rates); 589 } else { 590 source_rates = g4x_rates; 591 size = ARRAY_SIZE(g4x_rates); 592 } 593 594 vbt_max_rate = vbt_max_link_rate(intel_dp); 595 if (max_rate && vbt_max_rate) 596 max_rate = min(max_rate, vbt_max_rate); 597 else if (vbt_max_rate) 598 max_rate = vbt_max_rate; 599 600 if (max_rate) 601 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 602 603 intel_dp->source_rates = source_rates; 604 intel_dp->num_source_rates = size; 605 } 606 607 static int intersect_rates(const int *source_rates, int source_len, 608 const int *sink_rates, int sink_len, 609 int *common_rates) 610 { 611 int i = 0, j = 0, k = 0; 612 613 while (i < source_len && j < sink_len) { 614 if (source_rates[i] == sink_rates[j]) { 615 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 616 return k; 617 common_rates[k] = source_rates[i]; 618 ++k; 619 ++i; 620 ++j; 621 } else if (source_rates[i] < sink_rates[j]) { 622 ++i; 623 } else { 624 ++j; 625 } 626 } 627 return k; 628 } 629 630 /* return index of rate in rates array, or -1 if not found */ 631 int intel_dp_rate_index(const int *rates, int len, int rate) 632 { 633 int i; 634 635 for (i = 0; i < len; i++) 636 if (rate == rates[i]) 637 return i; 638 639 return -1; 640 } 641 642 static int intel_dp_link_config_rate(struct intel_dp *intel_dp, 643 const struct intel_dp_link_config *lc) 644 { 645 return intel_dp_common_rate(intel_dp, lc->link_rate_idx); 646 } 647 648 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) 649 { 650 return 1 << lc->lane_count_exp; 651 } 652 653 static int intel_dp_link_config_bw(struct intel_dp *intel_dp, 654 const struct intel_dp_link_config *lc) 655 { 656 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), 657 intel_dp_link_config_lane_count(lc)); 658 } 659 660 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) 661 { 662 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ 663 const struct intel_dp_link_config *lc_a = a; 664 const struct intel_dp_link_config *lc_b = b; 665 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); 666 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); 667 668 if (bw_a != bw_b) 669 return bw_a - bw_b; 670 671 return intel_dp_link_config_rate(intel_dp, lc_a) - 672 intel_dp_link_config_rate(intel_dp, lc_b); 673 } 674 675 static void intel_dp_link_config_init(struct intel_dp *intel_dp) 676 { 677 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 678 struct intel_dp_link_config *lc; 679 int num_common_lane_configs; 680 int i; 681 int j; 682 683 if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) 684 return; 685 686 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; 687 688 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs > 689 ARRAY_SIZE(intel_dp->link.configs))) 690 return; 691 692 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs; 693 694 lc = &intel_dp->link.configs[0]; 695 for (i = 0; i < intel_dp->num_common_rates; i++) { 696 for (j = 0; j < num_common_lane_configs; j++) { 697 lc->lane_count_exp = j; 698 lc->link_rate_idx = i; 699 700 lc++; 701 } 702 } 703 704 sort_r(intel_dp->link.configs, intel_dp->link.num_configs, 705 sizeof(intel_dp->link.configs[0]), 706 link_config_cmp_by_bw, NULL, 707 intel_dp); 708 } 709 710 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) 711 { 712 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 713 const struct intel_dp_link_config *lc; 714 715 if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs)) 716 idx = 0; 717 718 lc = &intel_dp->link.configs[idx]; 719 720 *link_rate = intel_dp_link_config_rate(intel_dp, lc); 721 *lane_count = intel_dp_link_config_lane_count(lc); 722 } 723 724 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) 725 { 726 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, 727 link_rate); 728 int lane_count_exp = ilog2(lane_count); 729 int i; 730 731 for (i = 0; i < intel_dp->link.num_configs; i++) { 732 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; 733 734 if (lc->lane_count_exp == lane_count_exp && 735 lc->link_rate_idx == link_rate_idx) 736 return i; 737 } 738 739 return -1; 740 } 741 742 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 743 { 744 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 745 746 drm_WARN_ON(&i915->drm, 747 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 748 749 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 750 intel_dp->num_source_rates, 751 intel_dp->sink_rates, 752 intel_dp->num_sink_rates, 753 intel_dp->common_rates); 754 755 /* Paranoia, there should always be something in common. */ 756 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { 757 intel_dp->common_rates[0] = 162000; 758 intel_dp->num_common_rates = 1; 759 } 760 761 intel_dp_link_config_init(intel_dp); 762 } 763 764 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 765 u8 lane_count) 766 { 767 /* 768 * FIXME: we need to synchronize the current link parameters with 769 * hardware readout. Currently fast link training doesn't work on 770 * boot-up. 771 */ 772 if (link_rate == 0 || 773 link_rate > intel_dp->link.max_rate) 774 return false; 775 776 if (lane_count == 0 || 777 lane_count > intel_dp_max_lane_count(intel_dp)) 778 return false; 779 780 return true; 781 } 782 783 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 784 { 785 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), 786 1000000U); 787 } 788 789 int intel_dp_bw_fec_overhead(bool fec_enabled) 790 { 791 /* 792 * TODO: Calculate the actual overhead for a given mode. 793 * The hard-coded 1/0.972261=2.853% overhead factor 794 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + 795 * 0.453% DSC overhead. This is enough for a 3840 width mode, 796 * which has a DSC overhead of up to ~0.2%, but may not be 797 * enough for a 1024 width mode where this is ~0.8% (on a 4 798 * lane DP link, with 2 DSC slices and 8 bpp color depth). 799 */ 800 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; 801 } 802 803 static int 804 small_joiner_ram_size_bits(struct drm_i915_private *i915) 805 { 806 if (DISPLAY_VER(i915) >= 13) 807 return 17280 * 8; 808 else if (DISPLAY_VER(i915) >= 11) 809 return 7680 * 8; 810 else 811 return 6144 * 8; 812 } 813 814 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp) 815 { 816 u32 bits_per_pixel = bpp; 817 int i; 818 819 /* Error out if the max bpp is less than smallest allowed valid bpp */ 820 if (bits_per_pixel < valid_dsc_bpp[0]) { 821 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", 822 bits_per_pixel, valid_dsc_bpp[0]); 823 return 0; 824 } 825 826 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 827 if (DISPLAY_VER(i915) >= 13) { 828 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 829 830 /* 831 * According to BSpec, 27 is the max DSC output bpp, 832 * 8 is the min DSC output bpp. 833 * While we can still clamp higher bpp values to 27, saving bandwidth, 834 * if it is required to oompress up to bpp < 8, means we can't do 835 * that and probably means we can't fit the required mode, even with 836 * DSC enabled. 837 */ 838 if (bits_per_pixel < 8) { 839 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n", 840 bits_per_pixel); 841 return 0; 842 } 843 bits_per_pixel = min_t(u32, bits_per_pixel, 27); 844 } else { 845 /* Find the nearest match in the array of known BPPs from VESA */ 846 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 847 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 848 break; 849 } 850 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n", 851 bits_per_pixel, valid_dsc_bpp[i]); 852 853 bits_per_pixel = valid_dsc_bpp[i]; 854 } 855 856 return bits_per_pixel; 857 } 858 859 static 860 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, 861 u32 mode_clock, u32 mode_hdisplay, 862 bool bigjoiner) 863 { 864 u32 max_bpp_small_joiner_ram; 865 866 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 867 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; 868 869 if (bigjoiner) { 870 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; 871 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 872 int ppc = 2; 873 u32 max_bpp_bigjoiner = 874 i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / 875 intel_dp_mode_to_fec_clock(mode_clock); 876 877 max_bpp_small_joiner_ram *= 2; 878 879 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); 880 } 881 882 return max_bpp_small_joiner_ram; 883 } 884 885 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, 886 u32 link_clock, u32 lane_count, 887 u32 mode_clock, u32 mode_hdisplay, 888 bool bigjoiner, 889 enum intel_output_format output_format, 890 u32 pipe_bpp, 891 u32 timeslots) 892 { 893 u32 bits_per_pixel, joiner_max_bpp; 894 895 /* 896 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 897 * (LinkSymbolClock)* 8 * (TimeSlots / 64) 898 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) 899 * for MST -> TimeSlots has to be calculated, based on mode requirements 900 * 901 * Due to FEC overhead, the available bw is reduced to 97.2261%. 902 * To support the given mode: 903 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead 904 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead 905 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock 906 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / 907 * (ModeClock / FEC Overhead) 908 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / 909 * (ModeClock / FEC Overhead * 8) 910 */ 911 bits_per_pixel = ((link_clock * lane_count) * timeslots) / 912 (intel_dp_mode_to_fec_clock(mode_clock) * 8); 913 914 /* Bandwidth required for 420 is half, that of 444 format */ 915 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 916 bits_per_pixel *= 2; 917 918 /* 919 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum 920 * supported PPS value can be 63.9375 and with the further 921 * mention that for 420, 422 formats, bpp should be programmed double 922 * the target bpp restricting our target bpp to be 31.9375 at max. 923 */ 924 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 925 bits_per_pixel = min_t(u32, bits_per_pixel, 31); 926 927 drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " 928 "total bw %u pixel clock %u\n", 929 bits_per_pixel, timeslots, 930 (link_clock * lane_count * 8), 931 intel_dp_mode_to_fec_clock(mode_clock)); 932 933 joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock, 934 mode_hdisplay, bigjoiner); 935 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); 936 937 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); 938 939 return bits_per_pixel; 940 } 941 942 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 943 int mode_clock, int mode_hdisplay, 944 bool bigjoiner) 945 { 946 struct drm_i915_private *i915 = to_i915(connector->base.dev); 947 u8 min_slice_count, i; 948 int max_slice_width; 949 950 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 951 min_slice_count = DIV_ROUND_UP(mode_clock, 952 DP_DSC_MAX_ENC_THROUGHPUT_0); 953 else 954 min_slice_count = DIV_ROUND_UP(mode_clock, 955 DP_DSC_MAX_ENC_THROUGHPUT_1); 956 957 /* 958 * Due to some DSC engine BW limitations, we need to enable second 959 * slice and VDSC engine, whenever we approach close enough to max CDCLK 960 */ 961 if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) 962 min_slice_count = max_t(u8, min_slice_count, 2); 963 964 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 965 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 966 drm_dbg_kms(&i915->drm, 967 "Unsupported slice width %d by DP DSC Sink device\n", 968 max_slice_width); 969 return 0; 970 } 971 /* Also take into account max slice width */ 972 min_slice_count = max_t(u8, min_slice_count, 973 DIV_ROUND_UP(mode_hdisplay, 974 max_slice_width)); 975 976 /* Find the closest match to the valid slice count values */ 977 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 978 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner; 979 980 if (test_slice_count > 981 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 982 break; 983 984 /* big joiner needs small joiner to be enabled */ 985 if (bigjoiner && test_slice_count < 4) 986 continue; 987 988 if (min_slice_count <= test_slice_count) 989 return test_slice_count; 990 } 991 992 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", 993 min_slice_count); 994 return 0; 995 } 996 997 static bool source_can_output(struct intel_dp *intel_dp, 998 enum intel_output_format format) 999 { 1000 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1001 1002 switch (format) { 1003 case INTEL_OUTPUT_FORMAT_RGB: 1004 return true; 1005 1006 case INTEL_OUTPUT_FORMAT_YCBCR444: 1007 /* 1008 * No YCbCr output support on gmch platforms. 1009 * Also, ILK doesn't seem capable of DP YCbCr output. 1010 * The displayed image is severly corrupted. SNB+ is fine. 1011 */ 1012 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915); 1013 1014 case INTEL_OUTPUT_FORMAT_YCBCR420: 1015 /* Platform < Gen 11 cannot output YCbCr420 format */ 1016 return DISPLAY_VER(i915) >= 11; 1017 1018 default: 1019 MISSING_CASE(format); 1020 return false; 1021 } 1022 } 1023 1024 static bool 1025 dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 1026 enum intel_output_format sink_format) 1027 { 1028 if (!drm_dp_is_branch(intel_dp->dpcd)) 1029 return false; 1030 1031 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1032 return intel_dp->dfp.rgb_to_ycbcr; 1033 1034 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1035 return intel_dp->dfp.rgb_to_ycbcr && 1036 intel_dp->dfp.ycbcr_444_to_420; 1037 1038 return false; 1039 } 1040 1041 static bool 1042 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 1043 enum intel_output_format sink_format) 1044 { 1045 if (!drm_dp_is_branch(intel_dp->dpcd)) 1046 return false; 1047 1048 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1049 return intel_dp->dfp.ycbcr_444_to_420; 1050 1051 return false; 1052 } 1053 1054 static bool 1055 dfp_can_convert(struct intel_dp *intel_dp, 1056 enum intel_output_format output_format, 1057 enum intel_output_format sink_format) 1058 { 1059 switch (output_format) { 1060 case INTEL_OUTPUT_FORMAT_RGB: 1061 return dfp_can_convert_from_rgb(intel_dp, sink_format); 1062 case INTEL_OUTPUT_FORMAT_YCBCR444: 1063 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 1064 default: 1065 MISSING_CASE(output_format); 1066 return false; 1067 } 1068 1069 return false; 1070 } 1071 1072 static enum intel_output_format 1073 intel_dp_output_format(struct intel_connector *connector, 1074 enum intel_output_format sink_format) 1075 { 1076 struct intel_dp *intel_dp = intel_attached_dp(connector); 1077 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1078 enum intel_output_format force_dsc_output_format = 1079 intel_dp->force_dsc_output_format; 1080 enum intel_output_format output_format; 1081 if (force_dsc_output_format) { 1082 if (source_can_output(intel_dp, force_dsc_output_format) && 1083 (!drm_dp_is_branch(intel_dp->dpcd) || 1084 sink_format != force_dsc_output_format || 1085 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 1086 return force_dsc_output_format; 1087 1088 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n"); 1089 } 1090 1091 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 1092 dfp_can_convert_from_rgb(intel_dp, sink_format)) 1093 output_format = INTEL_OUTPUT_FORMAT_RGB; 1094 1095 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 1096 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 1097 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 1098 1099 else 1100 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1101 1102 drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format)); 1103 1104 return output_format; 1105 } 1106 1107 int intel_dp_min_bpp(enum intel_output_format output_format) 1108 { 1109 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 1110 return 6 * 3; 1111 else 1112 return 8 * 3; 1113 } 1114 1115 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1116 { 1117 /* 1118 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1119 * format of the number of bytes per pixel will be half the number 1120 * of bytes of RGB pixel. 1121 */ 1122 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1123 bpp /= 2; 1124 1125 return bpp; 1126 } 1127 1128 static enum intel_output_format 1129 intel_dp_sink_format(struct intel_connector *connector, 1130 const struct drm_display_mode *mode) 1131 { 1132 const struct drm_display_info *info = &connector->base.display_info; 1133 1134 if (drm_mode_is_420_only(info, mode)) 1135 return INTEL_OUTPUT_FORMAT_YCBCR420; 1136 1137 return INTEL_OUTPUT_FORMAT_RGB; 1138 } 1139 1140 static int 1141 intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1142 const struct drm_display_mode *mode) 1143 { 1144 enum intel_output_format output_format, sink_format; 1145 1146 sink_format = intel_dp_sink_format(connector, mode); 1147 1148 output_format = intel_dp_output_format(connector, sink_format); 1149 1150 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1151 } 1152 1153 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, 1154 int hdisplay) 1155 { 1156 /* 1157 * Older platforms don't like hdisplay==4096 with DP. 1158 * 1159 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1160 * and frame counter increment), but we don't get vblank interrupts, 1161 * and the pipe underruns immediately. The link also doesn't seem 1162 * to get trained properly. 1163 * 1164 * On CHV the vblank interrupts don't seem to disappear but 1165 * otherwise the symptoms are similar. 1166 * 1167 * TODO: confirm the behaviour on HSW+ 1168 */ 1169 return hdisplay == 4096 && !HAS_DDI(dev_priv); 1170 } 1171 1172 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1173 { 1174 struct intel_connector *connector = intel_dp->attached_connector; 1175 const struct drm_display_info *info = &connector->base.display_info; 1176 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1177 1178 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1179 if (max_tmds_clock && info->max_tmds_clock) 1180 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1181 1182 return max_tmds_clock; 1183 } 1184 1185 static enum drm_mode_status 1186 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1187 int clock, int bpc, 1188 enum intel_output_format sink_format, 1189 bool respect_downstream_limits) 1190 { 1191 int tmds_clock, min_tmds_clock, max_tmds_clock; 1192 1193 if (!respect_downstream_limits) 1194 return MODE_OK; 1195 1196 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1197 1198 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1199 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1200 1201 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1202 return MODE_CLOCK_LOW; 1203 1204 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1205 return MODE_CLOCK_HIGH; 1206 1207 return MODE_OK; 1208 } 1209 1210 static enum drm_mode_status 1211 intel_dp_mode_valid_downstream(struct intel_connector *connector, 1212 const struct drm_display_mode *mode, 1213 int target_clock) 1214 { 1215 struct intel_dp *intel_dp = intel_attached_dp(connector); 1216 const struct drm_display_info *info = &connector->base.display_info; 1217 enum drm_mode_status status; 1218 enum intel_output_format sink_format; 1219 1220 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1221 if (intel_dp->dfp.pcon_max_frl_bw) { 1222 int target_bw; 1223 int max_frl_bw; 1224 int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1225 1226 target_bw = bpp * target_clock; 1227 1228 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1229 1230 /* converting bw from Gbps to Kbps*/ 1231 max_frl_bw = max_frl_bw * 1000000; 1232 1233 if (target_bw > max_frl_bw) 1234 return MODE_CLOCK_HIGH; 1235 1236 return MODE_OK; 1237 } 1238 1239 if (intel_dp->dfp.max_dotclock && 1240 target_clock > intel_dp->dfp.max_dotclock) 1241 return MODE_CLOCK_HIGH; 1242 1243 sink_format = intel_dp_sink_format(connector, mode); 1244 1245 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1246 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1247 8, sink_format, true); 1248 1249 if (status != MODE_OK) { 1250 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 1251 !connector->base.ycbcr_420_allowed || 1252 !drm_mode_is_420_also(info, mode)) 1253 return status; 1254 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1255 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1256 8, sink_format, true); 1257 if (status != MODE_OK) 1258 return status; 1259 } 1260 1261 return MODE_OK; 1262 } 1263 1264 bool intel_dp_need_joiner(struct intel_dp *intel_dp, 1265 struct intel_connector *connector, 1266 int hdisplay, int clock) 1267 { 1268 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1269 1270 if (!intel_dp_has_joiner(intel_dp)) 1271 return false; 1272 1273 return clock > i915->display.cdclk.max_dotclk_freq || hdisplay > 5120 || 1274 connector->force_bigjoiner_enable; 1275 } 1276 1277 bool intel_dp_has_dsc(const struct intel_connector *connector) 1278 { 1279 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1280 1281 if (!HAS_DSC(i915)) 1282 return false; 1283 1284 if (connector->mst_port && !HAS_DSC_MST(i915)) 1285 return false; 1286 1287 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && 1288 connector->panel.vbt.edp.dsc_disable) 1289 return false; 1290 1291 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) 1292 return false; 1293 1294 return true; 1295 } 1296 1297 static enum drm_mode_status 1298 intel_dp_mode_valid(struct drm_connector *_connector, 1299 struct drm_display_mode *mode) 1300 { 1301 struct intel_connector *connector = to_intel_connector(_connector); 1302 struct intel_dp *intel_dp = intel_attached_dp(connector); 1303 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1304 const struct drm_display_mode *fixed_mode; 1305 int target_clock = mode->clock; 1306 int max_rate, mode_rate, max_lanes, max_link_clock; 1307 int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq; 1308 u16 dsc_max_compressed_bpp = 0; 1309 u8 dsc_slice_count = 0; 1310 enum drm_mode_status status; 1311 bool dsc = false, joiner = false; 1312 1313 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 1314 if (status != MODE_OK) 1315 return status; 1316 1317 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1318 return MODE_H_ILLEGAL; 1319 1320 if (mode->clock < 10000) 1321 return MODE_CLOCK_LOW; 1322 1323 fixed_mode = intel_panel_fixed_mode(connector, mode); 1324 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 1325 status = intel_panel_mode_valid(connector, mode); 1326 if (status != MODE_OK) 1327 return status; 1328 1329 target_clock = fixed_mode->clock; 1330 } 1331 1332 if (intel_dp_need_joiner(intel_dp, connector, 1333 mode->hdisplay, target_clock)) { 1334 joiner = true; 1335 max_dotclk *= 2; 1336 } 1337 if (target_clock > max_dotclk) 1338 return MODE_CLOCK_HIGH; 1339 1340 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) 1341 return MODE_H_ILLEGAL; 1342 1343 max_link_clock = intel_dp_max_link_rate(intel_dp); 1344 max_lanes = intel_dp_max_lane_count(intel_dp); 1345 1346 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1347 1348 mode_rate = intel_dp_link_required(target_clock, 1349 intel_dp_mode_min_output_bpp(connector, mode)); 1350 1351 if (intel_dp_has_dsc(connector)) { 1352 enum intel_output_format sink_format, output_format; 1353 int pipe_bpp; 1354 1355 sink_format = intel_dp_sink_format(connector, mode); 1356 output_format = intel_dp_output_format(connector, sink_format); 1357 /* 1358 * TBD pass the connector BPC, 1359 * for now U8_MAX so that max BPC on that platform would be picked 1360 */ 1361 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1362 1363 /* 1364 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1365 * integer value since we support only integer values of bpp. 1366 */ 1367 if (intel_dp_is_edp(intel_dp)) { 1368 dsc_max_compressed_bpp = 1369 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1370 dsc_slice_count = 1371 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 1372 true); 1373 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1374 dsc_max_compressed_bpp = 1375 intel_dp_dsc_get_max_compressed_bpp(dev_priv, 1376 max_link_clock, 1377 max_lanes, 1378 target_clock, 1379 mode->hdisplay, 1380 joiner, 1381 output_format, 1382 pipe_bpp, 64); 1383 dsc_slice_count = 1384 intel_dp_dsc_get_slice_count(connector, 1385 target_clock, 1386 mode->hdisplay, 1387 joiner); 1388 } 1389 1390 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1391 } 1392 1393 if (intel_dp_joiner_needs_dsc(dev_priv, joiner) && !dsc) 1394 return MODE_CLOCK_HIGH; 1395 1396 if (mode_rate > max_rate && !dsc) 1397 return MODE_CLOCK_HIGH; 1398 1399 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); 1400 if (status != MODE_OK) 1401 return status; 1402 1403 return intel_mode_valid_max_plane_size(dev_priv, mode, joiner); 1404 } 1405 1406 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915) 1407 { 1408 return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915); 1409 } 1410 1411 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915) 1412 { 1413 return DISPLAY_VER(i915) >= 10; 1414 } 1415 1416 static void snprintf_int_array(char *str, size_t len, 1417 const int *array, int nelem) 1418 { 1419 int i; 1420 1421 str[0] = '\0'; 1422 1423 for (i = 0; i < nelem; i++) { 1424 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1425 if (r >= len) 1426 return; 1427 str += r; 1428 len -= r; 1429 } 1430 } 1431 1432 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1433 { 1434 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1435 char str[128]; /* FIXME: too big for stack? */ 1436 1437 if (!drm_debug_enabled(DRM_UT_KMS)) 1438 return; 1439 1440 snprintf_int_array(str, sizeof(str), 1441 intel_dp->source_rates, intel_dp->num_source_rates); 1442 drm_dbg_kms(&i915->drm, "source rates: %s\n", str); 1443 1444 snprintf_int_array(str, sizeof(str), 1445 intel_dp->sink_rates, intel_dp->num_sink_rates); 1446 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); 1447 1448 snprintf_int_array(str, sizeof(str), 1449 intel_dp->common_rates, intel_dp->num_common_rates); 1450 drm_dbg_kms(&i915->drm, "common rates: %s\n", str); 1451 } 1452 1453 static int forced_link_rate(struct intel_dp *intel_dp) 1454 { 1455 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate); 1456 1457 if (len == 0) 1458 return intel_dp_common_rate(intel_dp, 0); 1459 1460 return intel_dp_common_rate(intel_dp, len - 1); 1461 } 1462 1463 int 1464 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1465 { 1466 int len; 1467 1468 if (intel_dp->link.force_rate) 1469 return forced_link_rate(intel_dp); 1470 1471 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); 1472 1473 return intel_dp_common_rate(intel_dp, len - 1); 1474 } 1475 1476 static int 1477 intel_dp_min_link_rate(struct intel_dp *intel_dp) 1478 { 1479 if (intel_dp->link.force_rate) 1480 return forced_link_rate(intel_dp); 1481 1482 return intel_dp_common_rate(intel_dp, 0); 1483 } 1484 1485 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1486 { 1487 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1488 int i = intel_dp_rate_index(intel_dp->sink_rates, 1489 intel_dp->num_sink_rates, rate); 1490 1491 if (drm_WARN_ON(&i915->drm, i < 0)) 1492 i = 0; 1493 1494 return i; 1495 } 1496 1497 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1498 u8 *link_bw, u8 *rate_select) 1499 { 1500 /* eDP 1.4 rate select method. */ 1501 if (intel_dp->use_rate_select) { 1502 *link_bw = 0; 1503 *rate_select = 1504 intel_dp_rate_select(intel_dp, port_clock); 1505 } else { 1506 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1507 *rate_select = 0; 1508 } 1509 } 1510 1511 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1512 { 1513 struct intel_connector *connector = intel_dp->attached_connector; 1514 1515 return connector->base.display_info.is_hdmi; 1516 } 1517 1518 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1519 const struct intel_crtc_state *pipe_config) 1520 { 1521 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1522 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1523 1524 if (DISPLAY_VER(dev_priv) >= 12) 1525 return true; 1526 1527 if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A && 1528 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) 1529 return true; 1530 1531 return false; 1532 } 1533 1534 bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1535 const struct intel_connector *connector, 1536 const struct intel_crtc_state *pipe_config) 1537 { 1538 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1539 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1540 } 1541 1542 bool intel_dp_supports_dsc(const struct intel_connector *connector, 1543 const struct intel_crtc_state *crtc_state) 1544 { 1545 if (!intel_dp_has_dsc(connector)) 1546 return false; 1547 1548 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) 1549 return false; 1550 1551 return intel_dsc_source_support(crtc_state); 1552 } 1553 1554 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1555 const struct intel_crtc_state *crtc_state, 1556 int bpc, bool respect_downstream_limits) 1557 { 1558 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1559 1560 /* 1561 * Current bpc could already be below 8bpc due to 1562 * FDI bandwidth constraints or other limits. 1563 * HDMI minimum is 8bpc however. 1564 */ 1565 bpc = max(bpc, 8); 1566 1567 /* 1568 * We will never exceed downstream TMDS clock limits while 1569 * attempting deep color. If the user insists on forcing an 1570 * out of spec mode they will have to be satisfied with 8bpc. 1571 */ 1572 if (!respect_downstream_limits) 1573 bpc = 8; 1574 1575 for (; bpc >= 8; bpc -= 2) { 1576 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1577 intel_dp_has_hdmi_sink(intel_dp)) && 1578 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1579 respect_downstream_limits) == MODE_OK) 1580 return bpc; 1581 } 1582 1583 return -EINVAL; 1584 } 1585 1586 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1587 const struct intel_crtc_state *crtc_state, 1588 bool respect_downstream_limits) 1589 { 1590 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1591 struct intel_connector *intel_connector = intel_dp->attached_connector; 1592 int bpp, bpc; 1593 1594 bpc = crtc_state->pipe_bpp / 3; 1595 1596 if (intel_dp->dfp.max_bpc) 1597 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1598 1599 if (intel_dp->dfp.min_tmds_clock) { 1600 int max_hdmi_bpc; 1601 1602 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1603 respect_downstream_limits); 1604 if (max_hdmi_bpc < 0) 1605 return 0; 1606 1607 bpc = min(bpc, max_hdmi_bpc); 1608 } 1609 1610 bpp = bpc * 3; 1611 if (intel_dp_is_edp(intel_dp)) { 1612 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1613 if (intel_connector->base.display_info.bpc == 0 && 1614 intel_connector->panel.vbt.edp.bpp && 1615 intel_connector->panel.vbt.edp.bpp < bpp) { 1616 drm_dbg_kms(&dev_priv->drm, 1617 "clamping bpp for eDP panel to BIOS-provided %i\n", 1618 intel_connector->panel.vbt.edp.bpp); 1619 bpp = intel_connector->panel.vbt.edp.bpp; 1620 } 1621 } 1622 1623 return bpp; 1624 } 1625 1626 /* Adjust link config limits based on compliance test requests. */ 1627 void 1628 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 1629 struct intel_crtc_state *pipe_config, 1630 struct link_config_limits *limits) 1631 { 1632 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1633 1634 /* For DP Compliance we override the computed bpp for the pipe */ 1635 if (intel_dp->compliance.test_data.bpc != 0) { 1636 int bpp = 3 * intel_dp->compliance.test_data.bpc; 1637 1638 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp; 1639 pipe_config->dither_force_disable = bpp == 6 * 3; 1640 1641 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); 1642 } 1643 1644 /* Use values requested by Compliance Test Request */ 1645 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 1646 int index; 1647 1648 /* Validate the compliance test data since max values 1649 * might have changed due to link train fallback. 1650 */ 1651 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, 1652 intel_dp->compliance.test_lane_count)) { 1653 index = intel_dp_rate_index(intel_dp->common_rates, 1654 intel_dp->num_common_rates, 1655 intel_dp->compliance.test_link_rate); 1656 if (index >= 0) 1657 limits->min_rate = limits->max_rate = 1658 intel_dp->compliance.test_link_rate; 1659 limits->min_lane_count = limits->max_lane_count = 1660 intel_dp->compliance.test_lane_count; 1661 } 1662 } 1663 } 1664 1665 static bool has_seamless_m_n(struct intel_connector *connector) 1666 { 1667 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1668 1669 /* 1670 * Seamless M/N reprogramming only implemented 1671 * for BDW+ double buffered M/N registers so far. 1672 */ 1673 return HAS_DOUBLE_BUFFERED_M_N(i915) && 1674 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1675 } 1676 1677 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1678 const struct drm_connector_state *conn_state) 1679 { 1680 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1681 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1682 1683 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1684 if (has_seamless_m_n(connector)) 1685 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1686 else 1687 return adjusted_mode->crtc_clock; 1688 } 1689 1690 /* Optimize link config in order: max bpp, min clock, min lanes */ 1691 static int 1692 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1693 struct intel_crtc_state *pipe_config, 1694 const struct drm_connector_state *conn_state, 1695 const struct link_config_limits *limits) 1696 { 1697 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1698 int mode_rate, link_rate, link_avail; 1699 1700 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1701 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1702 bpp -= 2 * 3) { 1703 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1704 1705 mode_rate = intel_dp_link_required(clock, link_bpp); 1706 1707 for (i = 0; i < intel_dp->num_common_rates; i++) { 1708 link_rate = intel_dp_common_rate(intel_dp, i); 1709 if (link_rate < limits->min_rate || 1710 link_rate > limits->max_rate) 1711 continue; 1712 1713 for (lane_count = limits->min_lane_count; 1714 lane_count <= limits->max_lane_count; 1715 lane_count <<= 1) { 1716 link_avail = intel_dp_max_link_data_rate(intel_dp, 1717 link_rate, 1718 lane_count); 1719 1720 1721 if (mode_rate <= link_avail) { 1722 pipe_config->lane_count = lane_count; 1723 pipe_config->pipe_bpp = bpp; 1724 pipe_config->port_clock = link_rate; 1725 1726 return 0; 1727 } 1728 } 1729 } 1730 } 1731 1732 return -EINVAL; 1733 } 1734 1735 static 1736 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) 1737 { 1738 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1739 if (DISPLAY_VER(i915) >= 12) 1740 return 12; 1741 if (DISPLAY_VER(i915) == 11) 1742 return 10; 1743 1744 return 0; 1745 } 1746 1747 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1748 u8 max_req_bpc) 1749 { 1750 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1751 int i, num_bpc; 1752 u8 dsc_bpc[3] = {}; 1753 u8 dsc_max_bpc; 1754 1755 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); 1756 1757 if (!dsc_max_bpc) 1758 return dsc_max_bpc; 1759 1760 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); 1761 1762 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1763 dsc_bpc); 1764 for (i = 0; i < num_bpc; i++) { 1765 if (dsc_max_bpc >= dsc_bpc[i]) 1766 return dsc_bpc[i] * 3; 1767 } 1768 1769 return 0; 1770 } 1771 1772 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915) 1773 { 1774 return DISPLAY_VER(i915) >= 14 ? 2 : 1; 1775 } 1776 1777 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1778 { 1779 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1780 DP_DSC_MINOR_SHIFT; 1781 } 1782 1783 static int intel_dp_get_slice_height(int vactive) 1784 { 1785 int slice_height; 1786 1787 /* 1788 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1789 * lines is an optimal slice height, but any size can be used as long as 1790 * vertical active integer multiple and maximum vertical slice count 1791 * requirements are met. 1792 */ 1793 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1794 if (vactive % slice_height == 0) 1795 return slice_height; 1796 1797 /* 1798 * Highly unlikely we reach here as most of the resolutions will end up 1799 * finding appropriate slice_height in above loop but returning 1800 * slice_height as 2 here as it should work with all resolutions. 1801 */ 1802 return 2; 1803 } 1804 1805 static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1806 struct intel_crtc_state *crtc_state) 1807 { 1808 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1809 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1810 int ret; 1811 1812 /* 1813 * RC_MODEL_SIZE is currently a constant across all configurations. 1814 * 1815 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1816 * DP_DSC_RC_BUF_SIZE for this. 1817 */ 1818 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1819 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1820 1821 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1822 1823 ret = intel_dsc_compute_params(crtc_state); 1824 if (ret) 1825 return ret; 1826 1827 vdsc_cfg->dsc_version_major = 1828 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1829 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1830 vdsc_cfg->dsc_version_minor = 1831 min(intel_dp_source_dsc_version_minor(i915), 1832 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1833 if (vdsc_cfg->convert_rgb) 1834 vdsc_cfg->convert_rgb = 1835 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1836 DP_DSC_RGB; 1837 1838 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, 1839 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); 1840 if (!vdsc_cfg->line_buf_depth) { 1841 drm_dbg_kms(&i915->drm, 1842 "DSC Sink Line Buffer Depth invalid\n"); 1843 return -EINVAL; 1844 } 1845 1846 vdsc_cfg->block_pred_enable = 1847 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1848 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1849 1850 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1851 } 1852 1853 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1854 enum intel_output_format output_format) 1855 { 1856 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1857 u8 sink_dsc_format; 1858 1859 switch (output_format) { 1860 case INTEL_OUTPUT_FORMAT_RGB: 1861 sink_dsc_format = DP_DSC_RGB; 1862 break; 1863 case INTEL_OUTPUT_FORMAT_YCBCR444: 1864 sink_dsc_format = DP_DSC_YCbCr444; 1865 break; 1866 case INTEL_OUTPUT_FORMAT_YCBCR420: 1867 if (min(intel_dp_source_dsc_version_minor(i915), 1868 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1869 return false; 1870 sink_dsc_format = DP_DSC_YCbCr420_Native; 1871 break; 1872 default: 1873 return false; 1874 } 1875 1876 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1877 } 1878 1879 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock, 1880 u32 lane_count, u32 mode_clock, 1881 enum intel_output_format output_format, 1882 int timeslots) 1883 { 1884 u32 available_bw, required_bw; 1885 1886 available_bw = (link_clock * lane_count * timeslots * 16) / 8; 1887 required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock)); 1888 1889 return available_bw > required_bw; 1890 } 1891 1892 static int dsc_compute_link_config(struct intel_dp *intel_dp, 1893 struct intel_crtc_state *pipe_config, 1894 struct link_config_limits *limits, 1895 u16 compressed_bppx16, 1896 int timeslots) 1897 { 1898 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1899 int link_rate, lane_count; 1900 int i; 1901 1902 for (i = 0; i < intel_dp->num_common_rates; i++) { 1903 link_rate = intel_dp_common_rate(intel_dp, i); 1904 if (link_rate < limits->min_rate || link_rate > limits->max_rate) 1905 continue; 1906 1907 for (lane_count = limits->min_lane_count; 1908 lane_count <= limits->max_lane_count; 1909 lane_count <<= 1) { 1910 if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, 1911 lane_count, adjusted_mode->clock, 1912 pipe_config->output_format, 1913 timeslots)) 1914 continue; 1915 1916 pipe_config->lane_count = lane_count; 1917 pipe_config->port_clock = link_rate; 1918 1919 return 0; 1920 } 1921 } 1922 1923 return -EINVAL; 1924 } 1925 1926 static 1927 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 1928 struct intel_crtc_state *pipe_config, 1929 int bpc) 1930 { 1931 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 1932 1933 if (max_bppx16) 1934 return max_bppx16; 1935 /* 1936 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 1937 * values as given in spec Table 2-157 DP v2.0 1938 */ 1939 switch (pipe_config->output_format) { 1940 case INTEL_OUTPUT_FORMAT_RGB: 1941 case INTEL_OUTPUT_FORMAT_YCBCR444: 1942 return (3 * bpc) << 4; 1943 case INTEL_OUTPUT_FORMAT_YCBCR420: 1944 return (3 * (bpc / 2)) << 4; 1945 default: 1946 MISSING_CASE(pipe_config->output_format); 1947 break; 1948 } 1949 1950 return 0; 1951 } 1952 1953 int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) 1954 { 1955 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 1956 switch (pipe_config->output_format) { 1957 case INTEL_OUTPUT_FORMAT_RGB: 1958 case INTEL_OUTPUT_FORMAT_YCBCR444: 1959 return 8; 1960 case INTEL_OUTPUT_FORMAT_YCBCR420: 1961 return 6; 1962 default: 1963 MISSING_CASE(pipe_config->output_format); 1964 break; 1965 } 1966 1967 return 0; 1968 } 1969 1970 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 1971 struct intel_crtc_state *pipe_config, 1972 int bpc) 1973 { 1974 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 1975 pipe_config, bpc) >> 4; 1976 } 1977 1978 static int dsc_src_min_compressed_bpp(void) 1979 { 1980 /* Min Compressed bpp supported by source is 8 */ 1981 return 8; 1982 } 1983 1984 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 1985 { 1986 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1987 1988 /* 1989 * Max Compressed bpp for Gen 13+ is 27bpp. 1990 * For earlier platform is 23bpp. (Bspec:49259). 1991 */ 1992 if (DISPLAY_VER(i915) < 13) 1993 return 23; 1994 else 1995 return 27; 1996 } 1997 1998 /* 1999 * From a list of valid compressed bpps try different compressed bpp and find a 2000 * suitable link configuration that can support it. 2001 */ 2002 static int 2003 icl_dsc_compute_link_config(struct intel_dp *intel_dp, 2004 struct intel_crtc_state *pipe_config, 2005 struct link_config_limits *limits, 2006 int dsc_max_bpp, 2007 int dsc_min_bpp, 2008 int pipe_bpp, 2009 int timeslots) 2010 { 2011 int i, ret; 2012 2013 /* Compressed BPP should be less than the Input DSC bpp */ 2014 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2015 2016 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 2017 if (valid_dsc_bpp[i] < dsc_min_bpp) 2018 continue; 2019 if (valid_dsc_bpp[i] > dsc_max_bpp) 2020 break; 2021 2022 ret = dsc_compute_link_config(intel_dp, 2023 pipe_config, 2024 limits, 2025 valid_dsc_bpp[i] << 4, 2026 timeslots); 2027 if (ret == 0) { 2028 pipe_config->dsc.compressed_bpp_x16 = 2029 fxp_q4_from_int(valid_dsc_bpp[i]); 2030 return 0; 2031 } 2032 } 2033 2034 return -EINVAL; 2035 } 2036 2037 /* 2038 * From XE_LPD onwards we supports compression bpps in steps of 1 up to 2039 * uncompressed bpp-1. So we start from max compressed bpp and see if any 2040 * link configuration is able to support that compressed bpp, if not we 2041 * step down and check for lower compressed bpp. 2042 */ 2043 static int 2044 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, 2045 const struct intel_connector *connector, 2046 struct intel_crtc_state *pipe_config, 2047 struct link_config_limits *limits, 2048 int dsc_max_bpp, 2049 int dsc_min_bpp, 2050 int pipe_bpp, 2051 int timeslots) 2052 { 2053 u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); 2054 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2055 u16 compressed_bppx16; 2056 u8 bppx16_step; 2057 int ret; 2058 2059 if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) 2060 bppx16_step = 16; 2061 else 2062 bppx16_step = 16 / bppx16_incr; 2063 2064 /* Compressed BPP should be less than the Input DSC bpp */ 2065 dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step); 2066 dsc_min_bpp = dsc_min_bpp << 4; 2067 2068 for (compressed_bppx16 = dsc_max_bpp; 2069 compressed_bppx16 >= dsc_min_bpp; 2070 compressed_bppx16 -= bppx16_step) { 2071 if (intel_dp->force_dsc_fractional_bpp_en && 2072 !fxp_q4_to_frac(compressed_bppx16)) 2073 continue; 2074 ret = dsc_compute_link_config(intel_dp, 2075 pipe_config, 2076 limits, 2077 compressed_bppx16, 2078 timeslots); 2079 if (ret == 0) { 2080 pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; 2081 if (intel_dp->force_dsc_fractional_bpp_en && 2082 fxp_q4_to_frac(compressed_bppx16)) 2083 drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n"); 2084 2085 return 0; 2086 } 2087 } 2088 return -EINVAL; 2089 } 2090 2091 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 2092 const struct intel_connector *connector, 2093 struct intel_crtc_state *pipe_config, 2094 struct link_config_limits *limits, 2095 int pipe_bpp, 2096 int timeslots) 2097 { 2098 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2099 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2100 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2101 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2102 int dsc_joiner_max_bpp; 2103 2104 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2105 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); 2106 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2107 dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16)); 2108 2109 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2110 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2111 pipe_config, 2112 pipe_bpp / 3); 2113 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2114 2115 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, 2116 adjusted_mode->hdisplay, 2117 pipe_config->joiner_pipes); 2118 dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp); 2119 dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2120 2121 if (DISPLAY_VER(i915) >= 13) 2122 return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits, 2123 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); 2124 return icl_dsc_compute_link_config(intel_dp, pipe_config, limits, 2125 dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); 2126 } 2127 2128 static 2129 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) 2130 { 2131 /* Min DSC Input BPC for ICL+ is 8 */ 2132 return HAS_DSC(i915) ? 8 : 0; 2133 } 2134 2135 static 2136 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, 2137 struct drm_connector_state *conn_state, 2138 struct link_config_limits *limits, 2139 int pipe_bpp) 2140 { 2141 u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp; 2142 2143 dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc); 2144 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); 2145 2146 dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); 2147 dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); 2148 2149 return pipe_bpp >= dsc_min_pipe_bpp && 2150 pipe_bpp <= dsc_max_pipe_bpp; 2151 } 2152 2153 static 2154 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 2155 struct drm_connector_state *conn_state, 2156 struct link_config_limits *limits) 2157 { 2158 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2159 int forced_bpp; 2160 2161 if (!intel_dp->force_dsc_bpc) 2162 return 0; 2163 2164 forced_bpp = intel_dp->force_dsc_bpc * 3; 2165 2166 if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) { 2167 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); 2168 return forced_bpp; 2169 } 2170 2171 drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 2172 intel_dp->force_dsc_bpc); 2173 2174 return 0; 2175 } 2176 2177 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2178 struct intel_crtc_state *pipe_config, 2179 struct drm_connector_state *conn_state, 2180 struct link_config_limits *limits, 2181 int timeslots) 2182 { 2183 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2184 const struct intel_connector *connector = 2185 to_intel_connector(conn_state->connector); 2186 u8 max_req_bpc = conn_state->max_requested_bpc; 2187 u8 dsc_max_bpc, dsc_max_bpp; 2188 u8 dsc_min_bpc, dsc_min_bpp; 2189 u8 dsc_bpc[3] = {}; 2190 int forced_bpp, pipe_bpp; 2191 int num_bpc, i, ret; 2192 2193 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); 2194 2195 if (forced_bpp) { 2196 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, 2197 limits, forced_bpp, timeslots); 2198 if (ret == 0) { 2199 pipe_config->pipe_bpp = forced_bpp; 2200 return 0; 2201 } 2202 } 2203 2204 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); 2205 if (!dsc_max_bpc) 2206 return -EINVAL; 2207 2208 dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); 2209 dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp); 2210 2211 dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); 2212 dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp); 2213 2214 /* 2215 * Get the maximum DSC bpc that will be supported by any valid 2216 * link configuration and compressed bpp. 2217 */ 2218 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); 2219 for (i = 0; i < num_bpc; i++) { 2220 pipe_bpp = dsc_bpc[i] * 3; 2221 if (pipe_bpp < dsc_min_bpp) 2222 break; 2223 if (pipe_bpp > dsc_max_bpp) 2224 continue; 2225 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, 2226 limits, pipe_bpp, timeslots); 2227 if (ret == 0) { 2228 pipe_config->pipe_bpp = pipe_bpp; 2229 return 0; 2230 } 2231 } 2232 2233 return -EINVAL; 2234 } 2235 2236 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2237 struct intel_crtc_state *pipe_config, 2238 struct drm_connector_state *conn_state, 2239 struct link_config_limits *limits) 2240 { 2241 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2242 struct intel_connector *connector = 2243 to_intel_connector(conn_state->connector); 2244 int pipe_bpp, forced_bpp; 2245 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2246 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2247 2248 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); 2249 2250 if (forced_bpp) { 2251 pipe_bpp = forced_bpp; 2252 } else { 2253 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc); 2254 2255 /* For eDP use max bpp that can be supported with DSC. */ 2256 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); 2257 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) { 2258 drm_dbg_kms(&i915->drm, 2259 "Computed BPC is not in DSC BPC limits\n"); 2260 return -EINVAL; 2261 } 2262 } 2263 pipe_config->port_clock = limits->max_rate; 2264 pipe_config->lane_count = limits->max_lane_count; 2265 2266 dsc_src_min_bpp = dsc_src_min_compressed_bpp(); 2267 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); 2268 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2269 dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16)); 2270 2271 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2272 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2273 pipe_config, 2274 pipe_bpp / 3); 2275 dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2276 dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); 2277 2278 /* Compressed BPP should be less than the Input DSC bpp */ 2279 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2280 2281 pipe_config->dsc.compressed_bpp_x16 = 2282 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); 2283 2284 pipe_config->pipe_bpp = pipe_bpp; 2285 2286 return 0; 2287 } 2288 2289 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2290 struct intel_crtc_state *pipe_config, 2291 struct drm_connector_state *conn_state, 2292 struct link_config_limits *limits, 2293 int timeslots, 2294 bool compute_pipe_bpp) 2295 { 2296 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2297 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2298 const struct intel_connector *connector = 2299 to_intel_connector(conn_state->connector); 2300 const struct drm_display_mode *adjusted_mode = 2301 &pipe_config->hw.adjusted_mode; 2302 int ret; 2303 2304 pipe_config->fec_enable = pipe_config->fec_enable || 2305 (!intel_dp_is_edp(intel_dp) && 2306 intel_dp_supports_fec(intel_dp, connector, pipe_config)); 2307 2308 if (!intel_dp_supports_dsc(connector, pipe_config)) 2309 return -EINVAL; 2310 2311 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2312 return -EINVAL; 2313 2314 /* 2315 * compute pipe bpp is set to false for DP MST DSC case 2316 * and compressed_bpp is calculated same time once 2317 * vpci timeslots are allocated, because overall bpp 2318 * calculation procedure is bit different for MST case. 2319 */ 2320 if (compute_pipe_bpp) { 2321 if (intel_dp_is_edp(intel_dp)) 2322 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2323 conn_state, limits); 2324 else 2325 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2326 conn_state, limits, timeslots); 2327 if (ret) { 2328 drm_dbg_kms(&dev_priv->drm, 2329 "No Valid pipe bpp for given mode ret = %d\n", ret); 2330 return ret; 2331 } 2332 } 2333 2334 /* Calculate Slice count */ 2335 if (intel_dp_is_edp(intel_dp)) { 2336 pipe_config->dsc.slice_count = 2337 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 2338 true); 2339 if (!pipe_config->dsc.slice_count) { 2340 drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n", 2341 pipe_config->dsc.slice_count); 2342 return -EINVAL; 2343 } 2344 } else { 2345 u8 dsc_dp_slice_count; 2346 2347 dsc_dp_slice_count = 2348 intel_dp_dsc_get_slice_count(connector, 2349 adjusted_mode->crtc_clock, 2350 adjusted_mode->crtc_hdisplay, 2351 pipe_config->joiner_pipes); 2352 if (!dsc_dp_slice_count) { 2353 drm_dbg_kms(&dev_priv->drm, 2354 "Compressed Slice Count not supported\n"); 2355 return -EINVAL; 2356 } 2357 2358 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2359 } 2360 /* 2361 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2362 * is greater than the maximum Cdclock and if slice count is even 2363 * then we need to use 2 VDSC instances. 2364 */ 2365 if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2366 pipe_config->dsc.dsc_split = true; 2367 2368 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2369 if (ret < 0) { 2370 drm_dbg_kms(&dev_priv->drm, 2371 "Cannot compute valid DSC parameters for Input Bpp = %d" 2372 "Compressed BPP = " FXP_Q4_FMT "\n", 2373 pipe_config->pipe_bpp, 2374 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2375 return ret; 2376 } 2377 2378 pipe_config->dsc.compression_enable = true; 2379 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " 2380 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2381 pipe_config->pipe_bpp, 2382 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2383 pipe_config->dsc.slice_count); 2384 2385 return 0; 2386 } 2387 2388 /** 2389 * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits 2390 * @intel_dp: intel DP 2391 * @crtc_state: crtc state 2392 * @dsc: DSC compression mode 2393 * @limits: link configuration limits 2394 * 2395 * Calculates the output link min, max bpp values in @limits based on the 2396 * pipe bpp range, @crtc_state and @dsc mode. 2397 * 2398 * Returns %true in case of success. 2399 */ 2400 bool 2401 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 2402 const struct intel_crtc_state *crtc_state, 2403 bool dsc, 2404 struct link_config_limits *limits) 2405 { 2406 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2407 const struct drm_display_mode *adjusted_mode = 2408 &crtc_state->hw.adjusted_mode; 2409 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2410 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2411 int max_link_bpp_x16; 2412 2413 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2414 fxp_q4_from_int(limits->pipe.max_bpp)); 2415 2416 if (!dsc) { 2417 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2418 2419 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2420 return false; 2421 2422 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2423 } else { 2424 /* 2425 * TODO: set the DSC link limits already here, atm these are 2426 * initialized only later in intel_edp_dsc_compute_pipe_bpp() / 2427 * intel_dp_dsc_compute_pipe_bpp() 2428 */ 2429 limits->link.min_bpp_x16 = 0; 2430 } 2431 2432 limits->link.max_bpp_x16 = max_link_bpp_x16; 2433 2434 drm_dbg_kms(&i915->drm, 2435 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2436 encoder->base.base.id, encoder->base.name, 2437 crtc->base.base.id, crtc->base.name, 2438 adjusted_mode->crtc_clock, 2439 dsc ? "on" : "off", 2440 limits->max_lane_count, 2441 limits->max_rate, 2442 limits->pipe.max_bpp, 2443 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2444 2445 return true; 2446 } 2447 2448 static bool 2449 intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2450 struct intel_crtc_state *crtc_state, 2451 bool respect_downstream_limits, 2452 bool dsc, 2453 struct link_config_limits *limits) 2454 { 2455 limits->min_rate = intel_dp_min_link_rate(intel_dp); 2456 limits->max_rate = intel_dp_max_link_rate(intel_dp); 2457 2458 /* FIXME 128b/132b SST support missing */ 2459 limits->max_rate = min(limits->max_rate, 810000); 2460 limits->min_rate = min(limits->min_rate, limits->max_rate); 2461 2462 limits->min_lane_count = intel_dp_min_lane_count(intel_dp); 2463 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2464 2465 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2466 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2467 respect_downstream_limits); 2468 2469 if (intel_dp->use_max_params) { 2470 /* 2471 * Use the maximum clock and number of lanes the eDP panel 2472 * advertizes being capable of in case the initial fast 2473 * optimal params failed us. The panels are generally 2474 * designed to support only a single clock and lane 2475 * configuration, and typically on older panels these 2476 * values correspond to the native resolution of the panel. 2477 */ 2478 limits->min_lane_count = limits->max_lane_count; 2479 limits->min_rate = limits->max_rate; 2480 } 2481 2482 intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); 2483 2484 return intel_dp_compute_config_link_bpp_limits(intel_dp, 2485 crtc_state, 2486 dsc, 2487 limits); 2488 } 2489 2490 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) 2491 { 2492 const struct drm_display_mode *adjusted_mode = 2493 &crtc_state->hw.adjusted_mode; 2494 int bpp = crtc_state->dsc.compression_enable ? 2495 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2496 crtc_state->pipe_bpp; 2497 2498 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2499 } 2500 2501 bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915, bool use_joiner) 2502 { 2503 /* 2504 * Pipe joiner needs compression up to display 12 due to bandwidth 2505 * limitation. DG2 onwards pipe joiner can be enabled without 2506 * compression. 2507 */ 2508 return DISPLAY_VER(i915) < 13 && use_joiner; 2509 } 2510 2511 static int 2512 intel_dp_compute_link_config(struct intel_encoder *encoder, 2513 struct intel_crtc_state *pipe_config, 2514 struct drm_connector_state *conn_state, 2515 bool respect_downstream_limits) 2516 { 2517 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2518 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2519 struct intel_connector *connector = 2520 to_intel_connector(conn_state->connector); 2521 const struct drm_display_mode *adjusted_mode = 2522 &pipe_config->hw.adjusted_mode; 2523 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2524 struct link_config_limits limits; 2525 bool dsc_needed, joiner_needs_dsc; 2526 int ret = 0; 2527 2528 if (pipe_config->fec_enable && 2529 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) 2530 return -EINVAL; 2531 2532 if (intel_dp_need_joiner(intel_dp, connector, 2533 adjusted_mode->crtc_hdisplay, 2534 adjusted_mode->crtc_clock)) 2535 pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); 2536 2537 joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, pipe_config->joiner_pipes); 2538 2539 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2540 !intel_dp_compute_config_limits(intel_dp, pipe_config, 2541 respect_downstream_limits, 2542 false, 2543 &limits); 2544 2545 if (!dsc_needed) { 2546 /* 2547 * Optimize for slow and wide for everything, because there are some 2548 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2549 */ 2550 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2551 conn_state, &limits); 2552 if (ret) 2553 dsc_needed = true; 2554 } 2555 2556 if (dsc_needed) { 2557 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2558 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2559 str_yes_no(intel_dp->force_dsc_en)); 2560 2561 if (!intel_dp_compute_config_limits(intel_dp, pipe_config, 2562 respect_downstream_limits, 2563 true, 2564 &limits)) 2565 return -EINVAL; 2566 2567 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2568 conn_state, &limits, 64, true); 2569 if (ret < 0) 2570 return ret; 2571 } 2572 2573 drm_dbg_kms(&i915->drm, 2574 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n", 2575 pipe_config->lane_count, pipe_config->port_clock, 2576 pipe_config->pipe_bpp, 2577 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2578 intel_dp_config_required_rate(pipe_config), 2579 intel_dp_max_link_data_rate(intel_dp, 2580 pipe_config->port_clock, 2581 pipe_config->lane_count)); 2582 2583 return 0; 2584 } 2585 2586 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2587 const struct drm_connector_state *conn_state) 2588 { 2589 const struct intel_digital_connector_state *intel_conn_state = 2590 to_intel_digital_connector_state(conn_state); 2591 const struct drm_display_mode *adjusted_mode = 2592 &crtc_state->hw.adjusted_mode; 2593 2594 /* 2595 * Our YCbCr output is always limited range. 2596 * crtc_state->limited_color_range only applies to RGB, 2597 * and it must never be set for YCbCr or we risk setting 2598 * some conflicting bits in TRANSCONF which will mess up 2599 * the colors on the monitor. 2600 */ 2601 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2602 return false; 2603 2604 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2605 /* 2606 * See: 2607 * CEA-861-E - 5.1 Default Encoding Parameters 2608 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2609 */ 2610 return crtc_state->pipe_bpp != 18 && 2611 drm_default_rgb_quant_range(adjusted_mode) == 2612 HDMI_QUANTIZATION_RANGE_LIMITED; 2613 } else { 2614 return intel_conn_state->broadcast_rgb == 2615 INTEL_BROADCAST_RGB_LIMITED; 2616 } 2617 } 2618 2619 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, 2620 enum port port) 2621 { 2622 if (IS_G4X(dev_priv)) 2623 return false; 2624 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A) 2625 return false; 2626 2627 return true; 2628 } 2629 2630 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2631 const struct drm_connector_state *conn_state, 2632 struct drm_dp_vsc_sdp *vsc) 2633 { 2634 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2635 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2636 2637 if (crtc_state->has_panel_replay) { 2638 /* 2639 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2640 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel 2641 * Encoding/Colorimetry Format indication. 2642 */ 2643 vsc->revision = 0x7; 2644 } else { 2645 /* 2646 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2647 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2648 * Colorimetry Format indication. 2649 */ 2650 vsc->revision = 0x5; 2651 } 2652 2653 vsc->length = 0x13; 2654 2655 /* DP 1.4a spec, Table 2-120 */ 2656 switch (crtc_state->output_format) { 2657 case INTEL_OUTPUT_FORMAT_YCBCR444: 2658 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2659 break; 2660 case INTEL_OUTPUT_FORMAT_YCBCR420: 2661 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2662 break; 2663 case INTEL_OUTPUT_FORMAT_RGB: 2664 default: 2665 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2666 } 2667 2668 switch (conn_state->colorspace) { 2669 case DRM_MODE_COLORIMETRY_BT709_YCC: 2670 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2671 break; 2672 case DRM_MODE_COLORIMETRY_XVYCC_601: 2673 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2674 break; 2675 case DRM_MODE_COLORIMETRY_XVYCC_709: 2676 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2677 break; 2678 case DRM_MODE_COLORIMETRY_SYCC_601: 2679 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2680 break; 2681 case DRM_MODE_COLORIMETRY_OPYCC_601: 2682 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2683 break; 2684 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2685 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2686 break; 2687 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2688 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2689 break; 2690 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2691 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2692 break; 2693 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2694 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2695 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2696 break; 2697 default: 2698 /* 2699 * RGB->YCBCR color conversion uses the BT.709 2700 * color space. 2701 */ 2702 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2703 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2704 else 2705 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2706 break; 2707 } 2708 2709 vsc->bpc = crtc_state->pipe_bpp / 3; 2710 2711 /* only RGB pixelformat supports 6 bpc */ 2712 drm_WARN_ON(&dev_priv->drm, 2713 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2714 2715 /* all YCbCr are always limited range */ 2716 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2717 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2718 } 2719 2720 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, 2721 struct intel_crtc_state *crtc_state) 2722 { 2723 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; 2724 const struct drm_display_mode *adjusted_mode = 2725 &crtc_state->hw.adjusted_mode; 2726 2727 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) 2728 return; 2729 2730 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 2731 2732 /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ 2733 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; 2734 as_sdp->length = 0x9; 2735 as_sdp->duration_incr_ms = 0; 2736 as_sdp->duration_incr_ms = 0; 2737 2738 if (crtc_state->cmrr.enable) { 2739 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; 2740 as_sdp->vtotal = adjusted_mode->vtotal; 2741 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); 2742 as_sdp->target_rr_divider = true; 2743 } else { 2744 as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; 2745 as_sdp->vtotal = adjusted_mode->vtotal; 2746 as_sdp->target_rr = 0; 2747 } 2748 } 2749 2750 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2751 struct intel_crtc_state *crtc_state, 2752 const struct drm_connector_state *conn_state) 2753 { 2754 struct drm_dp_vsc_sdp *vsc; 2755 2756 if ((!intel_dp->colorimetry_support || 2757 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && 2758 !crtc_state->has_psr) 2759 return; 2760 2761 vsc = &crtc_state->infoframes.vsc; 2762 2763 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 2764 vsc->sdp_type = DP_SDP_VSC; 2765 2766 /* Needs colorimetry */ 2767 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 2768 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 2769 vsc); 2770 } else if (crtc_state->has_panel_replay) { 2771 /* 2772 * [Panel Replay without colorimetry info] 2773 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2774 * VSC SDP supporting 3D stereo + Panel Replay. 2775 */ 2776 vsc->revision = 0x6; 2777 vsc->length = 0x10; 2778 } else if (crtc_state->has_sel_update) { 2779 /* 2780 * [PSR2 without colorimetry] 2781 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 2782 * 3D stereo + PSR/PSR2 + Y-coordinate. 2783 */ 2784 vsc->revision = 0x4; 2785 vsc->length = 0xe; 2786 } else { 2787 /* 2788 * [PSR1] 2789 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2790 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 2791 * higher). 2792 */ 2793 vsc->revision = 0x2; 2794 vsc->length = 0x8; 2795 } 2796 } 2797 2798 static void 2799 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 2800 struct intel_crtc_state *crtc_state, 2801 const struct drm_connector_state *conn_state) 2802 { 2803 int ret; 2804 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2805 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 2806 2807 if (!conn_state->hdr_output_metadata) 2808 return; 2809 2810 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 2811 2812 if (ret) { 2813 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); 2814 return; 2815 } 2816 2817 crtc_state->infoframes.enable |= 2818 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 2819 } 2820 2821 static bool can_enable_drrs(struct intel_connector *connector, 2822 const struct intel_crtc_state *pipe_config, 2823 const struct drm_display_mode *downclock_mode) 2824 { 2825 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2826 2827 if (pipe_config->vrr.enable) 2828 return false; 2829 2830 /* 2831 * DRRS and PSR can't be enable together, so giving preference to PSR 2832 * as it allows more power-savings by complete shutting down display, 2833 * so to guarantee this, intel_drrs_compute_config() must be called 2834 * after intel_psr_compute_config(). 2835 */ 2836 if (pipe_config->has_psr) 2837 return false; 2838 2839 /* FIXME missing FDI M2/N2 etc. */ 2840 if (pipe_config->has_pch_encoder) 2841 return false; 2842 2843 if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) 2844 return false; 2845 2846 return downclock_mode && 2847 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 2848 } 2849 2850 static void 2851 intel_dp_drrs_compute_config(struct intel_connector *connector, 2852 struct intel_crtc_state *pipe_config, 2853 int link_bpp_x16) 2854 { 2855 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2856 const struct drm_display_mode *downclock_mode = 2857 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 2858 int pixel_clock; 2859 2860 /* 2861 * FIXME all joined pipes share the same transcoder. 2862 * Need to account for that when updating M/N live. 2863 */ 2864 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) 2865 pipe_config->update_m_n = true; 2866 2867 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 2868 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 2869 intel_zero_m_n(&pipe_config->dp_m2_n2); 2870 return; 2871 } 2872 2873 if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 2874 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 2875 2876 pipe_config->has_drrs = true; 2877 2878 pixel_clock = downclock_mode->clock; 2879 if (pipe_config->splitter.enable) 2880 pixel_clock /= pipe_config->splitter.link_count; 2881 2882 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, 2883 pipe_config->port_clock, 2884 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 2885 &pipe_config->dp_m2_n2); 2886 2887 /* FIXME: abstract this better */ 2888 if (pipe_config->splitter.enable) 2889 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 2890 } 2891 2892 static bool intel_dp_has_audio(struct intel_encoder *encoder, 2893 const struct drm_connector_state *conn_state) 2894 { 2895 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2896 const struct intel_digital_connector_state *intel_conn_state = 2897 to_intel_digital_connector_state(conn_state); 2898 struct intel_connector *connector = 2899 to_intel_connector(conn_state->connector); 2900 2901 if (!intel_dp_port_has_audio(i915, encoder->port)) 2902 return false; 2903 2904 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2905 return connector->base.display_info.has_audio; 2906 else 2907 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2908 } 2909 2910 static int 2911 intel_dp_compute_output_format(struct intel_encoder *encoder, 2912 struct intel_crtc_state *crtc_state, 2913 struct drm_connector_state *conn_state, 2914 bool respect_downstream_limits) 2915 { 2916 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2918 struct intel_connector *connector = intel_dp->attached_connector; 2919 const struct drm_display_info *info = &connector->base.display_info; 2920 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2921 bool ycbcr_420_only; 2922 int ret; 2923 2924 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2925 2926 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { 2927 drm_dbg_kms(&i915->drm, 2928 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2929 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2930 } else { 2931 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); 2932 } 2933 2934 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 2935 2936 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 2937 respect_downstream_limits); 2938 if (ret) { 2939 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2940 !connector->base.ycbcr_420_allowed || 2941 !drm_mode_is_420_also(info, adjusted_mode)) 2942 return ret; 2943 2944 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2945 crtc_state->output_format = intel_dp_output_format(connector, 2946 crtc_state->sink_format); 2947 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 2948 respect_downstream_limits); 2949 } 2950 2951 return ret; 2952 } 2953 2954 void 2955 intel_dp_audio_compute_config(struct intel_encoder *encoder, 2956 struct intel_crtc_state *pipe_config, 2957 struct drm_connector_state *conn_state) 2958 { 2959 pipe_config->has_audio = 2960 intel_dp_has_audio(encoder, conn_state) && 2961 intel_audio_compute_config(encoder, pipe_config, conn_state); 2962 2963 pipe_config->sdp_split_enable = pipe_config->has_audio && 2964 intel_dp_is_uhbr(pipe_config); 2965 } 2966 2967 static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) 2968 { 2969 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2970 2971 drm_connector_get(&connector->base); 2972 if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work)) 2973 drm_connector_put(&connector->base); 2974 } 2975 2976 void 2977 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 2978 struct intel_encoder *encoder, 2979 const struct intel_crtc_state *crtc_state) 2980 { 2981 struct intel_connector *connector; 2982 struct intel_digital_connector_state *conn_state; 2983 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2984 int i; 2985 2986 if (intel_dp->needs_modeset_retry) 2987 return; 2988 2989 intel_dp->needs_modeset_retry = true; 2990 2991 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2992 intel_dp_queue_modeset_retry_work(intel_dp->attached_connector); 2993 2994 return; 2995 } 2996 2997 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 2998 if (!conn_state->base.crtc) 2999 continue; 3000 3001 if (connector->mst_port == intel_dp) 3002 intel_dp_queue_modeset_retry_work(connector); 3003 } 3004 } 3005 3006 int 3007 intel_dp_compute_config(struct intel_encoder *encoder, 3008 struct intel_crtc_state *pipe_config, 3009 struct drm_connector_state *conn_state) 3010 { 3011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3012 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 3013 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 3014 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3015 const struct drm_display_mode *fixed_mode; 3016 struct intel_connector *connector = intel_dp->attached_connector; 3017 int ret = 0, link_bpp_x16; 3018 3019 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) 3020 pipe_config->has_pch_encoder = true; 3021 3022 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 3023 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 3024 ret = intel_panel_compute_config(connector, adjusted_mode); 3025 if (ret) 3026 return ret; 3027 } 3028 3029 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 3030 return -EINVAL; 3031 3032 if (!connector->base.interlace_allowed && 3033 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 3034 return -EINVAL; 3035 3036 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 3037 return -EINVAL; 3038 3039 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) 3040 return -EINVAL; 3041 3042 /* 3043 * Try to respect downstream TMDS clock limits first, if 3044 * that fails assume the user might know something we don't. 3045 */ 3046 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); 3047 if (ret) 3048 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); 3049 if (ret) 3050 return ret; 3051 3052 if ((intel_dp_is_edp(intel_dp) && fixed_mode) || 3053 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3054 ret = intel_panel_fitting(pipe_config, conn_state); 3055 if (ret) 3056 return ret; 3057 } 3058 3059 pipe_config->limited_color_range = 3060 intel_dp_limited_color_range(pipe_config, conn_state); 3061 3062 pipe_config->enhanced_framing = 3063 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3064 3065 if (pipe_config->dsc.compression_enable) 3066 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3067 else 3068 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3069 pipe_config->pipe_bpp)); 3070 3071 if (intel_dp->mso_link_count) { 3072 int n = intel_dp->mso_link_count; 3073 int overlap = intel_dp->mso_pixel_overlap; 3074 3075 pipe_config->splitter.enable = true; 3076 pipe_config->splitter.link_count = n; 3077 pipe_config->splitter.pixel_overlap = overlap; 3078 3079 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n", 3080 n, overlap); 3081 3082 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 3083 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 3084 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 3085 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 3086 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 3087 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 3088 adjusted_mode->crtc_clock /= n; 3089 } 3090 3091 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 3092 3093 intel_link_compute_m_n(link_bpp_x16, 3094 pipe_config->lane_count, 3095 adjusted_mode->crtc_clock, 3096 pipe_config->port_clock, 3097 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3098 &pipe_config->dp_m_n); 3099 3100 /* FIXME: abstract this better */ 3101 if (pipe_config->splitter.enable) 3102 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3103 3104 if (!HAS_DDI(dev_priv)) 3105 g4x_dp_set_clock(encoder, pipe_config); 3106 3107 intel_vrr_compute_config(pipe_config, conn_state); 3108 intel_dp_compute_as_sdp(intel_dp, pipe_config); 3109 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 3110 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); 3111 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); 3112 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 3113 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 3114 3115 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, 3116 pipe_config); 3117 } 3118 3119 void intel_dp_set_link_params(struct intel_dp *intel_dp, 3120 int link_rate, int lane_count) 3121 { 3122 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3123 intel_dp->link_trained = false; 3124 intel_dp->needs_modeset_retry = false; 3125 intel_dp->link_rate = link_rate; 3126 intel_dp->lane_count = lane_count; 3127 } 3128 3129 void intel_dp_reset_link_params(struct intel_dp *intel_dp) 3130 { 3131 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); 3132 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); 3133 intel_dp->link.mst_probed_lane_count = 0; 3134 intel_dp->link.mst_probed_rate = 0; 3135 intel_dp->link.retrain_disabled = false; 3136 intel_dp->link.seq_train_failures = 0; 3137 } 3138 3139 /* Enable backlight PWM and backlight PP control. */ 3140 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3141 const struct drm_connector_state *conn_state) 3142 { 3143 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3144 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3145 3146 if (!intel_dp_is_edp(intel_dp)) 3147 return; 3148 3149 drm_dbg_kms(&i915->drm, "\n"); 3150 3151 intel_backlight_enable(crtc_state, conn_state); 3152 intel_pps_backlight_on(intel_dp); 3153 } 3154 3155 /* Disable backlight PP control and backlight PWM. */ 3156 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3157 { 3158 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3159 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3160 3161 if (!intel_dp_is_edp(intel_dp)) 3162 return; 3163 3164 drm_dbg_kms(&i915->drm, "\n"); 3165 3166 intel_pps_backlight_off(intel_dp); 3167 intel_backlight_disable(old_conn_state); 3168 } 3169 3170 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3171 { 3172 /* 3173 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3174 * be capable of signalling downstream hpd with a long pulse. 3175 * Whether or not that means D3 is safe to use is not clear, 3176 * but let's assume so until proven otherwise. 3177 * 3178 * FIXME should really check all downstream ports... 3179 */ 3180 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3181 drm_dp_is_branch(intel_dp->dpcd) && 3182 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3183 } 3184 3185 static int 3186 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) 3187 { 3188 int err; 3189 u8 val; 3190 3191 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); 3192 if (err < 0) 3193 return err; 3194 3195 if (set) 3196 val |= flag; 3197 else 3198 val &= ~flag; 3199 3200 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); 3201 } 3202 3203 static void 3204 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, 3205 bool enable) 3206 { 3207 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3208 3209 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, 3210 DP_DECOMPRESSION_EN, enable) < 0) 3211 drm_dbg_kms(&i915->drm, 3212 "Failed to %s sink decompression state\n", 3213 str_enable_disable(enable)); 3214 } 3215 3216 static void 3217 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, 3218 bool enable) 3219 { 3220 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3221 struct drm_dp_aux *aux = connector->port ? 3222 connector->port->passthrough_aux : NULL; 3223 3224 if (!aux) 3225 return; 3226 3227 if (write_dsc_decompression_flag(aux, 3228 DP_DSC_PASSTHROUGH_EN, enable) < 0) 3229 drm_dbg_kms(&i915->drm, 3230 "Failed to %s sink compression passthrough state\n", 3231 str_enable_disable(enable)); 3232 } 3233 3234 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, 3235 const struct intel_connector *connector, 3236 bool for_get_ref) 3237 { 3238 struct drm_i915_private *i915 = to_i915(state->base.dev); 3239 struct drm_connector *_connector_iter; 3240 struct drm_connector_state *old_conn_state; 3241 struct drm_connector_state *new_conn_state; 3242 int ref_count = 0; 3243 int i; 3244 3245 /* 3246 * On SST the decompression AUX device won't be shared, each connector 3247 * uses for this its own AUX targeting the sink device. 3248 */ 3249 if (!connector->mst_port) 3250 return connector->dp.dsc_decompression_enabled ? 1 : 0; 3251 3252 for_each_oldnew_connector_in_state(&state->base, _connector_iter, 3253 old_conn_state, new_conn_state, i) { 3254 const struct intel_connector * 3255 connector_iter = to_intel_connector(_connector_iter); 3256 3257 if (connector_iter->mst_port != connector->mst_port) 3258 continue; 3259 3260 if (!connector_iter->dp.dsc_decompression_enabled) 3261 continue; 3262 3263 drm_WARN_ON(&i915->drm, 3264 (for_get_ref && !new_conn_state->crtc) || 3265 (!for_get_ref && !old_conn_state->crtc)); 3266 3267 if (connector_iter->dp.dsc_decompression_aux == 3268 connector->dp.dsc_decompression_aux) 3269 ref_count++; 3270 } 3271 3272 return ref_count; 3273 } 3274 3275 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, 3276 struct intel_connector *connector) 3277 { 3278 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; 3279 3280 connector->dp.dsc_decompression_enabled = true; 3281 3282 return ret; 3283 } 3284 3285 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, 3286 struct intel_connector *connector) 3287 { 3288 connector->dp.dsc_decompression_enabled = false; 3289 3290 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; 3291 } 3292 3293 /** 3294 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device 3295 * @state: atomic state 3296 * @connector: connector to enable the decompression for 3297 * @new_crtc_state: new state for the CRTC driving @connector 3298 * 3299 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3300 * register of the appropriate sink/branch device. On SST this is always the 3301 * sink device, whereas on MST based on each device's DSC capabilities it's 3302 * either the last branch device (enabling decompression in it) or both the 3303 * last branch device (enabling passthrough in it) and the sink device 3304 * (enabling decompression in it). 3305 */ 3306 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 3307 struct intel_connector *connector, 3308 const struct intel_crtc_state *new_crtc_state) 3309 { 3310 struct drm_i915_private *i915 = to_i915(state->base.dev); 3311 3312 if (!new_crtc_state->dsc.compression_enable) 3313 return; 3314 3315 if (drm_WARN_ON(&i915->drm, 3316 !connector->dp.dsc_decompression_aux || 3317 connector->dp.dsc_decompression_enabled)) 3318 return; 3319 3320 if (!intel_dp_dsc_aux_get_ref(state, connector)) 3321 return; 3322 3323 intel_dp_sink_set_dsc_passthrough(connector, true); 3324 intel_dp_sink_set_dsc_decompression(connector, true); 3325 } 3326 3327 /** 3328 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device 3329 * @state: atomic state 3330 * @connector: connector to disable the decompression for 3331 * @old_crtc_state: old state for the CRTC driving @connector 3332 * 3333 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3334 * register of the appropriate sink/branch device, corresponding to the 3335 * sequence in intel_dp_sink_enable_decompression(). 3336 */ 3337 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 3338 struct intel_connector *connector, 3339 const struct intel_crtc_state *old_crtc_state) 3340 { 3341 struct drm_i915_private *i915 = to_i915(state->base.dev); 3342 3343 if (!old_crtc_state->dsc.compression_enable) 3344 return; 3345 3346 if (drm_WARN_ON(&i915->drm, 3347 !connector->dp.dsc_decompression_aux || 3348 !connector->dp.dsc_decompression_enabled)) 3349 return; 3350 3351 if (!intel_dp_dsc_aux_put_ref(state, connector)) 3352 return; 3353 3354 intel_dp_sink_set_dsc_decompression(connector, false); 3355 intel_dp_sink_set_dsc_passthrough(connector, false); 3356 } 3357 3358 static void 3359 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) 3360 { 3361 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3362 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3363 u8 buf[3] = {}; 3364 3365 /* 3366 * During driver init, we want to be careful and avoid changing the source OUI if it's 3367 * already set to what we want, so as to avoid clearing any state by accident 3368 */ 3369 if (careful) { 3370 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3371 drm_err(&i915->drm, "Failed to read source OUI\n"); 3372 3373 if (memcmp(oui, buf, sizeof(oui)) == 0) 3374 return; 3375 } 3376 3377 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) 3378 drm_err(&i915->drm, "Failed to write source OUI\n"); 3379 3380 intel_dp->last_oui_write = jiffies; 3381 } 3382 3383 void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 3384 { 3385 struct intel_connector *connector = intel_dp->attached_connector; 3386 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3387 3388 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 3389 connector->base.base.id, connector->base.name, 3390 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3391 3392 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 3393 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3394 } 3395 3396 /* If the device supports it, try to set the power state appropriately */ 3397 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3398 { 3399 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3400 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3401 int ret, i; 3402 3403 /* Should have a valid DPCD by this point */ 3404 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3405 return; 3406 3407 if (mode != DP_SET_POWER_D0) { 3408 if (downstream_hpd_needs_d0(intel_dp)) 3409 return; 3410 3411 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3412 } else { 3413 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 3414 3415 lspcon_resume(dp_to_dig_port(intel_dp)); 3416 3417 /* Write the source OUI as early as possible */ 3418 if (intel_dp_is_edp(intel_dp)) 3419 intel_edp_init_source_oui(intel_dp, false); 3420 3421 /* 3422 * When turning on, we need to retry for 1ms to give the sink 3423 * time to wake up. 3424 */ 3425 for (i = 0; i < 3; i++) { 3426 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3427 if (ret == 1) 3428 break; 3429 msleep(1); 3430 } 3431 3432 if (ret == 1 && lspcon->active) 3433 lspcon_wait_pcon_mode(lspcon); 3434 } 3435 3436 if (ret != 1) 3437 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n", 3438 encoder->base.base.id, encoder->base.name, 3439 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3440 } 3441 3442 static bool 3443 intel_dp_get_dpcd(struct intel_dp *intel_dp); 3444 3445 /** 3446 * intel_dp_sync_state - sync the encoder state during init/resume 3447 * @encoder: intel encoder to sync 3448 * @crtc_state: state for the CRTC connected to the encoder 3449 * 3450 * Sync any state stored in the encoder wrt. HW state during driver init 3451 * and system resume. 3452 */ 3453 void intel_dp_sync_state(struct intel_encoder *encoder, 3454 const struct intel_crtc_state *crtc_state) 3455 { 3456 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3457 bool dpcd_updated = false; 3458 3459 /* 3460 * Don't clobber DPCD if it's been already read out during output 3461 * setup (eDP) or detect. 3462 */ 3463 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { 3464 intel_dp_get_dpcd(intel_dp); 3465 dpcd_updated = true; 3466 } 3467 3468 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3469 3470 if (crtc_state) { 3471 intel_dp_reset_link_params(intel_dp); 3472 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3473 intel_dp->link_trained = true; 3474 } 3475 } 3476 3477 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3478 struct intel_crtc_state *crtc_state) 3479 { 3480 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3481 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3482 bool fastset = true; 3483 3484 /* 3485 * If BIOS has set an unsupported or non-standard link rate for some 3486 * reason force an encoder recompute and full modeset. 3487 */ 3488 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3489 crtc_state->port_clock) < 0) { 3490 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3491 encoder->base.base.id, encoder->base.name); 3492 crtc_state->uapi.connectors_changed = true; 3493 fastset = false; 3494 } 3495 3496 /* 3497 * FIXME hack to force full modeset when DSC is being used. 3498 * 3499 * As long as we do not have full state readout and config comparison 3500 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3501 * Remove once we have readout for DSC. 3502 */ 3503 if (crtc_state->dsc.compression_enable) { 3504 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3505 encoder->base.base.id, encoder->base.name); 3506 crtc_state->uapi.mode_changed = true; 3507 fastset = false; 3508 } 3509 3510 if (CAN_PANEL_REPLAY(intel_dp)) { 3511 drm_dbg_kms(&i915->drm, 3512 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n", 3513 encoder->base.base.id, encoder->base.name); 3514 crtc_state->uapi.mode_changed = true; 3515 fastset = false; 3516 } 3517 3518 return fastset; 3519 } 3520 3521 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3522 { 3523 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3524 3525 /* Clear the cached register set to avoid using stale values */ 3526 3527 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 3528 3529 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 3530 intel_dp->pcon_dsc_dpcd, 3531 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 3532 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", 3533 DP_PCON_DSC_ENCODER); 3534 3535 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", 3536 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 3537 } 3538 3539 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3540 { 3541 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3542 int i; 3543 3544 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 3545 if (frl_bw_mask & (1 << i)) 3546 return bw_gbps[i]; 3547 } 3548 return 0; 3549 } 3550 3551 static int intel_dp_pcon_set_frl_mask(int max_frl) 3552 { 3553 switch (max_frl) { 3554 case 48: 3555 return DP_PCON_FRL_BW_MASK_48GBPS; 3556 case 40: 3557 return DP_PCON_FRL_BW_MASK_40GBPS; 3558 case 32: 3559 return DP_PCON_FRL_BW_MASK_32GBPS; 3560 case 24: 3561 return DP_PCON_FRL_BW_MASK_24GBPS; 3562 case 18: 3563 return DP_PCON_FRL_BW_MASK_18GBPS; 3564 case 9: 3565 return DP_PCON_FRL_BW_MASK_9GBPS; 3566 } 3567 3568 return 0; 3569 } 3570 3571 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 3572 { 3573 struct intel_connector *intel_connector = intel_dp->attached_connector; 3574 struct drm_connector *connector = &intel_connector->base; 3575 int max_frl_rate; 3576 int max_lanes, rate_per_lane; 3577 int max_dsc_lanes, dsc_rate_per_lane; 3578 3579 max_lanes = connector->display_info.hdmi.max_lanes; 3580 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; 3581 max_frl_rate = max_lanes * rate_per_lane; 3582 3583 if (connector->display_info.hdmi.dsc_cap.v_1p2) { 3584 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes; 3585 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane; 3586 if (max_dsc_lanes && dsc_rate_per_lane) 3587 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 3588 } 3589 3590 return max_frl_rate; 3591 } 3592 3593 static bool 3594 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 3595 u8 max_frl_bw_mask, u8 *frl_trained_mask) 3596 { 3597 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 3598 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 3599 *frl_trained_mask >= max_frl_bw_mask) 3600 return true; 3601 3602 return false; 3603 } 3604 3605 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 3606 { 3607 #define TIMEOUT_FRL_READY_MS 500 3608 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 3609 3610 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3611 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 3612 u8 max_frl_bw_mask = 0, frl_trained_mask; 3613 bool is_active; 3614 3615 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 3616 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 3617 3618 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 3619 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw); 3620 3621 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 3622 3623 if (max_frl_bw <= 0) 3624 return -EINVAL; 3625 3626 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 3627 drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 3628 3629 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 3630 goto frl_trained; 3631 3632 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 3633 if (ret < 0) 3634 return ret; 3635 /* Wait for PCON to be FRL Ready */ 3636 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); 3637 3638 if (!is_active) 3639 return -ETIMEDOUT; 3640 3641 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 3642 DP_PCON_ENABLE_SEQUENTIAL_LINK); 3643 if (ret < 0) 3644 return ret; 3645 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 3646 DP_PCON_FRL_LINK_TRAIN_NORMAL); 3647 if (ret < 0) 3648 return ret; 3649 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 3650 if (ret < 0) 3651 return ret; 3652 /* 3653 * Wait for FRL to be completed 3654 * Check if the HDMI Link is up and active. 3655 */ 3656 wait_for(is_active = 3657 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 3658 TIMEOUT_HDMI_LINK_ACTIVE_MS); 3659 3660 if (!is_active) 3661 return -ETIMEDOUT; 3662 3663 frl_trained: 3664 drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 3665 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 3666 intel_dp->frl.is_trained = true; 3667 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps); 3668 3669 return 0; 3670 } 3671 3672 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 3673 { 3674 if (drm_dp_is_branch(intel_dp->dpcd) && 3675 intel_dp_has_hdmi_sink(intel_dp) && 3676 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 3677 return true; 3678 3679 return false; 3680 } 3681 3682 static 3683 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 3684 { 3685 int ret; 3686 u8 buf = 0; 3687 3688 /* Set PCON source control mode */ 3689 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 3690 3691 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3692 if (ret < 0) 3693 return ret; 3694 3695 /* Set HDMI LINK ENABLE */ 3696 buf |= DP_PCON_ENABLE_HDMI_LINK; 3697 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3698 if (ret < 0) 3699 return ret; 3700 3701 return 0; 3702 } 3703 3704 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 3705 { 3706 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3707 3708 /* 3709 * Always go for FRL training if: 3710 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 3711 * -sink is HDMI2.1 3712 */ 3713 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 3714 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 3715 intel_dp->frl.is_trained) 3716 return; 3717 3718 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 3719 int ret, mode; 3720 3721 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n"); 3722 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 3723 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 3724 3725 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 3726 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n"); 3727 } else { 3728 drm_dbg(&dev_priv->drm, "FRL training Completed\n"); 3729 } 3730 } 3731 3732 static int 3733 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 3734 { 3735 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 3736 3737 return intel_hdmi_dsc_get_slice_height(vactive); 3738 } 3739 3740 static int 3741 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 3742 const struct intel_crtc_state *crtc_state) 3743 { 3744 struct intel_connector *intel_connector = intel_dp->attached_connector; 3745 struct drm_connector *connector = &intel_connector->base; 3746 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice; 3747 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; 3748 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 3749 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 3750 3751 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 3752 pcon_max_slice_width, 3753 hdmi_max_slices, hdmi_throughput); 3754 } 3755 3756 static int 3757 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 3758 const struct intel_crtc_state *crtc_state, 3759 int num_slices, int slice_width) 3760 { 3761 struct intel_connector *intel_connector = intel_dp->attached_connector; 3762 struct drm_connector *connector = &intel_connector->base; 3763 int output_format = crtc_state->output_format; 3764 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; 3765 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 3766 int hdmi_max_chunk_bytes = 3767 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024; 3768 3769 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 3770 num_slices, output_format, hdmi_all_bpp, 3771 hdmi_max_chunk_bytes); 3772 } 3773 3774 void 3775 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 3776 const struct intel_crtc_state *crtc_state) 3777 { 3778 u8 pps_param[6]; 3779 int slice_height; 3780 int slice_width; 3781 int num_slices; 3782 int bits_per_pixel; 3783 int ret; 3784 struct intel_connector *intel_connector = intel_dp->attached_connector; 3785 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3786 struct drm_connector *connector; 3787 bool hdmi_is_dsc_1_2; 3788 3789 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 3790 return; 3791 3792 if (!intel_connector) 3793 return; 3794 connector = &intel_connector->base; 3795 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; 3796 3797 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 3798 !hdmi_is_dsc_1_2) 3799 return; 3800 3801 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 3802 if (!slice_height) 3803 return; 3804 3805 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 3806 if (!num_slices) 3807 return; 3808 3809 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 3810 num_slices); 3811 3812 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 3813 num_slices, slice_width); 3814 if (!bits_per_pixel) 3815 return; 3816 3817 pps_param[0] = slice_height & 0xFF; 3818 pps_param[1] = slice_height >> 8; 3819 pps_param[2] = slice_width & 0xFF; 3820 pps_param[3] = slice_width >> 8; 3821 pps_param[4] = bits_per_pixel & 0xFF; 3822 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 3823 3824 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 3825 if (ret < 0) 3826 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); 3827 } 3828 3829 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 3830 const struct intel_crtc_state *crtc_state) 3831 { 3832 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3833 bool ycbcr444_to_420 = false; 3834 bool rgb_to_ycbcr = false; 3835 u8 tmp; 3836 3837 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 3838 return; 3839 3840 if (!drm_dp_is_branch(intel_dp->dpcd)) 3841 return; 3842 3843 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 3844 3845 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3846 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 3847 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", 3848 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 3849 3850 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3851 switch (crtc_state->output_format) { 3852 case INTEL_OUTPUT_FORMAT_YCBCR420: 3853 break; 3854 case INTEL_OUTPUT_FORMAT_YCBCR444: 3855 ycbcr444_to_420 = true; 3856 break; 3857 case INTEL_OUTPUT_FORMAT_RGB: 3858 rgb_to_ycbcr = true; 3859 ycbcr444_to_420 = true; 3860 break; 3861 default: 3862 MISSING_CASE(crtc_state->output_format); 3863 break; 3864 } 3865 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 3866 switch (crtc_state->output_format) { 3867 case INTEL_OUTPUT_FORMAT_YCBCR444: 3868 break; 3869 case INTEL_OUTPUT_FORMAT_RGB: 3870 rgb_to_ycbcr = true; 3871 break; 3872 default: 3873 MISSING_CASE(crtc_state->output_format); 3874 break; 3875 } 3876 } 3877 3878 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 3879 3880 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3881 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 3882 drm_dbg_kms(&i915->drm, 3883 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 3884 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 3885 3886 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 3887 3888 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 3889 drm_dbg_kms(&i915->drm, 3890 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 3891 str_enable_disable(tmp)); 3892 } 3893 3894 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 3895 { 3896 u8 dprx = 0; 3897 3898 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 3899 &dprx) != 1) 3900 return false; 3901 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 3902 } 3903 3904 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 3905 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 3906 { 3907 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, 3908 DP_DSC_RECEIVER_CAP_SIZE) < 0) { 3909 drm_err(aux->drm_dev, 3910 "Failed to read DPCD register 0x%x\n", 3911 DP_DSC_SUPPORT); 3912 return; 3913 } 3914 3915 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 3916 DP_DSC_RECEIVER_CAP_SIZE, 3917 dsc_dpcd); 3918 } 3919 3920 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) 3921 { 3922 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3923 3924 /* 3925 * Clear the cached register set to avoid using stale values 3926 * for the sinks that do not support DSC. 3927 */ 3928 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 3929 3930 /* Clear fec_capable to avoid using stale values */ 3931 connector->dp.fec_capability = 0; 3932 3933 if (dpcd_rev < DP_DPCD_REV_14) 3934 return; 3935 3936 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 3937 connector->dp.dsc_dpcd); 3938 3939 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 3940 &connector->dp.fec_capability) < 0) { 3941 drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); 3942 return; 3943 } 3944 3945 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", 3946 connector->dp.fec_capability); 3947 } 3948 3949 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 3950 { 3951 if (edp_dpcd_rev < DP_EDP_14) 3952 return; 3953 3954 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); 3955 } 3956 3957 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 3958 struct drm_display_mode *mode) 3959 { 3960 struct intel_dp *intel_dp = intel_attached_dp(connector); 3961 struct drm_i915_private *i915 = to_i915(connector->base.dev); 3962 int n = intel_dp->mso_link_count; 3963 int overlap = intel_dp->mso_pixel_overlap; 3964 3965 if (!mode || !n) 3966 return; 3967 3968 mode->hdisplay = (mode->hdisplay - overlap) * n; 3969 mode->hsync_start = (mode->hsync_start - overlap) * n; 3970 mode->hsync_end = (mode->hsync_end - overlap) * n; 3971 mode->htotal = (mode->htotal - overlap) * n; 3972 mode->clock *= n; 3973 3974 drm_mode_set_name(mode); 3975 3976 drm_dbg_kms(&i915->drm, 3977 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 3978 connector->base.base.id, connector->base.name, 3979 DRM_MODE_ARG(mode)); 3980 } 3981 3982 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 3983 { 3984 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3985 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3986 struct intel_connector *connector = intel_dp->attached_connector; 3987 3988 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 3989 /* 3990 * This is a big fat ugly hack. 3991 * 3992 * Some machines in UEFI boot mode provide us a VBT that has 18 3993 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3994 * unknown we fail to light up. Yet the same BIOS boots up with 3995 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3996 * max, not what it tells us to use. 3997 * 3998 * Note: This will still be broken if the eDP panel is not lit 3999 * up by the BIOS, and thus we can't get the mode at module 4000 * load. 4001 */ 4002 drm_dbg_kms(&dev_priv->drm, 4003 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4004 pipe_bpp, connector->panel.vbt.edp.bpp); 4005 connector->panel.vbt.edp.bpp = pipe_bpp; 4006 } 4007 } 4008 4009 static void intel_edp_mso_init(struct intel_dp *intel_dp) 4010 { 4011 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4012 struct intel_connector *connector = intel_dp->attached_connector; 4013 struct drm_display_info *info = &connector->base.display_info; 4014 u8 mso; 4015 4016 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 4017 return; 4018 4019 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 4020 drm_err(&i915->drm, "Failed to read MSO cap\n"); 4021 return; 4022 } 4023 4024 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 4025 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 4026 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 4027 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); 4028 mso = 0; 4029 } 4030 4031 if (mso) { 4032 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n", 4033 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 4034 info->mso_pixel_overlap); 4035 if (!HAS_MSO(i915)) { 4036 drm_err(&i915->drm, "No source MSO support, disabling\n"); 4037 mso = 0; 4038 } 4039 } 4040 4041 intel_dp->mso_link_count = mso; 4042 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 4043 } 4044 4045 static bool 4046 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 4047 { 4048 struct drm_i915_private *dev_priv = 4049 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 4050 4051 /* this function is meant to be called only once */ 4052 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4053 4054 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4055 return false; 4056 4057 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4058 drm_dp_is_branch(intel_dp->dpcd)); 4059 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4060 4061 /* 4062 * Read the eDP display control registers. 4063 * 4064 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4065 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4066 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4067 * method). The display control registers should read zero if they're 4068 * not supported anyway. 4069 */ 4070 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4071 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4072 sizeof(intel_dp->edp_dpcd)) { 4073 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", 4074 (int)sizeof(intel_dp->edp_dpcd), 4075 intel_dp->edp_dpcd); 4076 4077 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 4078 } 4079 4080 /* 4081 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4082 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4083 */ 4084 intel_psr_init_dpcd(intel_dp); 4085 4086 /* Clear the default sink rates */ 4087 intel_dp->num_sink_rates = 0; 4088 4089 /* Read the eDP 1.4+ supported link rates. */ 4090 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4091 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4092 int i; 4093 4094 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4095 sink_rates, sizeof(sink_rates)); 4096 4097 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4098 int val = le16_to_cpu(sink_rates[i]); 4099 4100 if (val == 0) 4101 break; 4102 4103 /* Value read multiplied by 200kHz gives the per-lane 4104 * link rate in kHz. The source rates are, however, 4105 * stored in terms of LS_Clk kHz. The full conversion 4106 * back to symbols is 4107 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4108 */ 4109 intel_dp->sink_rates[i] = (val * 200) / 10; 4110 } 4111 intel_dp->num_sink_rates = i; 4112 } 4113 4114 /* 4115 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4116 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4117 */ 4118 if (intel_dp->num_sink_rates) 4119 intel_dp->use_rate_select = true; 4120 else 4121 intel_dp_set_sink_rates(intel_dp); 4122 intel_dp_set_max_sink_lane_count(intel_dp); 4123 4124 /* Read the eDP DSC DPCD registers */ 4125 if (HAS_DSC(dev_priv)) 4126 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 4127 connector); 4128 4129 /* 4130 * If needed, program our source OUI so we can make various Intel-specific AUX services 4131 * available (such as HDR backlight controls) 4132 */ 4133 intel_edp_init_source_oui(intel_dp, true); 4134 4135 return true; 4136 } 4137 4138 static bool 4139 intel_dp_has_sink_count(struct intel_dp *intel_dp) 4140 { 4141 if (!intel_dp->attached_connector) 4142 return false; 4143 4144 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4145 intel_dp->dpcd, 4146 &intel_dp->desc); 4147 } 4148 4149 void intel_dp_update_sink_caps(struct intel_dp *intel_dp) 4150 { 4151 intel_dp_set_sink_rates(intel_dp); 4152 intel_dp_set_max_sink_lane_count(intel_dp); 4153 intel_dp_set_common_rates(intel_dp); 4154 } 4155 4156 static bool 4157 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4158 { 4159 int ret; 4160 4161 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 4162 return false; 4163 4164 /* 4165 * Don't clobber cached eDP rates. Also skip re-reading 4166 * the OUI/ID since we know it won't change. 4167 */ 4168 if (!intel_dp_is_edp(intel_dp)) { 4169 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4170 drm_dp_is_branch(intel_dp->dpcd)); 4171 4172 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4173 4174 intel_dp_update_sink_caps(intel_dp); 4175 } 4176 4177 if (intel_dp_has_sink_count(intel_dp)) { 4178 ret = drm_dp_read_sink_count(&intel_dp->aux); 4179 if (ret < 0) 4180 return false; 4181 4182 /* 4183 * Sink count can change between short pulse hpd hence 4184 * a member variable in intel_dp will track any changes 4185 * between short pulse interrupts. 4186 */ 4187 intel_dp->sink_count = ret; 4188 4189 /* 4190 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4191 * a dongle is present but no display. Unless we require to know 4192 * if a dongle is present or not, we don't need to update 4193 * downstream port information. So, an early return here saves 4194 * time from performing other operations which are not required. 4195 */ 4196 if (!intel_dp->sink_count) 4197 return false; 4198 } 4199 4200 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4201 intel_dp->downstream_ports) == 0; 4202 } 4203 4204 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) 4205 { 4206 if (mst_mode == DRM_DP_MST) 4207 return "MST"; 4208 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) 4209 return "SST w/ sideband messaging"; 4210 else 4211 return "SST"; 4212 } 4213 4214 static enum drm_dp_mst_mode 4215 intel_dp_mst_mode_choose(struct intel_dp *intel_dp, 4216 enum drm_dp_mst_mode sink_mst_mode) 4217 { 4218 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4219 4220 if (!i915->display.params.enable_dp_mst) 4221 return DRM_DP_SST; 4222 4223 if (!intel_dp_mst_source_support(intel_dp)) 4224 return DRM_DP_SST; 4225 4226 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && 4227 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) 4228 return DRM_DP_SST; 4229 4230 return sink_mst_mode; 4231 } 4232 4233 static enum drm_dp_mst_mode 4234 intel_dp_mst_detect(struct intel_dp *intel_dp) 4235 { 4236 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4237 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4238 enum drm_dp_mst_mode sink_mst_mode; 4239 enum drm_dp_mst_mode mst_detect; 4240 4241 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4242 4243 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); 4244 4245 drm_dbg_kms(&i915->drm, 4246 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", 4247 encoder->base.base.id, encoder->base.name, 4248 str_yes_no(intel_dp_mst_source_support(intel_dp)), 4249 intel_dp_mst_mode_str(sink_mst_mode), 4250 str_yes_no(i915->display.params.enable_dp_mst), 4251 intel_dp_mst_mode_str(mst_detect)); 4252 4253 return mst_detect; 4254 } 4255 4256 static void 4257 intel_dp_mst_configure(struct intel_dp *intel_dp) 4258 { 4259 if (!intel_dp_mst_source_support(intel_dp)) 4260 return; 4261 4262 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4263 4264 if (intel_dp->is_mst) 4265 intel_dp_mst_prepare_probe(intel_dp); 4266 4267 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4268 4269 /* Avoid stale info on the next detect cycle. */ 4270 intel_dp->mst_detect = DRM_DP_SST; 4271 } 4272 4273 static void 4274 intel_dp_mst_disconnect(struct intel_dp *intel_dp) 4275 { 4276 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4277 4278 if (!intel_dp->is_mst) 4279 return; 4280 4281 drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n", 4282 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4283 intel_dp->is_mst = false; 4284 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4285 } 4286 4287 static bool 4288 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 4289 { 4290 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 4291 } 4292 4293 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 4294 { 4295 int retry; 4296 4297 for (retry = 0; retry < 3; retry++) { 4298 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 4299 &esi[1], 3) == 3) 4300 return true; 4301 } 4302 4303 return false; 4304 } 4305 4306 bool 4307 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 4308 const struct drm_connector_state *conn_state) 4309 { 4310 /* 4311 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 4312 * of Color Encoding Format and Content Color Gamut], in order to 4313 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 4314 */ 4315 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 4316 return true; 4317 4318 switch (conn_state->colorspace) { 4319 case DRM_MODE_COLORIMETRY_SYCC_601: 4320 case DRM_MODE_COLORIMETRY_OPYCC_601: 4321 case DRM_MODE_COLORIMETRY_BT2020_YCC: 4322 case DRM_MODE_COLORIMETRY_BT2020_RGB: 4323 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 4324 return true; 4325 default: 4326 break; 4327 } 4328 4329 return false; 4330 } 4331 4332 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, 4333 struct dp_sdp *sdp, size_t size) 4334 { 4335 size_t length = sizeof(struct dp_sdp); 4336 4337 if (size < length) 4338 return -ENOSPC; 4339 4340 memset(sdp, 0, size); 4341 4342 /* Prepare AS (Adaptive Sync) SDP Header */ 4343 sdp->sdp_header.HB0 = 0; 4344 sdp->sdp_header.HB1 = as_sdp->sdp_type; 4345 sdp->sdp_header.HB2 = 0x02; 4346 sdp->sdp_header.HB3 = as_sdp->length; 4347 4348 /* Fill AS (Adaptive Sync) SDP Payload */ 4349 sdp->db[0] = as_sdp->mode; 4350 sdp->db[1] = as_sdp->vtotal & 0xFF; 4351 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; 4352 sdp->db[3] = as_sdp->target_rr & 0xFF; 4353 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; 4354 4355 if (as_sdp->target_rr_divider) 4356 sdp->db[4] |= 0x20; 4357 4358 return length; 4359 } 4360 4361 static ssize_t 4362 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915, 4363 const struct hdmi_drm_infoframe *drm_infoframe, 4364 struct dp_sdp *sdp, 4365 size_t size) 4366 { 4367 size_t length = sizeof(struct dp_sdp); 4368 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 4369 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 4370 ssize_t len; 4371 4372 if (size < length) 4373 return -ENOSPC; 4374 4375 memset(sdp, 0, size); 4376 4377 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 4378 if (len < 0) { 4379 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n"); 4380 return -ENOSPC; 4381 } 4382 4383 if (len != infoframe_size) { 4384 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n"); 4385 return -ENOSPC; 4386 } 4387 4388 /* 4389 * Set up the infoframe sdp packet for HDR static metadata. 4390 * Prepare VSC Header for SU as per DP 1.4a spec, 4391 * Table 2-100 and Table 2-101 4392 */ 4393 4394 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 4395 sdp->sdp_header.HB0 = 0; 4396 /* 4397 * Packet Type 80h + Non-audio INFOFRAME Type value 4398 * HDMI_INFOFRAME_TYPE_DRM: 0x87 4399 * - 80h + Non-audio INFOFRAME Type value 4400 * - InfoFrame Type: 0x07 4401 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 4402 */ 4403 sdp->sdp_header.HB1 = drm_infoframe->type; 4404 /* 4405 * Least Significant Eight Bits of (Data Byte Count – 1) 4406 * infoframe_size - 1 4407 */ 4408 sdp->sdp_header.HB2 = 0x1D; 4409 /* INFOFRAME SDP Version Number */ 4410 sdp->sdp_header.HB3 = (0x13 << 2); 4411 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4412 sdp->db[0] = drm_infoframe->version; 4413 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4414 sdp->db[1] = drm_infoframe->length; 4415 /* 4416 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 4417 * HDMI_INFOFRAME_HEADER_SIZE 4418 */ 4419 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 4420 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 4421 HDMI_DRM_INFOFRAME_SIZE); 4422 4423 /* 4424 * Size of DP infoframe sdp packet for HDR static metadata consists of 4425 * - DP SDP Header(struct dp_sdp_header): 4 bytes 4426 * - Two Data Blocks: 2 bytes 4427 * CTA Header Byte2 (INFOFRAME Version Number) 4428 * CTA Header Byte3 (Length of INFOFRAME) 4429 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 4430 * 4431 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 4432 * infoframe size. But GEN11+ has larger than that size, write_infoframe 4433 * will pad rest of the size. 4434 */ 4435 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 4436 } 4437 4438 static void intel_write_dp_sdp(struct intel_encoder *encoder, 4439 const struct intel_crtc_state *crtc_state, 4440 unsigned int type) 4441 { 4442 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4443 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4444 struct dp_sdp sdp = {}; 4445 ssize_t len; 4446 4447 if ((crtc_state->infoframes.enable & 4448 intel_hdmi_infoframe_enable(type)) == 0) 4449 return; 4450 4451 switch (type) { 4452 case DP_SDP_VSC: 4453 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp); 4454 break; 4455 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4456 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv, 4457 &crtc_state->infoframes.drm.drm, 4458 &sdp, sizeof(sdp)); 4459 break; 4460 case DP_SDP_ADAPTIVE_SYNC: 4461 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, 4462 sizeof(sdp)); 4463 break; 4464 default: 4465 MISSING_CASE(type); 4466 return; 4467 } 4468 4469 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 4470 return; 4471 4472 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 4473 } 4474 4475 void intel_dp_set_infoframes(struct intel_encoder *encoder, 4476 bool enable, 4477 const struct intel_crtc_state *crtc_state, 4478 const struct drm_connector_state *conn_state) 4479 { 4480 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4481 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv, 4482 crtc_state->cpu_transcoder); 4483 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 4484 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 4485 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 4486 4487 if (HAS_AS_SDP(dev_priv)) 4488 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; 4489 4490 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; 4491 4492 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ 4493 if (!enable && HAS_DSC(dev_priv)) 4494 val &= ~VDIP_ENABLE_PPS; 4495 4496 /* 4497 * This routine disables VSC DIP if the function is called 4498 * to disable SDP or if it does not have PSR 4499 */ 4500 if (!enable || !crtc_state->has_psr) 4501 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4502 4503 intel_de_write(dev_priv, reg, val); 4504 intel_de_posting_read(dev_priv, reg); 4505 4506 if (!enable) 4507 return; 4508 4509 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 4510 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); 4511 4512 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 4513 } 4514 4515 static 4516 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, 4517 const void *buffer, size_t size) 4518 { 4519 const struct dp_sdp *sdp = buffer; 4520 4521 if (size < sizeof(struct dp_sdp)) 4522 return -EINVAL; 4523 4524 memset(as_sdp, 0, sizeof(*as_sdp)); 4525 4526 if (sdp->sdp_header.HB0 != 0) 4527 return -EINVAL; 4528 4529 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) 4530 return -EINVAL; 4531 4532 if (sdp->sdp_header.HB2 != 0x02) 4533 return -EINVAL; 4534 4535 if ((sdp->sdp_header.HB3 & 0x3F) != 9) 4536 return -EINVAL; 4537 4538 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; 4539 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; 4540 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; 4541 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); 4542 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; 4543 4544 return 0; 4545 } 4546 4547 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 4548 const void *buffer, size_t size) 4549 { 4550 const struct dp_sdp *sdp = buffer; 4551 4552 if (size < sizeof(struct dp_sdp)) 4553 return -EINVAL; 4554 4555 memset(vsc, 0, sizeof(*vsc)); 4556 4557 if (sdp->sdp_header.HB0 != 0) 4558 return -EINVAL; 4559 4560 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 4561 return -EINVAL; 4562 4563 vsc->sdp_type = sdp->sdp_header.HB1; 4564 vsc->revision = sdp->sdp_header.HB2; 4565 vsc->length = sdp->sdp_header.HB3; 4566 4567 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 4568 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || 4569 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { 4570 /* 4571 * - HB2 = 0x2, HB3 = 0x8 4572 * VSC SDP supporting 3D stereo + PSR 4573 * - HB2 = 0x4, HB3 = 0xe 4574 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 4575 * first scan line of the SU region (applies to eDP v1.4b 4576 * and higher). 4577 * - HB2 = 0x6, HB3 = 0x10 4578 * VSC SDP supporting 3D stereo + Panel Replay. 4579 */ 4580 return 0; 4581 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 4582 /* 4583 * - HB2 = 0x5, HB3 = 0x13 4584 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 4585 * Format. 4586 */ 4587 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 4588 vsc->colorimetry = sdp->db[16] & 0xf; 4589 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 4590 4591 switch (sdp->db[17] & 0x7) { 4592 case 0x0: 4593 vsc->bpc = 6; 4594 break; 4595 case 0x1: 4596 vsc->bpc = 8; 4597 break; 4598 case 0x2: 4599 vsc->bpc = 10; 4600 break; 4601 case 0x3: 4602 vsc->bpc = 12; 4603 break; 4604 case 0x4: 4605 vsc->bpc = 16; 4606 break; 4607 default: 4608 MISSING_CASE(sdp->db[17] & 0x7); 4609 return -EINVAL; 4610 } 4611 4612 vsc->content_type = sdp->db[18] & 0x7; 4613 } else { 4614 return -EINVAL; 4615 } 4616 4617 return 0; 4618 } 4619 4620 static void 4621 intel_read_dp_as_sdp(struct intel_encoder *encoder, 4622 struct intel_crtc_state *crtc_state, 4623 struct drm_dp_as_sdp *as_sdp) 4624 { 4625 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4626 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4627 unsigned int type = DP_SDP_ADAPTIVE_SYNC; 4628 struct dp_sdp sdp = {}; 4629 int ret; 4630 4631 if ((crtc_state->infoframes.enable & 4632 intel_hdmi_infoframe_enable(type)) == 0) 4633 return; 4634 4635 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4636 sizeof(sdp)); 4637 4638 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); 4639 if (ret) 4640 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n"); 4641 } 4642 4643 static int 4644 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 4645 const void *buffer, size_t size) 4646 { 4647 int ret; 4648 4649 const struct dp_sdp *sdp = buffer; 4650 4651 if (size < sizeof(struct dp_sdp)) 4652 return -EINVAL; 4653 4654 if (sdp->sdp_header.HB0 != 0) 4655 return -EINVAL; 4656 4657 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 4658 return -EINVAL; 4659 4660 /* 4661 * Least Significant Eight Bits of (Data Byte Count – 1) 4662 * 1Dh (i.e., Data Byte Count = 30 bytes). 4663 */ 4664 if (sdp->sdp_header.HB2 != 0x1D) 4665 return -EINVAL; 4666 4667 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 4668 if ((sdp->sdp_header.HB3 & 0x3) != 0) 4669 return -EINVAL; 4670 4671 /* INFOFRAME SDP Version Number */ 4672 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 4673 return -EINVAL; 4674 4675 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4676 if (sdp->db[0] != 1) 4677 return -EINVAL; 4678 4679 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4680 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 4681 return -EINVAL; 4682 4683 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 4684 HDMI_DRM_INFOFRAME_SIZE); 4685 4686 return ret; 4687 } 4688 4689 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 4690 struct intel_crtc_state *crtc_state, 4691 struct drm_dp_vsc_sdp *vsc) 4692 { 4693 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4694 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4695 unsigned int type = DP_SDP_VSC; 4696 struct dp_sdp sdp = {}; 4697 int ret; 4698 4699 if ((crtc_state->infoframes.enable & 4700 intel_hdmi_infoframe_enable(type)) == 0) 4701 return; 4702 4703 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 4704 4705 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 4706 4707 if (ret) 4708 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); 4709 } 4710 4711 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 4712 struct intel_crtc_state *crtc_state, 4713 struct hdmi_drm_infoframe *drm_infoframe) 4714 { 4715 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4716 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4717 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 4718 struct dp_sdp sdp = {}; 4719 int ret; 4720 4721 if ((crtc_state->infoframes.enable & 4722 intel_hdmi_infoframe_enable(type)) == 0) 4723 return; 4724 4725 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 4726 sizeof(sdp)); 4727 4728 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 4729 sizeof(sdp)); 4730 4731 if (ret) 4732 drm_dbg_kms(&dev_priv->drm, 4733 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 4734 } 4735 4736 void intel_read_dp_sdp(struct intel_encoder *encoder, 4737 struct intel_crtc_state *crtc_state, 4738 unsigned int type) 4739 { 4740 switch (type) { 4741 case DP_SDP_VSC: 4742 intel_read_dp_vsc_sdp(encoder, crtc_state, 4743 &crtc_state->infoframes.vsc); 4744 break; 4745 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4746 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 4747 &crtc_state->infoframes.drm.drm); 4748 break; 4749 case DP_SDP_ADAPTIVE_SYNC: 4750 intel_read_dp_as_sdp(encoder, crtc_state, 4751 &crtc_state->infoframes.as_sdp); 4752 break; 4753 default: 4754 MISSING_CASE(type); 4755 break; 4756 } 4757 } 4758 4759 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) 4760 { 4761 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4762 int status = 0; 4763 int test_link_rate; 4764 u8 test_lane_count, test_link_bw; 4765 /* (DP CTS 1.2) 4766 * 4.3.1.11 4767 */ 4768 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ 4769 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, 4770 &test_lane_count); 4771 4772 if (status <= 0) { 4773 drm_dbg_kms(&i915->drm, "Lane count read failed\n"); 4774 return DP_TEST_NAK; 4775 } 4776 test_lane_count &= DP_MAX_LANE_COUNT_MASK; 4777 4778 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, 4779 &test_link_bw); 4780 if (status <= 0) { 4781 drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); 4782 return DP_TEST_NAK; 4783 } 4784 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); 4785 4786 /* Validate the requested link rate and lane count */ 4787 if (!intel_dp_link_params_valid(intel_dp, test_link_rate, 4788 test_lane_count)) 4789 return DP_TEST_NAK; 4790 4791 intel_dp->compliance.test_lane_count = test_lane_count; 4792 intel_dp->compliance.test_link_rate = test_link_rate; 4793 4794 return DP_TEST_ACK; 4795 } 4796 4797 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 4798 { 4799 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4800 u8 test_pattern; 4801 u8 test_misc; 4802 __be16 h_width, v_height; 4803 int status = 0; 4804 4805 /* Read the TEST_PATTERN (DP CTS 3.1.5) */ 4806 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, 4807 &test_pattern); 4808 if (status <= 0) { 4809 drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); 4810 return DP_TEST_NAK; 4811 } 4812 if (test_pattern != DP_COLOR_RAMP) 4813 return DP_TEST_NAK; 4814 4815 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, 4816 &h_width, 2); 4817 if (status <= 0) { 4818 drm_dbg_kms(&i915->drm, "H Width read failed\n"); 4819 return DP_TEST_NAK; 4820 } 4821 4822 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, 4823 &v_height, 2); 4824 if (status <= 0) { 4825 drm_dbg_kms(&i915->drm, "V Height read failed\n"); 4826 return DP_TEST_NAK; 4827 } 4828 4829 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, 4830 &test_misc); 4831 if (status <= 0) { 4832 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); 4833 return DP_TEST_NAK; 4834 } 4835 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) 4836 return DP_TEST_NAK; 4837 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) 4838 return DP_TEST_NAK; 4839 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { 4840 case DP_TEST_BIT_DEPTH_6: 4841 intel_dp->compliance.test_data.bpc = 6; 4842 break; 4843 case DP_TEST_BIT_DEPTH_8: 4844 intel_dp->compliance.test_data.bpc = 8; 4845 break; 4846 default: 4847 return DP_TEST_NAK; 4848 } 4849 4850 intel_dp->compliance.test_data.video_pattern = test_pattern; 4851 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); 4852 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); 4853 /* Set test active flag here so userspace doesn't interrupt things */ 4854 intel_dp->compliance.test_active = true; 4855 4856 return DP_TEST_ACK; 4857 } 4858 4859 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) 4860 { 4861 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4862 u8 test_result = DP_TEST_ACK; 4863 struct intel_connector *intel_connector = intel_dp->attached_connector; 4864 struct drm_connector *connector = &intel_connector->base; 4865 4866 if (intel_connector->detect_edid == NULL || 4867 connector->edid_corrupt || 4868 intel_dp->aux.i2c_defer_count > 6) { 4869 /* Check EDID read for NACKs, DEFERs and corruption 4870 * (DP CTS 1.2 Core r1.1) 4871 * 4.2.2.4 : Failed EDID read, I2C_NAK 4872 * 4.2.2.5 : Failed EDID read, I2C_DEFER 4873 * 4.2.2.6 : EDID corruption detected 4874 * Use failsafe mode for all cases 4875 */ 4876 if (intel_dp->aux.i2c_nack_count > 0 || 4877 intel_dp->aux.i2c_defer_count > 0) 4878 drm_dbg_kms(&i915->drm, 4879 "EDID read had %d NACKs, %d DEFERs\n", 4880 intel_dp->aux.i2c_nack_count, 4881 intel_dp->aux.i2c_defer_count); 4882 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; 4883 } else { 4884 /* FIXME: Get rid of drm_edid_raw() */ 4885 const struct edid *block = drm_edid_raw(intel_connector->detect_edid); 4886 4887 /* We have to write the checksum of the last block read */ 4888 block += block->extensions; 4889 4890 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, 4891 block->checksum) <= 0) 4892 drm_dbg_kms(&i915->drm, 4893 "Failed to write EDID checksum\n"); 4894 4895 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 4896 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; 4897 } 4898 4899 /* Set test active flag here so userspace doesn't interrupt things */ 4900 intel_dp->compliance.test_active = true; 4901 4902 return test_result; 4903 } 4904 4905 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 4906 const struct intel_crtc_state *crtc_state) 4907 { 4908 struct drm_i915_private *dev_priv = 4909 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 4910 struct drm_dp_phy_test_params *data = 4911 &intel_dp->compliance.test_data.phytest; 4912 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4913 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4914 enum pipe pipe = crtc->pipe; 4915 u32 pattern_val; 4916 4917 switch (data->phy_pattern) { 4918 case DP_LINK_QUAL_PATTERN_DISABLE: 4919 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); 4920 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 4921 if (DISPLAY_VER(dev_priv) >= 10) 4922 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 4923 DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, 4924 DP_TP_CTL_LINK_TRAIN_NORMAL); 4925 break; 4926 case DP_LINK_QUAL_PATTERN_D10_2: 4927 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); 4928 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4929 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); 4930 break; 4931 case DP_LINK_QUAL_PATTERN_ERROR_RATE: 4932 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); 4933 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4934 DDI_DP_COMP_CTL_ENABLE | 4935 DDI_DP_COMP_CTL_SCRAMBLED_0); 4936 break; 4937 case DP_LINK_QUAL_PATTERN_PRBS7: 4938 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); 4939 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4940 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); 4941 break; 4942 case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: 4943 /* 4944 * FIXME: Ideally pattern should come from DPCD 0x250. As 4945 * current firmware of DPR-100 could not set it, so hardcoding 4946 * now for complaince test. 4947 */ 4948 drm_dbg_kms(&dev_priv->drm, 4949 "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); 4950 pattern_val = 0x3e0f83e0; 4951 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); 4952 pattern_val = 0x0f83e0f8; 4953 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); 4954 pattern_val = 0x0000f83e; 4955 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); 4956 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4957 DDI_DP_COMP_CTL_ENABLE | 4958 DDI_DP_COMP_CTL_CUSTOM80); 4959 break; 4960 case DP_LINK_QUAL_PATTERN_CP2520_PAT_1: 4961 /* 4962 * FIXME: Ideally pattern should come from DPCD 0x24A. As 4963 * current firmware of DPR-100 could not set it, so hardcoding 4964 * now for complaince test. 4965 */ 4966 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n"); 4967 pattern_val = 0xFB; 4968 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4969 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | 4970 pattern_val); 4971 break; 4972 case DP_LINK_QUAL_PATTERN_CP2520_PAT_3: 4973 if (DISPLAY_VER(dev_priv) < 10) { 4974 drm_warn(&dev_priv->drm, "Platform does not support TPS4\n"); 4975 break; 4976 } 4977 drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n"); 4978 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 4979 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 4980 DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, 4981 DP_TP_CTL_TRAIN_PAT4_SEL_TP4A | DP_TP_CTL_LINK_TRAIN_PAT4); 4982 break; 4983 default: 4984 drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n"); 4985 } 4986 } 4987 4988 static void intel_dp_process_phy_request(struct intel_dp *intel_dp, 4989 const struct intel_crtc_state *crtc_state) 4990 { 4991 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4992 struct drm_dp_phy_test_params *data = 4993 &intel_dp->compliance.test_data.phytest; 4994 u8 link_status[DP_LINK_STATUS_SIZE]; 4995 4996 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 4997 link_status) < 0) { 4998 drm_dbg_kms(&i915->drm, "failed to get link status\n"); 4999 return; 5000 } 5001 5002 /* retrieve vswing & pre-emphasis setting */ 5003 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, 5004 link_status); 5005 5006 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX); 5007 5008 intel_dp_phy_pattern_update(intel_dp, crtc_state); 5009 5010 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 5011 intel_dp->train_set, crtc_state->lane_count); 5012 5013 drm_dp_set_phy_test_pattern(&intel_dp->aux, data, 5014 intel_dp->dpcd[DP_DPCD_REV]); 5015 } 5016 5017 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 5018 { 5019 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5020 struct drm_dp_phy_test_params *data = 5021 &intel_dp->compliance.test_data.phytest; 5022 5023 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { 5024 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n"); 5025 return DP_TEST_NAK; 5026 } 5027 5028 /* Set test active flag here so userspace doesn't interrupt things */ 5029 intel_dp->compliance.test_active = true; 5030 5031 return DP_TEST_ACK; 5032 } 5033 5034 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 5035 { 5036 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5037 u8 response = DP_TEST_NAK; 5038 u8 request = 0; 5039 int status; 5040 5041 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); 5042 if (status <= 0) { 5043 drm_dbg_kms(&i915->drm, 5044 "Could not read test request from sink\n"); 5045 goto update_status; 5046 } 5047 5048 switch (request) { 5049 case DP_TEST_LINK_TRAINING: 5050 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); 5051 response = intel_dp_autotest_link_training(intel_dp); 5052 break; 5053 case DP_TEST_LINK_VIDEO_PATTERN: 5054 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); 5055 response = intel_dp_autotest_video_pattern(intel_dp); 5056 break; 5057 case DP_TEST_LINK_EDID_READ: 5058 drm_dbg_kms(&i915->drm, "EDID test requested\n"); 5059 response = intel_dp_autotest_edid(intel_dp); 5060 break; 5061 case DP_TEST_LINK_PHY_TEST_PATTERN: 5062 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); 5063 response = intel_dp_autotest_phy_pattern(intel_dp); 5064 break; 5065 default: 5066 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", 5067 request); 5068 break; 5069 } 5070 5071 if (response & DP_TEST_ACK) 5072 intel_dp->compliance.test_type = request; 5073 5074 update_status: 5075 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); 5076 if (status <= 0) 5077 drm_dbg_kms(&i915->drm, 5078 "Could not write test response to sink\n"); 5079 } 5080 5081 static bool intel_dp_link_ok(struct intel_dp *intel_dp, 5082 u8 link_status[DP_LINK_STATUS_SIZE]) 5083 { 5084 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5085 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 5086 bool uhbr = intel_dp->link_rate >= 1000000; 5087 bool ok; 5088 5089 if (uhbr) 5090 ok = drm_dp_128b132b_lane_channel_eq_done(link_status, 5091 intel_dp->lane_count); 5092 else 5093 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 5094 5095 if (ok) 5096 return true; 5097 5098 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 5099 drm_dbg_kms(&i915->drm, 5100 "[ENCODER:%d:%s] %s link not ok, retraining\n", 5101 encoder->base.base.id, encoder->base.name, 5102 uhbr ? "128b/132b" : "8b/10b"); 5103 5104 return false; 5105 } 5106 5107 static void 5108 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 5109 { 5110 bool handled = false; 5111 5112 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled); 5113 5114 if (esi[1] & DP_CP_IRQ) { 5115 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5116 ack[1] |= DP_CP_IRQ; 5117 } 5118 } 5119 5120 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) 5121 { 5122 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5123 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 5124 u8 link_status[DP_LINK_STATUS_SIZE] = {}; 5125 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; 5126 5127 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, 5128 esi_link_status_size) != esi_link_status_size) { 5129 drm_err(&i915->drm, 5130 "[ENCODER:%d:%s] Failed to read link status\n", 5131 encoder->base.base.id, encoder->base.name); 5132 return false; 5133 } 5134 5135 return intel_dp_link_ok(intel_dp, link_status); 5136 } 5137 5138 /** 5139 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 5140 * @intel_dp: Intel DP struct 5141 * 5142 * Read any pending MST interrupts, call MST core to handle these and ack the 5143 * interrupts. Check if the main and AUX link state is ok. 5144 * 5145 * Returns: 5146 * - %true if pending interrupts were serviced (or no interrupts were 5147 * pending) w/o detecting an error condition. 5148 * - %false if an error condition - like AUX failure or a loss of link - is 5149 * detected, or another condition - like a DP tunnel BW state change - needs 5150 * servicing from the hotplug work. 5151 */ 5152 static bool 5153 intel_dp_check_mst_status(struct intel_dp *intel_dp) 5154 { 5155 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5156 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5157 struct intel_encoder *encoder = &dig_port->base; 5158 bool link_ok = true; 5159 bool reprobe_needed = false; 5160 5161 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); 5162 5163 for (;;) { 5164 u8 esi[4] = {}; 5165 u8 ack[4] = {}; 5166 5167 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 5168 drm_dbg_kms(&i915->drm, 5169 "failed to get ESI - device may have failed\n"); 5170 link_ok = false; 5171 5172 break; 5173 } 5174 5175 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi); 5176 5177 if (intel_dp->active_mst_links > 0 && link_ok && 5178 esi[3] & LINK_STATUS_CHANGED) { 5179 if (!intel_dp_mst_link_status(intel_dp)) 5180 link_ok = false; 5181 ack[3] |= LINK_STATUS_CHANGED; 5182 } 5183 5184 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 5185 5186 if (esi[3] & DP_TUNNELING_IRQ) { 5187 if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr, 5188 &intel_dp->aux)) 5189 reprobe_needed = true; 5190 ack[3] |= DP_TUNNELING_IRQ; 5191 } 5192 5193 if (mem_is_zero(ack, sizeof(ack))) 5194 break; 5195 5196 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) 5197 drm_dbg_kms(&i915->drm, "Failed to ack ESI\n"); 5198 5199 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 5200 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); 5201 } 5202 5203 if (!link_ok || intel_dp->link.force_retrain) 5204 intel_encoder_link_check_queue_work(encoder, 0); 5205 5206 return !reprobe_needed; 5207 } 5208 5209 static void 5210 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 5211 { 5212 bool is_active; 5213 u8 buf = 0; 5214 5215 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 5216 if (intel_dp->frl.is_trained && !is_active) { 5217 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 5218 return; 5219 5220 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 5221 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 5222 return; 5223 5224 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 5225 5226 intel_dp->frl.is_trained = false; 5227 5228 /* Restart FRL training or fall back to TMDS mode */ 5229 intel_dp_check_frl_training(intel_dp); 5230 } 5231 } 5232 5233 static bool 5234 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 5235 { 5236 u8 link_status[DP_LINK_STATUS_SIZE]; 5237 5238 if (!intel_dp->link_trained) 5239 return false; 5240 5241 /* 5242 * While PSR source HW is enabled, it will control main-link sending 5243 * frames, enabling and disabling it so trying to do a retrain will fail 5244 * as the link would or not be on or it could mix training patterns 5245 * and frame data at the same time causing retrain to fail. 5246 * Also when exiting PSR, HW will retrain the link anyways fixing 5247 * any link status error. 5248 */ 5249 if (intel_psr_enabled(intel_dp)) 5250 return false; 5251 5252 if (intel_dp->link.force_retrain) 5253 return true; 5254 5255 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5256 link_status) < 0) 5257 return false; 5258 5259 /* 5260 * Validate the cached values of intel_dp->link_rate and 5261 * intel_dp->lane_count before attempting to retrain. 5262 * 5263 * FIXME would be nice to user the crtc state here, but since 5264 * we need to call this from the short HPD handler that seems 5265 * a bit hard. 5266 */ 5267 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 5268 intel_dp->lane_count)) 5269 return false; 5270 5271 if (intel_dp->link.retrain_disabled) 5272 return false; 5273 5274 if (intel_dp->link.seq_train_failures) 5275 return true; 5276 5277 /* Retrain if link not ok */ 5278 return !intel_dp_link_ok(intel_dp, link_status); 5279 } 5280 5281 static bool intel_dp_has_connector(struct intel_dp *intel_dp, 5282 const struct drm_connector_state *conn_state) 5283 { 5284 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5285 struct intel_encoder *encoder; 5286 enum pipe pipe; 5287 5288 if (!conn_state->best_encoder) 5289 return false; 5290 5291 /* SST */ 5292 encoder = &dp_to_dig_port(intel_dp)->base; 5293 if (conn_state->best_encoder == &encoder->base) 5294 return true; 5295 5296 /* MST */ 5297 for_each_pipe(i915, pipe) { 5298 encoder = &intel_dp->mst_encoders[pipe]->base; 5299 if (conn_state->best_encoder == &encoder->base) 5300 return true; 5301 } 5302 5303 return false; 5304 } 5305 5306 int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 5307 struct drm_modeset_acquire_ctx *ctx, 5308 u8 *pipe_mask) 5309 { 5310 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5311 struct drm_connector_list_iter conn_iter; 5312 struct intel_connector *connector; 5313 int ret = 0; 5314 5315 *pipe_mask = 0; 5316 5317 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 5318 for_each_intel_connector_iter(connector, &conn_iter) { 5319 struct drm_connector_state *conn_state = 5320 connector->base.state; 5321 struct intel_crtc_state *crtc_state; 5322 struct intel_crtc *crtc; 5323 5324 if (!intel_dp_has_connector(intel_dp, conn_state)) 5325 continue; 5326 5327 crtc = to_intel_crtc(conn_state->crtc); 5328 if (!crtc) 5329 continue; 5330 5331 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5332 if (ret) 5333 break; 5334 5335 crtc_state = to_intel_crtc_state(crtc->base.state); 5336 5337 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 5338 5339 if (!crtc_state->hw.active) 5340 continue; 5341 5342 if (conn_state->commit) 5343 drm_WARN_ON(&i915->drm, 5344 !wait_for_completion_timeout(&conn_state->commit->hw_done, 5345 msecs_to_jiffies(5000))); 5346 5347 *pipe_mask |= BIT(crtc->pipe); 5348 } 5349 drm_connector_list_iter_end(&conn_iter); 5350 5351 return ret; 5352 } 5353 5354 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 5355 { 5356 struct intel_connector *connector = intel_dp->attached_connector; 5357 5358 return connector->base.status == connector_status_connected || 5359 intel_dp->is_mst; 5360 } 5361 5362 static int intel_dp_retrain_link(struct intel_encoder *encoder, 5363 struct drm_modeset_acquire_ctx *ctx) 5364 { 5365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5366 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5367 u8 pipe_mask; 5368 int ret; 5369 5370 if (!intel_dp_is_connected(intel_dp)) 5371 return 0; 5372 5373 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 5374 ctx); 5375 if (ret) 5376 return ret; 5377 5378 if (!intel_dp_needs_link_retrain(intel_dp)) 5379 return 0; 5380 5381 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); 5382 if (ret) 5383 return ret; 5384 5385 if (pipe_mask == 0) 5386 return 0; 5387 5388 if (!intel_dp_needs_link_retrain(intel_dp)) 5389 return 0; 5390 5391 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n", 5392 encoder->base.base.id, encoder->base.name, 5393 str_yes_no(intel_dp->link.force_retrain)); 5394 5395 ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); 5396 if (ret == -EDEADLK) 5397 return ret; 5398 5399 intel_dp->link.force_retrain = false; 5400 5401 if (ret) 5402 drm_dbg_kms(&dev_priv->drm, 5403 "[ENCODER:%d:%s] link retraining failed: %pe\n", 5404 encoder->base.base.id, encoder->base.name, 5405 ERR_PTR(ret)); 5406 5407 return ret; 5408 } 5409 5410 void intel_dp_link_check(struct intel_encoder *encoder) 5411 { 5412 struct drm_modeset_acquire_ctx ctx; 5413 int ret; 5414 5415 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 5416 ret = intel_dp_retrain_link(encoder, &ctx); 5417 } 5418 5419 void intel_dp_check_link_state(struct intel_dp *intel_dp) 5420 { 5421 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5422 struct intel_encoder *encoder = &dig_port->base; 5423 5424 if (!intel_dp_is_connected(intel_dp)) 5425 return; 5426 5427 if (!intel_dp_needs_link_retrain(intel_dp)) 5428 return; 5429 5430 intel_encoder_link_check_queue_work(encoder, 0); 5431 } 5432 5433 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, 5434 struct drm_modeset_acquire_ctx *ctx, 5435 u8 *pipe_mask) 5436 { 5437 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5438 struct drm_connector_list_iter conn_iter; 5439 struct intel_connector *connector; 5440 int ret = 0; 5441 5442 *pipe_mask = 0; 5443 5444 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 5445 for_each_intel_connector_iter(connector, &conn_iter) { 5446 struct drm_connector_state *conn_state = 5447 connector->base.state; 5448 struct intel_crtc_state *crtc_state; 5449 struct intel_crtc *crtc; 5450 5451 if (!intel_dp_has_connector(intel_dp, conn_state)) 5452 continue; 5453 5454 crtc = to_intel_crtc(conn_state->crtc); 5455 if (!crtc) 5456 continue; 5457 5458 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5459 if (ret) 5460 break; 5461 5462 crtc_state = to_intel_crtc_state(crtc->base.state); 5463 5464 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 5465 5466 if (!crtc_state->hw.active) 5467 continue; 5468 5469 if (conn_state->commit && 5470 !try_wait_for_completion(&conn_state->commit->hw_done)) 5471 continue; 5472 5473 *pipe_mask |= BIT(crtc->pipe); 5474 } 5475 drm_connector_list_iter_end(&conn_iter); 5476 5477 return ret; 5478 } 5479 5480 static int intel_dp_do_phy_test(struct intel_encoder *encoder, 5481 struct drm_modeset_acquire_ctx *ctx) 5482 { 5483 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5484 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5485 struct intel_crtc *crtc; 5486 u8 pipe_mask; 5487 int ret; 5488 5489 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 5490 ctx); 5491 if (ret) 5492 return ret; 5493 5494 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask); 5495 if (ret) 5496 return ret; 5497 5498 if (pipe_mask == 0) 5499 return 0; 5500 5501 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", 5502 encoder->base.base.id, encoder->base.name); 5503 5504 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { 5505 const struct intel_crtc_state *crtc_state = 5506 to_intel_crtc_state(crtc->base.state); 5507 5508 /* test on the MST master transcoder */ 5509 if (DISPLAY_VER(dev_priv) >= 12 && 5510 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 5511 !intel_dp_mst_is_master_trans(crtc_state)) 5512 continue; 5513 5514 intel_dp_process_phy_request(intel_dp, crtc_state); 5515 break; 5516 } 5517 5518 return 0; 5519 } 5520 5521 void intel_dp_phy_test(struct intel_encoder *encoder) 5522 { 5523 struct drm_modeset_acquire_ctx ctx; 5524 int ret; 5525 5526 drm_modeset_acquire_init(&ctx, 0); 5527 5528 for (;;) { 5529 ret = intel_dp_do_phy_test(encoder, &ctx); 5530 5531 if (ret == -EDEADLK) { 5532 drm_modeset_backoff(&ctx); 5533 continue; 5534 } 5535 5536 break; 5537 } 5538 5539 drm_modeset_drop_locks(&ctx); 5540 drm_modeset_acquire_fini(&ctx); 5541 drm_WARN(encoder->base.dev, ret, 5542 "Acquiring modeset locks failed with %i\n", ret); 5543 } 5544 5545 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 5546 { 5547 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5548 u8 val; 5549 5550 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5551 return; 5552 5553 if (drm_dp_dpcd_readb(&intel_dp->aux, 5554 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 5555 return; 5556 5557 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 5558 5559 if (val & DP_AUTOMATED_TEST_REQUEST) 5560 intel_dp_handle_test_request(intel_dp); 5561 5562 if (val & DP_CP_IRQ) 5563 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5564 5565 if (val & DP_SINK_SPECIFIC_IRQ) 5566 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); 5567 } 5568 5569 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 5570 { 5571 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5572 bool reprobe_needed = false; 5573 u8 val; 5574 5575 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5576 return false; 5577 5578 if (drm_dp_dpcd_readb(&intel_dp->aux, 5579 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 5580 return false; 5581 5582 if ((val & DP_TUNNELING_IRQ) && 5583 drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr, 5584 &intel_dp->aux)) 5585 reprobe_needed = true; 5586 5587 if (drm_dp_dpcd_writeb(&intel_dp->aux, 5588 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 5589 return reprobe_needed; 5590 5591 if (val & HDMI_LINK_STATUS_CHANGED) 5592 intel_dp_handle_hdmi_link_status_change(intel_dp); 5593 5594 return reprobe_needed; 5595 } 5596 5597 /* 5598 * According to DP spec 5599 * 5.1.2: 5600 * 1. Read DPCD 5601 * 2. Configure link according to Receiver Capabilities 5602 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5603 * 4. Check link status on receipt of hot-plug interrupt 5604 * 5605 * intel_dp_short_pulse - handles short pulse interrupts 5606 * when full detection is not required. 5607 * Returns %true if short pulse is handled and full detection 5608 * is NOT required and %false otherwise. 5609 */ 5610 static bool 5611 intel_dp_short_pulse(struct intel_dp *intel_dp) 5612 { 5613 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 5614 u8 old_sink_count = intel_dp->sink_count; 5615 bool reprobe_needed = false; 5616 bool ret; 5617 5618 /* 5619 * Clearing compliance test variables to allow capturing 5620 * of values for next automated test request. 5621 */ 5622 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 5623 5624 /* 5625 * Now read the DPCD to see if it's actually running 5626 * If the current value of sink count doesn't match with 5627 * the value that was stored earlier or dpcd read failed 5628 * we need to do full detection 5629 */ 5630 ret = intel_dp_get_dpcd(intel_dp); 5631 5632 if ((old_sink_count != intel_dp->sink_count) || !ret) { 5633 /* No need to proceed if we are going to do full detect */ 5634 return false; 5635 } 5636 5637 intel_dp_check_device_service_irq(intel_dp); 5638 reprobe_needed = intel_dp_check_link_service_irq(intel_dp); 5639 5640 /* Handle CEC interrupts, if any */ 5641 drm_dp_cec_irq(&intel_dp->aux); 5642 5643 intel_dp_check_link_state(intel_dp); 5644 5645 intel_psr_short_pulse(intel_dp); 5646 5647 switch (intel_dp->compliance.test_type) { 5648 case DP_TEST_LINK_TRAINING: 5649 drm_dbg_kms(&dev_priv->drm, 5650 "Link Training Compliance Test requested\n"); 5651 /* Send a Hotplug Uevent to userspace to start modeset */ 5652 drm_kms_helper_hotplug_event(&dev_priv->drm); 5653 break; 5654 case DP_TEST_LINK_PHY_TEST_PATTERN: 5655 drm_dbg_kms(&dev_priv->drm, 5656 "PHY test pattern Compliance Test requested\n"); 5657 /* 5658 * Schedule long hpd to do the test 5659 * 5660 * FIXME get rid of the ad-hoc phy test modeset code 5661 * and properly incorporate it into the normal modeset. 5662 */ 5663 reprobe_needed = true; 5664 } 5665 5666 return !reprobe_needed; 5667 } 5668 5669 /* XXX this is probably wrong for multiple downstream ports */ 5670 static enum drm_connector_status 5671 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5672 { 5673 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5674 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5675 u8 *dpcd = intel_dp->dpcd; 5676 u8 type; 5677 5678 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) 5679 return connector_status_connected; 5680 5681 lspcon_resume(dig_port); 5682 5683 if (!intel_dp_get_dpcd(intel_dp)) 5684 return connector_status_disconnected; 5685 5686 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); 5687 5688 /* if there's no downstream port, we're done */ 5689 if (!drm_dp_is_branch(dpcd)) 5690 return connector_status_connected; 5691 5692 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5693 if (intel_dp_has_sink_count(intel_dp) && 5694 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5695 return intel_dp->sink_count ? 5696 connector_status_connected : connector_status_disconnected; 5697 } 5698 5699 if (intel_dp->mst_detect == DRM_DP_MST) 5700 return connector_status_connected; 5701 5702 /* If no HPD, poke DDC gently */ 5703 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5704 return connector_status_connected; 5705 5706 /* Well we tried, say unknown for unreliable port types */ 5707 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5708 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5709 if (type == DP_DS_PORT_TYPE_VGA || 5710 type == DP_DS_PORT_TYPE_NON_EDID) 5711 return connector_status_unknown; 5712 } else { 5713 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5714 DP_DWN_STRM_PORT_TYPE_MASK; 5715 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5716 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5717 return connector_status_unknown; 5718 } 5719 5720 /* Anything else is out of spec, warn and ignore */ 5721 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); 5722 return connector_status_disconnected; 5723 } 5724 5725 static enum drm_connector_status 5726 edp_detect(struct intel_dp *intel_dp) 5727 { 5728 return connector_status_connected; 5729 } 5730 5731 void intel_digital_port_lock(struct intel_encoder *encoder) 5732 { 5733 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5734 5735 if (dig_port->lock) 5736 dig_port->lock(dig_port); 5737 } 5738 5739 void intel_digital_port_unlock(struct intel_encoder *encoder) 5740 { 5741 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5742 5743 if (dig_port->unlock) 5744 dig_port->unlock(dig_port); 5745 } 5746 5747 /* 5748 * intel_digital_port_connected_locked - is the specified port connected? 5749 * @encoder: intel_encoder 5750 * 5751 * In cases where there's a connector physically connected but it can't be used 5752 * by our hardware we also return false, since the rest of the driver should 5753 * pretty much treat the port as disconnected. This is relevant for type-C 5754 * (starting on ICL) where there's ownership involved. 5755 * 5756 * The caller must hold the lock acquired by calling intel_digital_port_lock() 5757 * when calling this function. 5758 * 5759 * Return %true if port is connected, %false otherwise. 5760 */ 5761 bool intel_digital_port_connected_locked(struct intel_encoder *encoder) 5762 { 5763 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5764 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5765 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5766 bool is_connected = false; 5767 intel_wakeref_t wakeref; 5768 5769 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 5770 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); 5771 5772 do { 5773 is_connected = dig_port->connected(encoder); 5774 if (is_connected || is_glitch_free) 5775 break; 5776 usleep_range(10, 30); 5777 } while (time_before(jiffies, wait_expires)); 5778 } 5779 5780 return is_connected; 5781 } 5782 5783 bool intel_digital_port_connected(struct intel_encoder *encoder) 5784 { 5785 bool ret; 5786 5787 intel_digital_port_lock(encoder); 5788 ret = intel_digital_port_connected_locked(encoder); 5789 intel_digital_port_unlock(encoder); 5790 5791 return ret; 5792 } 5793 5794 static const struct drm_edid * 5795 intel_dp_get_edid(struct intel_dp *intel_dp) 5796 { 5797 struct intel_connector *connector = intel_dp->attached_connector; 5798 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5799 5800 /* Use panel fixed edid if we have one */ 5801 if (fixed_edid) { 5802 /* invalid edid */ 5803 if (IS_ERR(fixed_edid)) 5804 return NULL; 5805 5806 return drm_edid_dup(fixed_edid); 5807 } 5808 5809 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5810 } 5811 5812 static void 5813 intel_dp_update_dfp(struct intel_dp *intel_dp, 5814 const struct drm_edid *drm_edid) 5815 { 5816 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5817 struct intel_connector *connector = intel_dp->attached_connector; 5818 5819 intel_dp->dfp.max_bpc = 5820 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5821 intel_dp->downstream_ports, drm_edid); 5822 5823 intel_dp->dfp.max_dotclock = 5824 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5825 intel_dp->downstream_ports); 5826 5827 intel_dp->dfp.min_tmds_clock = 5828 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5829 intel_dp->downstream_ports, 5830 drm_edid); 5831 intel_dp->dfp.max_tmds_clock = 5832 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5833 intel_dp->downstream_ports, 5834 drm_edid); 5835 5836 intel_dp->dfp.pcon_max_frl_bw = 5837 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5838 intel_dp->downstream_ports); 5839 5840 drm_dbg_kms(&i915->drm, 5841 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5842 connector->base.base.id, connector->base.name, 5843 intel_dp->dfp.max_bpc, 5844 intel_dp->dfp.max_dotclock, 5845 intel_dp->dfp.min_tmds_clock, 5846 intel_dp->dfp.max_tmds_clock, 5847 intel_dp->dfp.pcon_max_frl_bw); 5848 5849 intel_dp_get_pcon_dsc_cap(intel_dp); 5850 } 5851 5852 static bool 5853 intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 5854 { 5855 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 5856 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 5857 return true; 5858 5859 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 5860 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5861 return true; 5862 5863 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 5864 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5865 return true; 5866 5867 return false; 5868 } 5869 5870 static void 5871 intel_dp_update_420(struct intel_dp *intel_dp) 5872 { 5873 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5874 struct intel_connector *connector = intel_dp->attached_connector; 5875 5876 intel_dp->dfp.ycbcr420_passthrough = 5877 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 5878 intel_dp->downstream_ports); 5879 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 5880 intel_dp->dfp.ycbcr_444_to_420 = 5881 dp_to_dig_port(intel_dp)->lspcon.active || 5882 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 5883 intel_dp->downstream_ports); 5884 intel_dp->dfp.rgb_to_ycbcr = 5885 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 5886 intel_dp->downstream_ports, 5887 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 5888 5889 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 5890 5891 drm_dbg_kms(&i915->drm, 5892 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 5893 connector->base.base.id, connector->base.name, 5894 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 5895 str_yes_no(connector->base.ycbcr_420_allowed), 5896 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 5897 } 5898 5899 static void 5900 intel_dp_set_edid(struct intel_dp *intel_dp) 5901 { 5902 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5903 struct intel_connector *connector = intel_dp->attached_connector; 5904 const struct drm_edid *drm_edid; 5905 bool vrr_capable; 5906 5907 intel_dp_unset_edid(intel_dp); 5908 drm_edid = intel_dp_get_edid(intel_dp); 5909 connector->detect_edid = drm_edid; 5910 5911 /* Below we depend on display info having been updated */ 5912 drm_edid_connector_update(&connector->base, drm_edid); 5913 5914 vrr_capable = intel_vrr_is_capable(connector); 5915 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 5916 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 5917 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 5918 5919 intel_dp_update_dfp(intel_dp, drm_edid); 5920 intel_dp_update_420(intel_dp); 5921 5922 drm_dp_cec_attach(&intel_dp->aux, 5923 connector->base.display_info.source_physical_address); 5924 } 5925 5926 static void 5927 intel_dp_unset_edid(struct intel_dp *intel_dp) 5928 { 5929 struct intel_connector *connector = intel_dp->attached_connector; 5930 5931 drm_dp_cec_unset_edid(&intel_dp->aux); 5932 drm_edid_free(connector->detect_edid); 5933 connector->detect_edid = NULL; 5934 5935 intel_dp->dfp.max_bpc = 0; 5936 intel_dp->dfp.max_dotclock = 0; 5937 intel_dp->dfp.min_tmds_clock = 0; 5938 intel_dp->dfp.max_tmds_clock = 0; 5939 5940 intel_dp->dfp.pcon_max_frl_bw = 0; 5941 5942 intel_dp->dfp.ycbcr_444_to_420 = false; 5943 connector->base.ycbcr_420_allowed = false; 5944 5945 drm_connector_set_vrr_capable_property(&connector->base, 5946 false); 5947 } 5948 5949 static void 5950 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 5951 { 5952 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5953 5954 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 5955 if (!HAS_DSC(i915)) 5956 return; 5957 5958 if (intel_dp_is_edp(intel_dp)) 5959 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 5960 connector); 5961 else 5962 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 5963 connector); 5964 } 5965 5966 static void 5967 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 5968 { 5969 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 5970 5971 intel_dp->as_sdp_supported = HAS_AS_SDP(i915) && 5972 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 5973 } 5974 5975 static int 5976 intel_dp_detect(struct drm_connector *connector, 5977 struct drm_modeset_acquire_ctx *ctx, 5978 bool force) 5979 { 5980 struct drm_i915_private *dev_priv = to_i915(connector->dev); 5981 struct intel_connector *intel_connector = 5982 to_intel_connector(connector); 5983 struct intel_dp *intel_dp = intel_attached_dp(intel_connector); 5984 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5985 struct intel_encoder *encoder = &dig_port->base; 5986 enum drm_connector_status status; 5987 int ret; 5988 5989 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 5990 connector->base.id, connector->name); 5991 drm_WARN_ON(&dev_priv->drm, 5992 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 5993 5994 if (!intel_display_device_enabled(dev_priv)) 5995 return connector_status_disconnected; 5996 5997 if (!intel_display_driver_check_access(dev_priv)) 5998 return connector->status; 5999 6000 /* Can't disconnect eDP */ 6001 if (intel_dp_is_edp(intel_dp)) 6002 status = edp_detect(intel_dp); 6003 else if (intel_digital_port_connected(encoder)) 6004 status = intel_dp_detect_dpcd(intel_dp); 6005 else 6006 status = connector_status_disconnected; 6007 6008 if (status != connector_status_disconnected && 6009 !intel_dp_mst_verify_dpcd_state(intel_dp)) 6010 /* 6011 * This requires retrying detection for instance to re-enable 6012 * the MST mode that got reset via a long HPD pulse. The retry 6013 * will happen either via the hotplug handler's retry logic, 6014 * ensured by setting the connector here to SST/disconnected, 6015 * or via a userspace connector probing in response to the 6016 * hotplug uevent sent when removing the MST connectors. 6017 */ 6018 status = connector_status_disconnected; 6019 6020 if (status == connector_status_disconnected) { 6021 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 6022 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); 6023 intel_dp->psr.sink_panel_replay_support = false; 6024 intel_dp->psr.sink_panel_replay_su_support = false; 6025 6026 intel_dp_mst_disconnect(intel_dp); 6027 6028 intel_dp_tunnel_disconnect(intel_dp); 6029 6030 goto out; 6031 } 6032 6033 ret = intel_dp_tunnel_detect(intel_dp, ctx); 6034 if (ret == -EDEADLK) 6035 return ret; 6036 6037 if (ret == 1) 6038 intel_connector->base.epoch_counter++; 6039 6040 if (!intel_dp_is_edp(intel_dp)) 6041 intel_psr_init_dpcd(intel_dp); 6042 6043 intel_dp_detect_dsc_caps(intel_dp, intel_connector); 6044 6045 intel_dp_detect_sdp_caps(intel_dp); 6046 6047 if (intel_dp->reset_link_params) { 6048 intel_dp_reset_link_params(intel_dp); 6049 intel_dp->reset_link_params = false; 6050 } 6051 6052 intel_dp_mst_configure(intel_dp); 6053 6054 intel_dp_print_rates(intel_dp); 6055 6056 if (intel_dp->is_mst) { 6057 /* 6058 * If we are in MST mode then this connector 6059 * won't appear connected or have anything 6060 * with EDID on it 6061 */ 6062 status = connector_status_disconnected; 6063 goto out; 6064 } 6065 6066 /* 6067 * Some external monitors do not signal loss of link synchronization 6068 * with an IRQ_HPD, so force a link status check. 6069 * 6070 * TODO: this probably became redundant, so remove it: the link state 6071 * is rechecked/recovered now after modesets, where the loss of 6072 * synchronization tends to occur. 6073 */ 6074 if (!intel_dp_is_edp(intel_dp)) 6075 intel_dp_check_link_state(intel_dp); 6076 6077 /* 6078 * Clearing NACK and defer counts to get their exact values 6079 * while reading EDID which are required by Compliance tests 6080 * 4.2.2.4 and 4.2.2.5 6081 */ 6082 intel_dp->aux.i2c_nack_count = 0; 6083 intel_dp->aux.i2c_defer_count = 0; 6084 6085 intel_dp_set_edid(intel_dp); 6086 if (intel_dp_is_edp(intel_dp) || 6087 to_intel_connector(connector)->detect_edid) 6088 status = connector_status_connected; 6089 6090 intel_dp_check_device_service_irq(intel_dp); 6091 6092 out: 6093 if (status != connector_status_connected && !intel_dp->is_mst) 6094 intel_dp_unset_edid(intel_dp); 6095 6096 if (!intel_dp_is_edp(intel_dp)) 6097 drm_dp_set_subconnector_property(connector, 6098 status, 6099 intel_dp->dpcd, 6100 intel_dp->downstream_ports); 6101 return status; 6102 } 6103 6104 static void 6105 intel_dp_force(struct drm_connector *connector) 6106 { 6107 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 6108 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6109 struct intel_encoder *intel_encoder = &dig_port->base; 6110 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 6111 6112 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 6113 connector->base.id, connector->name); 6114 6115 if (!intel_display_driver_check_access(dev_priv)) 6116 return; 6117 6118 intel_dp_unset_edid(intel_dp); 6119 6120 if (connector->status != connector_status_connected) 6121 return; 6122 6123 intel_dp_set_edid(intel_dp); 6124 } 6125 6126 static int intel_dp_get_modes(struct drm_connector *connector) 6127 { 6128 struct intel_connector *intel_connector = to_intel_connector(connector); 6129 int num_modes; 6130 6131 /* drm_edid_connector_update() done in ->detect() or ->force() */ 6132 num_modes = drm_edid_connector_add_modes(connector); 6133 6134 /* Also add fixed mode, which may or may not be present in EDID */ 6135 if (intel_dp_is_edp(intel_attached_dp(intel_connector))) 6136 num_modes += intel_panel_get_modes(intel_connector); 6137 6138 if (num_modes) 6139 return num_modes; 6140 6141 if (!intel_connector->detect_edid) { 6142 struct intel_dp *intel_dp = intel_attached_dp(intel_connector); 6143 struct drm_display_mode *mode; 6144 6145 mode = drm_dp_downstream_mode(connector->dev, 6146 intel_dp->dpcd, 6147 intel_dp->downstream_ports); 6148 if (mode) { 6149 drm_mode_probed_add(connector, mode); 6150 num_modes++; 6151 } 6152 } 6153 6154 return num_modes; 6155 } 6156 6157 static int 6158 intel_dp_connector_register(struct drm_connector *connector) 6159 { 6160 struct drm_i915_private *i915 = to_i915(connector->dev); 6161 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 6162 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6163 struct intel_lspcon *lspcon = &dig_port->lspcon; 6164 int ret; 6165 6166 ret = intel_connector_register(connector); 6167 if (ret) 6168 return ret; 6169 6170 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", 6171 intel_dp->aux.name, connector->kdev->kobj.name); 6172 6173 intel_dp->aux.dev = connector->kdev; 6174 ret = drm_dp_aux_register(&intel_dp->aux); 6175 if (!ret) 6176 drm_dp_cec_register_connector(&intel_dp->aux, connector); 6177 6178 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 6179 return ret; 6180 6181 /* 6182 * ToDo: Clean this up to handle lspcon init and resume more 6183 * efficiently and streamlined. 6184 */ 6185 if (lspcon_init(dig_port)) { 6186 lspcon_detect_hdr_capability(lspcon); 6187 if (lspcon->hdr_supported) 6188 drm_connector_attach_hdr_output_metadata_property(connector); 6189 } 6190 6191 return ret; 6192 } 6193 6194 static void 6195 intel_dp_connector_unregister(struct drm_connector *connector) 6196 { 6197 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 6198 6199 drm_dp_cec_unregister_connector(&intel_dp->aux); 6200 drm_dp_aux_unregister(&intel_dp->aux); 6201 intel_connector_unregister(connector); 6202 } 6203 6204 void intel_dp_connector_sync_state(struct intel_connector *connector, 6205 const struct intel_crtc_state *crtc_state) 6206 { 6207 struct drm_i915_private *i915 = to_i915(connector->base.dev); 6208 6209 if (crtc_state && crtc_state->dsc.compression_enable) { 6210 drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux); 6211 connector->dp.dsc_decompression_enabled = true; 6212 } else { 6213 connector->dp.dsc_decompression_enabled = false; 6214 } 6215 } 6216 6217 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) 6218 { 6219 struct intel_encoder *encoder = to_intel_encoder(_encoder); 6220 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 6221 struct intel_dp *intel_dp = &dig_port->dp; 6222 6223 intel_encoder_link_check_flush_work(encoder); 6224 6225 intel_dp_mst_encoder_cleanup(dig_port); 6226 6227 intel_dp_tunnel_destroy(intel_dp); 6228 6229 intel_pps_vdd_off_sync(intel_dp); 6230 6231 /* 6232 * Ensure power off delay is respected on module remove, so that we can 6233 * reduce delays at driver probe. See pps_init_timestamps(). 6234 */ 6235 intel_pps_wait_power_cycle(intel_dp); 6236 6237 intel_dp_aux_fini(intel_dp); 6238 } 6239 6240 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 6241 { 6242 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 6243 6244 intel_pps_vdd_off_sync(intel_dp); 6245 6246 intel_dp_tunnel_suspend(intel_dp); 6247 } 6248 6249 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) 6250 { 6251 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 6252 6253 intel_pps_wait_power_cycle(intel_dp); 6254 } 6255 6256 static int intel_modeset_tile_group(struct intel_atomic_state *state, 6257 int tile_group_id) 6258 { 6259 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6260 struct drm_connector_list_iter conn_iter; 6261 struct drm_connector *connector; 6262 int ret = 0; 6263 6264 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 6265 drm_for_each_connector_iter(connector, &conn_iter) { 6266 struct drm_connector_state *conn_state; 6267 struct intel_crtc_state *crtc_state; 6268 struct intel_crtc *crtc; 6269 6270 if (!connector->has_tile || 6271 connector->tile_group->id != tile_group_id) 6272 continue; 6273 6274 conn_state = drm_atomic_get_connector_state(&state->base, 6275 connector); 6276 if (IS_ERR(conn_state)) { 6277 ret = PTR_ERR(conn_state); 6278 break; 6279 } 6280 6281 crtc = to_intel_crtc(conn_state->crtc); 6282 6283 if (!crtc) 6284 continue; 6285 6286 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6287 crtc_state->uapi.mode_changed = true; 6288 6289 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6290 if (ret) 6291 break; 6292 } 6293 drm_connector_list_iter_end(&conn_iter); 6294 6295 return ret; 6296 } 6297 6298 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 6299 { 6300 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 6301 struct intel_crtc *crtc; 6302 6303 if (transcoders == 0) 6304 return 0; 6305 6306 for_each_intel_crtc(&dev_priv->drm, crtc) { 6307 struct intel_crtc_state *crtc_state; 6308 int ret; 6309 6310 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6311 if (IS_ERR(crtc_state)) 6312 return PTR_ERR(crtc_state); 6313 6314 if (!crtc_state->hw.enable) 6315 continue; 6316 6317 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6318 continue; 6319 6320 crtc_state->uapi.mode_changed = true; 6321 6322 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6323 if (ret) 6324 return ret; 6325 6326 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6327 if (ret) 6328 return ret; 6329 6330 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6331 } 6332 6333 drm_WARN_ON(&dev_priv->drm, transcoders != 0); 6334 6335 return 0; 6336 } 6337 6338 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6339 struct drm_connector *connector) 6340 { 6341 const struct drm_connector_state *old_conn_state = 6342 drm_atomic_get_old_connector_state(&state->base, connector); 6343 const struct intel_crtc_state *old_crtc_state; 6344 struct intel_crtc *crtc; 6345 u8 transcoders; 6346 6347 crtc = to_intel_crtc(old_conn_state->crtc); 6348 if (!crtc) 6349 return 0; 6350 6351 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6352 6353 if (!old_crtc_state->hw.active) 6354 return 0; 6355 6356 transcoders = old_crtc_state->sync_mode_slaves_mask; 6357 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 6358 transcoders |= BIT(old_crtc_state->master_transcoder); 6359 6360 return intel_modeset_affected_transcoders(state, 6361 transcoders); 6362 } 6363 6364 static int intel_dp_connector_atomic_check(struct drm_connector *conn, 6365 struct drm_atomic_state *_state) 6366 { 6367 struct drm_i915_private *dev_priv = to_i915(conn->dev); 6368 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6369 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn); 6370 struct intel_connector *intel_conn = to_intel_connector(conn); 6371 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder); 6372 int ret; 6373 6374 ret = intel_digital_connector_atomic_check(conn, &state->base); 6375 if (ret) 6376 return ret; 6377 6378 if (intel_dp_mst_source_support(intel_dp)) { 6379 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); 6380 if (ret) 6381 return ret; 6382 } 6383 6384 if (!intel_connector_needs_modeset(state, conn)) 6385 return 0; 6386 6387 ret = intel_dp_tunnel_atomic_check_state(state, 6388 intel_dp, 6389 intel_conn); 6390 if (ret) 6391 return ret; 6392 6393 /* 6394 * We don't enable port sync on BDW due to missing w/as and 6395 * due to not having adjusted the modeset sequence appropriately. 6396 */ 6397 if (DISPLAY_VER(dev_priv) < 9) 6398 return 0; 6399 6400 if (conn->has_tile) { 6401 ret = intel_modeset_tile_group(state, conn->tile_group->id); 6402 if (ret) 6403 return ret; 6404 } 6405 6406 return intel_modeset_synced_crtcs(state, conn); 6407 } 6408 6409 static void intel_dp_oob_hotplug_event(struct drm_connector *connector, 6410 enum drm_connector_status hpd_state) 6411 { 6412 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 6413 struct drm_i915_private *i915 = to_i915(connector->dev); 6414 bool hpd_high = hpd_state == connector_status_connected; 6415 unsigned int hpd_pin = encoder->hpd_pin; 6416 bool need_work = false; 6417 6418 spin_lock_irq(&i915->irq_lock); 6419 if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) { 6420 i915->display.hotplug.event_bits |= BIT(hpd_pin); 6421 6422 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high); 6423 need_work = true; 6424 } 6425 spin_unlock_irq(&i915->irq_lock); 6426 6427 if (need_work) 6428 intel_hpd_schedule_detection(i915); 6429 } 6430 6431 static const struct drm_connector_funcs intel_dp_connector_funcs = { 6432 .force = intel_dp_force, 6433 .fill_modes = drm_helper_probe_single_connector_modes, 6434 .atomic_get_property = intel_digital_connector_atomic_get_property, 6435 .atomic_set_property = intel_digital_connector_atomic_set_property, 6436 .late_register = intel_dp_connector_register, 6437 .early_unregister = intel_dp_connector_unregister, 6438 .destroy = intel_connector_destroy, 6439 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6440 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6441 .oob_hotplug_event = intel_dp_oob_hotplug_event, 6442 }; 6443 6444 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6445 .detect_ctx = intel_dp_detect, 6446 .get_modes = intel_dp_get_modes, 6447 .mode_valid = intel_dp_mode_valid, 6448 .atomic_check = intel_dp_connector_atomic_check, 6449 }; 6450 6451 enum irqreturn 6452 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 6453 { 6454 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 6455 struct intel_dp *intel_dp = &dig_port->dp; 6456 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 6457 6458 if (dig_port->base.type == INTEL_OUTPUT_EDP && 6459 (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) { 6460 /* 6461 * vdd off can generate a long/short pulse on eDP which 6462 * would require vdd on to handle it, and thus we 6463 * would end up in an endless cycle of 6464 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 6465 */ 6466 drm_dbg_kms(&i915->drm, 6467 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 6468 long_hpd ? "long" : "short", 6469 dig_port->base.base.base.id, 6470 dig_port->base.base.name); 6471 return IRQ_HANDLED; 6472 } 6473 6474 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 6475 dig_port->base.base.base.id, 6476 dig_port->base.base.name, 6477 long_hpd ? "long" : "short"); 6478 6479 /* 6480 * TBT DP tunnels require the GFX driver to read out the DPRX caps in 6481 * response to long HPD pulses. The DP hotplug handler does that, 6482 * however the hotplug handler may be blocked by another 6483 * connector's/encoder's hotplug handler. Since the TBT CM may not 6484 * complete the DP tunnel BW request for the latter connector/encoder 6485 * waiting for this encoder's DPRX read, perform a dummy read here. 6486 */ 6487 if (long_hpd) 6488 intel_dp_read_dprx_caps(intel_dp, dpcd); 6489 6490 if (long_hpd) { 6491 intel_dp->reset_link_params = true; 6492 return IRQ_NONE; 6493 } 6494 6495 if (intel_dp->is_mst) { 6496 if (!intel_dp_check_mst_status(intel_dp)) 6497 return IRQ_NONE; 6498 } else if (!intel_dp_short_pulse(intel_dp)) { 6499 return IRQ_NONE; 6500 } 6501 6502 return IRQ_HANDLED; 6503 } 6504 6505 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv, 6506 const struct intel_bios_encoder_data *devdata, 6507 enum port port) 6508 { 6509 /* 6510 * eDP not supported on g4x. so bail out early just 6511 * for a bit extra safety in case the VBT is bonkers. 6512 */ 6513 if (DISPLAY_VER(dev_priv) < 5) 6514 return false; 6515 6516 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A) 6517 return true; 6518 6519 return devdata && intel_bios_encoder_supports_edp(devdata); 6520 } 6521 6522 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port) 6523 { 6524 struct intel_display *display = &i915->display; 6525 const struct intel_bios_encoder_data *devdata = 6526 intel_bios_encoder_data_lookup(display, port); 6527 6528 return _intel_dp_is_port_edp(i915, devdata, port); 6529 } 6530 6531 bool 6532 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) 6533 { 6534 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 6535 enum port port = encoder->port; 6536 6537 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 6538 return false; 6539 6540 if (DISPLAY_VER(i915) >= 11) 6541 return true; 6542 6543 if (port == PORT_A) 6544 return false; 6545 6546 if (IS_HASWELL(i915) || IS_BROADWELL(i915) || 6547 DISPLAY_VER(i915) >= 9) 6548 return true; 6549 6550 return false; 6551 } 6552 6553 static void 6554 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 6555 { 6556 struct drm_i915_private *dev_priv = to_i915(connector->dev); 6557 enum port port = dp_to_dig_port(intel_dp)->base.port; 6558 6559 if (!intel_dp_is_edp(intel_dp)) 6560 drm_connector_attach_dp_subconnector_property(connector); 6561 6562 if (!IS_G4X(dev_priv) && port != PORT_A) 6563 intel_attach_force_audio_property(connector); 6564 6565 intel_attach_broadcast_rgb_property(connector); 6566 if (HAS_GMCH(dev_priv)) 6567 drm_connector_attach_max_bpc_property(connector, 6, 10); 6568 else if (DISPLAY_VER(dev_priv) >= 5) 6569 drm_connector_attach_max_bpc_property(connector, 6, 12); 6570 6571 /* Register HDMI colorspace for case of lspcon */ 6572 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 6573 drm_connector_attach_content_type_property(connector); 6574 intel_attach_hdmi_colorspace_property(connector); 6575 } else { 6576 intel_attach_dp_colorspace_property(connector); 6577 } 6578 6579 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 6580 drm_connector_attach_hdr_output_metadata_property(connector); 6581 6582 if (HAS_VRR(dev_priv)) 6583 drm_connector_attach_vrr_capable_property(connector); 6584 } 6585 6586 static void 6587 intel_edp_add_properties(struct intel_dp *intel_dp) 6588 { 6589 struct intel_connector *connector = intel_dp->attached_connector; 6590 struct drm_i915_private *i915 = to_i915(connector->base.dev); 6591 const struct drm_display_mode *fixed_mode = 6592 intel_panel_preferred_fixed_mode(connector); 6593 6594 intel_attach_scaling_mode_property(&connector->base); 6595 6596 drm_connector_set_panel_orientation_with_quirk(&connector->base, 6597 i915->display.vbt.orientation, 6598 fixed_mode->hdisplay, 6599 fixed_mode->vdisplay); 6600 } 6601 6602 static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 6603 struct intel_connector *connector) 6604 { 6605 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 6606 enum pipe pipe = INVALID_PIPE; 6607 6608 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 6609 /* 6610 * Figure out the current pipe for the initial backlight setup. 6611 * If the current pipe isn't valid, try the PPS pipe, and if that 6612 * fails just assume pipe A. 6613 */ 6614 pipe = vlv_active_pipe(intel_dp); 6615 6616 if (pipe != PIPE_A && pipe != PIPE_B) 6617 pipe = intel_dp->pps.pps_pipe; 6618 6619 if (pipe != PIPE_A && pipe != PIPE_B) 6620 pipe = PIPE_A; 6621 } 6622 6623 intel_backlight_setup(connector, pipe); 6624 } 6625 6626 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6627 struct intel_connector *intel_connector) 6628 { 6629 struct intel_display *display = to_intel_display(intel_dp); 6630 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6631 struct drm_connector *connector = &intel_connector->base; 6632 struct drm_display_mode *fixed_mode; 6633 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6634 bool has_dpcd; 6635 const struct drm_edid *drm_edid; 6636 6637 if (!intel_dp_is_edp(intel_dp)) 6638 return true; 6639 6640 /* 6641 * On IBX/CPT we may get here with LVDS already registered. Since the 6642 * driver uses the only internal power sequencer available for both 6643 * eDP and LVDS bail out early in this case to prevent interfering 6644 * with an already powered-on LVDS power sequencer. 6645 */ 6646 if (intel_get_lvds_encoder(dev_priv)) { 6647 drm_WARN_ON(&dev_priv->drm, 6648 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 6649 drm_info(&dev_priv->drm, 6650 "LVDS was detected, not registering eDP\n"); 6651 6652 return false; 6653 } 6654 6655 intel_bios_init_panel_early(display, &intel_connector->panel, 6656 encoder->devdata); 6657 6658 if (!intel_pps_init(intel_dp)) { 6659 drm_info(&dev_priv->drm, 6660 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6661 encoder->base.base.id, encoder->base.name); 6662 /* 6663 * The BIOS may have still enabled VDD on the PPS even 6664 * though it's unusable. Make sure we turn it back off 6665 * and to release the power domain references/etc. 6666 */ 6667 goto out_vdd_off; 6668 } 6669 6670 /* 6671 * Enable HPD sense for live status check. 6672 * intel_hpd_irq_setup() will turn it off again 6673 * if it's no longer needed later. 6674 * 6675 * The DPCD probe below will make sure VDD is on. 6676 */ 6677 intel_hpd_enable_detection(encoder); 6678 6679 intel_alpm_init_dpcd(intel_dp); 6680 6681 /* Cache DPCD and EDID for edp. */ 6682 has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector); 6683 6684 if (!has_dpcd) { 6685 /* if this fails, presume the device is a ghost */ 6686 drm_info(&dev_priv->drm, 6687 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6688 encoder->base.base.id, encoder->base.name); 6689 goto out_vdd_off; 6690 } 6691 6692 /* 6693 * VBT and straps are liars. Also check HPD as that seems 6694 * to be the most reliable piece of information available. 6695 * 6696 * ... expect on devices that forgot to hook HPD up for eDP 6697 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6698 * ports are attempting to use the same AUX CH, according to VBT. 6699 */ 6700 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6701 /* 6702 * If this fails, presume the DPCD answer came 6703 * from some other port using the same AUX CH. 6704 * 6705 * FIXME maybe cleaner to check this before the 6706 * DPCD read? Would need sort out the VDD handling... 6707 */ 6708 if (!intel_digital_port_connected(encoder)) { 6709 drm_info(&dev_priv->drm, 6710 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6711 encoder->base.base.id, encoder->base.name); 6712 goto out_vdd_off; 6713 } 6714 6715 /* 6716 * Unfortunately even the HPD based detection fails on 6717 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6718 * back to checking for a VGA branch device. Only do this 6719 * on known affected platforms to minimize false positives. 6720 */ 6721 if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6722 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6723 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6724 drm_info(&dev_priv->drm, 6725 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6726 encoder->base.base.id, encoder->base.name); 6727 goto out_vdd_off; 6728 } 6729 } 6730 6731 mutex_lock(&dev_priv->drm.mode_config.mutex); 6732 drm_edid = drm_edid_read_ddc(connector, connector->ddc); 6733 if (!drm_edid) { 6734 /* Fallback to EDID from ACPI OpRegion, if any */ 6735 drm_edid = intel_opregion_get_edid(intel_connector); 6736 if (drm_edid) 6737 drm_dbg_kms(&dev_priv->drm, 6738 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6739 connector->base.id, connector->name); 6740 } 6741 if (drm_edid) { 6742 if (drm_edid_connector_update(connector, drm_edid) || 6743 !drm_edid_connector_add_modes(connector)) { 6744 drm_edid_connector_update(connector, NULL); 6745 drm_edid_free(drm_edid); 6746 drm_edid = ERR_PTR(-EINVAL); 6747 } 6748 } else { 6749 drm_edid = ERR_PTR(-ENOENT); 6750 } 6751 6752 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, 6753 IS_ERR(drm_edid) ? NULL : drm_edid); 6754 6755 intel_panel_add_edid_fixed_modes(intel_connector, true); 6756 6757 /* MSO requires information from the EDID */ 6758 intel_edp_mso_init(intel_dp); 6759 6760 /* multiply the mode clock and horizontal timings for MSO */ 6761 list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head) 6762 intel_edp_mso_mode_fixup(intel_connector, fixed_mode); 6763 6764 /* fallback to VBT if available for eDP */ 6765 if (!intel_panel_preferred_fixed_mode(intel_connector)) 6766 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 6767 6768 mutex_unlock(&dev_priv->drm.mode_config.mutex); 6769 6770 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 6771 drm_info(&dev_priv->drm, 6772 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6773 encoder->base.base.id, encoder->base.name); 6774 goto out_vdd_off; 6775 } 6776 6777 intel_panel_init(intel_connector, drm_edid); 6778 6779 intel_edp_backlight_setup(intel_dp, intel_connector); 6780 6781 intel_edp_add_properties(intel_dp); 6782 6783 intel_pps_init_late(intel_dp); 6784 6785 return true; 6786 6787 out_vdd_off: 6788 intel_pps_vdd_off_sync(intel_dp); 6789 6790 return false; 6791 } 6792 6793 static void intel_dp_modeset_retry_work_fn(struct work_struct *work) 6794 { 6795 struct intel_connector *intel_connector; 6796 struct drm_connector *connector; 6797 6798 intel_connector = container_of(work, typeof(*intel_connector), 6799 modeset_retry_work); 6800 connector = &intel_connector->base; 6801 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id, 6802 connector->name); 6803 6804 /* Grab the locks before changing connector property*/ 6805 mutex_lock(&connector->dev->mode_config.mutex); 6806 /* Set connector link status to BAD and send a Uevent to notify 6807 * userspace to do a modeset. 6808 */ 6809 drm_connector_set_link_status_property(connector, 6810 DRM_MODE_LINK_STATUS_BAD); 6811 mutex_unlock(&connector->dev->mode_config.mutex); 6812 /* Send Hotplug uevent so userspace can reprobe */ 6813 drm_kms_helper_connector_hotplug_event(connector); 6814 6815 drm_connector_put(connector); 6816 } 6817 6818 void intel_dp_init_modeset_retry_work(struct intel_connector *connector) 6819 { 6820 INIT_WORK(&connector->modeset_retry_work, 6821 intel_dp_modeset_retry_work_fn); 6822 } 6823 6824 bool 6825 intel_dp_init_connector(struct intel_digital_port *dig_port, 6826 struct intel_connector *intel_connector) 6827 { 6828 struct drm_connector *connector = &intel_connector->base; 6829 struct intel_dp *intel_dp = &dig_port->dp; 6830 struct intel_encoder *intel_encoder = &dig_port->base; 6831 struct drm_device *dev = intel_encoder->base.dev; 6832 struct drm_i915_private *dev_priv = to_i915(dev); 6833 enum port port = intel_encoder->port; 6834 int type; 6835 6836 /* Initialize the work for modeset in case of link train failure */ 6837 intel_dp_init_modeset_retry_work(intel_connector); 6838 6839 if (drm_WARN(dev, dig_port->max_lanes < 1, 6840 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 6841 dig_port->max_lanes, intel_encoder->base.base.id, 6842 intel_encoder->base.name)) 6843 return false; 6844 6845 intel_dp->reset_link_params = true; 6846 intel_dp->pps.pps_pipe = INVALID_PIPE; 6847 intel_dp->pps.active_pipe = INVALID_PIPE; 6848 6849 /* Preserve the current hw state. */ 6850 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 6851 intel_dp->attached_connector = intel_connector; 6852 6853 if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) { 6854 /* 6855 * Currently we don't support eDP on TypeC ports, although in 6856 * theory it could work on TypeC legacy ports. 6857 */ 6858 drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder)); 6859 type = DRM_MODE_CONNECTOR_eDP; 6860 intel_encoder->type = INTEL_OUTPUT_EDP; 6861 6862 /* eDP only on port B and/or C on vlv/chv */ 6863 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || 6864 IS_CHERRYVIEW(dev_priv)) && 6865 port != PORT_B && port != PORT_C)) 6866 return false; 6867 } else { 6868 type = DRM_MODE_CONNECTOR_DisplayPort; 6869 } 6870 6871 intel_dp_set_default_sink_rates(intel_dp); 6872 intel_dp_set_default_max_sink_lane_count(intel_dp); 6873 6874 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6875 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); 6876 6877 intel_dp_aux_init(intel_dp); 6878 intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; 6879 6880 drm_dbg_kms(&dev_priv->drm, 6881 "Adding %s connector on [ENCODER:%d:%s]\n", 6882 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 6883 intel_encoder->base.base.id, intel_encoder->base.name); 6884 6885 drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs, 6886 type, &intel_dp->aux.ddc); 6887 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 6888 6889 if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12) 6890 connector->interlace_allowed = true; 6891 6892 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 6893 intel_connector->base.polled = intel_connector->polled; 6894 6895 intel_connector_attach_encoder(intel_connector, intel_encoder); 6896 6897 if (HAS_DDI(dev_priv)) 6898 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 6899 else 6900 intel_connector->get_hw_state = intel_connector_get_hw_state; 6901 intel_connector->sync_state = intel_dp_connector_sync_state; 6902 6903 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 6904 intel_dp_aux_fini(intel_dp); 6905 goto fail; 6906 } 6907 6908 intel_dp_set_source_rates(intel_dp); 6909 intel_dp_set_common_rates(intel_dp); 6910 intel_dp_reset_link_params(intel_dp); 6911 6912 /* init MST on ports that can support it */ 6913 intel_dp_mst_encoder_init(dig_port, 6914 intel_connector->base.base.id); 6915 6916 intel_dp_add_properties(intel_dp, connector); 6917 6918 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { 6919 int ret = intel_dp_hdcp_init(dig_port, intel_connector); 6920 if (ret) 6921 drm_dbg_kms(&dev_priv->drm, 6922 "HDCP init failed, skipping.\n"); 6923 } 6924 6925 intel_dp->colorimetry_support = 6926 intel_dp_get_colorimetry_status(intel_dp); 6927 6928 intel_dp->frl.is_trained = false; 6929 intel_dp->frl.trained_rate_gbps = 0; 6930 6931 intel_psr_init(intel_dp); 6932 6933 return true; 6934 6935 fail: 6936 intel_display_power_flush_work(dev_priv); 6937 drm_connector_cleanup(connector); 6938 6939 return false; 6940 } 6941 6942 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) 6943 { 6944 struct intel_encoder *encoder; 6945 6946 if (!HAS_DISPLAY(dev_priv)) 6947 return; 6948 6949 for_each_intel_encoder(&dev_priv->drm, encoder) { 6950 struct intel_dp *intel_dp; 6951 6952 if (encoder->type != INTEL_OUTPUT_DDI) 6953 continue; 6954 6955 intel_dp = enc_to_intel_dp(encoder); 6956 6957 if (!intel_dp_mst_source_support(intel_dp)) 6958 continue; 6959 6960 if (intel_dp->is_mst) 6961 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); 6962 } 6963 } 6964 6965 void intel_dp_mst_resume(struct drm_i915_private *dev_priv) 6966 { 6967 struct intel_encoder *encoder; 6968 6969 if (!HAS_DISPLAY(dev_priv)) 6970 return; 6971 6972 for_each_intel_encoder(&dev_priv->drm, encoder) { 6973 struct intel_dp *intel_dp; 6974 int ret; 6975 6976 if (encoder->type != INTEL_OUTPUT_DDI) 6977 continue; 6978 6979 intel_dp = enc_to_intel_dp(encoder); 6980 6981 if (!intel_dp_mst_source_support(intel_dp)) 6982 continue; 6983 6984 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, 6985 true); 6986 if (ret) { 6987 intel_dp->is_mst = false; 6988 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 6989 false); 6990 } 6991 } 6992 } 6993