1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_probe_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_connector.h" 40 #include "intel_crt.h" 41 #include "intel_crt_regs.h" 42 #include "intel_crtc.h" 43 #include "intel_ddi.h" 44 #include "intel_ddi_buf_trans.h" 45 #include "intel_de.h" 46 #include "intel_display_driver.h" 47 #include "intel_display_types.h" 48 #include "intel_fdi.h" 49 #include "intel_fdi_regs.h" 50 #include "intel_fifo_underrun.h" 51 #include "intel_gmbus.h" 52 #include "intel_hotplug.h" 53 #include "intel_hotplug_irq.h" 54 #include "intel_load_detect.h" 55 #include "intel_pch_display.h" 56 #include "intel_pch_refclk.h" 57 #include "intel_pfit.h" 58 59 /* Here's the desired hotplug mode */ 60 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE | \ 61 ADPA_CRT_HOTPLUG_PERIOD_128 | \ 62 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 63 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 64 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 65 ADPA_CRT_HOTPLUG_VOLREF_325MV) 66 #define ADPA_HOTPLUG_MASK (ADPA_CRT_HOTPLUG_MONITOR_MASK | \ 67 ADPA_CRT_HOTPLUG_ENABLE | \ 68 ADPA_CRT_HOTPLUG_PERIOD_MASK | \ 69 ADPA_CRT_HOTPLUG_WARMUP_MASK | \ 70 ADPA_CRT_HOTPLUG_SAMPLE_MASK | \ 71 ADPA_CRT_HOTPLUG_VOLTAGE_MASK | \ 72 ADPA_CRT_HOTPLUG_VOLREF_MASK | \ 73 ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 74 75 struct intel_crt { 76 struct intel_encoder base; 77 bool force_hotplug_required; 78 i915_reg_t adpa_reg; 79 }; 80 81 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 82 { 83 return container_of(encoder, struct intel_crt, base); 84 } 85 86 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 87 { 88 return intel_encoder_to_crt(intel_attached_encoder(connector)); 89 } 90 91 bool intel_crt_port_enabled(struct intel_display *display, 92 i915_reg_t adpa_reg, enum pipe *pipe) 93 { 94 struct drm_i915_private *dev_priv = to_i915(display->drm); 95 u32 val; 96 97 val = intel_de_read(display, adpa_reg); 98 99 /* asserts want to know the pipe even if the port is disabled */ 100 if (HAS_PCH_CPT(dev_priv)) 101 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val); 102 else 103 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val); 104 105 return val & ADPA_DAC_ENABLE; 106 } 107 108 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 109 enum pipe *pipe) 110 { 111 struct intel_display *display = to_intel_display(encoder); 112 struct intel_crt *crt = intel_encoder_to_crt(encoder); 113 intel_wakeref_t wakeref; 114 bool ret; 115 116 wakeref = intel_display_power_get_if_enabled(display, 117 encoder->power_domain); 118 if (!wakeref) 119 return false; 120 121 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); 122 123 intel_display_power_put(display, encoder->power_domain, wakeref); 124 125 return ret; 126 } 127 128 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 129 { 130 struct intel_display *display = to_intel_display(encoder); 131 struct intel_crt *crt = intel_encoder_to_crt(encoder); 132 u32 tmp, flags = 0; 133 134 tmp = intel_de_read(display, crt->adpa_reg); 135 136 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 137 flags |= DRM_MODE_FLAG_PHSYNC; 138 else 139 flags |= DRM_MODE_FLAG_NHSYNC; 140 141 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 142 flags |= DRM_MODE_FLAG_PVSYNC; 143 else 144 flags |= DRM_MODE_FLAG_NVSYNC; 145 146 return flags; 147 } 148 149 static void intel_crt_get_config(struct intel_encoder *encoder, 150 struct intel_crtc_state *crtc_state) 151 { 152 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 153 154 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 155 156 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 157 } 158 159 static void hsw_crt_get_config(struct intel_encoder *encoder, 160 struct intel_crtc_state *crtc_state) 161 { 162 lpt_pch_get_config(crtc_state); 163 164 hsw_ddi_get_config(encoder, crtc_state); 165 166 crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 167 DRM_MODE_FLAG_NHSYNC | 168 DRM_MODE_FLAG_PVSYNC | 169 DRM_MODE_FLAG_NVSYNC); 170 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 171 } 172 173 /* Note: The caller is required to filter out dpms modes not supported by the 174 * platform. */ 175 static void intel_crt_set_dpms(struct intel_encoder *encoder, 176 const struct intel_crtc_state *crtc_state, 177 int mode) 178 { 179 struct intel_display *display = to_intel_display(encoder); 180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 181 struct intel_crt *crt = intel_encoder_to_crt(encoder); 182 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 183 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 184 u32 adpa; 185 186 if (DISPLAY_VER(display) >= 5) 187 adpa = ADPA_HOTPLUG_BITS; 188 else 189 adpa = 0; 190 191 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 192 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 193 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 194 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 195 196 /* For CPT allow 3 pipe config, for others just use A or B */ 197 if (HAS_PCH_LPT(dev_priv)) 198 ; /* Those bits don't exist here */ 199 else if (HAS_PCH_CPT(dev_priv)) 200 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 201 else 202 adpa |= ADPA_PIPE_SEL(crtc->pipe); 203 204 if (!HAS_PCH_SPLIT(dev_priv)) 205 intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); 206 207 switch (mode) { 208 case DRM_MODE_DPMS_ON: 209 adpa |= ADPA_DAC_ENABLE; 210 break; 211 case DRM_MODE_DPMS_STANDBY: 212 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 213 break; 214 case DRM_MODE_DPMS_SUSPEND: 215 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 216 break; 217 case DRM_MODE_DPMS_OFF: 218 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 219 break; 220 } 221 222 intel_de_write(display, crt->adpa_reg, adpa); 223 } 224 225 static void intel_disable_crt(struct intel_atomic_state *state, 226 struct intel_encoder *encoder, 227 const struct intel_crtc_state *old_crtc_state, 228 const struct drm_connector_state *old_conn_state) 229 { 230 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 231 } 232 233 static void pch_disable_crt(struct intel_atomic_state *state, 234 struct intel_encoder *encoder, 235 const struct intel_crtc_state *old_crtc_state, 236 const struct drm_connector_state *old_conn_state) 237 { 238 } 239 240 static void pch_post_disable_crt(struct intel_atomic_state *state, 241 struct intel_encoder *encoder, 242 const struct intel_crtc_state *old_crtc_state, 243 const struct drm_connector_state *old_conn_state) 244 { 245 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state); 246 } 247 248 static void hsw_disable_crt(struct intel_atomic_state *state, 249 struct intel_encoder *encoder, 250 const struct intel_crtc_state *old_crtc_state, 251 const struct drm_connector_state *old_conn_state) 252 { 253 struct intel_display *display = to_intel_display(encoder); 254 255 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); 256 257 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 258 } 259 260 static void hsw_post_disable_crt(struct intel_atomic_state *state, 261 struct intel_encoder *encoder, 262 const struct intel_crtc_state *old_crtc_state, 263 const struct drm_connector_state *old_conn_state) 264 { 265 struct intel_display *display = to_intel_display(encoder); 266 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 267 268 intel_crtc_vblank_off(old_crtc_state); 269 270 intel_disable_transcoder(old_crtc_state); 271 272 intel_ddi_disable_transcoder_func(old_crtc_state); 273 274 ilk_pfit_disable(old_crtc_state); 275 276 intel_ddi_disable_transcoder_clock(old_crtc_state); 277 278 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state); 279 280 lpt_pch_disable(state, crtc); 281 282 hsw_fdi_disable(encoder); 283 284 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); 285 286 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 287 } 288 289 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, 290 struct intel_encoder *encoder, 291 const struct intel_crtc_state *crtc_state, 292 const struct drm_connector_state *conn_state) 293 { 294 struct intel_display *display = to_intel_display(encoder); 295 296 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 297 298 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 299 } 300 301 static void hsw_pre_enable_crt(struct intel_atomic_state *state, 302 struct intel_encoder *encoder, 303 const struct intel_crtc_state *crtc_state, 304 const struct drm_connector_state *conn_state) 305 { 306 struct intel_display *display = to_intel_display(encoder); 307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 308 enum pipe pipe = crtc->pipe; 309 310 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 311 312 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 313 314 hsw_fdi_link_train(encoder, crtc_state); 315 316 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 317 } 318 319 static void hsw_enable_crt(struct intel_atomic_state *state, 320 struct intel_encoder *encoder, 321 const struct intel_crtc_state *crtc_state, 322 const struct drm_connector_state *conn_state) 323 { 324 struct intel_display *display = to_intel_display(encoder); 325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 326 enum pipe pipe = crtc->pipe; 327 328 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 329 330 intel_ddi_enable_transcoder_func(encoder, crtc_state); 331 332 intel_enable_transcoder(crtc_state); 333 334 lpt_pch_enable(state, crtc); 335 336 intel_crtc_vblank_on(crtc_state); 337 338 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 339 340 intel_crtc_wait_for_next_vblank(crtc); 341 intel_crtc_wait_for_next_vblank(crtc); 342 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 343 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 344 } 345 346 static void intel_enable_crt(struct intel_atomic_state *state, 347 struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state, 349 const struct drm_connector_state *conn_state) 350 { 351 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 352 } 353 354 static enum drm_mode_status 355 intel_crt_mode_valid(struct drm_connector *connector, 356 const struct drm_display_mode *mode) 357 { 358 struct intel_display *display = to_intel_display(connector->dev); 359 struct drm_i915_private *dev_priv = to_i915(connector->dev); 360 int max_dotclk = display->cdclk.max_dotclk_freq; 361 enum drm_mode_status status; 362 int max_clock; 363 364 status = intel_cpu_transcoder_mode_valid(display, mode); 365 if (status != MODE_OK) 366 return status; 367 368 if (mode->clock < 25000) 369 return MODE_CLOCK_LOW; 370 371 if (HAS_PCH_LPT(dev_priv)) 372 max_clock = 180000; 373 else if (IS_VALLEYVIEW(dev_priv)) 374 /* 375 * 270 MHz due to current DPLL limits, 376 * DAC limit supposedly 355 MHz. 377 */ 378 max_clock = 270000; 379 else if (IS_DISPLAY_VER(display, 3, 4)) 380 max_clock = 400000; 381 else 382 max_clock = 350000; 383 if (mode->clock > max_clock) 384 return MODE_CLOCK_HIGH; 385 386 if (mode->clock > max_dotclk) 387 return MODE_CLOCK_HIGH; 388 389 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 390 if (HAS_PCH_LPT(dev_priv) && 391 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 392 return MODE_CLOCK_HIGH; 393 394 /* HSW/BDW FDI limited to 4k */ 395 if (mode->hdisplay > 4096) 396 return MODE_H_ILLEGAL; 397 398 return MODE_OK; 399 } 400 401 static int intel_crt_compute_config(struct intel_encoder *encoder, 402 struct intel_crtc_state *crtc_state, 403 struct drm_connector_state *conn_state) 404 { 405 struct drm_display_mode *adjusted_mode = 406 &crtc_state->hw.adjusted_mode; 407 408 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 409 return -EINVAL; 410 411 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 412 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 413 414 return 0; 415 } 416 417 static int pch_crt_compute_config(struct intel_encoder *encoder, 418 struct intel_crtc_state *crtc_state, 419 struct drm_connector_state *conn_state) 420 { 421 struct drm_display_mode *adjusted_mode = 422 &crtc_state->hw.adjusted_mode; 423 424 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 425 return -EINVAL; 426 427 crtc_state->has_pch_encoder = true; 428 if (!intel_fdi_compute_pipe_bpp(crtc_state)) 429 return -EINVAL; 430 431 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 432 433 return 0; 434 } 435 436 static int hsw_crt_compute_config(struct intel_encoder *encoder, 437 struct intel_crtc_state *crtc_state, 438 struct drm_connector_state *conn_state) 439 { 440 struct intel_display *display = to_intel_display(encoder); 441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 442 struct drm_display_mode *adjusted_mode = 443 &crtc_state->hw.adjusted_mode; 444 445 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 446 return -EINVAL; 447 448 /* HSW/BDW FDI limited to 4k */ 449 if (adjusted_mode->crtc_hdisplay > 4096 || 450 adjusted_mode->crtc_hblank_start > 4096) 451 return -EINVAL; 452 453 crtc_state->has_pch_encoder = true; 454 if (!intel_fdi_compute_pipe_bpp(crtc_state)) 455 return -EINVAL; 456 457 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 458 459 /* LPT FDI RX only supports 8bpc. */ 460 if (HAS_PCH_LPT(dev_priv)) { 461 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ 462 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { 463 drm_dbg_kms(display->drm, 464 "LPT only supports 24bpp\n"); 465 return -EINVAL; 466 } 467 468 crtc_state->pipe_bpp = 24; 469 } 470 471 /* FDI must always be 2.7 GHz */ 472 crtc_state->port_clock = 135000 * 2; 473 474 crtc_state->enhanced_framing = true; 475 476 adjusted_mode->crtc_clock = lpt_iclkip(crtc_state); 477 478 return 0; 479 } 480 481 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 482 { 483 struct intel_display *display = to_intel_display(connector->dev); 484 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 485 struct drm_i915_private *dev_priv = to_i915(connector->dev); 486 u32 adpa; 487 bool ret; 488 489 /* The first time through, trigger an explicit detection cycle */ 490 if (crt->force_hotplug_required) { 491 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 492 u32 save_adpa; 493 494 crt->force_hotplug_required = false; 495 496 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); 497 drm_dbg_kms(display->drm, 498 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 499 500 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 501 if (turn_off_dac) 502 adpa &= ~ADPA_DAC_ENABLE; 503 504 intel_de_write(display, crt->adpa_reg, adpa); 505 506 if (intel_de_wait_for_clear(display, 507 crt->adpa_reg, 508 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 509 1000)) 510 drm_dbg_kms(display->drm, 511 "timed out waiting for FORCE_TRIGGER"); 512 513 if (turn_off_dac) { 514 intel_de_write(display, crt->adpa_reg, save_adpa); 515 intel_de_posting_read(display, crt->adpa_reg); 516 } 517 } 518 519 /* Check the status to see if both blue and green are on now */ 520 adpa = intel_de_read(display, crt->adpa_reg); 521 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 522 ret = true; 523 else 524 ret = false; 525 drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n", 526 adpa, ret); 527 528 return ret; 529 } 530 531 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 532 { 533 struct intel_display *display = to_intel_display(connector->dev); 534 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 535 struct drm_i915_private *dev_priv = to_i915(connector->dev); 536 bool reenable_hpd; 537 u32 adpa; 538 bool ret; 539 u32 save_adpa; 540 541 /* 542 * Doing a force trigger causes a hpd interrupt to get sent, which can 543 * get us stuck in a loop if we're polling: 544 * - We enable power wells and reset the ADPA 545 * - output_poll_exec does force probe on VGA, triggering a hpd 546 * - HPD handler waits for poll to unlock dev->mode_config.mutex 547 * - output_poll_exec shuts off the ADPA, unlocks 548 * dev->mode_config.mutex 549 * - HPD handler runs, resets ADPA and brings us back to the start 550 * 551 * Just disable HPD interrupts here to prevent this 552 */ 553 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 554 555 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); 556 drm_dbg_kms(display->drm, 557 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 558 559 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 560 561 intel_de_write(display, crt->adpa_reg, adpa); 562 563 if (intel_de_wait_for_clear(display, crt->adpa_reg, 564 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 565 drm_dbg_kms(display->drm, 566 "timed out waiting for FORCE_TRIGGER"); 567 intel_de_write(display, crt->adpa_reg, save_adpa); 568 } 569 570 /* Check the status to see if both blue and green are on now */ 571 adpa = intel_de_read(display, crt->adpa_reg); 572 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 573 ret = true; 574 else 575 ret = false; 576 577 drm_dbg_kms(display->drm, 578 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 579 580 if (reenable_hpd) 581 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 582 583 return ret; 584 } 585 586 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 587 { 588 struct intel_display *display = to_intel_display(connector->dev); 589 struct drm_i915_private *dev_priv = to_i915(connector->dev); 590 u32 stat; 591 bool ret = false; 592 int i, tries = 0; 593 594 if (HAS_PCH_SPLIT(dev_priv)) 595 return ilk_crt_detect_hotplug(connector); 596 597 if (IS_VALLEYVIEW(dev_priv)) 598 return valleyview_crt_detect_hotplug(connector); 599 600 /* 601 * On 4 series desktop, CRT detect sequence need to be done twice 602 * to get a reliable result. 603 */ 604 605 if (IS_G45(dev_priv)) 606 tries = 2; 607 else 608 tries = 1; 609 610 for (i = 0; i < tries ; i++) { 611 /* turn on the FORCE_DETECT */ 612 i915_hotplug_interrupt_update(dev_priv, 613 CRT_HOTPLUG_FORCE_DETECT, 614 CRT_HOTPLUG_FORCE_DETECT); 615 /* wait for FORCE_DETECT to go off */ 616 if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display), 617 CRT_HOTPLUG_FORCE_DETECT, 1000)) 618 drm_dbg_kms(display->drm, 619 "timed out waiting for FORCE_DETECT to go off"); 620 } 621 622 stat = intel_de_read(display, PORT_HOTPLUG_STAT(display)); 623 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 624 ret = true; 625 626 /* clear the interrupt we just generated, if any */ 627 intel_de_write(display, PORT_HOTPLUG_STAT(display), 628 CRT_HOTPLUG_INT_STATUS); 629 630 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 631 632 return ret; 633 } 634 635 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector, 636 struct i2c_adapter *ddc) 637 { 638 const struct drm_edid *drm_edid; 639 640 drm_edid = drm_edid_read_ddc(connector, ddc); 641 642 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 643 drm_dbg_kms(connector->dev, 644 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 645 intel_gmbus_force_bit(ddc, true); 646 drm_edid = drm_edid_read_ddc(connector, ddc); 647 intel_gmbus_force_bit(ddc, false); 648 } 649 650 return drm_edid; 651 } 652 653 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 654 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 655 struct i2c_adapter *ddc) 656 { 657 const struct drm_edid *drm_edid; 658 int ret; 659 660 drm_edid = intel_crt_get_edid(connector, ddc); 661 if (!drm_edid) 662 return 0; 663 664 ret = intel_connector_update_modes(connector, drm_edid); 665 666 drm_edid_free(drm_edid); 667 668 return ret; 669 } 670 671 static bool intel_crt_detect_ddc(struct drm_connector *connector) 672 { 673 struct intel_display *display = to_intel_display(connector->dev); 674 const struct drm_edid *drm_edid; 675 bool ret = false; 676 677 drm_edid = intel_crt_get_edid(connector, connector->ddc); 678 679 if (drm_edid) { 680 /* 681 * This may be a DVI-I connector with a shared DDC 682 * link between analog and digital outputs, so we 683 * have to check the EDID input spec of the attached device. 684 */ 685 if (drm_edid_is_digital(drm_edid)) { 686 drm_dbg_kms(display->drm, 687 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 688 } else { 689 drm_dbg_kms(display->drm, 690 "CRT detected via DDC:0x50 [EDID]\n"); 691 ret = true; 692 } 693 } else { 694 drm_dbg_kms(display->drm, 695 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); 696 } 697 698 drm_edid_free(drm_edid); 699 700 return ret; 701 } 702 703 static enum drm_connector_status 704 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) 705 { 706 struct intel_display *display = to_intel_display(&crt->base); 707 enum transcoder cpu_transcoder = (enum transcoder)pipe; 708 u32 save_bclrpat; 709 u32 save_vtotal; 710 u32 vtotal, vactive; 711 u32 vsample; 712 u32 vblank, vblank_start, vblank_end; 713 u32 dsl; 714 u8 st00; 715 enum drm_connector_status status; 716 717 drm_dbg_kms(display->drm, "starting load-detect on CRT\n"); 718 719 save_bclrpat = intel_de_read(display, 720 BCLRPAT(display, cpu_transcoder)); 721 save_vtotal = intel_de_read(display, 722 TRANS_VTOTAL(display, cpu_transcoder)); 723 vblank = intel_de_read(display, 724 TRANS_VBLANK(display, cpu_transcoder)); 725 726 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; 727 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; 728 729 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; 730 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; 731 732 /* Set the border color to purple. */ 733 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050); 734 735 if (DISPLAY_VER(display) != 2) { 736 u32 transconf = intel_de_read(display, 737 TRANSCONF(display, cpu_transcoder)); 738 739 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 740 transconf | TRANSCONF_FORCE_BORDER); 741 intel_de_posting_read(display, 742 TRANSCONF(display, cpu_transcoder)); 743 /* 744 * Wait for next Vblank to substitute 745 * border color for Color info. 746 */ 747 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 748 st00 = intel_de_read8(display, _VGA_MSR_WRITE); 749 status = ((st00 & (1 << 4)) != 0) ? 750 connector_status_connected : 751 connector_status_disconnected; 752 753 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 754 transconf); 755 } else { 756 bool restore_vblank = false; 757 int count, detect; 758 759 /* 760 * If there isn't any border, add some. 761 * Yes, this will flicker 762 */ 763 if (vblank_start <= vactive && vblank_end >= vtotal) { 764 u32 vsync = intel_de_read(display, 765 TRANS_VSYNC(display, cpu_transcoder)); 766 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; 767 768 vblank_start = vsync_start; 769 intel_de_write(display, 770 TRANS_VBLANK(display, cpu_transcoder), 771 VBLANK_START(vblank_start - 1) | 772 VBLANK_END(vblank_end - 1)); 773 restore_vblank = true; 774 } 775 /* sample in the vertical border, selecting the larger one */ 776 if (vblank_start - vactive >= vtotal - vblank_end) 777 vsample = (vblank_start + vactive) >> 1; 778 else 779 vsample = (vtotal + vblank_end) >> 1; 780 781 /* 782 * Wait for the border to be displayed 783 */ 784 while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive) 785 ; 786 while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample) 787 ; 788 /* 789 * Watch ST00 for an entire scanline 790 */ 791 detect = 0; 792 count = 0; 793 do { 794 count++; 795 /* Read the ST00 VGA status register */ 796 st00 = intel_de_read8(display, _VGA_MSR_WRITE); 797 if (st00 & (1 << 4)) 798 detect++; 799 } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl)); 800 801 /* restore vblank if necessary */ 802 if (restore_vblank) 803 intel_de_write(display, 804 TRANS_VBLANK(display, cpu_transcoder), 805 vblank); 806 /* 807 * If more than 3/4 of the scanline detected a monitor, 808 * then it is assumed to be present. This works even on i830, 809 * where there isn't any way to force the border color across 810 * the screen 811 */ 812 status = detect * 4 > count * 3 ? 813 connector_status_connected : 814 connector_status_disconnected; 815 } 816 817 /* Restore previous settings */ 818 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 819 save_bclrpat); 820 821 return status; 822 } 823 824 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 825 { 826 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 827 return 1; 828 } 829 830 static const struct dmi_system_id intel_spurious_crt_detect[] = { 831 { 832 .callback = intel_spurious_crt_detect_dmi_callback, 833 .ident = "ACER ZGB", 834 .matches = { 835 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 836 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 837 }, 838 }, 839 { 840 .callback = intel_spurious_crt_detect_dmi_callback, 841 .ident = "Intel DZ77BH-55K", 842 .matches = { 843 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 844 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 845 }, 846 }, 847 { } 848 }; 849 850 static int 851 intel_crt_detect(struct drm_connector *connector, 852 struct drm_modeset_acquire_ctx *ctx, 853 bool force) 854 { 855 struct intel_display *display = to_intel_display(connector->dev); 856 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 857 struct intel_encoder *encoder = &crt->base; 858 struct drm_atomic_state *state; 859 intel_wakeref_t wakeref; 860 int status; 861 862 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", 863 connector->base.id, connector->name, 864 force); 865 866 if (!intel_display_device_enabled(display)) 867 return connector_status_disconnected; 868 869 if (!intel_display_driver_check_access(display)) 870 return connector->status; 871 872 if (display->params.load_detect_test) { 873 wakeref = intel_display_power_get(display, encoder->power_domain); 874 goto load_detect; 875 } 876 877 /* Skip machines without VGA that falsely report hotplug events */ 878 if (dmi_check_system(intel_spurious_crt_detect)) 879 return connector_status_disconnected; 880 881 wakeref = intel_display_power_get(display, encoder->power_domain); 882 883 if (I915_HAS_HOTPLUG(display)) { 884 /* We can not rely on the HPD pin always being correctly wired 885 * up, for example many KVM do not pass it through, and so 886 * only trust an assertion that the monitor is connected. 887 */ 888 if (intel_crt_detect_hotplug(connector)) { 889 drm_dbg_kms(display->drm, 890 "CRT detected via hotplug\n"); 891 status = connector_status_connected; 892 goto out; 893 } else 894 drm_dbg_kms(display->drm, 895 "CRT not detected via hotplug\n"); 896 } 897 898 if (intel_crt_detect_ddc(connector)) { 899 status = connector_status_connected; 900 goto out; 901 } 902 903 /* Load detection is broken on HPD capable machines. Whoever wants a 904 * broken monitor (without edid) to work behind a broken kvm (that fails 905 * to have the right resistors for HP detection) needs to fix this up. 906 * For now just bail out. */ 907 if (I915_HAS_HOTPLUG(display)) { 908 status = connector_status_disconnected; 909 goto out; 910 } 911 912 load_detect: 913 if (!force) { 914 status = connector->status; 915 goto out; 916 } 917 918 /* for pre-945g platforms use load detect */ 919 state = intel_load_detect_get_pipe(connector, ctx); 920 if (IS_ERR(state)) { 921 status = PTR_ERR(state); 922 } else if (!state) { 923 status = connector_status_unknown; 924 } else { 925 if (intel_crt_detect_ddc(connector)) 926 status = connector_status_connected; 927 else if (DISPLAY_VER(display) < 4) 928 status = intel_crt_load_detect(crt, 929 to_intel_crtc(connector->state->crtc)->pipe); 930 else if (display->params.load_detect_test) 931 status = connector_status_disconnected; 932 else 933 status = connector_status_unknown; 934 intel_load_detect_release_pipe(connector, state, ctx); 935 } 936 937 out: 938 intel_display_power_put(display, encoder->power_domain, wakeref); 939 940 return status; 941 } 942 943 static int intel_crt_get_modes(struct drm_connector *connector) 944 { 945 struct intel_display *display = to_intel_display(connector->dev); 946 struct drm_i915_private *dev_priv = to_i915(connector->dev); 947 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 948 struct intel_encoder *encoder = &crt->base; 949 intel_wakeref_t wakeref; 950 struct i2c_adapter *ddc; 951 int ret; 952 953 if (!intel_display_driver_check_access(display)) 954 return drm_edid_connector_add_modes(connector); 955 956 wakeref = intel_display_power_get(display, encoder->power_domain); 957 958 ret = intel_crt_ddc_get_modes(connector, connector->ddc); 959 if (ret || !IS_G4X(dev_priv)) 960 goto out; 961 962 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 963 ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB); 964 ret = intel_crt_ddc_get_modes(connector, ddc); 965 966 out: 967 intel_display_power_put(display, encoder->power_domain, wakeref); 968 969 return ret; 970 } 971 972 void intel_crt_reset(struct drm_encoder *encoder) 973 { 974 struct intel_display *display = to_intel_display(encoder->dev); 975 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 976 977 if (DISPLAY_VER(display) >= 5) { 978 u32 adpa; 979 980 adpa = intel_de_read(display, crt->adpa_reg); 981 adpa &= ~ADPA_HOTPLUG_MASK; 982 adpa |= ADPA_HOTPLUG_BITS; 983 intel_de_write(display, crt->adpa_reg, adpa); 984 intel_de_posting_read(display, crt->adpa_reg); 985 986 drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa); 987 crt->force_hotplug_required = true; 988 } 989 990 } 991 992 /* 993 * Routines for controlling stuff on the analog port 994 */ 995 996 static const struct drm_connector_funcs intel_crt_connector_funcs = { 997 .fill_modes = drm_helper_probe_single_connector_modes, 998 .late_register = intel_connector_register, 999 .early_unregister = intel_connector_unregister, 1000 .destroy = intel_connector_destroy, 1001 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1002 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1003 }; 1004 1005 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 1006 .detect_ctx = intel_crt_detect, 1007 .mode_valid = intel_crt_mode_valid, 1008 .get_modes = intel_crt_get_modes, 1009 }; 1010 1011 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 1012 .reset = intel_crt_reset, 1013 .destroy = intel_encoder_destroy, 1014 }; 1015 1016 void intel_crt_init(struct intel_display *display) 1017 { 1018 struct drm_i915_private *dev_priv = to_i915(display->drm); 1019 struct intel_connector *connector; 1020 struct intel_crt *crt; 1021 i915_reg_t adpa_reg; 1022 u8 ddc_pin; 1023 u32 adpa; 1024 1025 if (HAS_PCH_SPLIT(dev_priv)) 1026 adpa_reg = PCH_ADPA; 1027 else if (IS_VALLEYVIEW(dev_priv)) 1028 adpa_reg = VLV_ADPA; 1029 else 1030 adpa_reg = ADPA; 1031 1032 adpa = intel_de_read(display, adpa_reg); 1033 if ((adpa & ADPA_DAC_ENABLE) == 0) { 1034 /* 1035 * On some machines (some IVB at least) CRT can be 1036 * fused off, but there's no known fuse bit to 1037 * indicate that. On these machine the ADPA register 1038 * works normally, except the DAC enable bit won't 1039 * take. So the only way to tell is attempt to enable 1040 * it and see what happens. 1041 */ 1042 intel_de_write(display, adpa_reg, 1043 adpa | ADPA_DAC_ENABLE | 1044 ADPA_HSYNC_CNTL_DISABLE | 1045 ADPA_VSYNC_CNTL_DISABLE); 1046 if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1047 return; 1048 intel_de_write(display, adpa_reg, adpa); 1049 } 1050 1051 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 1052 if (!crt) 1053 return; 1054 1055 connector = intel_connector_alloc(); 1056 if (!connector) { 1057 kfree(crt); 1058 return; 1059 } 1060 1061 ddc_pin = display->vbt.crt_ddc_pin; 1062 1063 drm_connector_init_with_ddc(display->drm, &connector->base, 1064 &intel_crt_connector_funcs, 1065 DRM_MODE_CONNECTOR_VGA, 1066 intel_gmbus_get_adapter(display, ddc_pin)); 1067 1068 drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs, 1069 DRM_MODE_ENCODER_DAC, "CRT"); 1070 1071 intel_connector_attach_encoder(connector, &crt->base); 1072 1073 crt->base.type = INTEL_OUTPUT_ANALOG; 1074 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); 1075 if (IS_I830(dev_priv)) 1076 crt->base.pipe_mask = BIT(PIPE_A); 1077 else 1078 crt->base.pipe_mask = ~0; 1079 1080 if (DISPLAY_VER(display) != 2) 1081 connector->base.interlace_allowed = true; 1082 1083 crt->adpa_reg = adpa_reg; 1084 1085 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1086 1087 if (I915_HAS_HOTPLUG(display) && 1088 !dmi_check_system(intel_spurious_crt_detect)) { 1089 crt->base.hpd_pin = HPD_CRT; 1090 crt->base.hotplug = intel_encoder_hotplug; 1091 connector->polled = DRM_CONNECTOR_POLL_HPD; 1092 } else { 1093 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1094 } 1095 connector->base.polled = connector->polled; 1096 1097 if (HAS_DDI(display)) { 1098 assert_port_valid(display, PORT_E); 1099 1100 crt->base.port = PORT_E; 1101 crt->base.get_config = hsw_crt_get_config; 1102 crt->base.get_hw_state = intel_ddi_get_hw_state; 1103 crt->base.compute_config = hsw_crt_compute_config; 1104 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1105 crt->base.pre_enable = hsw_pre_enable_crt; 1106 crt->base.enable = hsw_enable_crt; 1107 crt->base.disable = hsw_disable_crt; 1108 crt->base.post_disable = hsw_post_disable_crt; 1109 crt->base.enable_clock = hsw_ddi_enable_clock; 1110 crt->base.disable_clock = hsw_ddi_disable_clock; 1111 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; 1112 1113 intel_ddi_buf_trans_init(&crt->base); 1114 } else { 1115 if (HAS_PCH_SPLIT(dev_priv)) { 1116 crt->base.compute_config = pch_crt_compute_config; 1117 crt->base.disable = pch_disable_crt; 1118 crt->base.post_disable = pch_post_disable_crt; 1119 } else { 1120 crt->base.compute_config = intel_crt_compute_config; 1121 crt->base.disable = intel_disable_crt; 1122 } 1123 crt->base.port = PORT_NONE; 1124 crt->base.get_config = intel_crt_get_config; 1125 crt->base.get_hw_state = intel_crt_get_hw_state; 1126 crt->base.enable = intel_enable_crt; 1127 } 1128 connector->get_hw_state = intel_connector_get_hw_state; 1129 1130 drm_connector_helper_add(&connector->base, &intel_crt_connector_helper_funcs); 1131 1132 /* 1133 * TODO: find a proper way to discover whether we need to set the the 1134 * polarity and link reversal bits or not, instead of relying on the 1135 * BIOS. 1136 */ 1137 if (HAS_PCH_LPT(dev_priv)) { 1138 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1139 FDI_RX_LINK_REVERSAL_OVERRIDE; 1140 1141 display->fdi.rx_config = intel_de_read(display, 1142 FDI_RX_CTL(PIPE_A)) & fdi_config; 1143 } 1144 1145 intel_crt_reset(&crt->base.base); 1146 } 1147