1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35
36 #include "i915_drv.h"
37 #include "i915_irq.h"
38 #include "i915_reg.h"
39 #include "intel_connector.h"
40 #include "intel_crt.h"
41 #include "intel_crtc.h"
42 #include "intel_ddi.h"
43 #include "intel_ddi_buf_trans.h"
44 #include "intel_de.h"
45 #include "intel_display_driver.h"
46 #include "intel_display_types.h"
47 #include "intel_fdi.h"
48 #include "intel_fdi_regs.h"
49 #include "intel_fifo_underrun.h"
50 #include "intel_gmbus.h"
51 #include "intel_hotplug.h"
52 #include "intel_hotplug_irq.h"
53 #include "intel_load_detect.h"
54 #include "intel_pch_display.h"
55 #include "intel_pch_refclk.h"
56
57 /* Here's the desired hotplug mode */
58 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
59 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
60 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
61 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
62 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
63 ADPA_CRT_HOTPLUG_ENABLE)
64
65 struct intel_crt {
66 struct intel_encoder base;
67 /* DPMS state is stored in the connector, which we need in the
68 * encoder's enable/disable callbacks */
69 struct intel_connector *connector;
70 bool force_hotplug_required;
71 i915_reg_t adpa_reg;
72 };
73
intel_encoder_to_crt(struct intel_encoder * encoder)74 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
75 {
76 return container_of(encoder, struct intel_crt, base);
77 }
78
intel_attached_crt(struct intel_connector * connector)79 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
80 {
81 return intel_encoder_to_crt(intel_attached_encoder(connector));
82 }
83
intel_crt_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t adpa_reg,enum pipe * pipe)84 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
85 i915_reg_t adpa_reg, enum pipe *pipe)
86 {
87 u32 val;
88
89 val = intel_de_read(dev_priv, adpa_reg);
90
91 /* asserts want to know the pipe even if the port is disabled */
92 if (HAS_PCH_CPT(dev_priv))
93 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
94 else
95 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
96
97 return val & ADPA_DAC_ENABLE;
98 }
99
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)100 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
101 enum pipe *pipe)
102 {
103 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
104 struct intel_crt *crt = intel_encoder_to_crt(encoder);
105 intel_wakeref_t wakeref;
106 bool ret;
107
108 wakeref = intel_display_power_get_if_enabled(dev_priv,
109 encoder->power_domain);
110 if (!wakeref)
111 return false;
112
113 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
114
115 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
116
117 return ret;
118 }
119
intel_crt_get_flags(struct intel_encoder * encoder)120 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
121 {
122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
123 struct intel_crt *crt = intel_encoder_to_crt(encoder);
124 u32 tmp, flags = 0;
125
126 tmp = intel_de_read(dev_priv, crt->adpa_reg);
127
128 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
129 flags |= DRM_MODE_FLAG_PHSYNC;
130 else
131 flags |= DRM_MODE_FLAG_NHSYNC;
132
133 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
134 flags |= DRM_MODE_FLAG_PVSYNC;
135 else
136 flags |= DRM_MODE_FLAG_NVSYNC;
137
138 return flags;
139 }
140
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)141 static void intel_crt_get_config(struct intel_encoder *encoder,
142 struct intel_crtc_state *pipe_config)
143 {
144 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
145
146 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
147
148 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
149 }
150
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)151 static void hsw_crt_get_config(struct intel_encoder *encoder,
152 struct intel_crtc_state *pipe_config)
153 {
154 lpt_pch_get_config(pipe_config);
155
156 hsw_ddi_get_config(encoder, pipe_config);
157
158 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
159 DRM_MODE_FLAG_NHSYNC |
160 DRM_MODE_FLAG_PVSYNC |
161 DRM_MODE_FLAG_NVSYNC);
162 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
163 }
164
165 /* Note: The caller is required to filter out dpms modes not supported by the
166 * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int mode)167 static void intel_crt_set_dpms(struct intel_encoder *encoder,
168 const struct intel_crtc_state *crtc_state,
169 int mode)
170 {
171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
172 struct intel_crt *crt = intel_encoder_to_crt(encoder);
173 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
174 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
175 u32 adpa;
176
177 if (DISPLAY_VER(dev_priv) >= 5)
178 adpa = ADPA_HOTPLUG_BITS;
179 else
180 adpa = 0;
181
182 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
183 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
184 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
185 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
186
187 /* For CPT allow 3 pipe config, for others just use A or B */
188 if (HAS_PCH_LPT(dev_priv))
189 ; /* Those bits don't exist here */
190 else if (HAS_PCH_CPT(dev_priv))
191 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
192 else
193 adpa |= ADPA_PIPE_SEL(crtc->pipe);
194
195 if (!HAS_PCH_SPLIT(dev_priv))
196 intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
197
198 switch (mode) {
199 case DRM_MODE_DPMS_ON:
200 adpa |= ADPA_DAC_ENABLE;
201 break;
202 case DRM_MODE_DPMS_STANDBY:
203 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
204 break;
205 case DRM_MODE_DPMS_SUSPEND:
206 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
207 break;
208 case DRM_MODE_DPMS_OFF:
209 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
210 break;
211 }
212
213 intel_de_write(dev_priv, crt->adpa_reg, adpa);
214 }
215
intel_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)216 static void intel_disable_crt(struct intel_atomic_state *state,
217 struct intel_encoder *encoder,
218 const struct intel_crtc_state *old_crtc_state,
219 const struct drm_connector_state *old_conn_state)
220 {
221 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
222 }
223
pch_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)224 static void pch_disable_crt(struct intel_atomic_state *state,
225 struct intel_encoder *encoder,
226 const struct intel_crtc_state *old_crtc_state,
227 const struct drm_connector_state *old_conn_state)
228 {
229 }
230
pch_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)231 static void pch_post_disable_crt(struct intel_atomic_state *state,
232 struct intel_encoder *encoder,
233 const struct intel_crtc_state *old_crtc_state,
234 const struct drm_connector_state *old_conn_state)
235 {
236 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
237 }
238
hsw_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)239 static void hsw_disable_crt(struct intel_atomic_state *state,
240 struct intel_encoder *encoder,
241 const struct intel_crtc_state *old_crtc_state,
242 const struct drm_connector_state *old_conn_state)
243 {
244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
245
246 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
247
248 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
249 }
250
hsw_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)251 static void hsw_post_disable_crt(struct intel_atomic_state *state,
252 struct intel_encoder *encoder,
253 const struct intel_crtc_state *old_crtc_state,
254 const struct drm_connector_state *old_conn_state)
255 {
256 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
258
259 intel_crtc_vblank_off(old_crtc_state);
260
261 intel_disable_transcoder(old_crtc_state);
262
263 intel_ddi_disable_transcoder_func(old_crtc_state);
264
265 ilk_pfit_disable(old_crtc_state);
266
267 intel_ddi_disable_transcoder_clock(old_crtc_state);
268
269 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
270
271 lpt_pch_disable(state, crtc);
272
273 hsw_fdi_disable(encoder);
274
275 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
276
277 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
278 }
279
hsw_pre_pll_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)280 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
281 struct intel_encoder *encoder,
282 const struct intel_crtc_state *crtc_state,
283 const struct drm_connector_state *conn_state)
284 {
285 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
286
287 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
288
289 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
290 }
291
hsw_pre_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)292 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
293 struct intel_encoder *encoder,
294 const struct intel_crtc_state *crtc_state,
295 const struct drm_connector_state *conn_state)
296 {
297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
298 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
299 enum pipe pipe = crtc->pipe;
300
301 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
302
303 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
304
305 hsw_fdi_link_train(encoder, crtc_state);
306
307 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
308 }
309
hsw_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)310 static void hsw_enable_crt(struct intel_atomic_state *state,
311 struct intel_encoder *encoder,
312 const struct intel_crtc_state *crtc_state,
313 const struct drm_connector_state *conn_state)
314 {
315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
316 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
317 enum pipe pipe = crtc->pipe;
318
319 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
320
321 intel_ddi_enable_transcoder_func(encoder, crtc_state);
322
323 intel_enable_transcoder(crtc_state);
324
325 lpt_pch_enable(state, crtc);
326
327 intel_crtc_vblank_on(crtc_state);
328
329 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
330
331 intel_crtc_wait_for_next_vblank(crtc);
332 intel_crtc_wait_for_next_vblank(crtc);
333 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
334 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
335 }
336
intel_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)337 static void intel_enable_crt(struct intel_atomic_state *state,
338 struct intel_encoder *encoder,
339 const struct intel_crtc_state *crtc_state,
340 const struct drm_connector_state *conn_state)
341 {
342 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
343 }
344
345 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)346 intel_crt_mode_valid(struct drm_connector *connector,
347 struct drm_display_mode *mode)
348 {
349 struct drm_device *dev = connector->dev;
350 struct drm_i915_private *dev_priv = to_i915(dev);
351 int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
352 enum drm_mode_status status;
353 int max_clock;
354
355 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
356 if (status != MODE_OK)
357 return status;
358
359 if (mode->clock < 25000)
360 return MODE_CLOCK_LOW;
361
362 if (HAS_PCH_LPT(dev_priv))
363 max_clock = 180000;
364 else if (IS_VALLEYVIEW(dev_priv))
365 /*
366 * 270 MHz due to current DPLL limits,
367 * DAC limit supposedly 355 MHz.
368 */
369 max_clock = 270000;
370 else if (IS_DISPLAY_VER(dev_priv, 3, 4))
371 max_clock = 400000;
372 else
373 max_clock = 350000;
374 if (mode->clock > max_clock)
375 return MODE_CLOCK_HIGH;
376
377 if (mode->clock > max_dotclk)
378 return MODE_CLOCK_HIGH;
379
380 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
381 if (HAS_PCH_LPT(dev_priv) &&
382 ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
383 return MODE_CLOCK_HIGH;
384
385 /* HSW/BDW FDI limited to 4k */
386 if (mode->hdisplay > 4096)
387 return MODE_H_ILLEGAL;
388
389 return MODE_OK;
390 }
391
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)392 static int intel_crt_compute_config(struct intel_encoder *encoder,
393 struct intel_crtc_state *pipe_config,
394 struct drm_connector_state *conn_state)
395 {
396 struct drm_display_mode *adjusted_mode =
397 &pipe_config->hw.adjusted_mode;
398
399 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
400 return -EINVAL;
401
402 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
403 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
404
405 return 0;
406 }
407
pch_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)408 static int pch_crt_compute_config(struct intel_encoder *encoder,
409 struct intel_crtc_state *pipe_config,
410 struct drm_connector_state *conn_state)
411 {
412 struct drm_display_mode *adjusted_mode =
413 &pipe_config->hw.adjusted_mode;
414
415 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
416 return -EINVAL;
417
418 pipe_config->has_pch_encoder = true;
419 if (!intel_fdi_compute_pipe_bpp(pipe_config))
420 return -EINVAL;
421
422 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
423
424 return 0;
425 }
426
hsw_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)427 static int hsw_crt_compute_config(struct intel_encoder *encoder,
428 struct intel_crtc_state *pipe_config,
429 struct drm_connector_state *conn_state)
430 {
431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
432 struct drm_display_mode *adjusted_mode =
433 &pipe_config->hw.adjusted_mode;
434
435 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
436 return -EINVAL;
437
438 /* HSW/BDW FDI limited to 4k */
439 if (adjusted_mode->crtc_hdisplay > 4096 ||
440 adjusted_mode->crtc_hblank_start > 4096)
441 return -EINVAL;
442
443 pipe_config->has_pch_encoder = true;
444 if (!intel_fdi_compute_pipe_bpp(pipe_config))
445 return -EINVAL;
446
447 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
448
449 /* LPT FDI RX only supports 8bpc. */
450 if (HAS_PCH_LPT(dev_priv)) {
451 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
452 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
453 drm_dbg_kms(&dev_priv->drm,
454 "LPT only supports 24bpp\n");
455 return -EINVAL;
456 }
457
458 pipe_config->pipe_bpp = 24;
459 }
460
461 /* FDI must always be 2.7 GHz */
462 pipe_config->port_clock = 135000 * 2;
463
464 pipe_config->enhanced_framing = true;
465
466 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
467
468 return 0;
469 }
470
ilk_crt_detect_hotplug(struct drm_connector * connector)471 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
472 {
473 struct drm_device *dev = connector->dev;
474 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
475 struct drm_i915_private *dev_priv = to_i915(dev);
476 u32 adpa;
477 bool ret;
478
479 /* The first time through, trigger an explicit detection cycle */
480 if (crt->force_hotplug_required) {
481 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
482 u32 save_adpa;
483
484 crt->force_hotplug_required = false;
485
486 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
487 drm_dbg_kms(&dev_priv->drm,
488 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
489
490 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
491 if (turn_off_dac)
492 adpa &= ~ADPA_DAC_ENABLE;
493
494 intel_de_write(dev_priv, crt->adpa_reg, adpa);
495
496 if (intel_de_wait_for_clear(dev_priv,
497 crt->adpa_reg,
498 ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
499 1000))
500 drm_dbg_kms(&dev_priv->drm,
501 "timed out waiting for FORCE_TRIGGER");
502
503 if (turn_off_dac) {
504 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
505 intel_de_posting_read(dev_priv, crt->adpa_reg);
506 }
507 }
508
509 /* Check the status to see if both blue and green are on now */
510 adpa = intel_de_read(dev_priv, crt->adpa_reg);
511 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
512 ret = true;
513 else
514 ret = false;
515 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
516 adpa, ret);
517
518 return ret;
519 }
520
valleyview_crt_detect_hotplug(struct drm_connector * connector)521 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
522 {
523 struct drm_device *dev = connector->dev;
524 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
525 struct drm_i915_private *dev_priv = to_i915(dev);
526 bool reenable_hpd;
527 u32 adpa;
528 bool ret;
529 u32 save_adpa;
530
531 /*
532 * Doing a force trigger causes a hpd interrupt to get sent, which can
533 * get us stuck in a loop if we're polling:
534 * - We enable power wells and reset the ADPA
535 * - output_poll_exec does force probe on VGA, triggering a hpd
536 * - HPD handler waits for poll to unlock dev->mode_config.mutex
537 * - output_poll_exec shuts off the ADPA, unlocks
538 * dev->mode_config.mutex
539 * - HPD handler runs, resets ADPA and brings us back to the start
540 *
541 * Just disable HPD interrupts here to prevent this
542 */
543 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
544
545 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
546 drm_dbg_kms(&dev_priv->drm,
547 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
548
549 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
550
551 intel_de_write(dev_priv, crt->adpa_reg, adpa);
552
553 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
554 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
555 drm_dbg_kms(&dev_priv->drm,
556 "timed out waiting for FORCE_TRIGGER");
557 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
558 }
559
560 /* Check the status to see if both blue and green are on now */
561 adpa = intel_de_read(dev_priv, crt->adpa_reg);
562 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
563 ret = true;
564 else
565 ret = false;
566
567 drm_dbg_kms(&dev_priv->drm,
568 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
569
570 if (reenable_hpd)
571 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
572
573 return ret;
574 }
575
intel_crt_detect_hotplug(struct drm_connector * connector)576 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
577 {
578 struct drm_device *dev = connector->dev;
579 struct drm_i915_private *dev_priv = to_i915(dev);
580 u32 stat;
581 bool ret = false;
582 int i, tries = 0;
583
584 if (HAS_PCH_SPLIT(dev_priv))
585 return ilk_crt_detect_hotplug(connector);
586
587 if (IS_VALLEYVIEW(dev_priv))
588 return valleyview_crt_detect_hotplug(connector);
589
590 /*
591 * On 4 series desktop, CRT detect sequence need to be done twice
592 * to get a reliable result.
593 */
594
595 if (IS_G45(dev_priv))
596 tries = 2;
597 else
598 tries = 1;
599
600 for (i = 0; i < tries ; i++) {
601 /* turn on the FORCE_DETECT */
602 i915_hotplug_interrupt_update(dev_priv,
603 CRT_HOTPLUG_FORCE_DETECT,
604 CRT_HOTPLUG_FORCE_DETECT);
605 /* wait for FORCE_DETECT to go off */
606 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
607 CRT_HOTPLUG_FORCE_DETECT, 1000))
608 drm_dbg_kms(&dev_priv->drm,
609 "timed out waiting for FORCE_DETECT to go off");
610 }
611
612 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
613 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
614 ret = true;
615
616 /* clear the interrupt we just generated, if any */
617 intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
618 CRT_HOTPLUG_INT_STATUS);
619
620 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
621
622 return ret;
623 }
624
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * ddc)625 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
626 struct i2c_adapter *ddc)
627 {
628 const struct drm_edid *drm_edid;
629
630 drm_edid = drm_edid_read_ddc(connector, ddc);
631
632 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
633 drm_dbg_kms(connector->dev,
634 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
635 intel_gmbus_force_bit(ddc, true);
636 drm_edid = drm_edid_read_ddc(connector, ddc);
637 intel_gmbus_force_bit(ddc, false);
638 }
639
640 return drm_edid;
641 }
642
643 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * ddc)644 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
645 struct i2c_adapter *ddc)
646 {
647 const struct drm_edid *drm_edid;
648 int ret;
649
650 drm_edid = intel_crt_get_edid(connector, ddc);
651 if (!drm_edid)
652 return 0;
653
654 ret = intel_connector_update_modes(connector, drm_edid);
655
656 drm_edid_free(drm_edid);
657
658 return ret;
659 }
660
intel_crt_detect_ddc(struct drm_connector * connector)661 static bool intel_crt_detect_ddc(struct drm_connector *connector)
662 {
663 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
664 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
665 const struct drm_edid *drm_edid;
666 bool ret = false;
667
668 drm_edid = intel_crt_get_edid(connector, connector->ddc);
669
670 if (drm_edid) {
671 /*
672 * This may be a DVI-I connector with a shared DDC
673 * link between analog and digital outputs, so we
674 * have to check the EDID input spec of the attached device.
675 */
676 if (drm_edid_is_digital(drm_edid)) {
677 drm_dbg_kms(&dev_priv->drm,
678 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
679 } else {
680 drm_dbg_kms(&dev_priv->drm,
681 "CRT detected via DDC:0x50 [EDID]\n");
682 ret = true;
683 }
684 } else {
685 drm_dbg_kms(&dev_priv->drm,
686 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
687 }
688
689 drm_edid_free(drm_edid);
690
691 return ret;
692 }
693
694 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt,enum pipe pipe)695 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
696 {
697 struct drm_device *dev = crt->base.base.dev;
698 struct drm_i915_private *dev_priv = to_i915(dev);
699 enum transcoder cpu_transcoder = (enum transcoder)pipe;
700 u32 save_bclrpat;
701 u32 save_vtotal;
702 u32 vtotal, vactive;
703 u32 vsample;
704 u32 vblank, vblank_start, vblank_end;
705 u32 dsl;
706 u8 st00;
707 enum drm_connector_status status;
708
709 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
710
711 save_bclrpat = intel_de_read(dev_priv,
712 BCLRPAT(dev_priv, cpu_transcoder));
713 save_vtotal = intel_de_read(dev_priv,
714 TRANS_VTOTAL(dev_priv, cpu_transcoder));
715 vblank = intel_de_read(dev_priv,
716 TRANS_VBLANK(dev_priv, cpu_transcoder));
717
718 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
719 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
720
721 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
722 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
723
724 /* Set the border color to purple. */
725 intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
726
727 if (DISPLAY_VER(dev_priv) != 2) {
728 u32 transconf = intel_de_read(dev_priv,
729 TRANSCONF(dev_priv, cpu_transcoder));
730
731 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
732 transconf | TRANSCONF_FORCE_BORDER);
733 intel_de_posting_read(dev_priv,
734 TRANSCONF(dev_priv, cpu_transcoder));
735 /* Wait for next Vblank to substitue
736 * border color for Color info */
737 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
738 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
739 status = ((st00 & (1 << 4)) != 0) ?
740 connector_status_connected :
741 connector_status_disconnected;
742
743 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
744 transconf);
745 } else {
746 bool restore_vblank = false;
747 int count, detect;
748
749 /*
750 * If there isn't any border, add some.
751 * Yes, this will flicker
752 */
753 if (vblank_start <= vactive && vblank_end >= vtotal) {
754 u32 vsync = intel_de_read(dev_priv,
755 TRANS_VSYNC(dev_priv, cpu_transcoder));
756 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
757
758 vblank_start = vsync_start;
759 intel_de_write(dev_priv,
760 TRANS_VBLANK(dev_priv, cpu_transcoder),
761 VBLANK_START(vblank_start - 1) |
762 VBLANK_END(vblank_end - 1));
763 restore_vblank = true;
764 }
765 /* sample in the vertical border, selecting the larger one */
766 if (vblank_start - vactive >= vtotal - vblank_end)
767 vsample = (vblank_start + vactive) >> 1;
768 else
769 vsample = (vtotal + vblank_end) >> 1;
770
771 /*
772 * Wait for the border to be displayed
773 */
774 while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
775 ;
776 while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
777 ;
778 /*
779 * Watch ST00 for an entire scanline
780 */
781 detect = 0;
782 count = 0;
783 do {
784 count++;
785 /* Read the ST00 VGA status register */
786 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
787 if (st00 & (1 << 4))
788 detect++;
789 } while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
790
791 /* restore vblank if necessary */
792 if (restore_vblank)
793 intel_de_write(dev_priv,
794 TRANS_VBLANK(dev_priv, cpu_transcoder),
795 vblank);
796 /*
797 * If more than 3/4 of the scanline detected a monitor,
798 * then it is assumed to be present. This works even on i830,
799 * where there isn't any way to force the border color across
800 * the screen
801 */
802 status = detect * 4 > count * 3 ?
803 connector_status_connected :
804 connector_status_disconnected;
805 }
806
807 /* Restore previous settings */
808 intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
809 save_bclrpat);
810
811 return status;
812 }
813
intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id * id)814 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
815 {
816 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
817 return 1;
818 }
819
820 static const struct dmi_system_id intel_spurious_crt_detect[] = {
821 {
822 .callback = intel_spurious_crt_detect_dmi_callback,
823 .ident = "ACER ZGB",
824 .matches = {
825 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
826 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
827 },
828 },
829 {
830 .callback = intel_spurious_crt_detect_dmi_callback,
831 .ident = "Intel DZ77BH-55K",
832 .matches = {
833 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
834 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
835 },
836 },
837 { }
838 };
839
840 static int
intel_crt_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)841 intel_crt_detect(struct drm_connector *connector,
842 struct drm_modeset_acquire_ctx *ctx,
843 bool force)
844 {
845 struct drm_i915_private *dev_priv = to_i915(connector->dev);
846 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
847 struct intel_encoder *intel_encoder = &crt->base;
848 struct drm_atomic_state *state;
849 intel_wakeref_t wakeref;
850 int status;
851
852 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
853 connector->base.id, connector->name,
854 force);
855
856 if (!intel_display_device_enabled(dev_priv))
857 return connector_status_disconnected;
858
859 if (!intel_display_driver_check_access(dev_priv))
860 return connector->status;
861
862 if (dev_priv->display.params.load_detect_test) {
863 wakeref = intel_display_power_get(dev_priv,
864 intel_encoder->power_domain);
865 goto load_detect;
866 }
867
868 /* Skip machines without VGA that falsely report hotplug events */
869 if (dmi_check_system(intel_spurious_crt_detect))
870 return connector_status_disconnected;
871
872 wakeref = intel_display_power_get(dev_priv,
873 intel_encoder->power_domain);
874
875 if (I915_HAS_HOTPLUG(dev_priv)) {
876 /* We can not rely on the HPD pin always being correctly wired
877 * up, for example many KVM do not pass it through, and so
878 * only trust an assertion that the monitor is connected.
879 */
880 if (intel_crt_detect_hotplug(connector)) {
881 drm_dbg_kms(&dev_priv->drm,
882 "CRT detected via hotplug\n");
883 status = connector_status_connected;
884 goto out;
885 } else
886 drm_dbg_kms(&dev_priv->drm,
887 "CRT not detected via hotplug\n");
888 }
889
890 if (intel_crt_detect_ddc(connector)) {
891 status = connector_status_connected;
892 goto out;
893 }
894
895 /* Load detection is broken on HPD capable machines. Whoever wants a
896 * broken monitor (without edid) to work behind a broken kvm (that fails
897 * to have the right resistors for HP detection) needs to fix this up.
898 * For now just bail out. */
899 if (I915_HAS_HOTPLUG(dev_priv)) {
900 status = connector_status_disconnected;
901 goto out;
902 }
903
904 load_detect:
905 if (!force) {
906 status = connector->status;
907 goto out;
908 }
909
910 /* for pre-945g platforms use load detect */
911 state = intel_load_detect_get_pipe(connector, ctx);
912 if (IS_ERR(state)) {
913 status = PTR_ERR(state);
914 } else if (!state) {
915 status = connector_status_unknown;
916 } else {
917 if (intel_crt_detect_ddc(connector))
918 status = connector_status_connected;
919 else if (DISPLAY_VER(dev_priv) < 4)
920 status = intel_crt_load_detect(crt,
921 to_intel_crtc(connector->state->crtc)->pipe);
922 else if (dev_priv->display.params.load_detect_test)
923 status = connector_status_disconnected;
924 else
925 status = connector_status_unknown;
926 intel_load_detect_release_pipe(connector, state, ctx);
927 }
928
929 out:
930 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
931
932 return status;
933 }
934
intel_crt_get_modes(struct drm_connector * connector)935 static int intel_crt_get_modes(struct drm_connector *connector)
936 {
937 struct drm_device *dev = connector->dev;
938 struct drm_i915_private *dev_priv = to_i915(dev);
939 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
940 struct intel_encoder *intel_encoder = &crt->base;
941 intel_wakeref_t wakeref;
942 struct i2c_adapter *ddc;
943 int ret;
944
945 if (!intel_display_driver_check_access(dev_priv))
946 return drm_edid_connector_add_modes(connector);
947
948 wakeref = intel_display_power_get(dev_priv,
949 intel_encoder->power_domain);
950
951 ret = intel_crt_ddc_get_modes(connector, connector->ddc);
952 if (ret || !IS_G4X(dev_priv))
953 goto out;
954
955 /* Try to probe digital port for output in DVI-I -> VGA mode. */
956 ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
957 ret = intel_crt_ddc_get_modes(connector, ddc);
958
959 out:
960 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
961
962 return ret;
963 }
964
intel_crt_reset(struct drm_encoder * encoder)965 void intel_crt_reset(struct drm_encoder *encoder)
966 {
967 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
968 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
969
970 if (DISPLAY_VER(dev_priv) >= 5) {
971 u32 adpa;
972
973 adpa = intel_de_read(dev_priv, crt->adpa_reg);
974 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
975 adpa |= ADPA_HOTPLUG_BITS;
976 intel_de_write(dev_priv, crt->adpa_reg, adpa);
977 intel_de_posting_read(dev_priv, crt->adpa_reg);
978
979 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
980 crt->force_hotplug_required = true;
981 }
982
983 }
984
985 /*
986 * Routines for controlling stuff on the analog port
987 */
988
989 static const struct drm_connector_funcs intel_crt_connector_funcs = {
990 .fill_modes = drm_helper_probe_single_connector_modes,
991 .late_register = intel_connector_register,
992 .early_unregister = intel_connector_unregister,
993 .destroy = intel_connector_destroy,
994 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
995 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
996 };
997
998 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
999 .detect_ctx = intel_crt_detect,
1000 .mode_valid = intel_crt_mode_valid,
1001 .get_modes = intel_crt_get_modes,
1002 };
1003
1004 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
1005 .reset = intel_crt_reset,
1006 .destroy = intel_encoder_destroy,
1007 };
1008
intel_crt_init(struct drm_i915_private * dev_priv)1009 void intel_crt_init(struct drm_i915_private *dev_priv)
1010 {
1011 struct drm_connector *connector;
1012 struct intel_crt *crt;
1013 struct intel_connector *intel_connector;
1014 i915_reg_t adpa_reg;
1015 u8 ddc_pin;
1016 u32 adpa;
1017
1018 if (HAS_PCH_SPLIT(dev_priv))
1019 adpa_reg = PCH_ADPA;
1020 else if (IS_VALLEYVIEW(dev_priv))
1021 adpa_reg = VLV_ADPA;
1022 else
1023 adpa_reg = ADPA;
1024
1025 adpa = intel_de_read(dev_priv, adpa_reg);
1026 if ((adpa & ADPA_DAC_ENABLE) == 0) {
1027 /*
1028 * On some machines (some IVB at least) CRT can be
1029 * fused off, but there's no known fuse bit to
1030 * indicate that. On these machine the ADPA register
1031 * works normally, except the DAC enable bit won't
1032 * take. So the only way to tell is attempt to enable
1033 * it and see what happens.
1034 */
1035 intel_de_write(dev_priv, adpa_reg,
1036 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1037 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1038 return;
1039 intel_de_write(dev_priv, adpa_reg, adpa);
1040 }
1041
1042 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1043 if (!crt)
1044 return;
1045
1046 intel_connector = intel_connector_alloc();
1047 if (!intel_connector) {
1048 kfree(crt);
1049 return;
1050 }
1051
1052 ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
1053
1054 connector = &intel_connector->base;
1055 crt->connector = intel_connector;
1056 drm_connector_init_with_ddc(&dev_priv->drm, connector,
1057 &intel_crt_connector_funcs,
1058 DRM_MODE_CONNECTOR_VGA,
1059 intel_gmbus_get_adapter(dev_priv, ddc_pin));
1060
1061 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1062 DRM_MODE_ENCODER_DAC, "CRT");
1063
1064 intel_connector_attach_encoder(intel_connector, &crt->base);
1065
1066 crt->base.type = INTEL_OUTPUT_ANALOG;
1067 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1068 if (IS_I830(dev_priv))
1069 crt->base.pipe_mask = BIT(PIPE_A);
1070 else
1071 crt->base.pipe_mask = ~0;
1072
1073 if (DISPLAY_VER(dev_priv) != 2)
1074 connector->interlace_allowed = true;
1075
1076 crt->adpa_reg = adpa_reg;
1077
1078 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1079
1080 if (I915_HAS_HOTPLUG(dev_priv) &&
1081 !dmi_check_system(intel_spurious_crt_detect)) {
1082 crt->base.hpd_pin = HPD_CRT;
1083 crt->base.hotplug = intel_encoder_hotplug;
1084 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1085 } else {
1086 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1087 }
1088 intel_connector->base.polled = intel_connector->polled;
1089
1090 if (HAS_DDI(dev_priv)) {
1091 assert_port_valid(dev_priv, PORT_E);
1092
1093 crt->base.port = PORT_E;
1094 crt->base.get_config = hsw_crt_get_config;
1095 crt->base.get_hw_state = intel_ddi_get_hw_state;
1096 crt->base.compute_config = hsw_crt_compute_config;
1097 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1098 crt->base.pre_enable = hsw_pre_enable_crt;
1099 crt->base.enable = hsw_enable_crt;
1100 crt->base.disable = hsw_disable_crt;
1101 crt->base.post_disable = hsw_post_disable_crt;
1102 crt->base.enable_clock = hsw_ddi_enable_clock;
1103 crt->base.disable_clock = hsw_ddi_disable_clock;
1104 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1105
1106 intel_ddi_buf_trans_init(&crt->base);
1107 } else {
1108 if (HAS_PCH_SPLIT(dev_priv)) {
1109 crt->base.compute_config = pch_crt_compute_config;
1110 crt->base.disable = pch_disable_crt;
1111 crt->base.post_disable = pch_post_disable_crt;
1112 } else {
1113 crt->base.compute_config = intel_crt_compute_config;
1114 crt->base.disable = intel_disable_crt;
1115 }
1116 crt->base.port = PORT_NONE;
1117 crt->base.get_config = intel_crt_get_config;
1118 crt->base.get_hw_state = intel_crt_get_hw_state;
1119 crt->base.enable = intel_enable_crt;
1120 }
1121 intel_connector->get_hw_state = intel_connector_get_hw_state;
1122
1123 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1124
1125 /*
1126 * TODO: find a proper way to discover whether we need to set the the
1127 * polarity and link reversal bits or not, instead of relying on the
1128 * BIOS.
1129 */
1130 if (HAS_PCH_LPT(dev_priv)) {
1131 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1132 FDI_RX_LINK_REVERSAL_OVERRIDE;
1133
1134 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
1135 FDI_RX_CTL(PIPE_A)) & fdi_config;
1136 }
1137
1138 intel_crt_reset(&crt->base.base);
1139 }
1140