1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __SKL_WATERMARK_H__ 7 #define __SKL_WATERMARK_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 #include "intel_global_state.h" 13 #include "intel_wm_types.h" 14 15 struct drm_i915_private; 16 struct intel_atomic_state; 17 struct intel_bw_state; 18 struct intel_crtc; 19 struct intel_crtc_state; 20 struct intel_display; 21 struct intel_plane; 22 struct intel_plane_state; 23 struct skl_pipe_wm; 24 struct skl_wm_level; 25 26 u8 intel_enabled_dbuf_slices_mask(struct intel_display *display); 27 28 void intel_sagv_pre_plane_update(struct intel_atomic_state *state); 29 void intel_sagv_post_plane_update(struct intel_atomic_state *state); 30 bool intel_can_enable_sagv(struct drm_i915_private *i915, 31 const struct intel_bw_state *bw_state); 32 bool intel_has_sagv(struct drm_i915_private *i915); 33 34 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, 35 const struct skl_ddb_entry *entry); 36 37 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 38 const struct skl_ddb_entry *entries, 39 int num_entries, int ignore_idx); 40 41 void intel_wm_state_verify(struct intel_atomic_state *state, 42 struct intel_crtc *crtc); 43 44 void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc); 45 void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, 46 struct intel_plane *plane); 47 48 void skl_watermark_ipc_init(struct drm_i915_private *i915); 49 void skl_watermark_ipc_update(struct drm_i915_private *i915); 50 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); 51 void skl_watermark_debugfs_register(struct drm_i915_private *i915); 52 53 unsigned int skl_watermark_max_latency(struct drm_i915_private *i915, 54 int initial_wm_level); 55 void skl_wm_init(struct drm_i915_private *i915); 56 57 const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, 58 enum plane_id plane_id, 59 int level); 60 const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, 61 enum plane_id plane_id); 62 unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, 63 struct intel_plane *plane, int width, 64 int height, int cpp); 65 66 struct intel_dbuf_state { 67 struct intel_global_state base; 68 69 struct skl_ddb_entry ddb[I915_MAX_PIPES]; 70 unsigned int weight[I915_MAX_PIPES]; 71 u8 slices[I915_MAX_PIPES]; 72 u8 enabled_slices; 73 u8 active_pipes; 74 u8 mdclk_cdclk_ratio; 75 bool joined_mbus; 76 }; 77 78 struct intel_dbuf_state * 79 intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 80 81 #define to_intel_dbuf_state(global_state) \ 82 container_of_const((global_state), struct intel_dbuf_state, base) 83 84 #define intel_atomic_get_old_dbuf_state(state) \ 85 to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj)) 86 #define intel_atomic_get_new_dbuf_state(state) \ 87 to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj)) 88 89 int intel_dbuf_init(struct drm_i915_private *i915); 90 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, 91 int ratio); 92 93 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); 94 void intel_dbuf_post_plane_update(struct intel_atomic_state *state); 95 void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, 96 int ratio, bool joined_mbus); 97 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); 98 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); 99 void intel_program_dpkgc_latency(struct intel_atomic_state *state); 100 101 #endif /* __SKL_WATERMARK_H__ */ 102 103