1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _TA_RAS_IF_H 25 #define _TA_RAS_IF_H 26 27 #define RAS_TA_HOST_IF_VER 0 28 29 /* Responses have bit 31 set */ 30 #define RSP_ID_MASK (1U << 31) 31 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) 32 33 /* invalid node instance value */ 34 #define TA_RAS_INV_NODE 0xffff 35 36 /* RAS related enumerations */ 37 /**********************************************************/ 38 enum ras_command { 39 TA_RAS_COMMAND__ENABLE_FEATURES = 0, 40 TA_RAS_COMMAND__DISABLE_FEATURES, 41 TA_RAS_COMMAND__TRIGGER_ERROR, 42 TA_RAS_COMMAND__QUERY_BLOCK_INFO, 43 TA_RAS_COMMAND__QUERY_SUB_BLOCK_INFO, 44 TA_RAS_COMMAND__QUERY_ADDRESS, 45 }; 46 47 enum ta_ras_status { 48 TA_RAS_STATUS__SUCCESS = 0x0000, 49 TA_RAS_STATUS__RESET_NEEDED = 0xA001, 50 TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0xA002, 51 TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003, 52 TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004, 53 TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0xA005, 54 TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0xA006, 55 TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007, 56 TA_RAS_STATUS__ERROR_TIMEOUT = 0xA008, 57 TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0XA009, 58 TA_RAS_STATUS__ERROR_GENERIC = 0xA00A, 59 TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B, 60 TA_RAS_STATUS__ERROR_GET_DEV_INFO = 0xA00C, 61 TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D, 62 TA_RAS_STATUS__ERROR_NOT_INITIALIZED = 0xA00E, 63 TA_RAS_STATUS__ERROR_TEE_INTERNAL = 0xA00F, 64 TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION = 0xA010, 65 TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011, 66 TA_RAS_STATUS__ERROR_RAS_READ_WRITE = 0xA012, 67 TA_RAS_STATUS__ERROR_NULL_PTR = 0xA013, 68 TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014, 69 TA_RAS_STATUS__ERROR_PCS_STATE_QUIET = 0xA015, 70 TA_RAS_STATUS__ERROR_PCS_STATE_ERROR = 0xA016, 71 TA_RAS_STATUS__ERROR_PCS_STATE_HANG = 0xA017, 72 TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN = 0xA018, 73 TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019, 74 TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED = 0xA01A 75 }; 76 77 enum ta_ras_block { 78 TA_RAS_BLOCK__UMC = 0, 79 TA_RAS_BLOCK__SDMA, 80 TA_RAS_BLOCK__GFX, 81 TA_RAS_BLOCK__MMHUB, 82 TA_RAS_BLOCK__ATHUB, 83 TA_RAS_BLOCK__PCIE_BIF, 84 TA_RAS_BLOCK__HDP, 85 TA_RAS_BLOCK__XGMI_WAFL, 86 TA_RAS_BLOCK__DF, 87 TA_RAS_BLOCK__SMN, 88 TA_RAS_BLOCK__SEM, 89 TA_RAS_BLOCK__MP0, 90 TA_RAS_BLOCK__MP1, 91 TA_RAS_BLOCK__FUSE, 92 TA_RAS_BLOCK__MCA, 93 TA_RAS_BLOCK__VCN, 94 TA_RAS_BLOCK__JPEG, 95 TA_NUM_BLOCK_MAX 96 }; 97 98 enum ta_ras_mca_block { 99 TA_RAS_MCA_BLOCK__MP0 = 0, 100 TA_RAS_MCA_BLOCK__MP1 = 1, 101 TA_RAS_MCA_BLOCK__MPIO = 2, 102 TA_RAS_MCA_BLOCK__IOHC = 3, 103 TA_MCA_NUM_BLOCK_MAX 104 }; 105 106 enum ta_ras_error_type { 107 TA_RAS_ERROR__NONE = 0, 108 TA_RAS_ERROR__PARITY = 1, 109 TA_RAS_ERROR__SINGLE_CORRECTABLE = 2, 110 TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 111 TA_RAS_ERROR__POISON = 8, 112 }; 113 114 enum ta_ras_address_type { 115 TA_RAS_MCA_TO_PA, 116 TA_RAS_PA_TO_MCA, 117 }; 118 119 enum ta_ras_nps_mode { 120 TA_RAS_UNKNOWN_MODE = 0, 121 TA_RAS_NPS1_MODE = 1, 122 TA_RAS_NPS2_MODE = 2, 123 TA_RAS_NPS4_MODE = 4, 124 TA_RAS_NPS8_MODE = 8, 125 }; 126 127 /* Input/output structures for RAS commands */ 128 /**********************************************************/ 129 130 struct ta_ras_enable_features_input { 131 enum ta_ras_block block_id; 132 enum ta_ras_error_type error_type; 133 }; 134 135 struct ta_ras_disable_features_input { 136 enum ta_ras_block block_id; 137 enum ta_ras_error_type error_type; 138 }; 139 140 struct ta_ras_trigger_error_input { 141 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx 142 enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable 143 uint32_t sub_block_index; // mem block. i.e. hbm, sram etc. 144 uint64_t address; // explicit address of error 145 uint64_t value; // method if error injection. i.e persistent, coherent etc. 146 }; 147 148 struct ta_ras_init_flags { 149 uint8_t poison_mode_en; 150 uint8_t dgpu_mode; 151 uint16_t xcc_mask; 152 uint8_t channel_dis_num; 153 uint8_t nps_mode; 154 }; 155 156 struct ta_ras_mca_addr { 157 uint64_t err_addr; 158 uint32_t ch_inst; 159 uint32_t umc_inst; 160 uint32_t node_inst; 161 uint32_t socket_id; 162 }; 163 164 struct ta_ras_phy_addr { 165 uint64_t pa; 166 uint32_t bank; 167 uint32_t channel_idx; 168 }; 169 170 struct ta_ras_query_address_input { 171 enum ta_ras_address_type addr_type; 172 struct ta_ras_mca_addr ma; 173 struct ta_ras_phy_addr pa; 174 }; 175 176 struct ta_ras_output_flags { 177 uint8_t ras_init_success_flag; 178 uint8_t err_inject_switch_disable_flag; 179 uint8_t reg_access_failure_flag; 180 }; 181 182 struct ta_ras_query_address_output { 183 /* don't use the flags here */ 184 struct ta_ras_output_flags flags; 185 struct ta_ras_mca_addr ma; 186 struct ta_ras_phy_addr pa; 187 }; 188 189 /* Common input structure for RAS callbacks */ 190 /**********************************************************/ 191 union ta_ras_cmd_input { 192 struct ta_ras_init_flags init_flags; 193 struct ta_ras_enable_features_input enable_features; 194 struct ta_ras_disable_features_input disable_features; 195 struct ta_ras_trigger_error_input trigger_error; 196 struct ta_ras_query_address_input address; 197 198 uint32_t reserve_pad[256]; 199 }; 200 201 union ta_ras_cmd_output { 202 struct ta_ras_output_flags flags; 203 struct ta_ras_query_address_output address; 204 205 uint32_t reserve_pad[256]; 206 }; 207 208 /* Shared Memory structures */ 209 /**********************************************************/ 210 struct ta_ras_shared_memory { 211 uint32_t cmd_id; 212 uint32_t resp_id; 213 uint32_t ras_status; 214 uint32_t if_version; 215 union ta_ras_cmd_input ras_in_message; 216 union ta_ras_cmd_output ras_out_message; 217 }; 218 219 #endif // TL_RAS_IF_H_ 220