1 /*
2 * Silicon Motion SM712 frame buffer device
3 *
4 * Copyright (C) 2006 Silicon Motion Technology Corp.
5 * Authors: Ge Wang, gewang@siliconmotion.com
6 * Boyod boyod.yang@siliconmotion.com.cn
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive for
13 * more details.
14 */
15
16 #define FB_ACCEL_SMI_LYNX 88
17
18 #define SCREEN_X_RES 1024
19 #define SCREEN_Y_RES_PC 768
20 #define SCREEN_Y_RES_NETBOOK 600
21 #define SCREEN_BPP 16
22
23 #define dac_reg (0x3c8)
24 #define dac_val (0x3c9)
25
26 extern void __iomem *smtc_regbaseaddress;
27 #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg)
28
29 #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg)
30
31 #define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
32 #define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
33 #define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
34 #define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
35 #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
36 #define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
37 #define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
38 #define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
39 #define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
40 #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
41
smtc_crtcw(int reg,int val)42 static inline void smtc_crtcw(int reg, int val)
43 {
44 smtc_mmiowb(reg, 0x3d4);
45 smtc_mmiowb(val, 0x3d5);
46 }
47
smtc_grphw(int reg,int val)48 static inline void smtc_grphw(int reg, int val)
49 {
50 smtc_mmiowb(reg, 0x3ce);
51 smtc_mmiowb(val, 0x3cf);
52 }
53
smtc_attrw(int reg,int val)54 static inline void smtc_attrw(int reg, int val)
55 {
56 smtc_mmiorb(0x3da);
57 smtc_mmiowb(reg, 0x3c0);
58 smtc_mmiorb(0x3c1);
59 smtc_mmiowb(val, 0x3c0);
60 }
61
smtc_seqw(int reg,int val)62 static inline void smtc_seqw(int reg, int val)
63 {
64 smtc_mmiowb(reg, 0x3c4);
65 smtc_mmiowb(val, 0x3c5);
66 }
67
smtc_seqr(int reg)68 static inline unsigned int smtc_seqr(int reg)
69 {
70 smtc_mmiowb(reg, 0x3c4);
71 return smtc_mmiorb(0x3c5);
72 }
73
74 /* The next structure holds all information relevant for a specific video mode.
75 */
76
77 struct modeinit {
78 int mmsizex;
79 int mmsizey;
80 int bpp;
81 int hz;
82 unsigned char init_misc;
83 unsigned char init_sr00_sr04[SIZE_SR00_SR04];
84 unsigned char init_sr10_sr24[SIZE_SR10_SR24];
85 unsigned char init_sr30_sr75[SIZE_SR30_SR75];
86 unsigned char init_sr80_sr93[SIZE_SR80_SR93];
87 unsigned char init_sra0_sraf[SIZE_SRA0_SRAF];
88 unsigned char init_gr00_gr08[SIZE_GR00_GR08];
89 unsigned char init_ar00_ar14[SIZE_AR00_AR14];
90 unsigned char init_cr00_cr18[SIZE_CR00_CR18];
91 unsigned char init_cr30_cr4d[SIZE_CR30_CR4D];
92 unsigned char init_cr90_cra7[SIZE_CR90_CRA7];
93 };
94
95 #ifdef __BIG_ENDIAN
96 #define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \
97 ((g & 0xe000) >> 13) | \
98 ((g & 0x1c00) << 3) | \
99 ((b & 0xf800) >> 3))
100 #define big_addr 0x800000
101 #define mmio_addr 0x00800000
102 #define seqw17() smtc_seqw(0x17, 0x30)
103 #define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } }
104 #define big_swap(p) ((p & 0xff00ff00 >> 8) | (p & 0x00ff00ff << 8))
105 #else
106 #define pal_rgb(r, g, b, val) val
107 #define big_addr 0
108 #define mmio_addr 0x00c00000
109 #define seqw17() do { } while (0)
110 #define big_pixel_depth(p, d) do { } while (0)
111 #define big_swap(p) p
112 #endif
113