1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #if defined(__FreeBSD__) 6 #define LINUXKPI_PARAM_PREFIX rtw89_debug_ 7 #endif 8 9 #include <linux/vmalloc.h> 10 11 #include "coex.h" 12 #include "debug.h" 13 #include "fw.h" 14 #include "mac.h" 15 #include "pci.h" 16 #include "phy.h" 17 #include "ps.h" 18 #include "reg.h" 19 #include "sar.h" 20 #if defined(__FreeBSD__) 21 #ifdef CONFIG_RTW89_DEBUGFS 22 #include <linux/debugfs.h> 23 #endif 24 #endif 25 26 #ifdef CONFIG_RTW89_DEBUGMSG 27 unsigned int rtw89_debug_mask; 28 EXPORT_SYMBOL(rtw89_debug_mask); 29 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 30 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 31 #endif 32 33 #ifdef CONFIG_RTW89_DEBUGFS 34 struct rtw89_debugfs_priv { 35 struct rtw89_dev *rtwdev; 36 int (*cb_read)(struct seq_file *m, void *v); 37 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 38 size_t count, loff_t *loff); 39 union { 40 u32 cb_data; 41 struct { 42 u32 addr; 43 u32 len; 44 } read_reg; 45 struct { 46 u32 addr; 47 u32 mask; 48 u8 path; 49 } read_rf; 50 struct { 51 u8 ss_dbg:1; 52 u8 dle_dbg:1; 53 u8 dmac_dbg:1; 54 u8 cmac_dbg:1; 55 u8 dbg_port:1; 56 } dbgpkg_en; 57 struct { 58 u32 start; 59 u32 len; 60 u8 sel; 61 } mac_mem; 62 }; 63 }; 64 65 struct rtw89_debugfs { 66 struct rtw89_debugfs_priv read_reg; 67 struct rtw89_debugfs_priv write_reg; 68 struct rtw89_debugfs_priv read_rf; 69 struct rtw89_debugfs_priv write_rf; 70 struct rtw89_debugfs_priv rf_reg_dump; 71 struct rtw89_debugfs_priv txpwr_table; 72 struct rtw89_debugfs_priv mac_reg_dump; 73 struct rtw89_debugfs_priv mac_mem_dump; 74 struct rtw89_debugfs_priv mac_dbg_port_dump; 75 struct rtw89_debugfs_priv send_h2c; 76 struct rtw89_debugfs_priv early_h2c; 77 struct rtw89_debugfs_priv fw_crash; 78 struct rtw89_debugfs_priv btc_info; 79 struct rtw89_debugfs_priv btc_manual; 80 struct rtw89_debugfs_priv fw_log_manual; 81 struct rtw89_debugfs_priv phy_info; 82 struct rtw89_debugfs_priv stations; 83 struct rtw89_debugfs_priv disable_dm; 84 }; 85 86 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 87 [RATE_INFO_BW_20] = 20, 88 [RATE_INFO_BW_40] = 40, 89 [RATE_INFO_BW_80] = 80, 90 [RATE_INFO_BW_160] = 160, 91 [RATE_INFO_BW_320] = 320, 92 }; 93 94 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 95 { 96 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 97 return rtw89_rate_info_bw_to_mhz_map[bw]; 98 99 return 0; 100 } 101 102 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 103 { 104 struct rtw89_debugfs_priv *debugfs_priv = m->private; 105 106 return debugfs_priv->cb_read(m, v); 107 } 108 109 static ssize_t rtw89_debugfs_single_write(struct file *filp, 110 const char __user *buffer, 111 size_t count, loff_t *loff) 112 { 113 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 114 115 return debugfs_priv->cb_write(filp, buffer, count, loff); 116 } 117 118 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 119 const char __user *buffer, 120 size_t count, loff_t *loff) 121 { 122 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 123 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 124 125 return debugfs_priv->cb_write(filp, buffer, count, loff); 126 } 127 128 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 129 { 130 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 131 } 132 133 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 134 { 135 return 0; 136 } 137 138 static const struct file_operations file_ops_single_r = { 139 .owner = THIS_MODULE, 140 .open = rtw89_debugfs_single_open, 141 .read = seq_read, 142 .llseek = seq_lseek, 143 .release = single_release, 144 }; 145 146 static const struct file_operations file_ops_common_rw = { 147 .owner = THIS_MODULE, 148 .open = rtw89_debugfs_single_open, 149 .release = single_release, 150 .read = seq_read, 151 .llseek = seq_lseek, 152 .write = rtw89_debugfs_seq_file_write, 153 }; 154 155 static const struct file_operations file_ops_single_w = { 156 .owner = THIS_MODULE, 157 .write = rtw89_debugfs_single_write, 158 .open = simple_open, 159 .release = rtw89_debugfs_close, 160 }; 161 162 static ssize_t 163 rtw89_debug_priv_read_reg_select(struct file *filp, 164 const char __user *user_buf, 165 size_t count, loff_t *loff) 166 { 167 struct seq_file *m = (struct seq_file *)filp->private_data; 168 struct rtw89_debugfs_priv *debugfs_priv = m->private; 169 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 170 char buf[32]; 171 size_t buf_size; 172 u32 addr, len; 173 int num; 174 175 buf_size = min(count, sizeof(buf) - 1); 176 if (copy_from_user(buf, user_buf, buf_size)) 177 return -EFAULT; 178 179 buf[buf_size] = '\0'; 180 num = sscanf(buf, "%x %x", &addr, &len); 181 if (num != 2) { 182 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 183 return -EINVAL; 184 } 185 186 debugfs_priv->read_reg.addr = addr; 187 debugfs_priv->read_reg.len = len; 188 189 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 190 191 return count; 192 } 193 194 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 195 { 196 struct rtw89_debugfs_priv *debugfs_priv = m->private; 197 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 198 u32 addr, end, data, k; 199 u32 len; 200 201 len = debugfs_priv->read_reg.len; 202 addr = debugfs_priv->read_reg.addr; 203 204 if (len > 4) 205 goto ndata; 206 207 switch (len) { 208 case 1: 209 data = rtw89_read8(rtwdev, addr); 210 break; 211 case 2: 212 data = rtw89_read16(rtwdev, addr); 213 break; 214 case 4: 215 data = rtw89_read32(rtwdev, addr); 216 break; 217 default: 218 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 219 return -EINVAL; 220 } 221 222 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 223 224 return 0; 225 226 ndata: 227 end = addr + len; 228 229 for (; addr < end; addr += 16) { 230 seq_printf(m, "%08xh : ", 0x18600000 + addr); 231 for (k = 0; k < 16; k += 4) { 232 data = rtw89_read32(rtwdev, addr + k); 233 seq_printf(m, "%08x ", data); 234 } 235 seq_puts(m, "\n"); 236 } 237 238 return 0; 239 } 240 241 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 242 const char __user *user_buf, 243 size_t count, loff_t *loff) 244 { 245 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 246 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 247 char buf[32]; 248 size_t buf_size; 249 u32 addr, val, len; 250 int num; 251 252 buf_size = min(count, sizeof(buf) - 1); 253 if (copy_from_user(buf, user_buf, buf_size)) 254 return -EFAULT; 255 256 buf[buf_size] = '\0'; 257 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 258 if (num != 3) { 259 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 260 return -EINVAL; 261 } 262 263 switch (len) { 264 case 1: 265 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 266 rtw89_write8(rtwdev, addr, (u8)val); 267 break; 268 case 2: 269 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 270 rtw89_write16(rtwdev, addr, (u16)val); 271 break; 272 case 4: 273 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 274 rtw89_write32(rtwdev, addr, (u32)val); 275 break; 276 default: 277 rtw89_info(rtwdev, "invalid read write len %d\n", len); 278 break; 279 } 280 281 return count; 282 } 283 284 static ssize_t 285 rtw89_debug_priv_read_rf_select(struct file *filp, 286 const char __user *user_buf, 287 size_t count, loff_t *loff) 288 { 289 struct seq_file *m = (struct seq_file *)filp->private_data; 290 struct rtw89_debugfs_priv *debugfs_priv = m->private; 291 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 292 char buf[32]; 293 size_t buf_size; 294 u32 addr, mask; 295 u8 path; 296 int num; 297 298 buf_size = min(count, sizeof(buf) - 1); 299 if (copy_from_user(buf, user_buf, buf_size)) 300 return -EFAULT; 301 302 buf[buf_size] = '\0'; 303 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 304 if (num != 3) { 305 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 306 return -EINVAL; 307 } 308 309 if (path >= rtwdev->chip->rf_path_num) { 310 rtw89_info(rtwdev, "wrong rf path\n"); 311 return -EINVAL; 312 } 313 debugfs_priv->read_rf.addr = addr; 314 debugfs_priv->read_rf.mask = mask; 315 debugfs_priv->read_rf.path = path; 316 317 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 318 319 return count; 320 } 321 322 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 323 { 324 struct rtw89_debugfs_priv *debugfs_priv = m->private; 325 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 326 u32 addr, data, mask; 327 u8 path; 328 329 addr = debugfs_priv->read_rf.addr; 330 mask = debugfs_priv->read_rf.mask; 331 path = debugfs_priv->read_rf.path; 332 333 data = rtw89_read_rf(rtwdev, path, addr, mask); 334 335 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 336 337 return 0; 338 } 339 340 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 341 const char __user *user_buf, 342 size_t count, loff_t *loff) 343 { 344 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 345 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 346 char buf[32]; 347 size_t buf_size; 348 u32 addr, val, mask; 349 u8 path; 350 int num; 351 352 buf_size = min(count, sizeof(buf) - 1); 353 if (copy_from_user(buf, user_buf, buf_size)) 354 return -EFAULT; 355 356 buf[buf_size] = '\0'; 357 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 358 if (num != 4) { 359 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 360 return -EINVAL; 361 } 362 363 if (path >= rtwdev->chip->rf_path_num) { 364 rtw89_info(rtwdev, "wrong rf path\n"); 365 return -EINVAL; 366 } 367 368 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 369 path, addr, val, mask); 370 rtw89_write_rf(rtwdev, path, addr, mask, val); 371 372 return count; 373 } 374 375 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 376 { 377 struct rtw89_debugfs_priv *debugfs_priv = m->private; 378 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 379 const struct rtw89_chip_info *chip = rtwdev->chip; 380 u32 addr, offset, data; 381 u8 path; 382 383 for (path = 0; path < chip->rf_path_num; path++) { 384 seq_printf(m, "RF path %d:\n\n", path); 385 for (addr = 0; addr < 0x100; addr += 4) { 386 seq_printf(m, "0x%08x: ", addr); 387 for (offset = 0; offset < 4; offset++) { 388 data = rtw89_read_rf(rtwdev, path, 389 addr + offset, RFREG_MASK); 390 seq_printf(m, "0x%05x ", data); 391 } 392 seq_puts(m, "\n"); 393 } 394 seq_puts(m, "\n"); 395 } 396 397 return 0; 398 } 399 400 struct txpwr_ent { 401 bool nested; 402 union { 403 const char *txt; 404 const struct txpwr_ent *ptr; 405 }; 406 u8 len; 407 }; 408 409 struct txpwr_map { 410 const struct txpwr_ent *ent; 411 u8 size; 412 u32 addr_from; 413 u32 addr_to; 414 u32 addr_to_1ss; 415 }; 416 417 #define __GEN_TXPWR_ENT_NESTED(_e) \ 418 { .nested = true, .ptr = __txpwr_ent_##_e, \ 419 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 420 421 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 422 423 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 424 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 425 426 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 427 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 428 429 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 430 { .len = 8, .txt = _t "\t- " \ 431 _e0 " " _e1 " " _e2 " " _e3 " " \ 432 _e4 " " _e5 " " _e6 " " _e7 } 433 434 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 435 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 436 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 437 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 438 /* 1NSS */ 439 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 440 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 441 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 442 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 443 /* 2NSS */ 444 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 445 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 446 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 447 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 448 }; 449 450 #if defined(__linux__) 451 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 452 #elif defined(__FreeBSD__) 453 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 454 #endif 455 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 456 457 static const struct txpwr_map __txpwr_map_byr_ax = { 458 .ent = __txpwr_ent_byr_ax, 459 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 460 .addr_from = R_AX_PWR_BY_RATE, 461 .addr_to = R_AX_PWR_BY_RATE_MAX, 462 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 463 }; 464 465 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 466 /* 1TX */ 467 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 468 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 469 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 470 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 471 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 472 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 473 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 474 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 475 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 476 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 477 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 478 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 479 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 480 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 481 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 482 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 483 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 484 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 485 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 486 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 487 /* 2TX */ 488 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 489 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 490 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 491 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 492 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 493 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 494 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 495 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 496 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 497 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 498 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 499 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 500 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 501 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 502 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 503 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 504 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 505 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 506 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 507 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 508 }; 509 510 #if defined(__linux__) 511 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 512 #elif defined(__FreeBSD__) 513 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 514 #endif 515 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 516 517 static const struct txpwr_map __txpwr_map_lmt_ax = { 518 .ent = __txpwr_ent_lmt_ax, 519 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 520 .addr_from = R_AX_PWR_LMT, 521 .addr_to = R_AX_PWR_LMT_MAX, 522 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 523 }; 524 525 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 526 /* 1TX */ 527 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 528 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 529 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 530 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 531 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 532 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 533 /* 2TX */ 534 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 535 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 536 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 537 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 538 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 539 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 540 }; 541 542 #if defined(__linux__) 543 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 544 #elif defined(__FreeBSD__) 545 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 546 #endif 547 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 548 549 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 550 .ent = __txpwr_ent_lmt_ru_ax, 551 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 552 .addr_from = R_AX_PWR_RU_LMT, 553 .addr_to = R_AX_PWR_RU_LMT_MAX, 554 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 555 }; 556 557 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 558 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 559 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 560 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 561 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 562 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 563 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 564 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 565 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 566 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 567 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 568 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 569 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 570 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 571 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 572 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 573 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 574 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 575 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 576 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 577 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 578 }; 579 580 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 581 __GEN_TXPWR_ENT0("BW20"), 582 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 583 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 584 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 585 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 586 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 587 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 588 589 __GEN_TXPWR_ENT0("BW40"), 590 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 591 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 592 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 593 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 594 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 595 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 596 597 /* there is no CCK section after BW80 */ 598 __GEN_TXPWR_ENT0("BW80"), 599 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 600 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 601 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 602 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 603 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 604 605 __GEN_TXPWR_ENT0("BW160"), 606 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 607 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 608 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 609 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 610 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 611 612 __GEN_TXPWR_ENT0("BW320"), 613 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 614 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 615 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 616 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 617 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 618 }; 619 620 static const struct txpwr_map __txpwr_map_byr_be = { 621 .ent = __txpwr_ent_byr_be, 622 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 623 .addr_from = R_BE_PWR_BY_RATE, 624 .addr_to = R_BE_PWR_BY_RATE_MAX, 625 .addr_to_1ss = 0, /* not support */ 626 }; 627 628 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 629 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 630 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 631 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 632 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 633 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 634 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 635 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 636 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 637 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 638 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 639 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 640 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 641 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 642 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 643 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 644 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 645 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 646 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 647 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 648 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 649 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 650 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 651 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 652 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 653 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 654 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 655 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 656 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 657 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 658 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 659 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 660 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 661 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 662 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 663 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 664 }; 665 666 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 667 __GEN_TXPWR_ENT0("1TX"), 668 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 669 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 670 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 671 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 672 673 __GEN_TXPWR_ENT0("2TX"), 674 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 675 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 678 }; 679 680 static const struct txpwr_map __txpwr_map_lmt_be = { 681 .ent = __txpwr_ent_lmt_be, 682 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 683 .addr_from = R_BE_PWR_LMT, 684 .addr_to = R_BE_PWR_LMT_MAX, 685 .addr_to_1ss = 0, /* not support */ 686 }; 687 688 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 689 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 690 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 691 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 692 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 693 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 694 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 695 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 696 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 697 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 698 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 699 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 700 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 701 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 702 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 703 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 704 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 705 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 706 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 707 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 708 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 709 }; 710 711 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 712 __GEN_TXPWR_ENT0("1TX"), 713 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 714 715 __GEN_TXPWR_ENT0("2TX"), 716 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 717 }; 718 719 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 720 .ent = __txpwr_ent_lmt_ru_be, 721 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 722 .addr_from = R_BE_PWR_RU_LMT, 723 .addr_to = R_BE_PWR_RU_LMT_MAX, 724 .addr_to_1ss = 0, /* not support */ 725 }; 726 727 static unsigned int 728 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 729 const s8 *buf, const unsigned int cur) 730 { 731 unsigned int cnt, i; 732 char *fmt; 733 734 if (ent->nested) { 735 for (cnt = 0, i = 0; i < ent->len; i++) 736 cnt += __print_txpwr_ent(m, ent->ptr + i, buf, 737 cur + cnt); 738 return cnt; 739 } 740 741 switch (ent->len) { 742 case 0: 743 seq_printf(m, "\t<< %s >>\n", ent->txt); 744 return 0; 745 case 2: 746 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 747 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 748 return 2; 749 case 4: 750 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 751 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 752 buf[cur + 2], buf[cur + 3]); 753 return 4; 754 case 8: 755 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 756 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 757 buf[cur + 2], buf[cur + 3], buf[cur + 4], 758 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 759 return 8; 760 default: 761 return 0; 762 } 763 } 764 765 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 766 const struct txpwr_map *map) 767 { 768 u8 fct = rtwdev->chip->txpwr_factor_mac; 769 u8 path_num = rtwdev->chip->rf_path_num; 770 unsigned int cur, i; 771 u32 max_valid_addr; 772 u32 val, addr; 773 s8 *buf, tmp; 774 int ret; 775 776 buf = vzalloc(map->addr_to - map->addr_from + 4); 777 if (!buf) 778 return -ENOMEM; 779 780 if (path_num == 1) 781 max_valid_addr = map->addr_to_1ss; 782 else 783 max_valid_addr = map->addr_to; 784 785 if (max_valid_addr == 0) 786 return -EOPNOTSUPP; 787 788 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 789 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 790 if (ret) 791 val = MASKDWORD; 792 793 cur = addr - map->addr_from; 794 for (i = 0; i < 4; i++, val >>= 8) { 795 /* signed 7 bits, and reserved BIT(7) */ 796 tmp = sign_extend32(val, 6); 797 buf[cur + i] = tmp >> fct; 798 } 799 } 800 801 for (cur = 0, i = 0; i < map->size; i++) 802 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 803 804 vfree(buf); 805 return 0; 806 } 807 808 #define case_REGD(_regd) \ 809 case RTW89_ ## _regd: \ 810 seq_puts(m, #_regd "\n"); \ 811 break 812 813 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev, 814 const struct rtw89_chan *chan) 815 { 816 u8 band = chan->band_type; 817 u8 regd = rtw89_regd_get(rtwdev, band); 818 819 switch (regd) { 820 default: 821 seq_printf(m, "UNKNOWN: %d\n", regd); 822 break; 823 case_REGD(WW); 824 case_REGD(ETSI); 825 case_REGD(FCC); 826 case_REGD(MKK); 827 case_REGD(NA); 828 case_REGD(IC); 829 case_REGD(KCC); 830 case_REGD(NCC); 831 case_REGD(CHILE); 832 case_REGD(ACMA); 833 case_REGD(MEXICO); 834 case_REGD(UKRAINE); 835 case_REGD(CN); 836 case_REGD(QATAR); 837 case_REGD(UK); 838 case_REGD(THAILAND); 839 } 840 } 841 842 #undef case_REGD 843 844 struct dbgfs_txpwr_table { 845 const struct txpwr_map *byr; 846 const struct txpwr_map *lmt; 847 const struct txpwr_map *lmt_ru; 848 }; 849 850 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 851 .byr = &__txpwr_map_byr_ax, 852 .lmt = &__txpwr_map_lmt_ax, 853 .lmt_ru = &__txpwr_map_lmt_ru_ax, 854 }; 855 856 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 857 .byr = &__txpwr_map_byr_be, 858 .lmt = &__txpwr_map_lmt_be, 859 .lmt_ru = &__txpwr_map_lmt_ru_be, 860 }; 861 862 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 863 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 864 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 865 }; 866 867 static 868 void rtw89_debug_priv_txpwr_table_get_regd(struct seq_file *m, 869 struct rtw89_dev *rtwdev, 870 const struct rtw89_chan *chan) 871 { 872 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 873 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 874 875 seq_printf(m, "[Chanctx] band %u, ch %u, bw %u\n", 876 chan->band_type, chan->channel, chan->band_width); 877 878 seq_puts(m, "[Regulatory] "); 879 __print_regd(m, rtwdev, chan); 880 881 if (chan->band_type == RTW89_BAND_6G) { 882 seq_printf(m, "[reg6_pwr_type] %u\n", regulatory->reg_6ghz_power); 883 884 if (tpe6->valid) 885 seq_printf(m, "[TPE] %d dBm\n", tpe6->constraint); 886 } 887 } 888 889 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 890 { 891 struct rtw89_debugfs_priv *debugfs_priv = m->private; 892 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 893 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 894 const struct dbgfs_txpwr_table *tbl; 895 const struct rtw89_chan *chan; 896 int ret = 0; 897 898 mutex_lock(&rtwdev->mutex); 899 rtw89_leave_ps_mode(rtwdev); 900 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 901 902 rtw89_debug_priv_txpwr_table_get_regd(m, rtwdev, chan); 903 904 seq_puts(m, "[SAR]\n"); 905 rtw89_print_sar(m, rtwdev, chan->freq); 906 907 seq_puts(m, "[TAS]\n"); 908 rtw89_print_tas(m, rtwdev); 909 910 seq_puts(m, "[DAG]\n"); 911 rtw89_print_ant_gain(m, rtwdev, chan); 912 913 tbl = dbgfs_txpwr_tables[chip_gen]; 914 if (!tbl) { 915 ret = -EOPNOTSUPP; 916 goto err; 917 } 918 919 seq_puts(m, "\n[TX power byrate]\n"); 920 ret = __print_txpwr_map(m, rtwdev, tbl->byr); 921 if (ret) 922 goto err; 923 924 seq_puts(m, "\n[TX power limit]\n"); 925 ret = __print_txpwr_map(m, rtwdev, tbl->lmt); 926 if (ret) 927 goto err; 928 929 seq_puts(m, "\n[TX power limit_ru]\n"); 930 ret = __print_txpwr_map(m, rtwdev, tbl->lmt_ru); 931 if (ret) 932 goto err; 933 934 err: 935 mutex_unlock(&rtwdev->mutex); 936 return ret; 937 } 938 939 static ssize_t 940 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 941 const char __user *user_buf, 942 size_t count, loff_t *loff) 943 { 944 struct seq_file *m = (struct seq_file *)filp->private_data; 945 struct rtw89_debugfs_priv *debugfs_priv = m->private; 946 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 947 const struct rtw89_chip_info *chip = rtwdev->chip; 948 char buf[32]; 949 size_t buf_size; 950 int sel; 951 int ret; 952 953 buf_size = min(count, sizeof(buf) - 1); 954 if (copy_from_user(buf, user_buf, buf_size)) 955 return -EFAULT; 956 957 buf[buf_size] = '\0'; 958 ret = kstrtoint(buf, 0, &sel); 959 if (ret) 960 return ret; 961 962 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 963 rtw89_info(rtwdev, "invalid args: %d\n", sel); 964 return -EINVAL; 965 } 966 967 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 968 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 969 chip->chip_id); 970 return -EINVAL; 971 } 972 973 debugfs_priv->cb_data = sel; 974 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 975 976 return count; 977 } 978 979 #define RTW89_MAC_PAGE_SIZE 0x100 980 981 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 982 { 983 struct rtw89_debugfs_priv *debugfs_priv = m->private; 984 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 985 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 986 u32 start, end; 987 u32 i, j, k, page; 988 u32 val; 989 990 switch (reg_sel) { 991 case RTW89_DBG_SEL_MAC_00: 992 seq_puts(m, "Debug selected MAC page 0x00\n"); 993 start = 0x000; 994 end = 0x014; 995 break; 996 case RTW89_DBG_SEL_MAC_30: 997 seq_puts(m, "Debug selected MAC page 0x30\n"); 998 start = 0x030; 999 end = 0x033; 1000 break; 1001 case RTW89_DBG_SEL_MAC_40: 1002 seq_puts(m, "Debug selected MAC page 0x40\n"); 1003 start = 0x040; 1004 end = 0x07f; 1005 break; 1006 case RTW89_DBG_SEL_MAC_80: 1007 seq_puts(m, "Debug selected MAC page 0x80\n"); 1008 start = 0x080; 1009 end = 0x09f; 1010 break; 1011 case RTW89_DBG_SEL_MAC_C0: 1012 seq_puts(m, "Debug selected MAC page 0xc0\n"); 1013 start = 0x0c0; 1014 end = 0x0df; 1015 break; 1016 case RTW89_DBG_SEL_MAC_E0: 1017 seq_puts(m, "Debug selected MAC page 0xe0\n"); 1018 start = 0x0e0; 1019 end = 0x0ff; 1020 break; 1021 case RTW89_DBG_SEL_BB: 1022 seq_puts(m, "Debug selected BB register\n"); 1023 start = 0x100; 1024 end = 0x17f; 1025 break; 1026 case RTW89_DBG_SEL_IQK: 1027 seq_puts(m, "Debug selected IQK register\n"); 1028 start = 0x180; 1029 end = 0x1bf; 1030 break; 1031 case RTW89_DBG_SEL_RFC: 1032 seq_puts(m, "Debug selected RFC register\n"); 1033 start = 0x1c0; 1034 end = 0x1ff; 1035 break; 1036 default: 1037 seq_puts(m, "Selected invalid register page\n"); 1038 return -EINVAL; 1039 } 1040 1041 for (i = start; i <= end; i++) { 1042 page = i << 8; 1043 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1044 seq_printf(m, "%08xh : ", 0x18600000 + j); 1045 for (k = 0; k < 4; k++) { 1046 val = rtw89_read32(rtwdev, j + (k << 2)); 1047 seq_printf(m, "%08x ", val); 1048 } 1049 seq_puts(m, "\n"); 1050 } 1051 } 1052 1053 return 0; 1054 } 1055 1056 static ssize_t 1057 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 1058 const char __user *user_buf, 1059 size_t count, loff_t *loff) 1060 { 1061 struct seq_file *m = (struct seq_file *)filp->private_data; 1062 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1063 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1064 char buf[32]; 1065 size_t buf_size; 1066 u32 sel, start_addr, len; 1067 int num; 1068 1069 buf_size = min(count, sizeof(buf) - 1); 1070 if (copy_from_user(buf, user_buf, buf_size)) 1071 return -EFAULT; 1072 1073 buf[buf_size] = '\0'; 1074 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1075 if (num != 3) { 1076 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1077 return -EINVAL; 1078 } 1079 1080 debugfs_priv->mac_mem.sel = sel; 1081 debugfs_priv->mac_mem.start = start_addr; 1082 debugfs_priv->mac_mem.len = len; 1083 1084 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1085 sel, start_addr, len); 1086 1087 return count; 1088 } 1089 1090 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 1091 struct rtw89_dev *rtwdev, 1092 u8 sel, u32 start_addr, u32 len) 1093 { 1094 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1095 u32 filter_model_addr = mac->filter_model_addr; 1096 u32 indir_access_addr = mac->indir_access_addr; 1097 u32 base_addr, start_page, residue; 1098 u32 i, j, p, pages; 1099 u32 dump_len, remain; 1100 u32 val; 1101 1102 remain = len; 1103 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 1104 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 1105 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 1106 base_addr = mac->mem_base_addrs[sel]; 1107 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 1108 1109 for (p = 0; p < pages; p++) { 1110 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 1111 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1112 for (i = indir_access_addr + residue; 1113 i < indir_access_addr + dump_len;) { 1114 seq_printf(m, "%08xh:", i); 1115 for (j = 0; 1116 j < 4 && i < indir_access_addr + dump_len; 1117 j++, i += 4) { 1118 val = rtw89_read32(rtwdev, i); 1119 seq_printf(m, " %08x", val); 1120 remain -= 4; 1121 } 1122 seq_puts(m, "\n"); 1123 } 1124 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 1125 } 1126 } 1127 1128 static int 1129 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 1130 { 1131 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1132 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1133 bool grant_read = false; 1134 1135 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1136 return -ENOENT; 1137 1138 if (rtwdev->chip->chip_id == RTL8852C) { 1139 switch (debugfs_priv->mac_mem.sel) { 1140 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1141 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1142 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1143 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1144 grant_read = true; 1145 break; 1146 default: 1147 break; 1148 } 1149 } 1150 1151 mutex_lock(&rtwdev->mutex); 1152 rtw89_leave_ps_mode(rtwdev); 1153 if (grant_read) 1154 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1155 rtw89_debug_dump_mac_mem(m, rtwdev, 1156 debugfs_priv->mac_mem.sel, 1157 debugfs_priv->mac_mem.start, 1158 debugfs_priv->mac_mem.len); 1159 if (grant_read) 1160 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1161 mutex_unlock(&rtwdev->mutex); 1162 1163 return 0; 1164 } 1165 1166 static ssize_t 1167 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 1168 const char __user *user_buf, 1169 size_t count, loff_t *loff) 1170 { 1171 struct seq_file *m = (struct seq_file *)filp->private_data; 1172 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1173 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1174 char buf[32]; 1175 size_t buf_size; 1176 int sel, set; 1177 int num; 1178 bool enable; 1179 1180 buf_size = min(count, sizeof(buf) - 1); 1181 if (copy_from_user(buf, user_buf, buf_size)) 1182 return -EFAULT; 1183 1184 buf[buf_size] = '\0'; 1185 num = sscanf(buf, "%d %d", &sel, &set); 1186 if (num != 2) { 1187 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1188 return -EINVAL; 1189 } 1190 1191 enable = set != 0; 1192 switch (sel) { 1193 case 0: 1194 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1195 break; 1196 case 1: 1197 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1198 break; 1199 case 2: 1200 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1201 break; 1202 case 3: 1203 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1204 break; 1205 case 4: 1206 debugfs_priv->dbgpkg_en.dbg_port = enable; 1207 break; 1208 default: 1209 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1210 return -EINVAL; 1211 } 1212 1213 rtw89_info(rtwdev, "%s debug port dump %d\n", 1214 enable ? "Enable" : "Disable", sel); 1215 1216 return count; 1217 } 1218 1219 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1220 struct seq_file *m) 1221 { 1222 return 0; 1223 } 1224 1225 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1226 struct seq_file *m) 1227 { 1228 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1229 ({ \ 1230 u32 __ctrl; \ 1231 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1232 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1233 u32 __data, __val32; \ 1234 int __ret; \ 1235 \ 1236 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1237 DLE_DFI_TYPE_##__target) | \ 1238 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1239 B_AX_WDE_DFI_ACTIVE; \ 1240 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1241 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1242 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1243 1000, 50000, false, \ 1244 rtwdev, __reg_ctrl); \ 1245 if (__ret) { \ 1246 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1247 #__type, #__target, __sel); \ 1248 return __ret; \ 1249 } \ 1250 \ 1251 __data = rtw89_read32(rtwdev, __reg_data); \ 1252 __data; \ 1253 }) 1254 1255 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 1256 ({ \ 1257 u32 __freepg, __pubpg; \ 1258 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1259 \ 1260 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1261 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1262 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1263 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1264 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1265 seq_printf(__m, "[%s] freepg head: %d\n", \ 1266 #__type, __freepg_head); \ 1267 seq_printf(__m, "[%s] freepg tail: %d\n", \ 1268 #__type, __freepg_tail); \ 1269 seq_printf(__m, "[%s] pubpg num : %d\n", \ 1270 #__type, __pubpg_num); \ 1271 }) 1272 1273 #define case_QUOTA(__m, __type, __id) \ 1274 case __type##_QTAID_##__id: \ 1275 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1276 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1277 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1278 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 1279 #__type, #__id, rsv_pgnum); \ 1280 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 1281 #__type, #__id, use_pgnum); \ 1282 break 1283 u32 quota_id; 1284 u32 val32; 1285 u16 rsv_pgnum, use_pgnum; 1286 int ret; 1287 1288 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1289 if (ret) { 1290 seq_puts(m, "[DLE] : DMAC not enabled\n"); 1291 return ret; 1292 } 1293 1294 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 1295 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 1296 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1297 switch (quota_id) { 1298 case_QUOTA(m, WDE, HOST_IF); 1299 case_QUOTA(m, WDE, WLAN_CPU); 1300 case_QUOTA(m, WDE, DATA_CPU); 1301 case_QUOTA(m, WDE, PKTIN); 1302 case_QUOTA(m, WDE, CPUIO); 1303 } 1304 } 1305 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1306 switch (quota_id) { 1307 case_QUOTA(m, PLE, B0_TXPL); 1308 case_QUOTA(m, PLE, B1_TXPL); 1309 case_QUOTA(m, PLE, C2H); 1310 case_QUOTA(m, PLE, H2C); 1311 case_QUOTA(m, PLE, WLAN_CPU); 1312 case_QUOTA(m, PLE, MPDU); 1313 case_QUOTA(m, PLE, CMAC0_RX); 1314 case_QUOTA(m, PLE, CMAC1_RX); 1315 case_QUOTA(m, PLE, CMAC1_BBRPT); 1316 case_QUOTA(m, PLE, WDRLS); 1317 case_QUOTA(m, PLE, CPUIO); 1318 } 1319 } 1320 1321 return 0; 1322 1323 #undef case_QUOTA 1324 #undef DLE_DFI_DUMP 1325 #undef DLE_DFI_FREE_PAGE_DUMP 1326 } 1327 1328 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1329 struct seq_file *m) 1330 { 1331 const struct rtw89_chip_info *chip = rtwdev->chip; 1332 u32 dmac_err; 1333 int i, ret; 1334 1335 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1336 if (ret) { 1337 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 1338 return ret; 1339 } 1340 1341 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1342 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1343 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1344 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1345 1346 if (dmac_err) { 1347 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1348 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1349 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1350 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1351 if (chip->chip_id == RTL8852C) { 1352 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1353 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1354 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1355 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1356 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1357 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1358 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1359 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1360 } 1361 } 1362 1363 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1364 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1365 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1366 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1367 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1368 if (chip->chip_id == RTL8852C) 1369 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1370 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1371 else 1372 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1373 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1374 } 1375 1376 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1377 if (chip->chip_id == RTL8852C) { 1378 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1379 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1380 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1381 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1382 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1383 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1384 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1385 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1386 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1387 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1388 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1389 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1390 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1391 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1392 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1393 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1394 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1395 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1396 1397 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1398 B_AX_DBG_SEL0, 0x8B); 1399 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1400 B_AX_DBG_SEL1, 0x8B); 1401 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1402 B_AX_SEL_0XC0_MASK, 1); 1403 for (i = 0; i < 0x10; i++) { 1404 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1405 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1406 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1407 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1408 } 1409 } else { 1410 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1411 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1412 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1413 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1414 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1415 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1416 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1417 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1418 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1419 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1420 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1421 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1422 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1423 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1424 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1425 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1426 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1427 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1428 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1429 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1430 } 1431 } 1432 1433 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1434 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1435 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1436 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1437 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1438 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1439 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1440 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1441 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1442 } 1443 1444 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1445 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1446 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1447 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1448 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1449 } 1450 1451 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1452 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1453 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1454 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1455 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1456 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1457 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1458 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1459 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1460 } 1461 1462 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1463 if (chip->chip_id == RTL8852C) { 1464 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1465 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1466 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1467 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1468 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1469 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1470 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1471 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1472 } else { 1473 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1474 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1475 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1476 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1477 } 1478 } 1479 1480 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1481 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1482 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1483 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1484 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1485 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1486 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1487 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1488 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1489 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1490 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1491 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1492 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1493 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1494 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1495 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1496 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1497 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1498 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1499 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1500 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1501 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1502 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1503 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1504 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1505 if (chip->chip_id == RTL8852C) { 1506 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1507 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1508 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1509 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1510 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1511 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1512 } else { 1513 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1514 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1515 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1516 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1517 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1518 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1519 } 1520 } 1521 1522 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1523 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1524 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1525 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1526 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1527 } 1528 1529 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1530 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1531 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1532 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1533 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1534 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1535 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1536 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1537 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1538 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1539 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1540 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1541 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1542 } 1543 1544 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1545 if (chip->chip_id == RTL8852C) { 1546 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1547 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1548 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1549 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1550 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1551 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1552 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1553 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1554 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1555 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1556 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1557 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1558 } else { 1559 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1560 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1561 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1562 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1563 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1564 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1565 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1566 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1567 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1568 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1569 } 1570 } 1571 1572 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1573 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1574 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1575 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1576 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1577 } 1578 1579 return 0; 1580 } 1581 1582 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1583 struct seq_file *m, 1584 enum rtw89_mac_idx band) 1585 { 1586 const struct rtw89_chip_info *chip = rtwdev->chip; 1587 u32 offset = 0; 1588 u32 cmac_err; 1589 int ret; 1590 1591 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1592 if (ret) { 1593 if (band) 1594 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1595 else 1596 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1597 return ret; 1598 } 1599 1600 if (band) 1601 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1602 1603 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1604 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1605 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1606 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1607 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1608 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1609 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1610 1611 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1612 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1613 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1614 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1615 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1616 } 1617 1618 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1619 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1620 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1621 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1622 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1623 } 1624 1625 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1626 if (chip->chip_id == RTL8852C) { 1627 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1628 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1629 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1630 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1631 } else { 1632 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1633 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1634 } 1635 } 1636 1637 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1638 if (chip->chip_id == RTL8852C) { 1639 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1640 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1641 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1642 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1643 } else { 1644 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1645 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1646 } 1647 } 1648 1649 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1650 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1651 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1652 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1653 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1654 } 1655 1656 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1657 if (chip->chip_id == RTL8852C) { 1658 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1659 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1660 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1661 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1662 } else { 1663 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1664 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1665 } 1666 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1667 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1668 } 1669 1670 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1671 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1672 1673 return 0; 1674 } 1675 1676 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1677 struct seq_file *m) 1678 { 1679 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1680 if (rtwdev->dbcc_en) 1681 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1682 1683 return 0; 1684 } 1685 1686 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1687 .sel_addr = R_AX_PTCL_DBG, 1688 .sel_byte = 1, 1689 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1690 .srt = 0x00, 1691 .end = 0x3F, 1692 .rd_addr = R_AX_PTCL_DBG_INFO, 1693 .rd_byte = 4, 1694 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1695 }; 1696 1697 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1698 .sel_addr = R_AX_PTCL_DBG_C1, 1699 .sel_byte = 1, 1700 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1701 .srt = 0x00, 1702 .end = 0x3F, 1703 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1704 .rd_byte = 4, 1705 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1706 }; 1707 1708 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1709 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1710 .sel_byte = 2, 1711 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1712 .srt = 0x0, 1713 .end = 0xD, 1714 .rd_addr = R_AX_DBG_PORT_SEL, 1715 .rd_byte = 4, 1716 .rd_msk = B_AX_DEBUG_ST_MASK 1717 }; 1718 1719 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1720 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1721 .sel_byte = 2, 1722 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1723 .srt = 0x0, 1724 .end = 0x5, 1725 .rd_addr = R_AX_DBG_PORT_SEL, 1726 .rd_byte = 4, 1727 .rd_msk = B_AX_DEBUG_ST_MASK 1728 }; 1729 1730 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1731 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1732 .sel_byte = 2, 1733 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1734 .srt = 0x0, 1735 .end = 0x9, 1736 .rd_addr = R_AX_DBG_PORT_SEL, 1737 .rd_byte = 4, 1738 .rd_msk = B_AX_DEBUG_ST_MASK 1739 }; 1740 1741 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1742 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1743 .sel_byte = 2, 1744 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1745 .srt = 0x0, 1746 .end = 0x3, 1747 .rd_addr = R_AX_DBG_PORT_SEL, 1748 .rd_byte = 4, 1749 .rd_msk = B_AX_DEBUG_ST_MASK 1750 }; 1751 1752 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1753 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1754 .sel_byte = 2, 1755 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1756 .srt = 0x0, 1757 .end = 0x1, 1758 .rd_addr = R_AX_DBG_PORT_SEL, 1759 .rd_byte = 4, 1760 .rd_msk = B_AX_DEBUG_ST_MASK 1761 }; 1762 1763 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1764 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1765 .sel_byte = 2, 1766 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1767 .srt = 0x0, 1768 .end = 0x0, 1769 .rd_addr = R_AX_DBG_PORT_SEL, 1770 .rd_byte = 4, 1771 .rd_msk = B_AX_DEBUG_ST_MASK 1772 }; 1773 1774 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1775 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1776 .sel_byte = 2, 1777 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1778 .srt = 0x0, 1779 .end = 0xB, 1780 .rd_addr = R_AX_DBG_PORT_SEL, 1781 .rd_byte = 4, 1782 .rd_msk = B_AX_DEBUG_ST_MASK 1783 }; 1784 1785 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1786 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1787 .sel_byte = 2, 1788 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1789 .srt = 0x0, 1790 .end = 0x4, 1791 .rd_addr = R_AX_DBG_PORT_SEL, 1792 .rd_byte = 4, 1793 .rd_msk = B_AX_DEBUG_ST_MASK 1794 }; 1795 1796 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1797 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1798 .sel_byte = 2, 1799 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1800 .srt = 0x0, 1801 .end = 0x8, 1802 .rd_addr = R_AX_DBG_PORT_SEL, 1803 .rd_byte = 4, 1804 .rd_msk = B_AX_DEBUG_ST_MASK 1805 }; 1806 1807 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1808 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1809 .sel_byte = 2, 1810 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1811 .srt = 0x0, 1812 .end = 0x7, 1813 .rd_addr = R_AX_DBG_PORT_SEL, 1814 .rd_byte = 4, 1815 .rd_msk = B_AX_DEBUG_ST_MASK 1816 }; 1817 1818 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1819 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1820 .sel_byte = 2, 1821 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1822 .srt = 0x0, 1823 .end = 0x1, 1824 .rd_addr = R_AX_DBG_PORT_SEL, 1825 .rd_byte = 4, 1826 .rd_msk = B_AX_DEBUG_ST_MASK 1827 }; 1828 1829 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1830 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1831 .sel_byte = 2, 1832 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1833 .srt = 0x0, 1834 .end = 0x3, 1835 .rd_addr = R_AX_DBG_PORT_SEL, 1836 .rd_byte = 4, 1837 .rd_msk = B_AX_DEBUG_ST_MASK 1838 }; 1839 1840 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1841 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1842 .sel_byte = 2, 1843 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1844 .srt = 0x0, 1845 .end = 0x0, 1846 .rd_addr = R_AX_DBG_PORT_SEL, 1847 .rd_byte = 4, 1848 .rd_msk = B_AX_DEBUG_ST_MASK 1849 }; 1850 1851 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1852 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1853 .sel_byte = 2, 1854 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1855 .srt = 0x0, 1856 .end = 0x8, 1857 .rd_addr = R_AX_DBG_PORT_SEL, 1858 .rd_byte = 4, 1859 .rd_msk = B_AX_DEBUG_ST_MASK 1860 }; 1861 1862 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1863 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1864 .sel_byte = 2, 1865 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1866 .srt = 0x0, 1867 .end = 0x0, 1868 .rd_addr = R_AX_DBG_PORT_SEL, 1869 .rd_byte = 4, 1870 .rd_msk = B_AX_DEBUG_ST_MASK 1871 }; 1872 1873 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1874 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1875 .sel_byte = 2, 1876 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1877 .srt = 0x0, 1878 .end = 0x6, 1879 .rd_addr = R_AX_DBG_PORT_SEL, 1880 .rd_byte = 4, 1881 .rd_msk = B_AX_DEBUG_ST_MASK 1882 }; 1883 1884 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1885 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1886 .sel_byte = 2, 1887 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1888 .srt = 0x0, 1889 .end = 0x0, 1890 .rd_addr = R_AX_DBG_PORT_SEL, 1891 .rd_byte = 4, 1892 .rd_msk = B_AX_DEBUG_ST_MASK 1893 }; 1894 1895 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1896 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1897 .sel_byte = 2, 1898 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1899 .srt = 0x0, 1900 .end = 0x0, 1901 .rd_addr = R_AX_DBG_PORT_SEL, 1902 .rd_byte = 4, 1903 .rd_msk = B_AX_DEBUG_ST_MASK 1904 }; 1905 1906 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1907 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1908 .sel_byte = 1, 1909 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1910 .srt = 0x0, 1911 .end = 0x3, 1912 .rd_addr = R_AX_DBG_PORT_SEL, 1913 .rd_byte = 4, 1914 .rd_msk = B_AX_DEBUG_ST_MASK 1915 }; 1916 1917 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1918 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1919 .sel_byte = 1, 1920 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1921 .srt = 0x0, 1922 .end = 0x6, 1923 .rd_addr = R_AX_DBG_PORT_SEL, 1924 .rd_byte = 4, 1925 .rd_msk = B_AX_DEBUG_ST_MASK 1926 }; 1927 1928 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1929 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1930 .sel_byte = 1, 1931 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1932 .srt = 0x0, 1933 .end = 0x0, 1934 .rd_addr = R_AX_DBG_PORT_SEL, 1935 .rd_byte = 4, 1936 .rd_msk = B_AX_DEBUG_ST_MASK 1937 }; 1938 1939 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1940 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1941 .sel_byte = 1, 1942 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1943 .srt = 0x8, 1944 .end = 0xE, 1945 .rd_addr = R_AX_DBG_PORT_SEL, 1946 .rd_byte = 4, 1947 .rd_msk = B_AX_DEBUG_ST_MASK 1948 }; 1949 1950 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1951 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1952 .sel_byte = 1, 1953 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1954 .srt = 0x0, 1955 .end = 0x5, 1956 .rd_addr = R_AX_DBG_PORT_SEL, 1957 .rd_byte = 4, 1958 .rd_msk = B_AX_DEBUG_ST_MASK 1959 }; 1960 1961 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1962 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1963 .sel_byte = 1, 1964 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1965 .srt = 0x0, 1966 .end = 0x6, 1967 .rd_addr = R_AX_DBG_PORT_SEL, 1968 .rd_byte = 4, 1969 .rd_msk = B_AX_DEBUG_ST_MASK 1970 }; 1971 1972 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1973 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1974 .sel_byte = 1, 1975 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1976 .srt = 0x0, 1977 .end = 0xF, 1978 .rd_addr = R_AX_DBG_PORT_SEL, 1979 .rd_byte = 4, 1980 .rd_msk = B_AX_DEBUG_ST_MASK 1981 }; 1982 1983 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1984 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1985 .sel_byte = 1, 1986 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1987 .srt = 0x0, 1988 .end = 0x9, 1989 .rd_addr = R_AX_DBG_PORT_SEL, 1990 .rd_byte = 4, 1991 .rd_msk = B_AX_DEBUG_ST_MASK 1992 }; 1993 1994 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1995 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1996 .sel_byte = 1, 1997 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1998 .srt = 0x0, 1999 .end = 0x3, 2000 .rd_addr = R_AX_DBG_PORT_SEL, 2001 .rd_byte = 4, 2002 .rd_msk = B_AX_DEBUG_ST_MASK 2003 }; 2004 2005 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2006 .sel_addr = R_AX_SCH_DBG_SEL, 2007 .sel_byte = 1, 2008 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2009 .srt = 0x00, 2010 .end = 0x2F, 2011 .rd_addr = R_AX_SCH_DBG, 2012 .rd_byte = 4, 2013 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2014 }; 2015 2016 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2017 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2018 .sel_byte = 1, 2019 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2020 .srt = 0x00, 2021 .end = 0x2F, 2022 .rd_addr = R_AX_SCH_DBG_C1, 2023 .rd_byte = 4, 2024 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2025 }; 2026 2027 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2028 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2029 .sel_byte = 1, 2030 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2031 .srt = 0x00, 2032 .end = 0x19, 2033 .rd_addr = R_AX_DBG_PORT_SEL, 2034 .rd_byte = 4, 2035 .rd_msk = B_AX_DEBUG_ST_MASK 2036 }; 2037 2038 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2039 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2040 .sel_byte = 1, 2041 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2042 .srt = 0x00, 2043 .end = 0x19, 2044 .rd_addr = R_AX_DBG_PORT_SEL, 2045 .rd_byte = 4, 2046 .rd_msk = B_AX_DEBUG_ST_MASK 2047 }; 2048 2049 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2050 .sel_addr = R_AX_RX_DEBUG_SELECT, 2051 .sel_byte = 1, 2052 .sel_msk = B_AX_DEBUG_SEL_MASK, 2053 .srt = 0x00, 2054 .end = 0x58, 2055 .rd_addr = R_AX_DBG_PORT_SEL, 2056 .rd_byte = 4, 2057 .rd_msk = B_AX_DEBUG_ST_MASK 2058 }; 2059 2060 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2061 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2062 .sel_byte = 1, 2063 .sel_msk = B_AX_DEBUG_SEL_MASK, 2064 .srt = 0x00, 2065 .end = 0x58, 2066 .rd_addr = R_AX_DBG_PORT_SEL, 2067 .rd_byte = 4, 2068 .rd_msk = B_AX_DEBUG_ST_MASK 2069 }; 2070 2071 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2072 .sel_addr = R_AX_RX_STATE_MONITOR, 2073 .sel_byte = 1, 2074 .sel_msk = B_AX_STATE_SEL_MASK, 2075 .srt = 0x00, 2076 .end = 0x17, 2077 .rd_addr = R_AX_RX_STATE_MONITOR, 2078 .rd_byte = 4, 2079 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2080 }; 2081 2082 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2083 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2084 .sel_byte = 1, 2085 .sel_msk = B_AX_STATE_SEL_MASK, 2086 .srt = 0x00, 2087 .end = 0x17, 2088 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2089 .rd_byte = 4, 2090 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2091 }; 2092 2093 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2094 .sel_addr = R_AX_RMAC_PLCP_MON, 2095 .sel_byte = 4, 2096 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2097 .srt = 0x0, 2098 .end = 0xF, 2099 .rd_addr = R_AX_RMAC_PLCP_MON, 2100 .rd_byte = 4, 2101 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2102 }; 2103 2104 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2105 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2106 .sel_byte = 4, 2107 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2108 .srt = 0x0, 2109 .end = 0xF, 2110 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2111 .rd_byte = 4, 2112 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2113 }; 2114 2115 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2116 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2117 .sel_byte = 1, 2118 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2119 .srt = 0x08, 2120 .end = 0x10, 2121 .rd_addr = R_AX_DBG_PORT_SEL, 2122 .rd_byte = 4, 2123 .rd_msk = B_AX_DEBUG_ST_MASK 2124 }; 2125 2126 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2127 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2128 .sel_byte = 1, 2129 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2130 .srt = 0x08, 2131 .end = 0x10, 2132 .rd_addr = R_AX_DBG_PORT_SEL, 2133 .rd_byte = 4, 2134 .rd_msk = B_AX_DEBUG_ST_MASK 2135 }; 2136 2137 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2138 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2139 .sel_byte = 1, 2140 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2141 .srt = 0x00, 2142 .end = 0x07, 2143 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2144 .rd_byte = 4, 2145 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2146 }; 2147 2148 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2149 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2150 .sel_byte = 1, 2151 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2152 .srt = 0x00, 2153 .end = 0x07, 2154 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2155 .rd_byte = 4, 2156 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2157 }; 2158 2159 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2160 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2161 .sel_byte = 1, 2162 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2163 .srt = 0x00, 2164 .end = 0x07, 2165 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2166 .rd_byte = 4, 2167 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2168 }; 2169 2170 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2171 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2172 .sel_byte = 1, 2173 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2174 .srt = 0x00, 2175 .end = 0x07, 2176 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2177 .rd_byte = 4, 2178 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2179 }; 2180 2181 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2182 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2183 .sel_byte = 1, 2184 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2185 .srt = 0x00, 2186 .end = 0x04, 2187 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2188 .rd_byte = 4, 2189 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2190 }; 2191 2192 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2193 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2194 .sel_byte = 1, 2195 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2196 .srt = 0x00, 2197 .end = 0x04, 2198 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2199 .rd_byte = 4, 2200 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2201 }; 2202 2203 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2204 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2205 .sel_byte = 1, 2206 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2207 .srt = 0x00, 2208 .end = 0x04, 2209 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2210 .rd_byte = 4, 2211 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2212 }; 2213 2214 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2215 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2216 .sel_byte = 1, 2217 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2218 .srt = 0x00, 2219 .end = 0x04, 2220 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2221 .rd_byte = 4, 2222 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2223 }; 2224 2225 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2226 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2227 .sel_byte = 4, 2228 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2229 .srt = 0x80000000, 2230 .end = 0x80000001, 2231 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2232 .rd_byte = 4, 2233 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2234 }; 2235 2236 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2237 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2238 .sel_byte = 4, 2239 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2240 .srt = 0x80010000, 2241 .end = 0x80010004, 2242 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2243 .rd_byte = 4, 2244 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2245 }; 2246 2247 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2248 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2249 .sel_byte = 4, 2250 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2251 .srt = 0x80020000, 2252 .end = 0x80020FFF, 2253 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2254 .rd_byte = 4, 2255 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2256 }; 2257 2258 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2259 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2260 .sel_byte = 4, 2261 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2262 .srt = 0x80030000, 2263 .end = 0x80030FFF, 2264 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2265 .rd_byte = 4, 2266 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2267 }; 2268 2269 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2270 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2271 .sel_byte = 4, 2272 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2273 .srt = 0x80040000, 2274 .end = 0x80040FFF, 2275 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2276 .rd_byte = 4, 2277 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2278 }; 2279 2280 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2281 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2282 .sel_byte = 4, 2283 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2284 .srt = 0x80050000, 2285 .end = 0x80050FFF, 2286 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2287 .rd_byte = 4, 2288 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2289 }; 2290 2291 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2292 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2293 .sel_byte = 4, 2294 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2295 .srt = 0x80060000, 2296 .end = 0x80060453, 2297 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2298 .rd_byte = 4, 2299 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2300 }; 2301 2302 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2303 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2304 .sel_byte = 4, 2305 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2306 .srt = 0x80070000, 2307 .end = 0x80070011, 2308 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2309 .rd_byte = 4, 2310 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2311 }; 2312 2313 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2314 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2315 .sel_byte = 4, 2316 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2317 .srt = 0x80000000, 2318 .end = 0x80000001, 2319 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2320 .rd_byte = 4, 2321 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2322 }; 2323 2324 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2325 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2326 .sel_byte = 4, 2327 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2328 .srt = 0x80010000, 2329 .end = 0x8001000A, 2330 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2331 .rd_byte = 4, 2332 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2333 }; 2334 2335 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2336 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2337 .sel_byte = 4, 2338 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2339 .srt = 0x80020000, 2340 .end = 0x80020DBF, 2341 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2342 .rd_byte = 4, 2343 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2344 }; 2345 2346 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2347 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2348 .sel_byte = 4, 2349 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2350 .srt = 0x80030000, 2351 .end = 0x80030DBF, 2352 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2353 .rd_byte = 4, 2354 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2355 }; 2356 2357 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2358 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2359 .sel_byte = 4, 2360 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2361 .srt = 0x80040000, 2362 .end = 0x80040DBF, 2363 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2364 .rd_byte = 4, 2365 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2366 }; 2367 2368 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2369 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2370 .sel_byte = 4, 2371 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2372 .srt = 0x80050000, 2373 .end = 0x80050DBF, 2374 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2375 .rd_byte = 4, 2376 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2377 }; 2378 2379 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2380 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2381 .sel_byte = 4, 2382 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2383 .srt = 0x80060000, 2384 .end = 0x80060041, 2385 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2386 .rd_byte = 4, 2387 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2388 }; 2389 2390 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2391 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2392 .sel_byte = 4, 2393 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2394 .srt = 0x80070000, 2395 .end = 0x80070001, 2396 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2397 .rd_byte = 4, 2398 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2399 }; 2400 2401 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2402 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2403 .sel_byte = 4, 2404 .sel_msk = B_AX_DFI_DATA_MASK, 2405 .srt = 0x80000000, 2406 .end = 0x8000017f, 2407 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2408 .rd_byte = 4, 2409 .rd_msk = B_AX_DFI_DATA_MASK 2410 }; 2411 2412 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2413 .sel_addr = R_AX_PCIE_DBG_CTRL, 2414 .sel_byte = 2, 2415 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2416 .srt = 0x00, 2417 .end = 0x03, 2418 .rd_addr = R_AX_DBG_PORT_SEL, 2419 .rd_byte = 4, 2420 .rd_msk = B_AX_DEBUG_ST_MASK 2421 }; 2422 2423 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2424 .sel_addr = R_AX_PCIE_DBG_CTRL, 2425 .sel_byte = 2, 2426 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2427 .srt = 0x00, 2428 .end = 0x04, 2429 .rd_addr = R_AX_DBG_PORT_SEL, 2430 .rd_byte = 4, 2431 .rd_msk = B_AX_DEBUG_ST_MASK 2432 }; 2433 2434 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2435 .sel_addr = R_AX_PCIE_DBG_CTRL, 2436 .sel_byte = 2, 2437 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2438 .srt = 0x00, 2439 .end = 0x01, 2440 .rd_addr = R_AX_DBG_PORT_SEL, 2441 .rd_byte = 4, 2442 .rd_msk = B_AX_DEBUG_ST_MASK 2443 }; 2444 2445 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2446 .sel_addr = R_AX_PCIE_DBG_CTRL, 2447 .sel_byte = 2, 2448 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2449 .srt = 0x00, 2450 .end = 0x05, 2451 .rd_addr = R_AX_DBG_PORT_SEL, 2452 .rd_byte = 4, 2453 .rd_msk = B_AX_DEBUG_ST_MASK 2454 }; 2455 2456 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2457 .sel_addr = R_AX_PCIE_DBG_CTRL, 2458 .sel_byte = 2, 2459 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2460 .srt = 0x00, 2461 .end = 0x05, 2462 .rd_addr = R_AX_DBG_PORT_SEL, 2463 .rd_byte = 4, 2464 .rd_msk = B_AX_DEBUG_ST_MASK 2465 }; 2466 2467 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2468 .sel_addr = R_AX_PCIE_DBG_CTRL, 2469 .sel_byte = 2, 2470 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2471 .srt = 0x00, 2472 .end = 0x06, 2473 .rd_addr = R_AX_DBG_PORT_SEL, 2474 .rd_byte = 4, 2475 .rd_msk = B_AX_DEBUG_ST_MASK 2476 }; 2477 2478 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2479 .sel_addr = R_AX_DBG_CTRL, 2480 .sel_byte = 1, 2481 .sel_msk = B_AX_DBG_SEL0, 2482 .srt = 0x34, 2483 .end = 0x3C, 2484 .rd_addr = R_AX_DBG_PORT_SEL, 2485 .rd_byte = 4, 2486 .rd_msk = B_AX_DEBUG_ST_MASK 2487 }; 2488 2489 static const struct rtw89_mac_dbg_port_info * 2490 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2491 struct rtw89_dev *rtwdev, u32 sel) 2492 { 2493 const struct rtw89_mac_dbg_port_info *info; 2494 u32 index; 2495 u32 val32; 2496 u16 val16; 2497 u8 val8; 2498 2499 switch (sel) { 2500 case RTW89_DBG_PORT_SEL_PTCL_C0: 2501 info = &dbg_port_ptcl_c0; 2502 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2503 val16 |= B_AX_PTCL_DBG_EN; 2504 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2505 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2506 break; 2507 case RTW89_DBG_PORT_SEL_PTCL_C1: 2508 info = &dbg_port_ptcl_c1; 2509 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2510 val16 |= B_AX_PTCL_DBG_EN; 2511 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2512 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2513 break; 2514 case RTW89_DBG_PORT_SEL_SCH_C0: 2515 info = &dbg_port_sch_c0; 2516 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2517 val32 |= B_AX_SCH_DBG_EN; 2518 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2519 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2520 break; 2521 case RTW89_DBG_PORT_SEL_SCH_C1: 2522 info = &dbg_port_sch_c1; 2523 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2524 val32 |= B_AX_SCH_DBG_EN; 2525 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2526 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2527 break; 2528 case RTW89_DBG_PORT_SEL_TMAC_C0: 2529 info = &dbg_port_tmac_c0; 2530 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2531 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2532 B_AX_DBGSEL_TRXPTCL_MASK); 2533 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2534 2535 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2536 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2537 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2538 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2539 2540 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2541 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2542 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2543 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2544 break; 2545 case RTW89_DBG_PORT_SEL_TMAC_C1: 2546 info = &dbg_port_tmac_c1; 2547 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2548 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2549 B_AX_DBGSEL_TRXPTCL_MASK); 2550 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2551 2552 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2553 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2554 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2555 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2556 2557 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2558 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2559 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2560 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2561 break; 2562 case RTW89_DBG_PORT_SEL_RMAC_C0: 2563 info = &dbg_port_rmac_c0; 2564 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2565 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2566 B_AX_DBGSEL_TRXPTCL_MASK); 2567 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2568 2569 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2570 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2571 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2572 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2573 2574 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2575 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2576 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2577 2578 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2579 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2580 B_AX_DBGSEL_TRXPTCL_MASK); 2581 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2582 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2583 break; 2584 case RTW89_DBG_PORT_SEL_RMAC_C1: 2585 info = &dbg_port_rmac_c1; 2586 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2587 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2588 B_AX_DBGSEL_TRXPTCL_MASK); 2589 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2590 2591 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2592 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2593 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2594 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2595 2596 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2597 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2598 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2599 2600 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2601 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2602 B_AX_DBGSEL_TRXPTCL_MASK); 2603 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2604 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2605 break; 2606 case RTW89_DBG_PORT_SEL_RMACST_C0: 2607 info = &dbg_port_rmacst_c0; 2608 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2609 break; 2610 case RTW89_DBG_PORT_SEL_RMACST_C1: 2611 info = &dbg_port_rmacst_c1; 2612 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2613 break; 2614 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2615 info = &dbg_port_rmac_plcp_c0; 2616 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2617 break; 2618 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2619 info = &dbg_port_rmac_plcp_c1; 2620 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2621 break; 2622 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2623 info = &dbg_port_trxptcl_c0; 2624 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2625 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2626 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2627 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2628 2629 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2630 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2631 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2632 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2633 break; 2634 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2635 info = &dbg_port_trxptcl_c1; 2636 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2637 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2638 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2639 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2640 2641 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2642 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2643 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2644 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2645 break; 2646 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2647 info = &dbg_port_tx_infol_c0; 2648 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2649 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2650 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2651 seq_puts(m, "Enable tx infol dump.\n"); 2652 break; 2653 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2654 info = &dbg_port_tx_infoh_c0; 2655 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2656 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2657 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2658 seq_puts(m, "Enable tx infoh dump.\n"); 2659 break; 2660 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2661 info = &dbg_port_tx_infol_c1; 2662 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2663 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2664 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2665 seq_puts(m, "Enable tx infol dump.\n"); 2666 break; 2667 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2668 info = &dbg_port_tx_infoh_c1; 2669 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2670 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2671 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2672 seq_puts(m, "Enable tx infoh dump.\n"); 2673 break; 2674 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2675 info = &dbg_port_txtf_infol_c0; 2676 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2677 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2678 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2679 seq_puts(m, "Enable tx tf infol dump.\n"); 2680 break; 2681 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2682 info = &dbg_port_txtf_infoh_c0; 2683 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2684 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2685 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2686 seq_puts(m, "Enable tx tf infoh dump.\n"); 2687 break; 2688 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2689 info = &dbg_port_txtf_infol_c1; 2690 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2691 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2692 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2693 seq_puts(m, "Enable tx tf infol dump.\n"); 2694 break; 2695 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2696 info = &dbg_port_txtf_infoh_c1; 2697 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2698 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2699 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2700 seq_puts(m, "Enable tx tf infoh dump.\n"); 2701 break; 2702 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2703 info = &dbg_port_wde_bufmgn_freepg; 2704 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2705 break; 2706 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2707 info = &dbg_port_wde_bufmgn_quota; 2708 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2709 break; 2710 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2711 info = &dbg_port_wde_bufmgn_pagellt; 2712 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2713 break; 2714 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2715 info = &dbg_port_wde_bufmgn_pktinfo; 2716 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2717 break; 2718 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2719 info = &dbg_port_wde_quemgn_prepkt; 2720 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2721 break; 2722 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2723 info = &dbg_port_wde_quemgn_nxtpkt; 2724 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2725 break; 2726 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2727 info = &dbg_port_wde_quemgn_qlnktbl; 2728 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2729 break; 2730 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2731 info = &dbg_port_wde_quemgn_qempty; 2732 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2733 break; 2734 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2735 info = &dbg_port_ple_bufmgn_freepg; 2736 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2737 break; 2738 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2739 info = &dbg_port_ple_bufmgn_quota; 2740 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2741 break; 2742 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2743 info = &dbg_port_ple_bufmgn_pagellt; 2744 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2745 break; 2746 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2747 info = &dbg_port_ple_bufmgn_pktinfo; 2748 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2749 break; 2750 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2751 info = &dbg_port_ple_quemgn_prepkt; 2752 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2753 break; 2754 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2755 info = &dbg_port_ple_quemgn_nxtpkt; 2756 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2757 break; 2758 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2759 info = &dbg_port_ple_quemgn_qlnktbl; 2760 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2761 break; 2762 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2763 info = &dbg_port_ple_quemgn_qempty; 2764 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2765 break; 2766 case RTW89_DBG_PORT_SEL_PKTINFO: 2767 info = &dbg_port_pktinfo; 2768 seq_puts(m, "Enable pktinfo dump.\n"); 2769 break; 2770 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2771 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2772 B_AX_DBG_SEL0, 0x80); 2773 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2774 B_AX_SEL_0XC0_MASK, 1); 2775 fallthrough; 2776 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2777 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2778 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2779 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2780 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2781 info = &dbg_port_dspt_hdt_tx0_5; 2782 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2783 rtw89_write16_mask(rtwdev, info->sel_addr, 2784 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2785 rtw89_write16_mask(rtwdev, info->sel_addr, 2786 B_AX_DISPATCHER_CH_SEL_MASK, index); 2787 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2788 break; 2789 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2790 info = &dbg_port_dspt_hdt_tx6; 2791 rtw89_write16_mask(rtwdev, info->sel_addr, 2792 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2793 rtw89_write16_mask(rtwdev, info->sel_addr, 2794 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2795 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2796 break; 2797 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2798 info = &dbg_port_dspt_hdt_tx7; 2799 rtw89_write16_mask(rtwdev, info->sel_addr, 2800 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2801 rtw89_write16_mask(rtwdev, info->sel_addr, 2802 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2803 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2804 break; 2805 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2806 info = &dbg_port_dspt_hdt_tx8; 2807 rtw89_write16_mask(rtwdev, info->sel_addr, 2808 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2809 rtw89_write16_mask(rtwdev, info->sel_addr, 2810 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2811 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2812 break; 2813 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2814 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2815 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2816 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2817 info = &dbg_port_dspt_hdt_tx9_C; 2818 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2819 rtw89_write16_mask(rtwdev, info->sel_addr, 2820 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2821 rtw89_write16_mask(rtwdev, info->sel_addr, 2822 B_AX_DISPATCHER_CH_SEL_MASK, index); 2823 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2824 break; 2825 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2826 info = &dbg_port_dspt_hdt_txD; 2827 rtw89_write16_mask(rtwdev, info->sel_addr, 2828 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2829 rtw89_write16_mask(rtwdev, info->sel_addr, 2830 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2831 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2832 break; 2833 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2834 info = &dbg_port_dspt_cdt_tx0; 2835 rtw89_write16_mask(rtwdev, info->sel_addr, 2836 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2837 rtw89_write16_mask(rtwdev, info->sel_addr, 2838 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2839 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2840 break; 2841 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2842 info = &dbg_port_dspt_cdt_tx1; 2843 rtw89_write16_mask(rtwdev, info->sel_addr, 2844 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2845 rtw89_write16_mask(rtwdev, info->sel_addr, 2846 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2847 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2848 break; 2849 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2850 info = &dbg_port_dspt_cdt_tx3; 2851 rtw89_write16_mask(rtwdev, info->sel_addr, 2852 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2853 rtw89_write16_mask(rtwdev, info->sel_addr, 2854 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2855 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2856 break; 2857 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2858 info = &dbg_port_dspt_cdt_tx4; 2859 rtw89_write16_mask(rtwdev, info->sel_addr, 2860 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2861 rtw89_write16_mask(rtwdev, info->sel_addr, 2862 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2863 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2864 break; 2865 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2866 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2867 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2868 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2869 info = &dbg_port_dspt_cdt_tx5_8; 2870 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2871 rtw89_write16_mask(rtwdev, info->sel_addr, 2872 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2873 rtw89_write16_mask(rtwdev, info->sel_addr, 2874 B_AX_DISPATCHER_CH_SEL_MASK, index); 2875 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2876 break; 2877 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2878 info = &dbg_port_dspt_cdt_tx9; 2879 rtw89_write16_mask(rtwdev, info->sel_addr, 2880 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2881 rtw89_write16_mask(rtwdev, info->sel_addr, 2882 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2883 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2884 break; 2885 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2886 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2887 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2888 info = &dbg_port_dspt_cdt_txA_C; 2889 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2890 rtw89_write16_mask(rtwdev, info->sel_addr, 2891 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2892 rtw89_write16_mask(rtwdev, info->sel_addr, 2893 B_AX_DISPATCHER_CH_SEL_MASK, index); 2894 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2895 break; 2896 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2897 info = &dbg_port_dspt_hdt_rx0; 2898 rtw89_write16_mask(rtwdev, info->sel_addr, 2899 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2900 rtw89_write16_mask(rtwdev, info->sel_addr, 2901 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2902 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2903 break; 2904 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2905 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2906 info = &dbg_port_dspt_hdt_rx1_2; 2907 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2908 rtw89_write16_mask(rtwdev, info->sel_addr, 2909 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2910 rtw89_write16_mask(rtwdev, info->sel_addr, 2911 B_AX_DISPATCHER_CH_SEL_MASK, index); 2912 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2913 break; 2914 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2915 info = &dbg_port_dspt_hdt_rx3; 2916 rtw89_write16_mask(rtwdev, info->sel_addr, 2917 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2918 rtw89_write16_mask(rtwdev, info->sel_addr, 2919 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2920 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2921 break; 2922 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2923 info = &dbg_port_dspt_hdt_rx4; 2924 rtw89_write16_mask(rtwdev, info->sel_addr, 2925 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2926 rtw89_write16_mask(rtwdev, info->sel_addr, 2927 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2928 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2929 break; 2930 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2931 info = &dbg_port_dspt_hdt_rx5; 2932 rtw89_write16_mask(rtwdev, info->sel_addr, 2933 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2934 rtw89_write16_mask(rtwdev, info->sel_addr, 2935 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2936 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2937 break; 2938 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2939 info = &dbg_port_dspt_cdt_rx_p0_0; 2940 rtw89_write16_mask(rtwdev, info->sel_addr, 2941 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2942 rtw89_write16_mask(rtwdev, info->sel_addr, 2943 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2944 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2945 break; 2946 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2947 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2948 info = &dbg_port_dspt_cdt_rx_p0_1; 2949 rtw89_write16_mask(rtwdev, info->sel_addr, 2950 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2951 rtw89_write16_mask(rtwdev, info->sel_addr, 2952 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2953 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2954 break; 2955 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2956 info = &dbg_port_dspt_cdt_rx_p0_2; 2957 rtw89_write16_mask(rtwdev, info->sel_addr, 2958 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2959 rtw89_write16_mask(rtwdev, info->sel_addr, 2960 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2961 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2962 break; 2963 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2964 info = &dbg_port_dspt_cdt_rx_p1; 2965 rtw89_write8_mask(rtwdev, info->sel_addr, 2966 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2967 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2968 break; 2969 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2970 info = &dbg_port_dspt_stf_ctrl; 2971 rtw89_write8_mask(rtwdev, info->sel_addr, 2972 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2973 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2974 break; 2975 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2976 info = &dbg_port_dspt_addr_ctrl; 2977 rtw89_write8_mask(rtwdev, info->sel_addr, 2978 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2979 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2980 break; 2981 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2982 info = &dbg_port_dspt_wde_intf; 2983 rtw89_write8_mask(rtwdev, info->sel_addr, 2984 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2985 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2986 break; 2987 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2988 info = &dbg_port_dspt_ple_intf; 2989 rtw89_write8_mask(rtwdev, info->sel_addr, 2990 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2991 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2992 break; 2993 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2994 info = &dbg_port_dspt_flow_ctrl; 2995 rtw89_write8_mask(rtwdev, info->sel_addr, 2996 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2997 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2998 break; 2999 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3000 info = &dbg_port_pcie_txdma; 3001 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3002 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3003 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3004 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3005 seq_puts(m, "Enable pcie txdma dump.\n"); 3006 break; 3007 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3008 info = &dbg_port_pcie_rxdma; 3009 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3010 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3011 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3012 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3013 seq_puts(m, "Enable pcie rxdma dump.\n"); 3014 break; 3015 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3016 info = &dbg_port_pcie_cvt; 3017 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3018 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3019 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3020 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3021 seq_puts(m, "Enable pcie cvt dump.\n"); 3022 break; 3023 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3024 info = &dbg_port_pcie_cxpl; 3025 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3026 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3027 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3028 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3029 seq_puts(m, "Enable pcie cxpl dump.\n"); 3030 break; 3031 case RTW89_DBG_PORT_SEL_PCIE_IO: 3032 info = &dbg_port_pcie_io; 3033 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3034 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3035 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3036 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3037 seq_puts(m, "Enable pcie io dump.\n"); 3038 break; 3039 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3040 info = &dbg_port_pcie_misc; 3041 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3042 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3043 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3044 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3045 seq_puts(m, "Enable pcie misc dump.\n"); 3046 break; 3047 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3048 info = &dbg_port_pcie_misc2; 3049 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3050 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3051 B_AX_PCIE_DBG_SEL_MASK); 3052 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3053 seq_puts(m, "Enable pcie misc2 dump.\n"); 3054 break; 3055 default: 3056 seq_puts(m, "Dbg port select err\n"); 3057 return NULL; 3058 } 3059 3060 return info; 3061 } 3062 3063 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3064 { 3065 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3066 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3067 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3068 return false; 3069 if (rtw89_is_rtl885xb(rtwdev) && 3070 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3071 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3072 return false; 3073 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3074 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3075 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3076 return false; 3077 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3078 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3079 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3080 return false; 3081 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3082 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3083 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3084 return false; 3085 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3086 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3087 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3088 return false; 3089 3090 return true; 3091 } 3092 3093 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3094 struct seq_file *m, u32 sel) 3095 { 3096 const struct rtw89_mac_dbg_port_info *info; 3097 u8 val8; 3098 u16 val16; 3099 u32 val32; 3100 u32 i; 3101 3102 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 3103 if (!info) { 3104 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3105 return -EINVAL; 3106 } 3107 3108 #define case_DBG_SEL(__sel) \ 3109 case RTW89_DBG_PORT_SEL_##__sel: \ 3110 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 3111 break 3112 3113 switch (sel) { 3114 case_DBG_SEL(PTCL_C0); 3115 case_DBG_SEL(PTCL_C1); 3116 case_DBG_SEL(SCH_C0); 3117 case_DBG_SEL(SCH_C1); 3118 case_DBG_SEL(TMAC_C0); 3119 case_DBG_SEL(TMAC_C1); 3120 case_DBG_SEL(RMAC_C0); 3121 case_DBG_SEL(RMAC_C1); 3122 case_DBG_SEL(RMACST_C0); 3123 case_DBG_SEL(RMACST_C1); 3124 case_DBG_SEL(TRXPTCL_C0); 3125 case_DBG_SEL(TRXPTCL_C1); 3126 case_DBG_SEL(TX_INFOL_C0); 3127 case_DBG_SEL(TX_INFOH_C0); 3128 case_DBG_SEL(TX_INFOL_C1); 3129 case_DBG_SEL(TX_INFOH_C1); 3130 case_DBG_SEL(TXTF_INFOL_C0); 3131 case_DBG_SEL(TXTF_INFOH_C0); 3132 case_DBG_SEL(TXTF_INFOL_C1); 3133 case_DBG_SEL(TXTF_INFOH_C1); 3134 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3135 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3136 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3137 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3138 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3139 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3140 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3141 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3142 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3143 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3144 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3145 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3146 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3147 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3148 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3149 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3150 case_DBG_SEL(PKTINFO); 3151 case_DBG_SEL(DSPT_HDT_TX0); 3152 case_DBG_SEL(DSPT_HDT_TX1); 3153 case_DBG_SEL(DSPT_HDT_TX2); 3154 case_DBG_SEL(DSPT_HDT_TX3); 3155 case_DBG_SEL(DSPT_HDT_TX4); 3156 case_DBG_SEL(DSPT_HDT_TX5); 3157 case_DBG_SEL(DSPT_HDT_TX6); 3158 case_DBG_SEL(DSPT_HDT_TX7); 3159 case_DBG_SEL(DSPT_HDT_TX8); 3160 case_DBG_SEL(DSPT_HDT_TX9); 3161 case_DBG_SEL(DSPT_HDT_TXA); 3162 case_DBG_SEL(DSPT_HDT_TXB); 3163 case_DBG_SEL(DSPT_HDT_TXC); 3164 case_DBG_SEL(DSPT_HDT_TXD); 3165 case_DBG_SEL(DSPT_HDT_TXE); 3166 case_DBG_SEL(DSPT_HDT_TXF); 3167 case_DBG_SEL(DSPT_CDT_TX0); 3168 case_DBG_SEL(DSPT_CDT_TX1); 3169 case_DBG_SEL(DSPT_CDT_TX3); 3170 case_DBG_SEL(DSPT_CDT_TX4); 3171 case_DBG_SEL(DSPT_CDT_TX5); 3172 case_DBG_SEL(DSPT_CDT_TX6); 3173 case_DBG_SEL(DSPT_CDT_TX7); 3174 case_DBG_SEL(DSPT_CDT_TX8); 3175 case_DBG_SEL(DSPT_CDT_TX9); 3176 case_DBG_SEL(DSPT_CDT_TXA); 3177 case_DBG_SEL(DSPT_CDT_TXB); 3178 case_DBG_SEL(DSPT_CDT_TXC); 3179 case_DBG_SEL(DSPT_HDT_RX0); 3180 case_DBG_SEL(DSPT_HDT_RX1); 3181 case_DBG_SEL(DSPT_HDT_RX2); 3182 case_DBG_SEL(DSPT_HDT_RX3); 3183 case_DBG_SEL(DSPT_HDT_RX4); 3184 case_DBG_SEL(DSPT_HDT_RX5); 3185 case_DBG_SEL(DSPT_CDT_RX_P0); 3186 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3187 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3188 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3189 case_DBG_SEL(DSPT_CDT_RX_P1); 3190 case_DBG_SEL(DSPT_STF_CTRL); 3191 case_DBG_SEL(DSPT_ADDR_CTRL); 3192 case_DBG_SEL(DSPT_WDE_INTF); 3193 case_DBG_SEL(DSPT_PLE_INTF); 3194 case_DBG_SEL(DSPT_FLOW_CTRL); 3195 case_DBG_SEL(PCIE_TXDMA); 3196 case_DBG_SEL(PCIE_RXDMA); 3197 case_DBG_SEL(PCIE_CVT); 3198 case_DBG_SEL(PCIE_CXPL); 3199 case_DBG_SEL(PCIE_IO); 3200 case_DBG_SEL(PCIE_MISC); 3201 case_DBG_SEL(PCIE_MISC2); 3202 } 3203 3204 #undef case_DBG_SEL 3205 3206 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 3207 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 3208 3209 for (i = info->srt; i <= info->end; i++) { 3210 switch (info->sel_byte) { 3211 case 1: 3212 default: 3213 rtw89_write8_mask(rtwdev, info->sel_addr, 3214 info->sel_msk, i); 3215 seq_printf(m, "0x%02X: ", i); 3216 break; 3217 case 2: 3218 rtw89_write16_mask(rtwdev, info->sel_addr, 3219 info->sel_msk, i); 3220 seq_printf(m, "0x%04X: ", i); 3221 break; 3222 case 4: 3223 rtw89_write32_mask(rtwdev, info->sel_addr, 3224 info->sel_msk, i); 3225 seq_printf(m, "0x%04X: ", i); 3226 break; 3227 } 3228 3229 udelay(10); 3230 3231 switch (info->rd_byte) { 3232 case 1: 3233 default: 3234 val8 = rtw89_read8_mask(rtwdev, 3235 info->rd_addr, info->rd_msk); 3236 seq_printf(m, "0x%02X\n", val8); 3237 break; 3238 case 2: 3239 val16 = rtw89_read16_mask(rtwdev, 3240 info->rd_addr, info->rd_msk); 3241 seq_printf(m, "0x%04X\n", val16); 3242 break; 3243 case 4: 3244 val32 = rtw89_read32_mask(rtwdev, 3245 info->rd_addr, info->rd_msk); 3246 seq_printf(m, "0x%08X\n", val32); 3247 break; 3248 } 3249 } 3250 3251 return 0; 3252 } 3253 3254 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3255 struct seq_file *m) 3256 { 3257 u32 sel; 3258 int ret = 0; 3259 3260 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3261 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3262 if (!is_dbg_port_valid(rtwdev, sel)) 3263 continue; 3264 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 3265 if (ret) { 3266 rtw89_err(rtwdev, 3267 "failed to dump debug port %d\n", sel); 3268 break; 3269 } 3270 } 3271 3272 return ret; 3273 } 3274 3275 static int 3276 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 3277 { 3278 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3279 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3280 3281 if (debugfs_priv->dbgpkg_en.ss_dbg) 3282 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 3283 if (debugfs_priv->dbgpkg_en.dle_dbg) 3284 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 3285 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3286 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 3287 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3288 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 3289 if (debugfs_priv->dbgpkg_en.dbg_port) 3290 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 3291 3292 return 0; 3293 }; 3294 3295 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 3296 const char __user *user_buf, size_t count) 3297 { 3298 char *buf; 3299 u8 *bin; 3300 int num; 3301 int err = 0; 3302 3303 buf = memdup_user(user_buf, count); 3304 if (IS_ERR(buf)) 3305 return buf; 3306 3307 num = count / 2; 3308 bin = kmalloc(num, GFP_KERNEL); 3309 if (!bin) { 3310 err = -EFAULT; 3311 goto out; 3312 } 3313 3314 if (hex2bin(bin, buf, num)) { 3315 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3316 kfree(bin); 3317 err = -EINVAL; 3318 } 3319 3320 out: 3321 kfree(buf); 3322 3323 return err ? ERR_PTR(err) : bin; 3324 } 3325 3326 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 3327 const char __user *user_buf, 3328 size_t count, loff_t *loff) 3329 { 3330 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3331 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3332 u8 *h2c; 3333 int ret; 3334 u16 h2c_len = count / 2; 3335 3336 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3337 if (IS_ERR(h2c)) 3338 return -EFAULT; 3339 3340 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3341 3342 kfree(h2c); 3343 3344 return ret ? ret : count; 3345 } 3346 3347 static int 3348 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3349 { 3350 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3351 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3352 struct rtw89_early_h2c *early_h2c; 3353 int seq = 0; 3354 3355 mutex_lock(&rtwdev->mutex); 3356 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3357 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3358 mutex_unlock(&rtwdev->mutex); 3359 3360 return 0; 3361 } 3362 3363 static ssize_t 3364 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3365 size_t count, loff_t *loff) 3366 { 3367 struct seq_file *m = (struct seq_file *)filp->private_data; 3368 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3369 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3370 struct rtw89_early_h2c *early_h2c; 3371 u8 *h2c; 3372 u16 h2c_len = count / 2; 3373 3374 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3375 if (IS_ERR(h2c)) 3376 return -EFAULT; 3377 3378 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3379 kfree(h2c); 3380 rtw89_fw_free_all_early_h2c(rtwdev); 3381 goto out; 3382 } 3383 3384 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3385 if (!early_h2c) { 3386 kfree(h2c); 3387 return -EFAULT; 3388 } 3389 3390 early_h2c->h2c = h2c; 3391 early_h2c->h2c_len = h2c_len; 3392 3393 mutex_lock(&rtwdev->mutex); 3394 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3395 mutex_unlock(&rtwdev->mutex); 3396 3397 out: 3398 return count; 3399 } 3400 3401 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3402 { 3403 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3404 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3405 u16 pkt_id; 3406 int ret; 3407 3408 rtw89_leave_ps_mode(rtwdev); 3409 3410 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3411 if (ret) 3412 return ret; 3413 3414 /* intentionally, enqueue two pkt, but has only one pkt id */ 3415 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3416 ctrl_para.start_pktid = pkt_id; 3417 ctrl_para.end_pktid = pkt_id; 3418 ctrl_para.pkt_num = 1; /* start from 0 */ 3419 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3420 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3421 3422 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3423 return -EFAULT; 3424 3425 return 0; 3426 } 3427 3428 static int 3429 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3430 { 3431 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3432 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3433 3434 seq_printf(m, "%d\n", 3435 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3436 return 0; 3437 } 3438 3439 enum rtw89_dbg_crash_simulation_type { 3440 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3441 RTW89_DBG_SIM_CTRL_ERROR = 2, 3442 }; 3443 3444 static ssize_t 3445 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3446 size_t count, loff_t *loff) 3447 { 3448 struct seq_file *m = (struct seq_file *)filp->private_data; 3449 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3450 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3451 int (*sim)(struct rtw89_dev *rtwdev); 3452 u8 crash_type; 3453 int ret; 3454 3455 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3456 if (ret) 3457 return -EINVAL; 3458 3459 switch (crash_type) { 3460 case RTW89_DBG_SIM_CPU_EXCEPTION: 3461 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3462 return -EOPNOTSUPP; 3463 sim = rtw89_fw_h2c_trigger_cpu_exception; 3464 break; 3465 case RTW89_DBG_SIM_CTRL_ERROR: 3466 sim = rtw89_dbg_trigger_ctrl_error; 3467 break; 3468 default: 3469 return -EINVAL; 3470 } 3471 3472 mutex_lock(&rtwdev->mutex); 3473 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3474 ret = sim(rtwdev); 3475 mutex_unlock(&rtwdev->mutex); 3476 3477 if (ret) 3478 return ret; 3479 3480 return count; 3481 } 3482 3483 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3484 { 3485 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3486 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3487 3488 rtw89_btc_dump_info(rtwdev, m); 3489 3490 return 0; 3491 } 3492 3493 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3494 const char __user *user_buf, 3495 size_t count, loff_t *loff) 3496 { 3497 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3498 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3499 struct rtw89_btc *btc = &rtwdev->btc; 3500 const struct rtw89_btc_ver *ver = btc->ver; 3501 int ret; 3502 3503 ret = kstrtobool_from_user(user_buf, count, &btc->manual_ctrl); 3504 if (ret) 3505 return ret; 3506 3507 if (ver->fcxctrl == 7) 3508 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3509 else 3510 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3511 3512 return count; 3513 } 3514 3515 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct file *filp, 3516 const char __user *user_buf, 3517 size_t count, loff_t *loff) 3518 { 3519 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3520 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3521 struct rtw89_fw_log *log = &rtwdev->fw.log; 3522 bool fw_log_manual; 3523 3524 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3525 goto out; 3526 3527 mutex_lock(&rtwdev->mutex); 3528 log->enable = fw_log_manual; 3529 if (log->enable) 3530 rtw89_fw_log_prepare(rtwdev); 3531 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3532 mutex_unlock(&rtwdev->mutex); 3533 out: 3534 return count; 3535 } 3536 3537 static void rtw89_sta_link_info_get_iter(struct seq_file *m, 3538 struct rtw89_dev *rtwdev, 3539 struct rtw89_sta_link *rtwsta_link) 3540 { 3541 static const char * const he_gi_str[] = { 3542 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3543 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3544 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3545 }; 3546 static const char * const eht_gi_str[] = { 3547 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3548 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3549 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3550 }; 3551 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3552 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3553 struct rtw89_hal *hal = &rtwdev->hal; 3554 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3555 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3556 struct ieee80211_link_sta *link_sta; 3557 u8 evm_min, evm_max, evm_1ss; 3558 u16 max_rc_amsdu_len; 3559 u8 rssi; 3560 u8 snr; 3561 int i; 3562 3563 rcu_read_lock(); 3564 3565 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3566 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3567 3568 rcu_read_unlock(); 3569 3570 seq_printf(m, "TX rate [%u, %u]: ", rtwsta_link->mac_id, rtwsta_link->link_id); 3571 3572 if (rate->flags & RATE_INFO_FLAGS_MCS) 3573 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3574 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3575 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3576 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3577 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3578 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3579 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3580 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3581 he_gi_str[rate->he_gi] : "N/A"); 3582 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3583 seq_printf(m, "EHT %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3584 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3585 eht_gi_str[rate->eht_gi] : "N/A"); 3586 else 3587 seq_printf(m, "Legacy %d", rate->legacy); 3588 seq_printf(m, "%s", rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3589 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3590 seq_printf(m, " (hw_rate=0x%x)", rtwsta_link->ra_report.hw_rate); 3591 seq_printf(m, " ==> agg_wait=%d (%d)\n", rtwsta_link->max_agg_wait, 3592 max_rc_amsdu_len); 3593 3594 seq_printf(m, "RX rate [%u, %u]: ", rtwsta_link->mac_id, rtwsta_link->link_id); 3595 3596 switch (status->encoding) { 3597 case RX_ENC_LEGACY: 3598 seq_printf(m, "Legacy %d", status->rate_idx + 3599 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3600 break; 3601 case RX_ENC_HT: 3602 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3603 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3604 break; 3605 case RX_ENC_VHT: 3606 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3607 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3608 break; 3609 case RX_ENC_HE: 3610 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3611 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3612 he_gi_str[status->he_gi] : "N/A"); 3613 break; 3614 case RX_ENC_EHT: 3615 seq_printf(m, "EHT %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3616 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3617 eht_gi_str[status->eht.gi] : "N/A"); 3618 break; 3619 } 3620 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3621 seq_printf(m, " (hw_rate=0x%x)\n", rtwsta_link->rx_hw_rate); 3622 3623 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3624 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3625 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta_link->prev_rssi); 3626 for (i = 0; i < ant_num; i++) { 3627 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3628 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3629 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3630 i + 1 == ant_num ? "" : ", "); 3631 } 3632 seq_puts(m, "]\n"); 3633 3634 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3635 seq_printf(m, "EVM: [%2u.%02u, ", evm_1ss >> 2, (evm_1ss & 0x3) * 25); 3636 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3637 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3638 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3639 3640 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ", 3641 evm_min >> 2, (evm_min & 0x3) * 25, 3642 evm_max >> 2, (evm_max & 0x3) * 25); 3643 } 3644 seq_puts(m, "]\t"); 3645 3646 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3647 seq_printf(m, "SNR: %u\n", snr); 3648 } 3649 3650 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3651 { 3652 struct seq_file *m = (struct seq_file *)data; 3653 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3654 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3655 struct rtw89_sta_link *rtwsta_link; 3656 unsigned int link_id; 3657 3658 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3659 rtw89_sta_link_info_get_iter(m, rtwdev, rtwsta_link); 3660 } 3661 3662 static void 3663 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3664 enum rtw89_hw_rate first_rate, int len) 3665 { 3666 int i; 3667 3668 for (i = 0; i < len; i++) 3669 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3670 pkt_stat->rx_rate_cnt[first_rate + i]); 3671 } 3672 3673 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3674 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3675 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3676 3677 static const struct rtw89_rx_rate_cnt_info { 3678 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3679 int len; 3680 int ext; 3681 const char *rate_mode; 3682 } rtw89_rx_rate_cnt_infos[] = { 3683 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3684 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3685 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3686 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3687 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3688 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3689 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3690 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3691 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3692 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3693 }; 3694 3695 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3696 { 3697 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3698 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3699 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3700 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3701 const struct rtw89_chip_info *chip = rtwdev->chip; 3702 const struct rtw89_rx_rate_cnt_info *info; 3703 struct rtw89_hal *hal = &rtwdev->hal; 3704 enum rtw89_hw_rate first_rate; 3705 u8 rssi; 3706 int i; 3707 3708 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3709 3710 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d", 3711 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv); 3712 if (hal->thermal_prot_lv) 3713 seq_printf(m, ", duty: %d%%", 3714 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 3715 seq_printf(m, "), RX: %u [%u] Mbps (lv: %d)\n", 3716 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3717 seq_printf(m, "Beacon: %u (%d dBm), TF: %u\n", pkt_stat->beacon_nr, 3718 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 3719 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3720 stats->rx_avg_len); 3721 3722 seq_puts(m, "RX count:\n"); 3723 3724 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3725 info = &rtw89_rx_rate_cnt_infos[i]; 3726 first_rate = info->first_rate[chip->chip_gen]; 3727 if (first_rate >= RTW89_HW_RATE_NR) 3728 continue; 3729 3730 seq_printf(m, "%10s [", info->rate_mode); 3731 rtw89_debug_append_rx_rate(m, pkt_stat, 3732 first_rate, info->len); 3733 if (info->ext) { 3734 seq_puts(m, "]["); 3735 rtw89_debug_append_rx_rate(m, pkt_stat, 3736 first_rate + info->len, info->ext); 3737 } 3738 seq_puts(m, "]\n"); 3739 } 3740 3741 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3742 3743 return 0; 3744 } 3745 3746 static void rtw89_dump_addr_cam(struct seq_file *m, 3747 struct rtw89_dev *rtwdev, 3748 struct rtw89_addr_cam_entry *addr_cam) 3749 { 3750 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3751 const struct rtw89_sec_cam_entry *sec_entry; 3752 u8 sec_cam_idx; 3753 int i; 3754 3755 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3756 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3757 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3758 addr_cam->sec_cam_map); 3759 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 3760 sec_cam_idx = addr_cam->sec_ent[i]; 3761 sec_entry = cam_info->sec_entries[sec_cam_idx]; 3762 if (!sec_entry) 3763 continue; 3764 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3765 if (sec_entry->ext_key) 3766 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3767 seq_puts(m, "\n"); 3768 } 3769 } 3770 3771 __printf(3, 4) 3772 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list, 3773 const char *fmt, ...) 3774 { 3775 struct rtw89_pktofld_info *info; 3776 struct va_format vaf; 3777 va_list args; 3778 3779 if (list_empty(pkt_list)) 3780 return; 3781 3782 va_start(args, fmt); 3783 vaf.va = &args; 3784 vaf.fmt = fmt; 3785 3786 seq_printf(m, "%pV", &vaf); 3787 3788 va_end(args); 3789 3790 list_for_each_entry(info, pkt_list, list) 3791 seq_printf(m, "%d ", info->id); 3792 3793 seq_puts(m, "\n"); 3794 } 3795 3796 static void rtw89_vif_link_ids_get(struct seq_file *m, u8 *mac, 3797 struct rtw89_dev *rtwdev, 3798 struct rtw89_vif_link *rtwvif_link) 3799 { 3800 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 3801 3802 seq_printf(m, " [%u] %pM\n", rtwvif_link->mac_id, rtwvif_link->mac_addr); 3803 seq_printf(m, "\tlink_id=%u\n", rtwvif_link->link_id); 3804 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3805 rtw89_dump_addr_cam(m, rtwdev, &rtwvif_link->addr_cam); 3806 rtw89_dump_pkt_offload(m, &rtwvif_link->general_pkt_list, 3807 "\tpkt_ofld[GENERAL]: "); 3808 } 3809 3810 static 3811 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3812 { 3813 struct seq_file *m = (struct seq_file *)data; 3814 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 3815 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3816 struct rtw89_vif_link *rtwvif_link; 3817 unsigned int link_id; 3818 3819 seq_printf(m, "VIF %pM\n", rtwvif->mac_addr); 3820 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3821 rtw89_vif_link_ids_get(m, mac, rtwdev, rtwvif_link); 3822 } 3823 3824 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_dev *rtwdev, 3825 struct rtw89_sta_link *rtwsta_link) 3826 { 3827 struct rtw89_ba_cam_entry *entry; 3828 bool first = true; 3829 3830 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 3831 if (first) { 3832 seq_puts(m, "\tba_cam "); 3833 first = false; 3834 } else { 3835 seq_puts(m, ", "); 3836 } 3837 seq_printf(m, "tid[%u]=%d", entry->tid, 3838 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3839 } 3840 seq_puts(m, "\n"); 3841 } 3842 3843 static void rtw89_sta_link_ids_get(struct seq_file *m, 3844 struct rtw89_dev *rtwdev, 3845 struct rtw89_sta_link *rtwsta_link) 3846 { 3847 struct ieee80211_link_sta *link_sta; 3848 3849 rcu_read_lock(); 3850 3851 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3852 3853 seq_printf(m, " [%u] %pM\n", rtwsta_link->mac_id, link_sta->addr); 3854 3855 rcu_read_unlock(); 3856 3857 seq_printf(m, "\tlink_id=%u\n", rtwsta_link->link_id); 3858 rtw89_dump_addr_cam(m, rtwdev, &rtwsta_link->addr_cam); 3859 rtw89_dump_ba_cam(m, rtwdev, rtwsta_link); 3860 } 3861 3862 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3863 { 3864 struct seq_file *m = (struct seq_file *)data; 3865 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3866 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3867 struct rtw89_sta_link *rtwsta_link; 3868 unsigned int link_id; 3869 3870 seq_printf(m, "STA %pM %s\n", sta->addr, sta->tdls ? "(TDLS)" : ""); 3871 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3872 rtw89_sta_link_ids_get(m, rtwdev, rtwsta_link); 3873 } 3874 3875 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3876 { 3877 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3878 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3879 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3880 u8 idx; 3881 3882 mutex_lock(&rtwdev->mutex); 3883 3884 seq_puts(m, "map:\n"); 3885 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3886 rtwdev->mac_id_map); 3887 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3888 cam_info->addr_cam_map); 3889 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3890 cam_info->bssid_cam_map); 3891 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3892 cam_info->sec_cam_map); 3893 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3894 cam_info->ba_cam_map); 3895 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload), 3896 rtwdev->pkt_offload); 3897 3898 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 3899 if (!(rtwdev->chip->support_bands & BIT(idx))) 3900 continue; 3901 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx], 3902 "\t\t[SCAN %u]: ", idx); 3903 } 3904 3905 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3906 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3907 3908 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3909 3910 mutex_unlock(&rtwdev->mutex); 3911 3912 return 0; 3913 } 3914 3915 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 3916 3917 static const struct rtw89_disabled_dm_info { 3918 enum rtw89_dm_type type; 3919 const char *name; 3920 } rtw89_disabled_dm_infos[] = { 3921 DM_INFO(DYNAMIC_EDCCA), 3922 DM_INFO(THERMAL_PROTECT), 3923 }; 3924 3925 static int 3926 rtw89_debug_priv_disable_dm_get(struct seq_file *m, void *v) 3927 { 3928 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3929 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3930 const struct rtw89_disabled_dm_info *info; 3931 struct rtw89_hal *hal = &rtwdev->hal; 3932 u32 disabled; 3933 int i; 3934 3935 seq_printf(m, "Disabled DM: 0x%x\n", hal->disabled_dm_bitmap); 3936 3937 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 3938 info = &rtw89_disabled_dm_infos[i]; 3939 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 3940 3941 seq_printf(m, "[%d] %s: %c\n", info->type, info->name, 3942 disabled ? 'X' : 'O'); 3943 } 3944 3945 return 0; 3946 } 3947 3948 static ssize_t 3949 rtw89_debug_priv_disable_dm_set(struct file *filp, const char __user *user_buf, 3950 size_t count, loff_t *loff) 3951 { 3952 struct seq_file *m = (struct seq_file *)filp->private_data; 3953 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3954 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3955 struct rtw89_hal *hal = &rtwdev->hal; 3956 u32 conf; 3957 int ret; 3958 3959 ret = kstrtou32_from_user(user_buf, count, 0, &conf); 3960 if (ret) 3961 return -EINVAL; 3962 3963 hal->disabled_dm_bitmap = conf; 3964 3965 return count; 3966 } 3967 3968 #define rtw89_debug_priv_get(name) \ 3969 { \ 3970 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3971 } 3972 3973 #define rtw89_debug_priv_set(name) \ 3974 { \ 3975 .cb_write = rtw89_debug_priv_ ##name## _set, \ 3976 } 3977 3978 #define rtw89_debug_priv_select_and_get(name) \ 3979 { \ 3980 .cb_write = rtw89_debug_priv_ ##name## _select, \ 3981 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3982 } 3983 3984 #define rtw89_debug_priv_set_and_get(name) \ 3985 { \ 3986 .cb_write = rtw89_debug_priv_ ##name## _set, \ 3987 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3988 } 3989 3990 static const struct rtw89_debugfs rtw89_debugfs_templ = { 3991 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 3992 .write_reg = rtw89_debug_priv_set(write_reg), 3993 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 3994 .write_rf = rtw89_debug_priv_set(write_rf), 3995 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump), 3996 .txpwr_table = rtw89_debug_priv_get(txpwr_table), 3997 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump), 3998 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump), 3999 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump), 4000 .send_h2c = rtw89_debug_priv_set(send_h2c), 4001 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c), 4002 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash), 4003 .btc_info = rtw89_debug_priv_get(btc_info), 4004 .btc_manual = rtw89_debug_priv_set(btc_manual), 4005 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual), 4006 .phy_info = rtw89_debug_priv_get(phy_info), 4007 .stations = rtw89_debug_priv_get(stations), 4008 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm), 4009 }; 4010 4011 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 4012 do { \ 4013 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 4014 priv->rtwdev = rtwdev; \ 4015 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 4016 &file_ops_ ##fopname))) \ 4017 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 4018 } while (0) 4019 4020 #define rtw89_debugfs_add_w(name) \ 4021 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 4022 #define rtw89_debugfs_add_rw(name) \ 4023 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4024 #define rtw89_debugfs_add_r(name) \ 4025 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4026 4027 static 4028 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4029 { 4030 rtw89_debugfs_add_rw(read_reg); 4031 rtw89_debugfs_add_w(write_reg); 4032 rtw89_debugfs_add_rw(read_rf); 4033 rtw89_debugfs_add_w(write_rf); 4034 rtw89_debugfs_add_r(rf_reg_dump); 4035 rtw89_debugfs_add_r(txpwr_table); 4036 rtw89_debugfs_add_rw(mac_reg_dump); 4037 rtw89_debugfs_add_rw(mac_mem_dump); 4038 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4039 } 4040 4041 static 4042 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4043 { 4044 rtw89_debugfs_add_w(send_h2c); 4045 rtw89_debugfs_add_rw(early_h2c); 4046 rtw89_debugfs_add_rw(fw_crash); 4047 rtw89_debugfs_add_r(btc_info); 4048 rtw89_debugfs_add_w(btc_manual); 4049 rtw89_debugfs_add_w(fw_log_manual); 4050 rtw89_debugfs_add_r(phy_info); 4051 rtw89_debugfs_add_r(stations); 4052 rtw89_debugfs_add_rw(disable_dm); 4053 } 4054 4055 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4056 { 4057 struct dentry *debugfs_topdir; 4058 4059 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4060 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4061 if (!rtwdev->debugfs) 4062 return; 4063 4064 #if defined(__linux__) 4065 debugfs_topdir = debugfs_create_dir("rtw89", 4066 #elif defined(__FreeBSD__) 4067 debugfs_topdir = debugfs_create_dir(dev_name(rtwdev->dev), 4068 #endif 4069 rtwdev->hw->wiphy->debugfsdir); 4070 4071 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4072 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4073 } 4074 4075 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4076 { 4077 kfree(rtwdev->debugfs); 4078 } 4079 #endif 4080 4081 #ifdef CONFIG_RTW89_DEBUGMSG 4082 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4083 const char *fmt, ...) 4084 { 4085 struct va_format vaf = { 4086 .fmt = fmt, 4087 }; 4088 4089 va_list args; 4090 4091 va_start(args, fmt); 4092 vaf.va = &args; 4093 4094 if (rtw89_debug_mask & mask) 4095 #if defined(__linux__) 4096 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4097 #elif defined(__FreeBSD__) 4098 { 4099 char *str; 4100 vasprintf(&str, M_KMALLOC, vaf.fmt, args); 4101 dev_printk(KERN_DEBUG, rtwdev->dev, "%s", str); 4102 free(str, M_KMALLOC); 4103 } 4104 #endif 4105 4106 va_end(args); 4107 } 4108 EXPORT_SYMBOL(rtw89_debug); 4109 #endif 4110