1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_platform.h"
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/reboot.h>
34
35 #include <vm/vm.h>
36 #include <vm/pmap.h>
37
38 #include <machine/armreg.h>
39 #include <machine/bus.h>
40 #include <machine/cpu.h>
41 #include <machine/machdep.h>
42
43 #include <arm/freescale/imx/imx_machdep.h>
44 #include <arm/freescale/imx/imx_wdogreg.h>
45
46 SYSCTL_NODE(_hw, OID_AUTO, imx, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,
47 "i.MX container");
48
49 static int last_reset_status;
50 SYSCTL_UINT(_hw_imx, OID_AUTO, last_reset_status, CTLFLAG_RD,
51 &last_reset_status, 0, "Last reset status register");
52
53 SYSCTL_STRING(_hw_imx, OID_AUTO, last_reset_reason, CTLFLAG_RD,
54 "unknown", 0, "Last reset reason");
55
56 /*
57 * This code which manipulates the watchdog hardware is here to implement
58 * cpu_reset() because the watchdog is the only way for software to reset the
59 * chip. Why here and not in imx_wdog.c? Because there's no requirement that
60 * the watchdog driver be compiled in, but it's nice to be able to reboot even
61 * if it's not.
62 */
63 void
imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr)64 imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr)
65 {
66 volatile uint16_t cr, *pcr;
67
68 if ((pcr = pmap_mapdev(wdcr_physaddr, sizeof(*pcr))) == NULL) {
69 printf("imx_wdog_cpu_reset(): "
70 "cannot find control register... locking up now.");
71 for (;;)
72 cpu_spinwait();
73 }
74 cr = *pcr;
75
76 /*
77 * If the watchdog hardware has been set up to trigger an external reset
78 * signal on watchdog timeout, then we do software-requested rebooting
79 * the same way, by asserting the external reset signal.
80 *
81 * Asserting external reset is supposed to result in some external
82 * component asserting the POR pin on the SoC, possibly after adjusting
83 * and stabilizing system voltages, or taking other system-wide reset
84 * actions. Just in case there is some kind of misconfiguration, we
85 * hang out and do nothing for a full second, then continue on into
86 * the code to assert a software reset as well.
87 */
88 if (cr & WDOG_CR_WDT) {
89 cr &= ~WDOG_CR_WDA; /* Assert active-low ext reset bit. */
90 *pcr = cr;
91 DELAY(1000000);
92 printf("imx_wdog_cpu_reset(): "
93 "External reset failed, trying internal cpu-reset\n");
94 DELAY(10000); /* Time for printf to appear */
95 }
96
97 /*
98 * Imx6 erratum ERR004346 says the SRS bit has to be cleared twice
99 * within the same cycle of the 32khz clock to reliably trigger the
100 * reset. Writing it 3 times in a row ensures at least 2 of the writes
101 * happen in the same 32k clock cycle.
102 */
103 cr &= ~WDOG_CR_SRS; /* Assert active-low software reset bit. */
104 *pcr = cr;
105 *pcr = cr;
106 *pcr = cr;
107
108 /* Reset happens on the next tick of the 32khz clock, wait for it. */
109 for (;;)
110 cpu_spinwait();
111 }
112
113 void
imx_wdog_init_last_reset(vm_offset_t wdsr_phys)114 imx_wdog_init_last_reset(vm_offset_t wdsr_phys)
115 {
116 volatile uint16_t * psr;
117
118 if ((psr = pmap_mapdev(wdsr_phys, sizeof(*psr))) == NULL)
119 return;
120 last_reset_status = *psr;
121 if (last_reset_status & WDOG_RSR_SFTW) {
122 sysctl___hw_imx_last_reset_reason.oid_arg1 = "SoftwareReset";
123 } else if (last_reset_status & WDOG_RSR_TOUT) {
124 sysctl___hw_imx_last_reset_reason.oid_arg1 = "WatchdogTimeout";
125 } else if (last_reset_status & WDOG_RSR_POR) {
126 sysctl___hw_imx_last_reset_reason.oid_arg1 = "PowerOnReset";
127 }
128 pmap_unmapdev((void *)(uintptr_t)psr, sizeof(*psr));
129 }
130