1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright 2021-2022 NXP
4 //
5 // Author: Peng Zhang <peng.zhang_8@nxp.com>
6 //
7 // Hardware interface for audio DSP on i.MX8ULP
8
9 #include <linux/arm-smccc.h>
10 #include <linux/clk.h>
11 #include <linux/firmware.h>
12 #include <linux/firmware/imx/dsp.h>
13 #include <linux/firmware/imx/ipc.h>
14 #include <linux/firmware/imx/svc/misc.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_reserved_mem.h>
21
22 #include <sound/sof.h>
23 #include <sound/sof/xtensa.h>
24
25 #include "../ops.h"
26 #include "../sof-of-dev.h"
27 #include "imx-common.h"
28
29 #define FSL_SIP_HIFI_XRDC 0xc200000e
30
31 /* SIM Domain register */
32 #define SYSCTRL0 0x8
33 #define EXECUTE_BIT BIT(13)
34 #define RESET_BIT BIT(16)
35 #define HIFI4_CLK_BIT BIT(17)
36 #define PB_CLK_BIT BIT(18)
37 #define PLAT_CLK_BIT BIT(19)
38 #define DEBUG_LOGIC_BIT BIT(25)
39
40 #define MBOX_OFFSET 0x800000
41 #define MBOX_SIZE 0x1000
42
43 struct imx8ulp_priv {
44 struct device *dev;
45 struct snd_sof_dev *sdev;
46
47 /* DSP IPC handler */
48 struct imx_dsp_ipc *dsp_ipc;
49 struct platform_device *ipc_dev;
50
51 struct regmap *regmap;
52 struct clk_bulk_data *clks;
53 int clk_num;
54 };
55
imx8ulp_sim_lpav_start(struct imx8ulp_priv * priv)56 static void imx8ulp_sim_lpav_start(struct imx8ulp_priv *priv)
57 {
58 /* Controls the HiFi4 DSP Reset: 1 in reset, 0 out of reset */
59 regmap_update_bits(priv->regmap, SYSCTRL0, RESET_BIT, 0);
60
61 /* Reset HiFi4 DSP Debug logic: 1 debug reset, 0 out of reset*/
62 regmap_update_bits(priv->regmap, SYSCTRL0, DEBUG_LOGIC_BIT, 0);
63
64 /* Stall HIFI4 DSP Execution: 1 stall, 0 run */
65 regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, 0);
66 }
67
imx8ulp_get_mailbox_offset(struct snd_sof_dev * sdev)68 static int imx8ulp_get_mailbox_offset(struct snd_sof_dev *sdev)
69 {
70 return MBOX_OFFSET;
71 }
72
imx8ulp_get_window_offset(struct snd_sof_dev * sdev,u32 id)73 static int imx8ulp_get_window_offset(struct snd_sof_dev *sdev, u32 id)
74 {
75 return MBOX_OFFSET;
76 }
77
imx8ulp_dsp_handle_reply(struct imx_dsp_ipc * ipc)78 static void imx8ulp_dsp_handle_reply(struct imx_dsp_ipc *ipc)
79 {
80 struct imx8ulp_priv *priv = imx_dsp_get_data(ipc);
81 unsigned long flags;
82
83 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
84
85 snd_sof_ipc_process_reply(priv->sdev, 0);
86
87 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
88 }
89
imx8ulp_dsp_handle_request(struct imx_dsp_ipc * ipc)90 static void imx8ulp_dsp_handle_request(struct imx_dsp_ipc *ipc)
91 {
92 struct imx8ulp_priv *priv = imx_dsp_get_data(ipc);
93 u32 p; /* panic code */
94
95 /* Read the message from the debug box. */
96 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
97
98 /* Check to see if the message is a panic code (0x0dead***) */
99 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
100 snd_sof_dsp_panic(priv->sdev, p, true);
101 else
102 snd_sof_ipc_msgs_rx(priv->sdev);
103 }
104
105 static struct imx_dsp_ops dsp_ops = {
106 .handle_reply = imx8ulp_dsp_handle_reply,
107 .handle_request = imx8ulp_dsp_handle_request,
108 };
109
imx8ulp_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)110 static int imx8ulp_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
111 {
112 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
113
114 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
115 msg->msg_size);
116 imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
117
118 return 0;
119 }
120
imx8ulp_run(struct snd_sof_dev * sdev)121 static int imx8ulp_run(struct snd_sof_dev *sdev)
122 {
123 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
124
125 imx8ulp_sim_lpav_start(priv);
126
127 return 0;
128 }
129
imx8ulp_reset(struct snd_sof_dev * sdev)130 static int imx8ulp_reset(struct snd_sof_dev *sdev)
131 {
132 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
133 struct arm_smccc_res smc_resource;
134
135 /* HiFi4 Platform Clock Enable: 1 enabled, 0 disabled */
136 regmap_update_bits(priv->regmap, SYSCTRL0, PLAT_CLK_BIT, PLAT_CLK_BIT);
137
138 /* HiFi4 PBCLK clock enable: 1 enabled, 0 disabled */
139 regmap_update_bits(priv->regmap, SYSCTRL0, PB_CLK_BIT, PB_CLK_BIT);
140
141 /* HiFi4 Clock Enable: 1 enabled, 0 disabled */
142 regmap_update_bits(priv->regmap, SYSCTRL0, HIFI4_CLK_BIT, HIFI4_CLK_BIT);
143
144 regmap_update_bits(priv->regmap, SYSCTRL0, RESET_BIT, RESET_BIT);
145 usleep_range(1, 2);
146
147 /* Stall HIFI4 DSP Execution: 1 stall, 0 not stall */
148 regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, EXECUTE_BIT);
149 usleep_range(1, 2);
150
151 arm_smccc_smc(FSL_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &smc_resource);
152
153 return 0;
154 }
155
imx8ulp_probe(struct snd_sof_dev * sdev)156 static int imx8ulp_probe(struct snd_sof_dev *sdev)
157 {
158 struct platform_device *pdev = to_platform_device(sdev->dev);
159 struct device_node *np = pdev->dev.of_node;
160 struct device_node *res_node;
161 struct resource *mmio;
162 struct imx8ulp_priv *priv;
163 struct resource res;
164 u32 base, size;
165 int ret = 0;
166
167 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
168 if (!priv)
169 return -ENOMEM;
170
171 sdev->num_cores = 1;
172 sdev->pdata->hw_pdata = priv;
173 priv->dev = sdev->dev;
174 priv->sdev = sdev;
175
176 /* System integration module(SIM) control dsp configuration */
177 priv->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,dsp-ctrl");
178 if (IS_ERR(priv->regmap))
179 return PTR_ERR(priv->regmap);
180
181 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
182 PLATFORM_DEVID_NONE,
183 pdev, sizeof(*pdev));
184 if (IS_ERR(priv->ipc_dev))
185 return PTR_ERR(priv->ipc_dev);
186
187 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
188 if (!priv->dsp_ipc) {
189 /* DSP IPC driver not probed yet, try later */
190 ret = -EPROBE_DEFER;
191 dev_err(sdev->dev, "Failed to get drvdata\n");
192 goto exit_pdev_unregister;
193 }
194
195 imx_dsp_set_data(priv->dsp_ipc, priv);
196 priv->dsp_ipc->ops = &dsp_ops;
197
198 /* DSP base */
199 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
200 if (mmio) {
201 base = mmio->start;
202 size = resource_size(mmio);
203 } else {
204 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
205 ret = -EINVAL;
206 goto exit_pdev_unregister;
207 }
208
209 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
210 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
211 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
212 base, size);
213 ret = -ENODEV;
214 goto exit_pdev_unregister;
215 }
216 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
217
218 res_node = of_parse_phandle(np, "memory-reserved", 0);
219 if (!res_node) {
220 dev_err(&pdev->dev, "failed to get memory region node\n");
221 ret = -ENODEV;
222 goto exit_pdev_unregister;
223 }
224
225 ret = of_address_to_resource(res_node, 0, &res);
226 of_node_put(res_node);
227 if (ret) {
228 dev_err(&pdev->dev, "failed to get reserved region address\n");
229 goto exit_pdev_unregister;
230 }
231
232 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
233 resource_size(&res));
234 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
235 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
236 base, size);
237 ret = -ENOMEM;
238 goto exit_pdev_unregister;
239 }
240 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
241
242 /* set default mailbox offset for FW ready message */
243 sdev->dsp_box.offset = MBOX_OFFSET;
244
245 ret = of_reserved_mem_device_init(sdev->dev);
246 if (ret) {
247 dev_err(&pdev->dev, "failed to init reserved memory region %d\n", ret);
248 goto exit_pdev_unregister;
249 }
250
251 ret = devm_clk_bulk_get_all(sdev->dev, &priv->clks);
252 if (ret < 0) {
253 dev_err(sdev->dev, "failed to fetch clocks: %d\n", ret);
254 goto exit_pdev_unregister;
255 }
256 priv->clk_num = ret;
257
258 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
259 if (ret < 0) {
260 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
261 goto exit_pdev_unregister;
262 }
263
264 return 0;
265
266 exit_pdev_unregister:
267 platform_device_unregister(priv->ipc_dev);
268
269 return ret;
270 }
271
imx8ulp_remove(struct snd_sof_dev * sdev)272 static void imx8ulp_remove(struct snd_sof_dev *sdev)
273 {
274 struct imx8ulp_priv *priv = sdev->pdata->hw_pdata;
275
276 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
277 platform_device_unregister(priv->ipc_dev);
278 }
279
280 /* on i.MX8 there is 1 to 1 match between type and BAR idx */
imx8ulp_get_bar_index(struct snd_sof_dev * sdev,u32 type)281 static int imx8ulp_get_bar_index(struct snd_sof_dev *sdev, u32 type)
282 {
283 return type;
284 }
285
imx8ulp_suspend(struct snd_sof_dev * sdev)286 static int imx8ulp_suspend(struct snd_sof_dev *sdev)
287 {
288 int i;
289 struct imx8ulp_priv *priv = (struct imx8ulp_priv *)sdev->pdata->hw_pdata;
290
291 /*Stall DSP, release in .run() */
292 regmap_update_bits(priv->regmap, SYSCTRL0, EXECUTE_BIT, EXECUTE_BIT);
293
294 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
295 imx_dsp_free_channel(priv->dsp_ipc, i);
296
297 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
298
299 return 0;
300 }
301
imx8ulp_resume(struct snd_sof_dev * sdev)302 static int imx8ulp_resume(struct snd_sof_dev *sdev)
303 {
304 struct imx8ulp_priv *priv = (struct imx8ulp_priv *)sdev->pdata->hw_pdata;
305 int i, ret;
306
307 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
308 if (ret < 0) {
309 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
310 return ret;
311 }
312
313 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
314 imx_dsp_request_channel(priv->dsp_ipc, i);
315
316 return 0;
317 }
318
imx8ulp_dsp_runtime_resume(struct snd_sof_dev * sdev)319 static int imx8ulp_dsp_runtime_resume(struct snd_sof_dev *sdev)
320 {
321 const struct sof_dsp_power_state target_dsp_state = {
322 .state = SOF_DSP_PM_D0,
323 .substate = 0,
324 };
325
326 imx8ulp_resume(sdev);
327
328 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
329 }
330
imx8ulp_dsp_runtime_suspend(struct snd_sof_dev * sdev)331 static int imx8ulp_dsp_runtime_suspend(struct snd_sof_dev *sdev)
332 {
333 const struct sof_dsp_power_state target_dsp_state = {
334 .state = SOF_DSP_PM_D3,
335 .substate = 0,
336 };
337
338 imx8ulp_suspend(sdev);
339
340 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
341 }
342
imx8ulp_dsp_suspend(struct snd_sof_dev * sdev,unsigned int target_state)343 static int imx8ulp_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
344 {
345 const struct sof_dsp_power_state target_dsp_state = {
346 .state = target_state,
347 .substate = 0,
348 };
349
350 if (!pm_runtime_suspended(sdev->dev))
351 imx8ulp_suspend(sdev);
352
353 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
354 }
355
imx8ulp_dsp_resume(struct snd_sof_dev * sdev)356 static int imx8ulp_dsp_resume(struct snd_sof_dev *sdev)
357 {
358 const struct sof_dsp_power_state target_dsp_state = {
359 .state = SOF_DSP_PM_D0,
360 .substate = 0,
361 };
362
363 imx8ulp_resume(sdev);
364
365 if (pm_runtime_suspended(sdev->dev)) {
366 pm_runtime_disable(sdev->dev);
367 pm_runtime_set_active(sdev->dev);
368 pm_runtime_mark_last_busy(sdev->dev);
369 pm_runtime_enable(sdev->dev);
370 pm_runtime_idle(sdev->dev);
371 }
372
373 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
374 }
375
376 static struct snd_soc_dai_driver imx8ulp_dai[] = {
377 {
378 .name = "sai5",
379 .playback = {
380 .channels_min = 1,
381 .channels_max = 32,
382 },
383 .capture = {
384 .channels_min = 1,
385 .channels_max = 32,
386 },
387 },
388 {
389 .name = "sai6",
390 .playback = {
391 .channels_min = 1,
392 .channels_max = 32,
393 },
394 .capture = {
395 .channels_min = 1,
396 .channels_max = 32,
397 },
398 },
399 };
400
imx8ulp_dsp_set_power_state(struct snd_sof_dev * sdev,const struct sof_dsp_power_state * target_state)401 static int imx8ulp_dsp_set_power_state(struct snd_sof_dev *sdev,
402 const struct sof_dsp_power_state *target_state)
403 {
404 sdev->dsp_power_state = *target_state;
405
406 return 0;
407 }
408
409 /* i.MX8 ops */
410 static const struct snd_sof_dsp_ops sof_imx8ulp_ops = {
411 /* probe and remove */
412 .probe = imx8ulp_probe,
413 .remove = imx8ulp_remove,
414 /* DSP core boot */
415 .run = imx8ulp_run,
416 .reset = imx8ulp_reset,
417
418 /* Block IO */
419 .block_read = sof_block_read,
420 .block_write = sof_block_write,
421
422 /* Module IO */
423 .read64 = sof_io_read64,
424
425 /* Mailbox IO */
426 .mailbox_read = sof_mailbox_read,
427 .mailbox_write = sof_mailbox_write,
428
429 /* ipc */
430 .send_msg = imx8ulp_send_msg,
431 .get_mailbox_offset = imx8ulp_get_mailbox_offset,
432 .get_window_offset = imx8ulp_get_window_offset,
433
434 .ipc_msg_data = sof_ipc_msg_data,
435 .set_stream_data_offset = sof_set_stream_data_offset,
436
437 /* stream callbacks */
438 .pcm_open = sof_stream_pcm_open,
439 .pcm_close = sof_stream_pcm_close,
440
441 /* module loading */
442 .get_bar_index = imx8ulp_get_bar_index,
443 /* firmware loading */
444 .load_firmware = snd_sof_load_firmware_memcpy,
445
446 /* Debug information */
447 .dbg_dump = imx8_dump,
448
449 /* Firmware ops */
450 .dsp_arch_ops = &sof_xtensa_arch_ops,
451
452 /* DAI drivers */
453 .drv = imx8ulp_dai,
454 .num_drv = ARRAY_SIZE(imx8ulp_dai),
455
456 /* ALSA HW info flags */
457 .hw_info = SNDRV_PCM_INFO_MMAP |
458 SNDRV_PCM_INFO_MMAP_VALID |
459 SNDRV_PCM_INFO_INTERLEAVED |
460 SNDRV_PCM_INFO_PAUSE |
461 SNDRV_PCM_INFO_BATCH |
462 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
463
464 /* PM */
465 .runtime_suspend = imx8ulp_dsp_runtime_suspend,
466 .runtime_resume = imx8ulp_dsp_runtime_resume,
467
468 .suspend = imx8ulp_dsp_suspend,
469 .resume = imx8ulp_dsp_resume,
470
471 .set_power_state = imx8ulp_dsp_set_power_state,
472 };
473
474 static struct snd_sof_of_mach sof_imx8ulp_machs[] = {
475 {
476 .compatible = "fsl,imx8ulp-evk",
477 .sof_tplg_filename = "sof-imx8ulp-btsco.tplg",
478 .drv_name = "asoc-audio-graph-card2",
479 },
480 {}
481 };
482
483 static struct sof_dev_desc sof_of_imx8ulp_desc = {
484 .of_machines = sof_imx8ulp_machs,
485 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
486 .ipc_default = SOF_IPC_TYPE_3,
487 .default_fw_path = {
488 [SOF_IPC_TYPE_3] = "imx/sof",
489 },
490 .default_tplg_path = {
491 [SOF_IPC_TYPE_3] = "imx/sof-tplg",
492 },
493 .default_fw_filename = {
494 [SOF_IPC_TYPE_3] = "sof-imx8ulp.ri",
495 },
496 .nocodec_tplg_filename = "sof-imx8ulp-nocodec.tplg",
497 .ops = &sof_imx8ulp_ops,
498 };
499
500 static const struct of_device_id sof_of_imx8ulp_ids[] = {
501 { .compatible = "fsl,imx8ulp-dsp", .data = &sof_of_imx8ulp_desc},
502 { }
503 };
504 MODULE_DEVICE_TABLE(of, sof_of_imx8ulp_ids);
505
506 /* DT driver definition */
507 static struct platform_driver snd_sof_of_imx8ulp_driver = {
508 .probe = sof_of_probe,
509 .remove = sof_of_remove,
510 .driver = {
511 .name = "sof-audio-of-imx8ulp",
512 .pm = &sof_of_pm,
513 .of_match_table = sof_of_imx8ulp_ids,
514 },
515 };
516 module_platform_driver(snd_sof_of_imx8ulp_driver);
517
518 MODULE_LICENSE("Dual BSD/GPL");
519 MODULE_DESCRIPTION("SOF support for IMX8ULP platforms");
520 MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA");
521