xref: /illumos-gate/usr/src/uts/sun4/io/px/px_ib.h (revision c17ca212a164f33e059475e39740f789fe154b5b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 
25 #ifndef	_SYS_PX_IB_H
26 #define	_SYS_PX_IB_H
27 
28 #ifdef	__cplusplus
29 extern "C" {
30 #endif
31 
32 #include <sys/ddi_subrdefs.h>
33 #include <sys/pci_tools.h>
34 
35 typedef struct px_ib		px_ib_t;
36 typedef struct px_ino		px_ino_t;
37 typedef struct px_ino_pil	px_ino_pil_t;
38 typedef struct px_ih		px_ih_t;
39 
40 /*
41  * interrupt block soft state structure:
42  *
43  * Each px node may share an interrupt block structure with its peer
44  * node or have its own private interrupt block structure.
45  */
46 struct px_ib {
47 	px_t		*ib_px_p;	/* link back to px soft state */
48 	px_ino_t	*ib_ino_lst;	/* ino link list */
49 	kmutex_t	ib_ino_lst_mutex; /* mutex for ino link list */
50 	kmutex_t	ib_intr_lock;	/* lock for internal intr  */
51 
52 	px_msiq_state_t	ib_msiq_state;	/* MSIQ soft state */
53 	px_msi_state_t	ib_msi_state;	/* MSI soft state */
54 };
55 
56 /*
57  * ih structure: one per every consumer of each ino and pil pair with interrupt
58  * registered.
59  */
60 struct px_ih {
61 	dev_info_t	*ih_dip;	/* devinfo structure */
62 	uint32_t	ih_inum;	/* interrupt number for this device */
63 	uint_t		(*ih_handler)(); /* interrupt handler */
64 	caddr_t		ih_handler_arg1; /* interrupt handler argument #1 */
65 	caddr_t		ih_handler_arg2; /* interrupt handler argument #2 */
66 	ddi_acc_handle_t ih_config_handle; /* config space reg map handle */
67 	uint_t		ih_intr_state;	/* only used for fixed interrupts */
68 	msiq_rec_type_t	ih_rec_type;	/* MSI or PCIe record type */
69 	msgcode_t	ih_msg_code;	/* MSI number or PCIe message code */
70 	uint8_t		ih_intr_flags;	/* interrupt handler status flags */
71 	px_ih_t		*ih_next;	/* Next entry in list */
72 	uint64_t	ih_ticks;	/* ticks spent in this handler */
73 	uint64_t	ih_nsec;	/* nsec spent in this handler */
74 	kstat_t		*ih_ksp;	/* pointer to kstat information */
75 	px_ino_pil_t	*ih_ipil_p;	/* only for use by kstat */
76 };
77 
78 /* Only used for fixed or legacy interrupts */
79 #define	PX_INTR_STATE_DISABLE	0	/* disabled */
80 #define	PX_INTR_STATE_ENABLE	1	/* enabled */
81 
82 /* Only used for MSI/X to track interrupt handler status */
83 #define	PX_INTR_IDLE		0x0	/* handler is idle */
84 #define	PX_INTR_RETARGET	0x1	/* retarget in progress */
85 #define	PX_INTR_PENDING		0x2	/* handler is pending */
86 
87 /*
88  * ino_pil structure: one per each ino and pil pair with interrupt registered
89  */
90 struct px_ino_pil {
91 	ushort_t	ipil_pil;	/* pil for this ino */
92 	ushort_t	ipil_ih_size;	/* size of px_ih_t list */
93 	px_ih_t		*ipil_ih_head;	/* px_ih_t list head */
94 	px_ih_t		*ipil_ih_tail;	/* px_ih_t list tail */
95 	px_ih_t		*ipil_ih_start;	/* starting point in px_ih_t list  */
96 	px_ino_t	*ipil_ino_p;	/* pointer to px_ino_t structure */
97 	px_ino_pil_t	*ipil_next_p;	/* pointer to next px_ino_pil_t */
98 };
99 
100 /*
101  * ino structure: one per each ino with interrupt registered
102  */
103 struct px_ino {
104 	devino_t	ino_ino;	/* INO number - 8 bit */
105 	sysino_t	ino_sysino;	/* Virtual inumber */
106 	px_ib_t		*ino_ib_p;	/* link back to interrupt block state */
107 	uint_t		ino_unclaimed_intrs; /* number of unclaimed intrs */
108 	clock_t		ino_spurintr_begin; /* begin time of spurious intr */
109 	cpuid_t		ino_cpuid;	/* current cpu for this ino */
110 	cpuid_t		ino_default_cpuid; /* default cpu for this ino */
111 	int32_t		ino_intr_weight; /* intr wt of devices sharing ino */
112 	ushort_t	ino_ipil_size;	/* no of px_ino_pil_t sharing ino */
113 	ushort_t	ino_lopil;	/* lowest pil sharing ino */
114 	ushort_t	ino_claimed;	/* pil bit masks, who claimed intr */
115 	px_msiq_t	*ino_msiq_p;	/* pointer to MSIQ used */
116 	px_ino_pil_t	*ino_ipil_p;	/* pointer to first px_ino_pil_t */
117 	px_ino_t	*ino_next_p;	/* pointer to next px_ino_t */
118 	ushort_t	ino_ipil_cntr;	/* counter for pil sharing ino */
119 };
120 
121 #define	IB_INTR_WAIT	1		/* wait for interrupt completion */
122 #define	IB_INTR_NOWAIT	0		/* already handling intr, no wait */
123 
124 #define	PX_INTR_ENABLE(dip, sysino, cpuid) \
125 	(void) px_lib_intr_settarget(dip, sysino, cpuid); \
126 	(void) px_lib_intr_setvalid(dip, sysino, INTR_VALID);
127 
128 #define	PX_INTR_DISABLE(dip, sysino) \
129 	(void) px_lib_intr_setvalid(dip, sysino, INTR_NOTVALID);
130 
131 extern int px_ib_attach(px_t *px_p);
132 extern void px_ib_detach(px_t *px_p);
133 extern void px_ib_intr_enable(px_t *px_p, cpuid_t cpuid, devino_t ino);
134 extern void px_ib_intr_disable(px_ib_t *ib_p, devino_t ino, int wait);
135 extern int px_ib_intr_pend(dev_info_t *dip, sysino_t sysino);
136 extern void px_ib_intr_dist_en(dev_info_t *dip, cpuid_t cpu_id, devino_t ino,
137     boolean_t wait_flag);
138 
139 extern px_ino_t *px_ib_locate_ino(px_ib_t *ib_p, devino_t ino_num);
140 extern void px_ib_free_ino_all(px_ib_t *ib_p);
141 
142 extern px_ino_pil_t *px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil);
143 extern px_ino_t *px_ib_alloc_ino(px_ib_t *ib_p, devino_t ino_num);
144 extern px_ino_pil_t *px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num,
145     uint_t pil, px_ih_t *ih_p);
146 extern void px_ib_delete_ino_pil(px_ib_t *ib_p, px_ino_pil_t *ipil_p);
147 extern int px_ib_ino_add_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
148 extern int px_ib_ino_rem_intr(px_t *px_p, px_ino_pil_t *ipil_p, px_ih_t *ih_p);
149 
150 extern px_ih_t *px_ib_intr_locate_ih(px_ino_pil_t *ipil_p, dev_info_t *dip,
151 	uint32_t inum, msiq_rec_type_t rec_type, msgcode_t msg_code);
152 extern px_ih_t *px_ib_alloc_ih(dev_info_t *rdip, uint32_t inum,
153 	uint_t (*int_handler)(caddr_t int_handler_arg1,
154 	caddr_t int_handler_arg2), caddr_t int_handler_arg1,
155 	caddr_t int_handler_arg2, msiq_rec_type_t rec_type, msgcode_t msg_code);
156 extern void px_ib_free_ih(px_ih_t *ih_p);
157 extern int px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum,
158 	devino_t ino, uint_t pil, uint_t new_intr_state,
159 	msiq_rec_type_t rec_type, msgcode_t msg_code);
160 extern int px_ib_get_intr_target(px_t *px_p, devino_t ino, cpuid_t *cpu_id_p);
161 extern int px_ib_set_intr_target(px_t *px_p, devino_t ino, cpuid_t cpu_id);
162 extern int px_ib_set_msix_target(px_t *px_p, ddi_intr_handle_impl_t *hdlp,
163 	msinum_t msi_num, cpuid_t cpuid);
164 extern uint8_t pxtool_ib_get_ino_devs(px_t *px_p, uint32_t ino,
165 	uint32_t msi_num, uint8_t *devs_ret, pcitool_intr_dev_t *devs);
166 extern int pxtool_ib_get_msi_info(px_t *px_p, devino_t ino, msinum_t msi_num,
167 	ddi_intr_handle_impl_t *hdlp);
168 extern void px_ib_log_new_cpu(px_ib_t *ib_p, cpuid_t old_cpu_id,
169 	cpuid_t new_cpu_id, uint32_t ino);
170 
171 #ifdef	__cplusplus
172 }
173 #endif
174 
175 #endif	/* _SYS_PX_IB_H */
176