1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26 #include <linux/args.h>
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <linux/msi_api.h>
42 #include <uapi/linux/pci.h>
43
44 #include <linux/pci_ids.h>
45
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 8
55
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
58
59 /*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
70 */
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
75 /* pci_slot represents a physical slot */
76 struct pci_slot {
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
82 };
83
pci_slot_name(const struct pci_slot * slot)84 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 {
86 return kobject_name(&slot->kobj);
87 }
88
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
90 enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93 };
94
95 /* For PCI devices, the region numbers are assigned this way: */
96 enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108 #endif
109
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_P2P_BRIDGE_RESOURCE_NUM 3
123 #define PCI_BRIDGE_RESOURCE_NUM 4
124
125 /* Resources assigned to buses behind the bridge */
126 PCI_BRIDGE_RESOURCES,
127 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
128 PCI_BRIDGE_RESOURCE_NUM - 1,
129
130 /* Total resources associated with a PCI device */
131 PCI_NUM_RESOURCES,
132
133 /* Preserve this for compatibility */
134 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
135 };
136
137 /**
138 * enum pci_interrupt_pin - PCI INTx interrupt values
139 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
140 * @PCI_INTERRUPT_INTA: PCI INTA pin
141 * @PCI_INTERRUPT_INTB: PCI INTB pin
142 * @PCI_INTERRUPT_INTC: PCI INTC pin
143 * @PCI_INTERRUPT_INTD: PCI INTD pin
144 *
145 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
146 * PCI_INTERRUPT_PIN register.
147 */
148 enum pci_interrupt_pin {
149 PCI_INTERRUPT_UNKNOWN,
150 PCI_INTERRUPT_INTA,
151 PCI_INTERRUPT_INTB,
152 PCI_INTERRUPT_INTC,
153 PCI_INTERRUPT_INTD,
154 };
155
156 /* The number of legacy PCI INTx interrupts */
157 #define PCI_NUM_INTX 4
158
159 /*
160 * Reading from a device that doesn't respond typically returns ~0. A
161 * successful read from a device may also return ~0, so you need additional
162 * information to reliably identify errors.
163 */
164 #define PCI_ERROR_RESPONSE (~0ULL)
165 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
166 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
167
168 /*
169 * pci_power_t values must match the bits in the Capabilities PME_Support
170 * and Control/Status PowerState fields in the Power Management capability.
171 */
172 typedef int __bitwise pci_power_t;
173
174 #define PCI_D0 ((pci_power_t __force) 0)
175 #define PCI_D1 ((pci_power_t __force) 1)
176 #define PCI_D2 ((pci_power_t __force) 2)
177 #define PCI_D3hot ((pci_power_t __force) 3)
178 #define PCI_D3cold ((pci_power_t __force) 4)
179 #define PCI_UNKNOWN ((pci_power_t __force) 5)
180 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
181
182 /* Remember to update this when the list above changes! */
183 extern const char *pci_power_names[];
184
pci_power_name(pci_power_t state)185 static inline const char *pci_power_name(pci_power_t state)
186 {
187 return pci_power_names[1 + (__force int) state];
188 }
189
190 /**
191 * typedef pci_channel_state_t
192 *
193 * The pci_channel state describes connectivity between the CPU and
194 * the PCI device. If some PCI bus between here and the PCI device
195 * has crashed or locked up, this info is reflected here.
196 */
197 typedef unsigned int __bitwise pci_channel_state_t;
198
199 enum {
200 /* I/O channel is in normal state */
201 pci_channel_io_normal = (__force pci_channel_state_t) 1,
202
203 /* I/O to channel is blocked */
204 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
205
206 /* PCI card is dead */
207 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
208 };
209
210 typedef unsigned int __bitwise pcie_reset_state_t;
211
212 enum pcie_reset_state {
213 /* Reset is NOT asserted (Use to deassert reset) */
214 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
215
216 /* Use #PERST to reset PCIe device */
217 pcie_warm_reset = (__force pcie_reset_state_t) 2,
218
219 /* Use PCIe Hot Reset to reset device */
220 pcie_hot_reset = (__force pcie_reset_state_t) 3
221 };
222
223 typedef unsigned short __bitwise pci_dev_flags_t;
224 enum pci_dev_flags {
225 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
226 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
227 /* Device configuration is irrevocably lost if disabled into D3 */
228 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
229 /* Provide indication device is assigned by a Virtual Machine Manager */
230 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
231 /* Flag for quirk use to store if quirk-specific ACS is enabled */
232 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
233 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
234 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
235 /* Do not use bus resets for device */
236 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
237 /* Do not use PM reset even if device advertises NoSoftRst- */
238 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
239 /* Get VPD from function 0 VPD */
240 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
241 /* A non-root bridge where translation occurs, stop alias search here */
242 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
243 /* Do not use FLR even if device advertises PCI_AF_CAP */
244 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
245 /* Don't use Relaxed Ordering for TLPs directed at this device */
246 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
247 /* Device does honor MSI masking despite saying otherwise */
248 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
249 /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */
250 PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13),
251 };
252
253 enum pci_irq_reroute_variant {
254 INTEL_IRQ_REROUTE_VARIANT = 1,
255 MAX_IRQ_REROUTE_VARIANTS = 3
256 };
257
258 typedef unsigned short __bitwise pci_bus_flags_t;
259 enum pci_bus_flags {
260 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
261 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
262 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
263 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
264 };
265
266 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
267 enum pcie_link_width {
268 PCIE_LNK_WIDTH_RESRV = 0x00,
269 PCIE_LNK_X1 = 0x01,
270 PCIE_LNK_X2 = 0x02,
271 PCIE_LNK_X4 = 0x04,
272 PCIE_LNK_X8 = 0x08,
273 PCIE_LNK_X12 = 0x0c,
274 PCIE_LNK_X16 = 0x10,
275 PCIE_LNK_X32 = 0x20,
276 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
277 };
278
279 /* See matching string table in pci_speed_string() */
280 enum pci_bus_speed {
281 PCI_SPEED_33MHz = 0x00,
282 PCI_SPEED_66MHz = 0x01,
283 PCI_SPEED_66MHz_PCIX = 0x02,
284 PCI_SPEED_100MHz_PCIX = 0x03,
285 PCI_SPEED_133MHz_PCIX = 0x04,
286 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
287 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
288 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
289 PCI_SPEED_66MHz_PCIX_266 = 0x09,
290 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
291 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
292 AGP_UNKNOWN = 0x0c,
293 AGP_1X = 0x0d,
294 AGP_2X = 0x0e,
295 AGP_4X = 0x0f,
296 AGP_8X = 0x10,
297 PCI_SPEED_66MHz_PCIX_533 = 0x11,
298 PCI_SPEED_100MHz_PCIX_533 = 0x12,
299 PCI_SPEED_133MHz_PCIX_533 = 0x13,
300 PCIE_SPEED_2_5GT = 0x14,
301 PCIE_SPEED_5_0GT = 0x15,
302 PCIE_SPEED_8_0GT = 0x16,
303 PCIE_SPEED_16_0GT = 0x17,
304 PCIE_SPEED_32_0GT = 0x18,
305 PCIE_SPEED_64_0GT = 0x19,
306 PCI_SPEED_UNKNOWN = 0xff,
307 };
308
309 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
310 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
311
312 struct pci_vpd {
313 struct mutex lock;
314 unsigned int len;
315 u8 cap;
316 };
317
318 struct irq_affinity;
319 struct pcie_bwctrl_data;
320 struct pcie_link_state;
321 struct pci_sriov;
322 struct pci_p2pdma;
323 struct rcec_ea;
324
325 /* struct pci_dev - describes a PCI device
326 *
327 * @supported_speeds: PCIe Supported Link Speeds Vector (+ reserved 0 at
328 * LSB). 0 when the supported speeds cannot be
329 * determined (e.g., for Root Complex Integrated
330 * Endpoints without the relevant Capability
331 * Registers).
332 * @is_hotplug_bridge: Hotplug bridge of any kind (e.g. PCIe Hot-Plug Capable,
333 * Conventional PCI Hot-Plug, ACPI slot).
334 * Such bridges are allocated additional MMIO and bus
335 * number resources to allow for hierarchy expansion.
336 * @is_pciehp: PCIe Hot-Plug Capable bridge.
337 */
338 struct pci_dev {
339 struct list_head bus_list; /* Node in per-bus list */
340 struct pci_bus *bus; /* Bus this device is on */
341 struct pci_bus *subordinate; /* Bus this device bridges to */
342
343 void *sysdata; /* Hook for sys-specific extension */
344 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
345 struct pci_slot *slot; /* Physical slot this device is in */
346
347 unsigned int devfn; /* Encoded device & function index */
348 unsigned short vendor;
349 unsigned short device;
350 unsigned short subsystem_vendor;
351 unsigned short subsystem_device;
352 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
353 u8 revision; /* PCI revision, low byte of class word */
354 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
355 #ifdef CONFIG_PCIEAER
356 u16 aer_cap; /* AER capability offset */
357 struct aer_info *aer_info; /* AER info for this device */
358 #endif
359 #ifdef CONFIG_PCIEPORTBUS
360 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
361 struct pci_dev *rcec; /* Associated RCEC device */
362 #endif
363 u32 devcap; /* PCIe Device Capabilities */
364 u16 rebar_cap; /* Resizable BAR capability offset */
365 u8 pcie_cap; /* PCIe capability offset */
366 u8 msi_cap; /* MSI capability offset */
367 u8 msix_cap; /* MSI-X capability offset */
368 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
369 u8 rom_base_reg; /* Config register controlling ROM */
370 u8 pin; /* Interrupt pin this device uses */
371 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
372 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
373
374 struct pci_driver *driver; /* Driver bound to this device */
375 u64 dma_mask; /* Mask of the bits of bus address this
376 device implements. Normally this is
377 0xffffffff. You only need to change
378 this if your device has broken DMA
379 or supports 64-bit transfers. */
380
381 struct device_dma_parameters dma_parms;
382
383 pci_power_t current_state; /* Current operating state. In ACPI,
384 this is D0-D3, D0 being fully
385 functional, and D3 being off. */
386 u8 pm_cap; /* PM capability offset */
387 unsigned int pme_support:5; /* Bitmask of states from which PME#
388 can be generated */
389 unsigned int pme_poll:1; /* Poll device's PME status bit */
390 unsigned int pinned:1; /* Whether this dev is pinned */
391 unsigned int config_rrs_sv:1; /* Config RRS software visibility */
392 unsigned int imm_ready:1; /* Supports Immediate Readiness */
393 unsigned int d1_support:1; /* Low power state D1 is supported */
394 unsigned int d2_support:1; /* Low power state D2 is supported */
395 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
396 unsigned int no_d3cold:1; /* D3cold is forbidden */
397 unsigned int bridge_d3:1; /* Allow D3 for bridge */
398 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
399 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
400 decoding during BAR sizing */
401 unsigned int wakeup_prepared:1;
402 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
403 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
404 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
405 controlled exclusively by
406 user sysfs */
407 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
408 bit manually */
409 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
410 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
411
412 u16 l1ss; /* L1SS Capability pointer */
413 #ifdef CONFIG_PCIEASPM
414 struct pcie_link_state *link_state; /* ASPM link state */
415 unsigned int aspm_l0s_support:1; /* ASPM L0s support */
416 unsigned int aspm_l1_support:1; /* ASPM L1 support */
417 unsigned int ltr_path:1; /* Latency Tolerance Reporting
418 supported from root to here */
419 #endif
420 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
421 unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=not supported */
422
423 pci_channel_state_t error_state; /* Current connectivity state */
424 struct device dev; /* Generic device interface */
425
426 int cfg_size; /* Size of config space */
427
428 /*
429 * Instead of touching interrupt line and base address registers
430 * directly, use the values stored here. They might be different!
431 */
432 unsigned int irq;
433 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
434 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
435
436 unsigned int transparent:1; /* Subtractive decode bridge */
437 unsigned int io_window:1; /* Bridge has I/O window */
438 unsigned int pref_window:1; /* Bridge has pref mem window */
439 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
440 unsigned int multifunction:1; /* Multi-function device */
441
442 unsigned int is_busmaster:1; /* Is busmaster */
443 unsigned int no_msi:1; /* May not use MSI */
444 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
445 unsigned int block_cfg_access:1; /* Config space access blocked */
446 unsigned int broken_parity_status:1; /* Generates false positive parity */
447 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
448 unsigned int msi_enabled:1;
449 unsigned int msix_enabled:1;
450 unsigned int ari_enabled:1; /* ARI forwarding */
451 unsigned int ats_enabled:1; /* Address Translation Svc */
452 unsigned int pasid_enabled:1; /* Process Address Space ID */
453 unsigned int pri_enabled:1; /* Page Request Interface */
454 unsigned int tph_enabled:1; /* TLP Processing Hints */
455 unsigned int fm_enabled:1; /* Flit Mode (segment captured) */
456 unsigned int is_managed:1; /* Managed via devres */
457 unsigned int is_msi_managed:1; /* MSI release via devres installed */
458 unsigned int needs_freset:1; /* Requires fundamental reset */
459 unsigned int state_saved:1;
460 unsigned int is_physfn:1;
461 unsigned int is_virtfn:1;
462 unsigned int is_hotplug_bridge:1;
463 unsigned int is_pciehp:1;
464 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
465 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
466 /*
467 * Devices marked being untrusted are the ones that can potentially
468 * execute DMA attacks and similar. They are typically connected
469 * through external ports such as Thunderbolt but not limited to
470 * that. When an IOMMU is enabled they should be getting full
471 * mappings to make sure they cannot access arbitrary memory.
472 */
473 unsigned int untrusted:1;
474 /*
475 * Info from the platform, e.g., ACPI or device tree, may mark a
476 * device as "external-facing". An external-facing device is
477 * itself internal but devices downstream from it are external.
478 */
479 unsigned int external_facing:1;
480 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
481 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
482 unsigned int irq_managed:1;
483 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
484 unsigned int is_probed:1; /* Device probing in progress */
485 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
486 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
487 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
488 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
489 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */
490 unsigned int non_mappable_bars:1; /* BARs can't be mapped to user-space */
491 pci_dev_flags_t dev_flags;
492 atomic_t enable_cnt; /* pci_enable_device has been called */
493
494 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
495 u32 saved_config_space[16]; /* Config space saved at suspend time */
496 struct hlist_head saved_cap_space;
497 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
498 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
499
500 #ifdef CONFIG_HOTPLUG_PCI_PCIE
501 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
502 #endif
503 #ifdef CONFIG_PCIE_PTM
504 u16 ptm_cap; /* PTM Capability */
505 unsigned int ptm_root:1;
506 unsigned int ptm_responder:1;
507 unsigned int ptm_requester:1;
508 unsigned int ptm_enabled:1;
509 u8 ptm_granularity;
510 #endif
511 #ifdef CONFIG_PCI_MSI
512 void __iomem *msix_base;
513 raw_spinlock_t msi_lock;
514 #endif
515 struct pci_vpd vpd;
516 #ifdef CONFIG_PCIE_DPC
517 u16 dpc_cap;
518 unsigned int dpc_rp_extensions:1;
519 u8 dpc_rp_log_size;
520 #endif
521 struct pcie_bwctrl_data *link_bwctrl;
522 #ifdef CONFIG_PCI_ATS
523 union {
524 struct pci_sriov *sriov; /* PF: SR-IOV info */
525 struct pci_dev *physfn; /* VF: related PF */
526 };
527 u16 ats_cap; /* ATS Capability offset */
528 u8 ats_stu; /* ATS Smallest Translation Unit */
529 #endif
530 #ifdef CONFIG_PCI_PRI
531 u16 pri_cap; /* PRI Capability offset */
532 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
533 unsigned int pasid_required:1; /* PRG Response PASID Required */
534 #endif
535 #ifdef CONFIG_PCI_PASID
536 u16 pasid_cap; /* PASID Capability offset */
537 u16 pasid_features;
538 #endif
539 #ifdef CONFIG_PCI_P2PDMA
540 struct pci_p2pdma __rcu *p2pdma;
541 #endif
542 #ifdef CONFIG_PCI_DOE
543 struct xarray doe_mbs; /* Data Object Exchange mailboxes */
544 #endif
545 #ifdef CONFIG_PCI_NPEM
546 struct npem *npem; /* Native PCIe Enclosure Management */
547 #endif
548 #ifdef CONFIG_PCI_IDE
549 u16 ide_cap; /* Link Integrity & Data Encryption */
550 u8 nr_ide_mem; /* Address association resources for streams */
551 u8 nr_link_ide; /* Link Stream count (Selective Stream offset) */
552 u16 nr_sel_ide; /* Selective Stream count (register block allocator) */
553 struct ida ide_stream_ida;
554 unsigned int ide_cfg:1; /* Config cycles over IDE */
555 unsigned int ide_tee_limit:1; /* Disallow T=0 traffic over IDE */
556 #endif
557 #ifdef CONFIG_PCI_TSM
558 struct pci_tsm *tsm; /* TSM operation state */
559 #endif
560 u16 acs_cap; /* ACS Capability offset */
561 u8 supported_speeds; /* Supported Link Speeds Vector */
562 phys_addr_t rom; /* Physical address if not from BAR */
563 size_t romlen; /* Length if not from BAR */
564 /*
565 * Driver name to force a match. Do not set directly, because core
566 * frees it. Use driver_set_override() to set or clear it.
567 */
568 const char *driver_override;
569
570 unsigned long priv_flags; /* Private flags for the PCI driver */
571
572 /* These methods index pci_reset_fn_methods[] */
573 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
574
575 #ifdef CONFIG_PCIE_TPH
576 u16 tph_cap; /* TPH capability offset */
577 u8 tph_mode; /* TPH mode */
578 u8 tph_req_type; /* TPH requester type */
579 #endif
580 };
581
pci_physfn(struct pci_dev * dev)582 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
583 {
584 #ifdef CONFIG_PCI_IOV
585 if (dev->is_virtfn)
586 dev = dev->physfn;
587 #endif
588 return dev;
589 }
590
591 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
592
593 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
594 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
595 #define for_each_pci_dev_reverse(d) \
596 while ((d = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
597
pci_channel_offline(struct pci_dev * pdev)598 static inline int pci_channel_offline(struct pci_dev *pdev)
599 {
600 return (pdev->error_state != pci_channel_io_normal);
601 }
602
603 /*
604 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
605 * Group number is limited to a 16-bit value, therefore (int)-1 is
606 * not a valid PCI domain number, and can be used as a sentinel
607 * value indicating ->domain_nr is not set by the driver (and
608 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
609 * pci_bus_find_domain_nr()).
610 */
611 #define PCI_DOMAIN_NR_NOT_SET (-1)
612
613 struct pci_host_bridge {
614 struct device dev;
615 struct pci_bus *bus; /* Root bus */
616 struct pci_ops *ops;
617 struct pci_ops *child_ops;
618 void *sysdata;
619 int busnr;
620 int domain_nr;
621 struct list_head windows; /* resource_entry */
622 struct list_head dma_ranges; /* dma ranges resource list */
623 #ifdef CONFIG_PCI_IDE
624 u16 nr_ide_streams; /* Max streams possibly active in @ide_stream_ida */
625 struct ida ide_stream_ida;
626 struct ida ide_stream_ids_ida; /* track unique ids per domain */
627 #endif
628 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
629 int (*map_irq)(const struct pci_dev *, u8, u8);
630 void (*release_fn)(struct pci_host_bridge *);
631 int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev);
632 void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev);
633 void *release_data;
634 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
635 unsigned int no_ext_tags:1; /* No Extended Tags */
636 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
637 unsigned int native_aer:1; /* OS may use PCIe AER */
638 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
639 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
640 unsigned int native_pme:1; /* OS may use PCIe PME */
641 unsigned int native_ltr:1; /* OS may use PCIe LTR */
642 unsigned int native_dpc:1; /* OS may use PCIe DPC */
643 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
644 unsigned int preserve_config:1; /* Preserve FW resource setup */
645 unsigned int size_windows:1; /* Enable root bus sizing */
646 unsigned int msi_domain:1; /* Bridge wants MSI domain */
647
648 /* Resource alignment requirements */
649 resource_size_t (*align_resource)(struct pci_dev *dev,
650 const struct resource *res,
651 resource_size_t start,
652 resource_size_t size,
653 resource_size_t align);
654 unsigned long private[] ____cacheline_aligned;
655 };
656
657 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
658
pci_host_bridge_priv(struct pci_host_bridge * bridge)659 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
660 {
661 return (void *)bridge->private;
662 }
663
pci_host_bridge_from_priv(void * priv)664 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
665 {
666 return container_of(priv, struct pci_host_bridge, private);
667 }
668
669 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
670 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
671 size_t priv);
672 void pci_free_host_bridge(struct pci_host_bridge *bridge);
673 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
674 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
675
676 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
677 void (*release_fn)(struct pci_host_bridge *),
678 void *release_data);
679
680 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
681
682 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
683
684 struct pci_bus {
685 struct list_head node; /* Node in list of buses */
686 struct pci_bus *parent; /* Parent bus this bridge is on */
687 struct list_head children; /* List of child buses */
688 struct list_head devices; /* List of devices on this bus */
689 struct pci_dev *self; /* Bridge device as seen by parent */
690 struct list_head slots; /* List of slots on this bus;
691 protected by pci_slot_mutex */
692 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
693 struct list_head resources; /* Address space routed to this bus */
694 struct resource busn_res; /* Bus numbers routed to this bus */
695
696 struct pci_ops *ops; /* Configuration access functions */
697 void *sysdata; /* Hook for sys-specific extension */
698 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
699
700 unsigned char number; /* Bus number */
701 unsigned char primary; /* Number of primary bridge */
702 unsigned char max_bus_speed; /* enum pci_bus_speed */
703 unsigned char cur_bus_speed; /* enum pci_bus_speed */
704 #ifdef CONFIG_PCI_DOMAINS_GENERIC
705 int domain_nr;
706 #endif
707
708 char name[48];
709
710 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
711 pci_bus_flags_t bus_flags; /* Inherited by child buses */
712 struct device *bridge;
713 struct device dev;
714 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
715 struct bin_attribute *legacy_mem; /* Legacy mem */
716 unsigned int is_added:1;
717 unsigned int unsafe_warn:1; /* warned about RW1C config write */
718 unsigned int flit_mode:1; /* Link in Flit mode */
719 };
720
721 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
722
pci_dev_id(struct pci_dev * dev)723 static inline u16 pci_dev_id(struct pci_dev *dev)
724 {
725 return PCI_DEVID(dev->bus->number, dev->devfn);
726 }
727
728 /*
729 * Returns true if the PCI bus is root (behind host-PCI bridge),
730 * false otherwise
731 *
732 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
733 * This is incorrect because "virtual" buses added for SR-IOV (via
734 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
735 */
pci_is_root_bus(struct pci_bus * pbus)736 static inline bool pci_is_root_bus(struct pci_bus *pbus)
737 {
738 return !(pbus->parent);
739 }
740
741 /**
742 * pci_is_bridge - check if the PCI device is a bridge
743 * @dev: PCI device
744 *
745 * Return true if the PCI device is bridge whether it has subordinate
746 * or not.
747 */
pci_is_bridge(struct pci_dev * dev)748 static inline bool pci_is_bridge(struct pci_dev *dev)
749 {
750 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
751 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
752 }
753
754 /**
755 * pci_is_vga - check if the PCI device is a VGA device
756 * @pdev: PCI device
757 *
758 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define
759 * VGA Base Class and Sub-Classes:
760 *
761 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible
762 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code)
763 *
764 * Return true if the PCI device is a VGA device and uses the legacy VGA
765 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and
766 * aliases).
767 */
pci_is_vga(struct pci_dev * pdev)768 static inline bool pci_is_vga(struct pci_dev *pdev)
769 {
770 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
771 return true;
772
773 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA)
774 return true;
775
776 return false;
777 }
778
779 /**
780 * pci_is_display - check if the PCI device is a display controller
781 * @pdev: PCI device
782 *
783 * Determine whether the given PCI device corresponds to a display
784 * controller. Display controllers are typically used for graphical output
785 * and are identified based on their class code.
786 *
787 * Return: true if the PCI device is a display controller, false otherwise.
788 */
pci_is_display(struct pci_dev * pdev)789 static inline bool pci_is_display(struct pci_dev *pdev)
790 {
791 return (pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY;
792 }
793
794 #define for_each_pci_bridge(dev, bus) \
795 list_for_each_entry(dev, &bus->devices, bus_list) \
796 if (!pci_is_bridge(dev)) {} else
797
pci_upstream_bridge(struct pci_dev * dev)798 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
799 {
800 dev = pci_physfn(dev);
801 if (pci_is_root_bus(dev->bus))
802 return NULL;
803
804 return dev->bus->self;
805 }
806
807 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)808 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
809 {
810 return pci_dev->msi_enabled || pci_dev->msix_enabled;
811 }
812 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)813 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
814 #endif
815
816 /* Error values that may be returned by PCI functions */
817 #define PCIBIOS_SUCCESSFUL 0x00
818 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
819 #define PCIBIOS_BAD_VENDOR_ID 0x83
820 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
821 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
822 #define PCIBIOS_SET_FAILED 0x88
823 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
824
825 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)826 static inline int pcibios_err_to_errno(int err)
827 {
828 if (err <= PCIBIOS_SUCCESSFUL)
829 return err; /* Assume already errno */
830
831 switch (err) {
832 case PCIBIOS_FUNC_NOT_SUPPORTED:
833 return -ENOENT;
834 case PCIBIOS_BAD_VENDOR_ID:
835 return -ENOTTY;
836 case PCIBIOS_DEVICE_NOT_FOUND:
837 return -ENODEV;
838 case PCIBIOS_BAD_REGISTER_NUMBER:
839 return -EFAULT;
840 case PCIBIOS_SET_FAILED:
841 return -EIO;
842 case PCIBIOS_BUFFER_TOO_SMALL:
843 return -ENOSPC;
844 }
845
846 return -ERANGE;
847 }
848
849 /* Low-level architecture-dependent routines */
850
851 struct pci_ops {
852 int (*add_bus)(struct pci_bus *bus);
853 void (*remove_bus)(struct pci_bus *bus);
854 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
855 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
856 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
857 int (*assert_perst)(struct pci_bus *bus, bool assert);
858 };
859
860 /*
861 * ACPI needs to be able to access PCI config space before we've done a
862 * PCI bus scan and created pci_bus structures.
863 */
864 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
865 int reg, int len, u32 *val);
866 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
867 int reg, int len, u32 val);
868
869 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
870 typedef u64 pci_bus_addr_t;
871 #else
872 typedef u32 pci_bus_addr_t;
873 #endif
874
875 struct pci_bus_region {
876 pci_bus_addr_t start;
877 pci_bus_addr_t end;
878 };
879
pci_bus_region_size(const struct pci_bus_region * region)880 static inline pci_bus_addr_t pci_bus_region_size(const struct pci_bus_region *region)
881 {
882 return region->end - region->start + 1;
883 }
884
885 struct pci_dynids {
886 spinlock_t lock; /* Protects list, index */
887 struct list_head list; /* For IDs added at runtime */
888 };
889
890
891 /*
892 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
893 * a set of callbacks in struct pci_error_handlers, that device driver
894 * will be notified of PCI bus errors, and will be driven to recovery
895 * when an error occurs.
896 */
897
898 typedef unsigned int __bitwise pci_ers_result_t;
899
900 enum pci_ers_result {
901 /* No result/none/not supported in device driver */
902 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
903
904 /* Device driver can recover without slot reset */
905 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
906
907 /* Device driver wants slot to be reset */
908 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
909
910 /* Device has completely failed, is unrecoverable */
911 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
912
913 /* Device driver is fully recovered and operational */
914 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
915
916 /* No AER capabilities registered for the driver */
917 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
918 };
919
920 /* PCI bus error event callbacks */
921 struct pci_error_handlers {
922 /* PCI bus error detected on this device */
923 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
924 pci_channel_state_t error);
925
926 /* MMIO has been re-enabled, but not DMA */
927 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
928
929 /* PCI slot has been reset */
930 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
931
932 /* PCI function reset prepare or completed */
933 void (*reset_prepare)(struct pci_dev *dev);
934 void (*reset_done)(struct pci_dev *dev);
935
936 /* Device driver may resume normal operations */
937 void (*resume)(struct pci_dev *dev);
938
939 /* Allow device driver to record more details of a correctable error */
940 void (*cor_error_detected)(struct pci_dev *dev);
941 };
942
943
944 struct module;
945
946 /**
947 * struct pci_driver - PCI driver structure
948 * @name: Driver name.
949 * @id_table: Pointer to table of device IDs the driver is
950 * interested in. Most drivers should export this
951 * table using MODULE_DEVICE_TABLE(pci,...).
952 * @probe: This probing function gets called (during execution
953 * of pci_register_driver() for already existing
954 * devices or later if a new device gets inserted) for
955 * all PCI devices which match the ID table and are not
956 * "owned" by the other drivers yet. This function gets
957 * passed a "struct pci_dev \*" for each device whose
958 * entry in the ID table matches the device. The probe
959 * function returns zero when the driver chooses to
960 * take "ownership" of the device or an error code
961 * (negative number) otherwise.
962 * The probe function always gets called from process
963 * context, so it can sleep.
964 * @remove: The remove() function gets called whenever a device
965 * being handled by this driver is removed (either during
966 * deregistration of the driver or when it's manually
967 * pulled out of a hot-pluggable slot).
968 * The remove function always gets called from process
969 * context, so it can sleep.
970 * @suspend: Put device into low power state.
971 * @resume: Wake device from low power state.
972 * (Please see Documentation/power/pci.rst for descriptions
973 * of PCI Power Management and the related functions.)
974 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
975 * Intended to stop any idling DMA operations.
976 * Useful for enabling wake-on-lan (NIC) or changing
977 * the power state of a device before reboot.
978 * e.g. drivers/net/e100.c.
979 * @sriov_configure: Optional driver callback to allow configuration of
980 * number of VFs to enable via sysfs "sriov_numvfs" file.
981 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
982 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
983 * This will change MSI-X Table Size in the VF Message Control
984 * registers.
985 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
986 * MSI-X vectors available for distribution to the VFs.
987 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
988 * @groups: Sysfs attribute groups.
989 * @dev_groups: Attributes attached to the device that will be
990 * created once it is bound to the driver.
991 * @driver: Driver model structure.
992 * @dynids: List of dynamically added device IDs.
993 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
994 * For most device drivers, no need to care about this flag
995 * as long as all DMAs are handled through the kernel DMA API.
996 * For some special ones, for example VFIO drivers, they know
997 * how to manage the DMA themselves and set this flag so that
998 * the IOMMU layer will allow them to setup and manage their
999 * own I/O address space.
1000 */
1001 struct pci_driver {
1002 const char *name;
1003 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
1004 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
1005 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
1006 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
1007 int (*resume)(struct pci_dev *dev); /* Device woken up */
1008 void (*shutdown)(struct pci_dev *dev);
1009 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
1010 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
1011 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
1012 const struct pci_error_handlers *err_handler;
1013 const struct attribute_group **groups;
1014 const struct attribute_group **dev_groups;
1015 struct device_driver driver;
1016 struct pci_dynids dynids;
1017 bool driver_managed_dma;
1018 };
1019
1020 #define to_pci_driver(__drv) \
1021 ( __drv ? container_of_const(__drv, struct pci_driver, driver) : NULL )
1022
1023 /**
1024 * PCI_DEVICE - macro used to describe a specific PCI device
1025 * @vend: the 16 bit PCI Vendor ID
1026 * @dev: the 16 bit PCI Device ID
1027 *
1028 * This macro is used to create a struct pci_device_id that matches a
1029 * specific device. The subvendor and subdevice fields will be set to
1030 * PCI_ANY_ID.
1031 */
1032 #define PCI_DEVICE(vend,dev) \
1033 .vendor = (vend), .device = (dev), \
1034 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1035
1036 /**
1037 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
1038 * override_only flags.
1039 * @vend: the 16 bit PCI Vendor ID
1040 * @dev: the 16 bit PCI Device ID
1041 * @driver_override: the 32 bit PCI Device override_only
1042 *
1043 * This macro is used to create a struct pci_device_id that matches only a
1044 * driver_override device. The subvendor and subdevice fields will be set to
1045 * PCI_ANY_ID.
1046 */
1047 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
1048 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
1049 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
1050
1051 /**
1052 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
1053 * "driver_override" PCI device.
1054 * @vend: the 16 bit PCI Vendor ID
1055 * @dev: the 16 bit PCI Device ID
1056 *
1057 * This macro is used to create a struct pci_device_id that matches a
1058 * specific device. The subvendor and subdevice fields will be set to
1059 * PCI_ANY_ID and the driver_override will be set to
1060 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
1061 */
1062 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
1063 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
1064
1065 /**
1066 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
1067 * @vend: the 16 bit PCI Vendor ID
1068 * @dev: the 16 bit PCI Device ID
1069 * @subvend: the 16 bit PCI Subvendor ID
1070 * @subdev: the 16 bit PCI Subdevice ID
1071 *
1072 * This macro is used to create a struct pci_device_id that matches a
1073 * specific device with subsystem information.
1074 */
1075 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1076 .vendor = (vend), .device = (dev), \
1077 .subvendor = (subvend), .subdevice = (subdev)
1078
1079 /**
1080 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1081 * @dev_class: the class, subclass, prog-if triple for this device
1082 * @dev_class_mask: the class mask for this device
1083 *
1084 * This macro is used to create a struct pci_device_id that matches a
1085 * specific PCI class. The vendor, device, subvendor, and subdevice
1086 * fields will be set to PCI_ANY_ID.
1087 */
1088 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1089 .class = (dev_class), .class_mask = (dev_class_mask), \
1090 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1091 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1092
1093 /**
1094 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1095 * @vend: the vendor name
1096 * @dev: the 16 bit PCI Device ID
1097 *
1098 * This macro is used to create a struct pci_device_id that matches a
1099 * specific PCI device. The subvendor, and subdevice fields will be set
1100 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1101 * private data.
1102 */
1103 #define PCI_VDEVICE(vend, dev) \
1104 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1106
1107 /**
1108 * PCI_VDEVICE_SUB - describe a specific PCI device/subdevice in a short form
1109 * @vend: the vendor name
1110 * @dev: the 16 bit PCI Device ID
1111 * @subvend: the 16 bit PCI Subvendor ID
1112 * @subdev: the 16 bit PCI Subdevice ID
1113 *
1114 * Generate the pci_device_id struct layout for the specific PCI
1115 * device/subdevice. Private data may follow the output.
1116 */
1117 #define PCI_VDEVICE_SUB(vend, dev, subvend, subdev) \
1118 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1119 .subvendor = (subvend), .subdevice = (subdev), 0, 0
1120
1121 /**
1122 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1123 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1124 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1125 * @data: the driver data to be filled
1126 *
1127 * This macro is used to create a struct pci_device_id that matches a
1128 * specific PCI device. The subvendor, and subdevice fields will be set
1129 * to PCI_ANY_ID.
1130 */
1131 #define PCI_DEVICE_DATA(vend, dev, data) \
1132 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1133 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1134 .driver_data = (kernel_ulong_t)(data)
1135
1136 enum {
1137 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1138 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1139 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1140 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1141 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1142 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1143 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1144 };
1145
1146 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
1147 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1148 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1149 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1150
1151 /* These external functions are only available when PCI support is enabled */
1152 #ifdef CONFIG_PCI
1153
1154 extern unsigned int pci_flags;
1155
pci_set_flags(int flags)1156 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1157 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1158 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1159 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1160
1161 void pcie_bus_configure_settings(struct pci_bus *bus);
1162
1163 enum pcie_bus_config_types {
1164 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1165 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1166 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1167 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1168 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1169 };
1170
1171 extern enum pcie_bus_config_types pcie_bus_config;
1172
1173 extern const struct bus_type pci_bus_type;
1174
1175 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1176 * code, or PCI core code. */
1177 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1178 /* Some device drivers need know if PCI is initiated */
1179 int no_pci_devices(void);
1180
1181 void pcibios_resource_survey_bus(struct pci_bus *bus);
1182 void pcibios_bus_add_device(struct pci_dev *pdev);
1183 void pcibios_add_bus(struct pci_bus *bus);
1184 void pcibios_remove_bus(struct pci_bus *bus);
1185 void pcibios_fixup_bus(struct pci_bus *);
1186 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1187 /* Architecture-specific versions may override this (weak) */
1188 char *pcibios_setup(char *str);
1189
1190 /* Used only when drivers/pci/setup.c is used */
1191 resource_size_t pcibios_align_resource(void *, const struct resource *,
1192 resource_size_t,
1193 resource_size_t);
1194
1195 /* Generic PCI functions used internally */
1196
1197 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1198 struct resource *res);
1199 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1200 struct pci_bus_region *region);
1201 void pcibios_scan_specific_bus(int busn);
1202 struct pci_bus *pci_find_bus(int domain, int busnr);
1203 void pci_bus_add_devices(const struct pci_bus *bus);
1204 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1205 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1206 struct pci_ops *ops, void *sysdata,
1207 struct list_head *resources);
1208 int pci_host_probe(struct pci_host_bridge *bridge);
1209 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1210 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1211 void pci_bus_release_busn_res(struct pci_bus *b);
1212 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1213 struct pci_ops *ops, void *sysdata,
1214 struct list_head *resources);
1215 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1216 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1217 int busnr);
1218 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1219 const char *name,
1220 struct hotplug_slot *hotplug);
1221 void pci_destroy_slot(struct pci_slot *slot);
1222 #ifdef CONFIG_SYSFS
1223 void pci_dev_assign_slot(struct pci_dev *dev);
1224 #else
pci_dev_assign_slot(struct pci_dev * dev)1225 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1226 #endif
1227 int pci_scan_slot(struct pci_bus *bus, int devfn);
1228 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1229 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1230 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1231 void pci_bus_add_device(struct pci_dev *dev);
1232 void pci_read_bridge_bases(struct pci_bus *child);
1233 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1234 struct resource *res);
1235 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1236 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1237 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1238 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1239 void pci_dev_put(struct pci_dev *dev);
1240 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T))
1241 void pci_remove_bus(struct pci_bus *b);
1242 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1243 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1244 void pci_stop_root_bus(struct pci_bus *bus);
1245 void pci_remove_root_bus(struct pci_bus *bus);
1246 void pci_setup_cardbus(struct pci_bus *bus);
1247 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1248 void pci_sort_breadthfirst(void);
1249 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1250 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1251
1252 /* Generic PCI functions exported to card drivers */
1253
1254 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1255 u8 pci_find_capability(struct pci_dev *dev, int cap);
1256 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1257 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1258 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1259 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1260 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1261 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1262 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1263 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1264
1265 u64 pci_get_dsn(struct pci_dev *dev);
1266
1267 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1268 struct pci_dev *from);
1269 struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device,
1270 struct pci_dev *from);
1271 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1272 unsigned int ss_vendor, unsigned int ss_device,
1273 struct pci_dev *from);
1274 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1275 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1276 unsigned int devfn);
1277 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1278 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
1279
1280 int pci_dev_present(const struct pci_device_id *ids);
1281
1282 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1283 int where, u8 *val);
1284 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1285 int where, u16 *val);
1286 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1287 int where, u32 *val);
1288 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1289 int where, u8 val);
1290 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1291 int where, u16 val);
1292 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1293 int where, u32 val);
1294
1295 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1296 int where, int size, u32 *val);
1297 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1298 int where, int size, u32 val);
1299 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1300 int where, int size, u32 *val);
1301 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1302 int where, int size, u32 val);
1303
1304 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1305
1306 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1307 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1308 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1309 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1310 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1311 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1312 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
1313 u32 clear, u32 set);
1314
1315 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1316 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1317 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1318 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1319 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
1320 u16 clear, u16 set);
1321 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
1322 u16 clear, u16 set);
1323 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1324 u32 clear, u32 set);
1325
1326 /**
1327 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
1328 * @dev: PCI device structure of the PCI Express device
1329 * @pos: PCI Express Capability Register
1330 * @clear: Clear bitmask
1331 * @set: Set bitmask
1332 *
1333 * Perform a Read-Modify-Write (RMW) operation using @clear and @set
1334 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
1335 * Capability Registers are accessed concurrently in RMW fashion, hence
1336 * require locking which is handled transparently to the caller.
1337 */
pcie_capability_clear_and_set_word(struct pci_dev * dev,int pos,u16 clear,u16 set)1338 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
1339 int pos,
1340 u16 clear, u16 set)
1341 {
1342 switch (pos) {
1343 case PCI_EXP_LNKCTL:
1344 case PCI_EXP_LNKCTL2:
1345 case PCI_EXP_RTCTL:
1346 return pcie_capability_clear_and_set_word_locked(dev, pos,
1347 clear, set);
1348 default:
1349 return pcie_capability_clear_and_set_word_unlocked(dev, pos,
1350 clear, set);
1351 }
1352 }
1353
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1354 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1355 u16 set)
1356 {
1357 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1358 }
1359
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1360 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1361 u32 set)
1362 {
1363 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1364 }
1365
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1366 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1367 u16 clear)
1368 {
1369 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1370 }
1371
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1372 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1373 u32 clear)
1374 {
1375 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1376 }
1377
1378 /* User-space driven config access */
1379 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1380 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1381 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1382 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1383 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1384 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1385
1386 int __must_check pci_enable_device(struct pci_dev *dev);
1387 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1388 int __must_check pci_reenable_device(struct pci_dev *);
1389 int __must_check pcim_enable_device(struct pci_dev *pdev);
1390 void pcim_pin_device(struct pci_dev *pdev);
1391
pci_intx_mask_supported(struct pci_dev * pdev)1392 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1393 {
1394 /*
1395 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1396 * writable and no quirk has marked the feature broken.
1397 */
1398 return !pdev->broken_intx_masking;
1399 }
1400
pci_is_enabled(struct pci_dev * pdev)1401 static inline int pci_is_enabled(struct pci_dev *pdev)
1402 {
1403 return (atomic_read(&pdev->enable_cnt) > 0);
1404 }
1405
pci_is_managed(struct pci_dev * pdev)1406 static inline int pci_is_managed(struct pci_dev *pdev)
1407 {
1408 return pdev->is_managed;
1409 }
1410
1411 void pci_disable_device(struct pci_dev *dev);
1412
1413 extern unsigned int pcibios_max_latency;
1414 void pci_set_master(struct pci_dev *dev);
1415 void pci_clear_master(struct pci_dev *dev);
1416
1417 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1418 int pci_set_cacheline_size(struct pci_dev *dev);
1419 int __must_check pci_set_mwi(struct pci_dev *dev);
1420 int __must_check pcim_set_mwi(struct pci_dev *dev);
1421 int pci_try_set_mwi(struct pci_dev *dev);
1422 void pci_clear_mwi(struct pci_dev *dev);
1423 void pci_disable_parity(struct pci_dev *dev);
1424 void pci_intx(struct pci_dev *dev, int enable);
1425 bool pci_check_and_mask_intx(struct pci_dev *dev);
1426 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1427 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1428 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1429 int pcix_get_max_mmrbc(struct pci_dev *dev);
1430 int pcix_get_mmrbc(struct pci_dev *dev);
1431 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1432 int pcie_get_readrq(struct pci_dev *dev);
1433 int pcie_set_readrq(struct pci_dev *dev, int rq);
1434 int pcie_get_mps(struct pci_dev *dev);
1435 int pcie_set_mps(struct pci_dev *dev, int mps);
1436 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1437 enum pci_bus_speed *speed,
1438 enum pcie_link_width *width);
1439 int pcie_link_speed_mbps(struct pci_dev *pdev);
1440 void pcie_print_link_status(struct pci_dev *dev);
1441 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1442 int pcie_flr(struct pci_dev *dev);
1443 int __pci_reset_function_locked(struct pci_dev *dev);
1444 int pci_reset_function(struct pci_dev *dev);
1445 int pci_reset_function_locked(struct pci_dev *dev);
1446 int pci_try_reset_function(struct pci_dev *dev);
1447 int pci_probe_reset_slot(struct pci_slot *slot);
1448 int pci_probe_reset_bus(struct pci_bus *bus);
1449 int pci_reset_bus(struct pci_dev *dev);
1450 void pci_reset_secondary_bus(struct pci_dev *dev);
1451 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1452 void pci_update_resource(struct pci_dev *dev, int resno);
1453 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1454 int pci_release_resource(struct pci_dev *dev, int resno);
1455
1456 /* Resizable BAR related routines */
1457 int pci_rebar_bytes_to_size(u64 bytes);
1458 resource_size_t pci_rebar_size_to_bytes(int size);
1459 u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1460 bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size);
1461 int pci_rebar_get_max_size(struct pci_dev *pdev, int bar);
1462 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size,
1463 int exclude_bars);
1464
1465 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1466 bool pci_device_is_present(struct pci_dev *pdev);
1467 void pci_ignore_hotplug(struct pci_dev *dev);
1468 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1469 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1470
1471 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1472 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1473 const char *fmt, ...);
1474 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1475
1476 /* ROM control related routines */
1477 int pci_enable_rom(struct pci_dev *pdev);
1478 void pci_disable_rom(struct pci_dev *pdev);
1479 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1480 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1481
1482 /* Power management related routines */
1483 int pci_save_state(struct pci_dev *dev);
1484 void pci_restore_state(struct pci_dev *dev);
1485 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1486 int pci_load_saved_state(struct pci_dev *dev,
1487 struct pci_saved_state *state);
1488 int pci_load_and_free_saved_state(struct pci_dev *dev,
1489 struct pci_saved_state **state);
1490 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1491 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1492 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state);
1493 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1494 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1495 void pci_pme_active(struct pci_dev *dev, bool enable);
1496 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1497 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1498 int pci_prepare_to_sleep(struct pci_dev *dev);
1499 int pci_back_from_sleep(struct pci_dev *dev);
1500 bool pci_dev_run_wake(struct pci_dev *dev);
1501 void pci_d3cold_enable(struct pci_dev *dev);
1502 void pci_d3cold_disable(struct pci_dev *dev);
1503 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1504 void pci_resume_bus(struct pci_bus *bus);
1505 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1506
1507 /* For use by arch with custom probe code */
1508 void set_pcie_port_type(struct pci_dev *pdev);
1509 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1510
1511 /* Functions for PCI Hotplug drivers to use */
1512 unsigned int pci_rescan_bus(struct pci_bus *bus);
1513 void pci_lock_rescan_remove(void);
1514 void pci_unlock_rescan_remove(void);
1515
1516 /* Vital Product Data routines */
1517 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1518 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1519 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1520 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1521
1522 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1523 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1524 void pci_bus_assign_resources(const struct pci_bus *bus);
1525 void pci_bus_claim_resources(struct pci_bus *bus);
1526 void pci_bus_size_bridges(struct pci_bus *bus);
1527 int pci_claim_resource(struct pci_dev *, int);
1528 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1529 void pci_assign_unassigned_resources(void);
1530 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1531 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1532 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1533 int pci_enable_resources(struct pci_dev *, int mask);
1534 void pci_assign_irq(struct pci_dev *dev);
1535 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1536 #define HAVE_PCI_REQ_REGIONS 2
1537 int __must_check pci_request_regions(struct pci_dev *, const char *);
1538 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1539 void pci_release_regions(struct pci_dev *);
1540 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1541 void pci_release_region(struct pci_dev *, int);
1542 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1543 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1544 void pci_release_selected_regions(struct pci_dev *, int);
1545
1546 static inline __must_check struct resource *
pci_request_config_region_exclusive(struct pci_dev * pdev,unsigned int offset,unsigned int len,const char * name)1547 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1548 unsigned int len, const char *name)
1549 {
1550 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1551 name, IORESOURCE_EXCLUSIVE);
1552 }
1553
pci_release_config_region(struct pci_dev * pdev,unsigned int offset,unsigned int len)1554 static inline void pci_release_config_region(struct pci_dev *pdev,
1555 unsigned int offset,
1556 unsigned int len)
1557 {
1558 __release_region(&pdev->driver_exclusive_resource, offset, len);
1559 }
1560
1561 /* drivers/pci/bus.c */
1562 void pci_add_resource(struct list_head *resources, struct resource *res);
1563 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1564 resource_size_t offset);
1565 void pci_free_resource_list(struct list_head *resources);
1566 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res);
1567 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1568 void pci_bus_remove_resources(struct pci_bus *bus);
1569 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1570 int devm_request_pci_bus_resources(struct device *dev,
1571 struct list_head *resources);
1572
1573 /* Temporary until new and working PCI SBR API in place */
1574 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1575
1576 #define __pci_bus_for_each_res0(bus, res, ...) \
1577 for (unsigned int __b = 0; \
1578 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1579 __b++)
1580
1581 #define __pci_bus_for_each_res1(bus, res, __b) \
1582 for (__b = 0; \
1583 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1584 __b++)
1585
1586 /**
1587 * pci_bus_for_each_resource - iterate over PCI bus resources
1588 * @bus: the PCI bus
1589 * @res: pointer to the current resource
1590 * @...: optional index of the current resource
1591 *
1592 * Iterate over PCI bus resources. The first part is to go over PCI bus
1593 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries.
1594 * After that continue with the separate list of the additional resources,
1595 * if not empty. That's why the Logical OR is being used.
1596 *
1597 * Possible usage:
1598 *
1599 * struct pci_bus *bus = ...;
1600 * struct resource *res;
1601 * unsigned int i;
1602 *
1603 * // With optional index
1604 * pci_bus_for_each_resource(bus, res, i)
1605 * pr_info("PCI bus resource[%u]: %pR\n", i, res);
1606 *
1607 * // Without index
1608 * pci_bus_for_each_resource(bus, res)
1609 * _do_something_(res);
1610 */
1611 #define pci_bus_for_each_resource(bus, res, ...) \
1612 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
1613 (bus, res, __VA_ARGS__)
1614
1615 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1616 struct resource *res, resource_size_t size,
1617 resource_size_t align, resource_size_t min,
1618 unsigned long type_mask,
1619 resource_alignf alignf,
1620 void *alignf_data);
1621
1622
1623 int pci_register_io_range(const struct fwnode_handle *fwnode, phys_addr_t addr,
1624 resource_size_t size);
1625 unsigned long pci_address_to_pio(phys_addr_t addr);
1626 phys_addr_t pci_pio_to_address(unsigned long pio);
1627 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1628 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1629 phys_addr_t phys_addr);
1630 void pci_unmap_iospace(struct resource *res);
1631 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1632 resource_size_t offset,
1633 resource_size_t size);
1634 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1635 struct resource *res);
1636
pci_bus_address(struct pci_dev * pdev,int bar)1637 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1638 {
1639 struct pci_bus_region region;
1640
1641 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1642 return region.start;
1643 }
1644
1645 /* Proper probing supporting hot-pluggable devices */
1646 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1647 const char *mod_name);
1648
1649 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1650 #define pci_register_driver(driver) \
1651 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1652
1653 void pci_unregister_driver(struct pci_driver *dev);
1654
1655 /**
1656 * module_pci_driver() - Helper macro for registering a PCI driver
1657 * @__pci_driver: pci_driver struct
1658 *
1659 * Helper macro for PCI drivers which do not do anything special in module
1660 * init/exit. This eliminates a lot of boilerplate. Each module may only
1661 * use this macro once, and calling it replaces module_init() and module_exit()
1662 */
1663 #define module_pci_driver(__pci_driver) \
1664 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1665
1666 /**
1667 * builtin_pci_driver() - Helper macro for registering a PCI driver
1668 * @__pci_driver: pci_driver struct
1669 *
1670 * Helper macro for PCI drivers which do not do anything special in their
1671 * init code. This eliminates a lot of boilerplate. Each driver may only
1672 * use this macro once, and calling it replaces device_initcall(...)
1673 */
1674 #define builtin_pci_driver(__pci_driver) \
1675 builtin_driver(__pci_driver, pci_register_driver)
1676
1677 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1678 int pci_add_dynid(struct pci_driver *drv,
1679 unsigned int vendor, unsigned int device,
1680 unsigned int subvendor, unsigned int subdevice,
1681 unsigned int class, unsigned int class_mask,
1682 unsigned long driver_data);
1683 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1684 struct pci_dev *dev);
1685 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1686 int pass);
1687
1688 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1689 void *userdata);
1690 void pci_walk_bus_reverse(struct pci_bus *top,
1691 int (*cb)(struct pci_dev *, void *), void *userdata);
1692 int pci_cfg_space_size(struct pci_dev *dev);
1693 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1694 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1695 unsigned long type);
1696
1697 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1698 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1699
1700 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1701 unsigned int command_bits, u32 flags);
1702
1703 /*
1704 * Virtual interrupts allow for more interrupts to be allocated
1705 * than the device has interrupts for. These are not programmed
1706 * into the device's MSI-X table and must be handled by some
1707 * other driver means.
1708 */
1709 #define PCI_IRQ_VIRTUAL (1 << 4)
1710
1711 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1712
1713 #include <linux/dmapool.h>
1714
1715 struct msix_entry {
1716 u32 vector; /* Kernel uses to write allocated vector */
1717 u16 entry; /* Driver uses to specify entry, OS writes */
1718 };
1719
1720 #ifdef CONFIG_PCI_MSI
1721 int pci_msi_vec_count(struct pci_dev *dev);
1722 void pci_disable_msi(struct pci_dev *dev);
1723 int pci_msix_vec_count(struct pci_dev *dev);
1724 void pci_disable_msix(struct pci_dev *dev);
1725 void pci_restore_msi_state(struct pci_dev *dev);
1726 bool pci_msi_enabled(void);
1727 int pci_enable_msi(struct pci_dev *dev);
1728 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1729 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1730 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1731 struct msix_entry *entries, int nvec)
1732 {
1733 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1734 if (rc < 0)
1735 return rc;
1736 return 0;
1737 }
1738 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1739 unsigned int max_vecs, unsigned int flags);
1740 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1741 unsigned int max_vecs, unsigned int flags,
1742 struct irq_affinity *affd);
1743
1744 bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1745 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1746 const struct irq_affinity_desc *affdesc);
1747 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1748
1749 void pci_free_irq_vectors(struct pci_dev *dev);
1750 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1751 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1752
1753 #else
pci_msi_vec_count(struct pci_dev * dev)1754 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1755 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1756 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1757 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1758 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1759 static inline bool pci_msi_enabled(void) { return false; }
pci_enable_msi(struct pci_dev * dev)1760 static inline int pci_enable_msi(struct pci_dev *dev)
1761 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1762 static inline int pci_enable_msix_range(struct pci_dev *dev,
1763 struct msix_entry *entries, int minvec, int maxvec)
1764 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1765 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1766 struct msix_entry *entries, int nvec)
1767 { return -ENOSYS; }
1768
1769 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1770 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1771 unsigned int max_vecs, unsigned int flags,
1772 struct irq_affinity *aff_desc)
1773 {
1774 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq)
1775 return 1;
1776 return -ENOSPC;
1777 }
1778 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1779 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1780 unsigned int max_vecs, unsigned int flags)
1781 {
1782 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1783 flags, NULL);
1784 }
1785
pci_msix_can_alloc_dyn(struct pci_dev * dev)1786 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)
1787 { return false; }
pci_msix_alloc_irq_at(struct pci_dev * dev,unsigned int index,const struct irq_affinity_desc * affdesc)1788 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1789 const struct irq_affinity_desc *affdesc)
1790 {
1791 struct msi_map map = { .index = -ENOSYS, };
1792
1793 return map;
1794 }
1795
pci_msix_free_irq(struct pci_dev * pdev,struct msi_map map)1796 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1797 {
1798 }
1799
pci_free_irq_vectors(struct pci_dev * dev)1800 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1801 {
1802 }
1803
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1804 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1805 {
1806 if (WARN_ON_ONCE(nr > 0))
1807 return -EINVAL;
1808 return dev->irq;
1809 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1810 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1811 int vec)
1812 {
1813 return cpu_possible_mask;
1814 }
1815 #endif
1816
1817 /**
1818 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1819 * @d: the INTx IRQ domain
1820 * @node: the DT node for the device whose interrupt we're translating
1821 * @intspec: the interrupt specifier data from the DT
1822 * @intsize: the number of entries in @intspec
1823 * @out_hwirq: pointer at which to write the hwirq number
1824 * @out_type: pointer at which to write the interrupt type
1825 *
1826 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1827 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1828 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1829 * INTx value to obtain the hwirq number.
1830 *
1831 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1832 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1833 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1834 struct device_node *node,
1835 const u32 *intspec,
1836 unsigned int intsize,
1837 unsigned long *out_hwirq,
1838 unsigned int *out_type)
1839 {
1840 const u32 intx = intspec[0];
1841
1842 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1843 return -EINVAL;
1844
1845 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1846 return 0;
1847 }
1848
1849 #ifdef CONFIG_PCIEPORTBUS
1850 extern bool pcie_ports_disabled;
1851 extern bool pcie_ports_native;
1852
1853 int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req,
1854 bool use_lt);
1855 #else
1856 #define pcie_ports_disabled true
1857 #define pcie_ports_native false
1858
pcie_set_target_speed(struct pci_dev * port,enum pci_bus_speed speed_req,bool use_lt)1859 static inline int pcie_set_target_speed(struct pci_dev *port,
1860 enum pci_bus_speed speed_req,
1861 bool use_lt)
1862 {
1863 return -EOPNOTSUPP;
1864 }
1865 #endif
1866
1867 #define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */
1868 #define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */
1869 #define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */
1870 #define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */
1871 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */
1872 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */
1873 #define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\
1874 PCIE_LINK_STATE_L1 |\
1875 PCIE_LINK_STATE_L1_1 |\
1876 PCIE_LINK_STATE_L1_2 |\
1877 PCIE_LINK_STATE_L1_1_PCIPM |\
1878 PCIE_LINK_STATE_L1_2_PCIPM)
1879 #define PCIE_LINK_STATE_CLKPM BIT(7)
1880 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\
1881 PCIE_LINK_STATE_CLKPM)
1882
1883 #ifdef CONFIG_PCIEASPM
1884 int pci_disable_link_state(struct pci_dev *pdev, int state);
1885 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1886 int pci_enable_link_state(struct pci_dev *pdev, int state);
1887 int pci_enable_link_state_locked(struct pci_dev *pdev, int state);
1888 void pcie_no_aspm(void);
1889 bool pcie_aspm_support_enabled(void);
1890 bool pcie_aspm_enabled(struct pci_dev *pdev);
1891 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1892 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1893 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1894 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1895 { return 0; }
pci_enable_link_state(struct pci_dev * pdev,int state)1896 static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1897 { return 0; }
pci_enable_link_state_locked(struct pci_dev * pdev,int state)1898 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
1899 { return 0; }
pcie_no_aspm(void)1900 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1901 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1902 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1903 #endif
1904
1905 #ifdef CONFIG_HOTPLUG_PCI
1906 void pci_hp_ignore_link_change(struct pci_dev *pdev);
1907 void pci_hp_unignore_link_change(struct pci_dev *pdev);
1908 #else
pci_hp_ignore_link_change(struct pci_dev * pdev)1909 static inline void pci_hp_ignore_link_change(struct pci_dev *pdev) { }
pci_hp_unignore_link_change(struct pci_dev * pdev)1910 static inline void pci_hp_unignore_link_change(struct pci_dev *pdev) { }
1911 #endif
1912
1913 #ifdef CONFIG_PCIEAER
1914 bool pci_aer_available(void);
1915 #else
pci_aer_available(void)1916 static inline bool pci_aer_available(void) { return false; }
1917 #endif
1918
1919 bool pci_ats_disabled(void);
1920
1921 #define PCIE_PTM_CONTEXT_UPDATE_AUTO 0
1922 #define PCIE_PTM_CONTEXT_UPDATE_MANUAL 1
1923
1924 struct pcie_ptm_ops {
1925 int (*check_capability)(void *drvdata);
1926 int (*context_update_write)(void *drvdata, u8 mode);
1927 int (*context_update_read)(void *drvdata, u8 *mode);
1928 int (*context_valid_write)(void *drvdata, bool valid);
1929 int (*context_valid_read)(void *drvdata, bool *valid);
1930 int (*local_clock_read)(void *drvdata, u64 *clock);
1931 int (*master_clock_read)(void *drvdata, u64 *clock);
1932 int (*t1_read)(void *drvdata, u64 *clock);
1933 int (*t2_read)(void *drvdata, u64 *clock);
1934 int (*t3_read)(void *drvdata, u64 *clock);
1935 int (*t4_read)(void *drvdata, u64 *clock);
1936
1937 bool (*context_update_visible)(void *drvdata);
1938 bool (*context_valid_visible)(void *drvdata);
1939 bool (*local_clock_visible)(void *drvdata);
1940 bool (*master_clock_visible)(void *drvdata);
1941 bool (*t1_visible)(void *drvdata);
1942 bool (*t2_visible)(void *drvdata);
1943 bool (*t3_visible)(void *drvdata);
1944 bool (*t4_visible)(void *drvdata);
1945 };
1946
1947 struct pci_ptm_debugfs {
1948 struct dentry *debugfs;
1949 const struct pcie_ptm_ops *ops;
1950 struct mutex lock;
1951 void *pdata;
1952 };
1953
1954 #ifdef CONFIG_PCIE_PTM
1955 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1956 void pci_disable_ptm(struct pci_dev *dev);
1957 bool pcie_ptm_enabled(struct pci_dev *dev);
1958 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1959 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1960 { return -EINVAL; }
pci_disable_ptm(struct pci_dev * dev)1961 static inline void pci_disable_ptm(struct pci_dev *dev) { }
pcie_ptm_enabled(struct pci_dev * dev)1962 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1963 { return false; }
1964 #endif
1965
1966 #if IS_ENABLED(CONFIG_DEBUG_FS) && IS_ENABLED(CONFIG_PCIE_PTM)
1967 struct pci_ptm_debugfs *pcie_ptm_create_debugfs(struct device *dev, void *pdata,
1968 const struct pcie_ptm_ops *ops);
1969 void pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs);
1970 #else
1971 static inline struct pci_ptm_debugfs
pcie_ptm_create_debugfs(struct device * dev,void * pdata,const struct pcie_ptm_ops * ops)1972 *pcie_ptm_create_debugfs(struct device *dev, void *pdata,
1973 const struct pcie_ptm_ops *ops) { return NULL; }
1974 static inline void
pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs * ptm_debugfs)1975 pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs) { }
1976 #endif
1977
1978 void pci_cfg_access_lock(struct pci_dev *dev);
1979 bool pci_cfg_access_trylock(struct pci_dev *dev);
1980 void pci_cfg_access_unlock(struct pci_dev *dev);
1981
1982 void pci_dev_lock(struct pci_dev *dev);
1983 int pci_dev_trylock(struct pci_dev *dev);
1984 void pci_dev_unlock(struct pci_dev *dev);
1985 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T))
1986
1987 /*
1988 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1989 * a PCI domain is defined to be a set of PCI buses which share
1990 * configuration space.
1991 */
1992 #ifdef CONFIG_PCI_DOMAINS
1993 extern int pci_domains_supported;
1994 int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max);
1995 void pci_bus_release_emul_domain_nr(int domain_nr);
1996 #else
1997 enum { pci_domains_supported = 0 };
1998 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1999 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
2000 static inline int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max)
2001 {
2002 return 0;
2003 }
2004 static inline void pci_bus_release_emul_domain_nr(int domain_nr) { }
2005 #endif /* CONFIG_PCI_DOMAINS */
2006
2007 /*
2008 * Generic implementation for PCI domain support. If your
2009 * architecture does not need custom management of PCI
2010 * domains then this implementation will be used
2011 */
2012 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)2013 static inline int pci_domain_nr(struct pci_bus *bus)
2014 {
2015 return bus->domain_nr;
2016 }
2017 #ifdef CONFIG_ACPI
2018 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
2019 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)2020 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
2021 { return 0; }
2022 #endif
2023 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
2024 void pci_bus_release_domain_nr(struct device *parent, int domain_nr);
2025 #endif
2026
2027 /* Some architectures require additional setup to direct VGA traffic */
2028 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
2029 unsigned int command_bits, u32 flags);
2030 void pci_register_set_vga_state(arch_set_vga_state_t func);
2031
2032 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)2033 pci_request_io_regions(struct pci_dev *pdev, const char *name)
2034 {
2035 return pci_request_selected_regions(pdev,
2036 pci_select_bars(pdev, IORESOURCE_IO), name);
2037 }
2038
2039 static inline void
pci_release_io_regions(struct pci_dev * pdev)2040 pci_release_io_regions(struct pci_dev *pdev)
2041 {
2042 return pci_release_selected_regions(pdev,
2043 pci_select_bars(pdev, IORESOURCE_IO));
2044 }
2045
2046 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)2047 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
2048 {
2049 return pci_request_selected_regions(pdev,
2050 pci_select_bars(pdev, IORESOURCE_MEM), name);
2051 }
2052
2053 static inline void
pci_release_mem_regions(struct pci_dev * pdev)2054 pci_release_mem_regions(struct pci_dev *pdev)
2055 {
2056 return pci_release_selected_regions(pdev,
2057 pci_select_bars(pdev, IORESOURCE_MEM));
2058 }
2059
2060 #else /* CONFIG_PCI is not enabled */
2061
pci_set_flags(int flags)2062 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)2063 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)2064 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)2065 static inline int pci_has_flag(int flag) { return 0; }
2066
2067 /*
2068 * If the system does not have PCI, clearly these return errors. Define
2069 * these as simple inline functions to avoid hair in drivers.
2070 */
2071 #define _PCI_NOP(o, s, t) \
2072 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
2073 int where, t val) \
2074 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
2075
2076 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
2077 _PCI_NOP(o, word, u16 x) \
2078 _PCI_NOP(o, dword, u32 x)
2079 _PCI_NOP_ALL(read, *)
2080 _PCI_NOP_ALL(write,)
2081
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)2082 static inline struct pci_dev *pci_get_device(unsigned int vendor,
2083 unsigned int device,
2084 struct pci_dev *from)
2085 { return NULL; }
2086
pci_get_device_reverse(unsigned int vendor,unsigned int device,struct pci_dev * from)2087 static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor,
2088 unsigned int device,
2089 struct pci_dev *from)
2090 { return NULL; }
2091
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)2092 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
2093 unsigned int device,
2094 unsigned int ss_vendor,
2095 unsigned int ss_device,
2096 struct pci_dev *from)
2097 { return NULL; }
2098
pci_get_class(unsigned int class,struct pci_dev * from)2099 static inline struct pci_dev *pci_get_class(unsigned int class,
2100 struct pci_dev *from)
2101 { return NULL; }
2102
pci_get_base_class(unsigned int class,struct pci_dev * from)2103 static inline struct pci_dev *pci_get_base_class(unsigned int class,
2104 struct pci_dev *from)
2105 { return NULL; }
2106
pci_dev_present(const struct pci_device_id * ids)2107 static inline int pci_dev_present(const struct pci_device_id *ids)
2108 { return 0; }
2109
2110 #define no_pci_devices() (1)
2111 #define pci_dev_put(dev) do { } while (0)
2112
pci_set_master(struct pci_dev * dev)2113 static inline void pci_set_master(struct pci_dev *dev) { }
pci_clear_master(struct pci_dev * dev)2114 static inline void pci_clear_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)2115 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)2116 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)2117 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)2118 static inline int pci_assign_resource(struct pci_dev *dev, int i)
2119 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)2120 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
2121 struct module *owner,
2122 const char *mod_name)
2123 { return 0; }
pci_register_driver(struct pci_driver * drv)2124 static inline int pci_register_driver(struct pci_driver *drv)
2125 { return 0; }
pci_unregister_driver(struct pci_driver * drv)2126 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)2127 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
2128 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)2129 static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap)
2130 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)2131 static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
2132 { return 0; }
2133
pci_get_dsn(struct pci_dev * dev)2134 static inline u64 pci_get_dsn(struct pci_dev *dev)
2135 { return 0; }
2136
2137 /* Power management related routines */
pci_save_state(struct pci_dev * dev)2138 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)2139 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)2140 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2141 { return 0; }
pci_set_power_state_locked(struct pci_dev * dev,pci_power_t state)2142 static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state)
2143 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)2144 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2145 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)2146 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
2147 pm_message_t state)
2148 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)2149 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
2150 int enable)
2151 { return 0; }
2152
pci_find_resource(struct pci_dev * dev,struct resource * res)2153 static inline struct resource *pci_find_resource(struct pci_dev *dev,
2154 struct resource *res)
2155 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)2156 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2157 { return -EIO; }
pci_release_regions(struct pci_dev * dev)2158 static inline void pci_release_regions(struct pci_dev *dev) { }
2159
pci_register_io_range(const struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)2160 static inline int pci_register_io_range(const struct fwnode_handle *fwnode,
2161 phys_addr_t addr, resource_size_t size)
2162 { return -EINVAL; }
2163
pci_address_to_pio(phys_addr_t addr)2164 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
2165
pci_find_next_bus(const struct pci_bus * from)2166 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
2167 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)2168 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
2169 unsigned int devfn)
2170 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)2171 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
2172 unsigned int bus, unsigned int devfn)
2173 { return NULL; }
2174
pci_domain_nr(struct pci_bus * bus)2175 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)2176 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
2177
2178 #define dev_is_pci(d) (false)
2179 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)2180 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2181 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)2182 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
2183 struct device_node *node,
2184 const u32 *intspec,
2185 unsigned int intsize,
2186 unsigned long *out_hwirq,
2187 unsigned int *out_type)
2188 { return -EINVAL; }
2189
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)2190 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
2191 struct pci_dev *dev)
2192 { return NULL; }
pci_ats_disabled(void)2193 static inline bool pci_ats_disabled(void) { return true; }
2194
pci_irq_vector(struct pci_dev * dev,unsigned int nr)2195 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
2196 {
2197 return -EINVAL;
2198 }
2199
2200 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)2201 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
2202 unsigned int max_vecs, unsigned int flags,
2203 struct irq_affinity *aff_desc)
2204 {
2205 return -ENOSPC;
2206 }
2207 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)2208 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
2209 unsigned int max_vecs, unsigned int flags)
2210 {
2211 return -ENOSPC;
2212 }
2213 #endif /* CONFIG_PCI */
2214
2215 /* Include architecture-dependent settings and functions */
2216
2217 #include <asm/pci.h>
2218
2219 /*
2220 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
2221 * is expected to be an offset within that region.
2222 *
2223 */
2224 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
2225 struct vm_area_struct *vma,
2226 enum pci_mmap_state mmap_state, int write_combine);
2227
2228 #ifndef arch_can_pci_mmap_wc
2229 #define arch_can_pci_mmap_wc() 0
2230 #endif
2231
2232 #ifndef arch_can_pci_mmap_io
2233 #define arch_can_pci_mmap_io() 0
2234 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
2235 #else
2236 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
2237 #endif
2238
2239 #ifndef pci_root_bus_fwnode
2240 #define pci_root_bus_fwnode(bus) NULL
2241 #endif
2242
2243 /*
2244 * These helpers provide future and backwards compatibility
2245 * for accessing popular PCI BAR info
2246 */
2247 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
2248 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
2249 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
2250 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
2251 #define pci_resource_len(dev,bar) \
2252 (pci_resource_end((dev), (bar)) ? \
2253 resource_size(pci_resource_n((dev), (bar))) : 0)
2254
2255 #define __pci_dev_for_each_res0(dev, res, ...) \
2256 for (unsigned int __b = 0; \
2257 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2258 __b++)
2259
2260 #define __pci_dev_for_each_res1(dev, res, __b) \
2261 for (__b = 0; \
2262 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2263 __b++)
2264
2265 #define pci_dev_for_each_resource(dev, res, ...) \
2266 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
2267 (dev, res, __VA_ARGS__)
2268
2269 /*
2270 * Similar to the helpers above, these manipulate per-pci_dev
2271 * driver-specific data. They are really just a wrapper around
2272 * the generic device structure functions of these calls.
2273 */
pci_get_drvdata(struct pci_dev * pdev)2274 static inline void *pci_get_drvdata(struct pci_dev *pdev)
2275 {
2276 return dev_get_drvdata(&pdev->dev);
2277 }
2278
pci_set_drvdata(struct pci_dev * pdev,void * data)2279 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
2280 {
2281 dev_set_drvdata(&pdev->dev, data);
2282 }
2283
pci_name(const struct pci_dev * pdev)2284 static inline const char *pci_name(const struct pci_dev *pdev)
2285 {
2286 return dev_name(&pdev->dev);
2287 }
2288
2289 void pci_resource_to_user(const struct pci_dev *dev, int bar,
2290 const struct resource *rsrc,
2291 resource_size_t *start, resource_size_t *end);
2292
2293 /*
2294 * The world is not perfect and supplies us with broken PCI devices.
2295 * For at least a part of these bugs we need a work-around, so both
2296 * generic (drivers/pci/quirks.c) and per-architecture code can define
2297 * fixup hooks to be called for particular buggy devices.
2298 */
2299
2300 struct pci_fixup {
2301 u16 vendor; /* Or PCI_ANY_ID */
2302 u16 device; /* Or PCI_ANY_ID */
2303 u32 class; /* Or PCI_ANY_ID */
2304 unsigned int class_shift; /* should be 0, 8, 16 */
2305 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2306 int hook_offset;
2307 #else
2308 void (*hook)(struct pci_dev *dev);
2309 #endif
2310 };
2311
2312 enum pci_fixup_pass {
2313 pci_fixup_early, /* Before probing BARs */
2314 pci_fixup_header, /* After reading configuration header */
2315 pci_fixup_final, /* Final phase of device fixups */
2316 pci_fixup_enable, /* pci_enable_device() time */
2317 pci_fixup_resume, /* pci_device_resume() */
2318 pci_fixup_suspend, /* pci_device_suspend() */
2319 pci_fixup_resume_early, /* pci_device_resume_early() */
2320 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2321 };
2322
2323 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2324 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2325 class_shift, hook) \
2326 __ADDRESSABLE(hook) \
2327 asm(".section " #sec ", \"a\" \n" \
2328 ".balign 16 \n" \
2329 ".short " #vendor ", " #device " \n" \
2330 ".long " #class ", " #class_shift " \n" \
2331 ".long " #hook " - . \n" \
2332 ".previous \n");
2333
2334 /*
2335 * Clang's LTO may rename static functions in C, but has no way to
2336 * handle such renamings when referenced from inline asm. To work
2337 * around this, create global C stubs for these cases.
2338 */
2339 #ifdef CONFIG_LTO_CLANG
2340 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2341 class_shift, hook, stub) \
2342 void stub(struct pci_dev *dev); \
2343 void stub(struct pci_dev *dev) \
2344 { \
2345 hook(dev); \
2346 } \
2347 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2348 class_shift, stub)
2349 #else
2350 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2351 class_shift, hook, stub) \
2352 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2353 class_shift, hook)
2354 #endif
2355
2356 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2357 class_shift, hook) \
2358 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2359 class_shift, hook, __UNIQUE_ID(hook))
2360 #else
2361 /* Anonymous variables would be nice... */
2362 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2363 class_shift, hook) \
2364 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2365 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2366 = { vendor, device, class, class_shift, hook };
2367 #endif
2368
2369 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2370 class_shift, hook) \
2371 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2372 hook, vendor, device, class, class_shift, hook)
2373 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2374 class_shift, hook) \
2375 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2376 hook, vendor, device, class, class_shift, hook)
2377 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2378 class_shift, hook) \
2379 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2380 hook, vendor, device, class, class_shift, hook)
2381 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2382 class_shift, hook) \
2383 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2384 hook, vendor, device, class, class_shift, hook)
2385 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2386 class_shift, hook) \
2387 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2388 resume##hook, vendor, device, class, class_shift, hook)
2389 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2390 class_shift, hook) \
2391 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2392 resume_early##hook, vendor, device, class, class_shift, hook)
2393 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2394 class_shift, hook) \
2395 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2396 suspend##hook, vendor, device, class, class_shift, hook)
2397 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2398 class_shift, hook) \
2399 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2400 suspend_late##hook, vendor, device, class, class_shift, hook)
2401
2402 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2403 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2404 hook, vendor, device, PCI_ANY_ID, 0, hook)
2405 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2406 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2407 hook, vendor, device, PCI_ANY_ID, 0, hook)
2408 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2409 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2410 hook, vendor, device, PCI_ANY_ID, 0, hook)
2411 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2412 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2413 hook, vendor, device, PCI_ANY_ID, 0, hook)
2414 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2415 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2416 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2417 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2418 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2419 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2420 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2421 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2422 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2423 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2424 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2425 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2426
2427 #ifdef CONFIG_PCI_QUIRKS
2428 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2429 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2430 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2431 struct pci_dev *dev) { }
2432 #endif
2433
2434 int pcim_intx(struct pci_dev *pdev, int enabled);
2435 int pcim_request_all_regions(struct pci_dev *pdev, const char *name);
2436 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2437 void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar,
2438 const char *name);
2439 void pcim_iounmap_region(struct pci_dev *pdev, int bar);
2440 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2441 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2442 int pcim_request_region(struct pci_dev *pdev, int bar, const char *name);
2443 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2444 void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar,
2445 unsigned long offset, unsigned long len);
2446
2447 extern int pci_pci_problems;
2448 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2449 #define PCIPCI_TRITON 2
2450 #define PCIPCI_NATOMA 4
2451 #define PCIPCI_VIAETBF 8
2452 #define PCIPCI_VSFX 16
2453 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2454 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2455
2456 extern u8 pci_dfl_cache_line_size;
2457 extern u8 pci_cache_line_size;
2458
2459 /* Architecture-specific versions may override these (weak) */
2460 void pcibios_disable_device(struct pci_dev *dev);
2461 void pcibios_set_master(struct pci_dev *dev);
2462 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2463 enum pcie_reset_state state);
2464 int pcibios_device_add(struct pci_dev *dev);
2465 void pcibios_release_device(struct pci_dev *dev);
2466 #ifdef CONFIG_PCI
2467 void pcibios_penalize_isa_irq(int irq, int active);
2468 #else
pcibios_penalize_isa_irq(int irq,int active)2469 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2470 #endif
2471 int pcibios_alloc_irq(struct pci_dev *dev);
2472 void pcibios_free_irq(struct pci_dev *dev);
2473 resource_size_t pcibios_default_alignment(void);
2474
2475 #if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
2476 extern int pci_create_resource_files(struct pci_dev *dev);
2477 extern void pci_remove_resource_files(struct pci_dev *dev);
2478 #endif
2479
2480 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2481 void __init pci_mmcfg_early_init(void);
2482 void __init pci_mmcfg_late_init(void);
2483 #else
pci_mmcfg_early_init(void)2484 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2485 static inline void pci_mmcfg_late_init(void) { }
2486 #endif
2487
2488 int pci_ext_cfg_avail(void);
2489
2490 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2491 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2492
2493 #ifdef CONFIG_PCI_IOV
2494 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2495 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2496 int pci_iov_vf_id(struct pci_dev *dev);
2497 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2498 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2499 void pci_disable_sriov(struct pci_dev *dev);
2500
2501 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2502 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2503 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2504 int pci_num_vf(struct pci_dev *dev);
2505 int pci_vfs_assigned(struct pci_dev *dev);
2506 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2507 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2508 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2509 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2510 int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size);
2511 u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs);
2512 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2513
2514 /* Arch may override these (weak) */
2515 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2516 int pcibios_sriov_disable(struct pci_dev *pdev);
2517 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2518 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2519 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2520 {
2521 return -ENOSYS;
2522 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2523 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2524 {
2525 return -ENOSYS;
2526 }
2527
pci_iov_vf_id(struct pci_dev * dev)2528 static inline int pci_iov_vf_id(struct pci_dev *dev)
2529 {
2530 return -ENOSYS;
2531 }
2532
pci_iov_get_pf_drvdata(struct pci_dev * dev,struct pci_driver * pf_driver)2533 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2534 struct pci_driver *pf_driver)
2535 {
2536 return ERR_PTR(-EINVAL);
2537 }
2538
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2539 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2540 { return -ENODEV; }
2541
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2542 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2543 struct pci_dev *virtfn, int id)
2544 {
2545 return -ENODEV;
2546 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2547 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2548 {
2549 return -ENOSYS;
2550 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2551 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2552 int id) { }
pci_disable_sriov(struct pci_dev * dev)2553 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2554 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2555 static inline int pci_vfs_assigned(struct pci_dev *dev)
2556 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2557 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2558 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2559 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2560 { return 0; }
2561 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2562 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2563 { return 0; }
pci_iov_vf_bar_set_size(struct pci_dev * dev,int resno,int size)2564 static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size)
2565 { return -ENODEV; }
pci_iov_vf_bar_get_sizes(struct pci_dev * dev,int resno,int num_vfs)2566 static inline u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs)
2567 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2568 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2569 #endif
2570
2571 /**
2572 * pci_pcie_cap - get the saved PCIe capability offset
2573 * @dev: PCI device
2574 *
2575 * PCIe capability offset is calculated at PCI device initialization
2576 * time and saved in the data structure. This function returns saved
2577 * PCIe capability offset. Using this instead of pci_find_capability()
2578 * reduces unnecessary search in the PCI configuration space. If you
2579 * need to calculate PCIe capability offset from raw device for some
2580 * reasons, please use pci_find_capability() instead.
2581 */
pci_pcie_cap(struct pci_dev * dev)2582 static inline int pci_pcie_cap(struct pci_dev *dev)
2583 {
2584 return dev->pcie_cap;
2585 }
2586
2587 /**
2588 * pci_is_pcie - check if the PCI device is PCI Express capable
2589 * @dev: PCI device
2590 *
2591 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2592 */
pci_is_pcie(struct pci_dev * dev)2593 static inline bool pci_is_pcie(struct pci_dev *dev)
2594 {
2595 return pci_pcie_cap(dev);
2596 }
2597
2598 /**
2599 * pcie_caps_reg - get the PCIe Capabilities Register
2600 * @dev: PCI device
2601 */
pcie_caps_reg(const struct pci_dev * dev)2602 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2603 {
2604 return dev->pcie_flags_reg;
2605 }
2606
2607 /**
2608 * pci_pcie_type - get the PCIe device/port type
2609 * @dev: PCI device
2610 */
pci_pcie_type(const struct pci_dev * dev)2611 static inline int pci_pcie_type(const struct pci_dev *dev)
2612 {
2613 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2614 }
2615
2616 /**
2617 * pcie_find_root_port - Get the PCIe root port device
2618 * @dev: PCI device
2619 *
2620 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2621 * for a given PCI/PCIe Device.
2622 */
pcie_find_root_port(struct pci_dev * dev)2623 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2624 {
2625 while (dev) {
2626 if (pci_is_pcie(dev) &&
2627 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2628 return dev;
2629 dev = pci_upstream_bridge(dev);
2630 }
2631
2632 return NULL;
2633 }
2634
pci_dev_is_disconnected(const struct pci_dev * dev)2635 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
2636 {
2637 /*
2638 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg()
2639 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache
2640 * the value (e.g. inside the loop in pci_dev_wait()).
2641 */
2642 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure;
2643 }
2644
2645 void pci_request_acs(void);
2646 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2647 bool pci_acs_path_enabled(struct pci_dev *start,
2648 struct pci_dev *end, u16 acs_flags);
2649 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2650
2651 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2652 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2653
2654 /* Large Resource Data Type Tag Item Names */
2655 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2656 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2657 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2658
2659 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2660 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2661 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2662
2663 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2664 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2665 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2666 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2667 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2668
2669 /**
2670 * pci_vpd_alloc - Allocate buffer and read VPD into it
2671 * @dev: PCI device
2672 * @size: pointer to field where VPD length is returned
2673 *
2674 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2675 */
2676 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2677
2678 /**
2679 * pci_vpd_find_id_string - Locate id string in VPD
2680 * @buf: Pointer to buffered VPD data
2681 * @len: The length of the buffer area in which to search
2682 * @size: Pointer to field where length of id string is returned
2683 *
2684 * Returns the index of the id string or -ENOENT if not found.
2685 */
2686 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2687
2688 /**
2689 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2690 * @buf: Pointer to buffered VPD data
2691 * @len: The length of the buffer area in which to search
2692 * @kw: The keyword to search for
2693 * @size: Pointer to field where length of found keyword data is returned
2694 *
2695 * Returns the index of the information field keyword data or -ENOENT if
2696 * not found.
2697 */
2698 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2699 const char *kw, unsigned int *size);
2700
2701 /**
2702 * pci_vpd_check_csum - Check VPD checksum
2703 * @buf: Pointer to buffered VPD data
2704 * @len: VPD size
2705 *
2706 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2707 */
2708 int pci_vpd_check_csum(const void *buf, unsigned int len);
2709
2710 /* PCI <-> OF binding helpers */
2711 #ifdef CONFIG_OF
2712 struct device_node;
2713 struct irq_domain;
2714 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2715 bool pci_host_of_has_msi_map(struct device *dev);
2716
2717 /* Arch may override this (weak) */
2718 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2719
2720 #else /* CONFIG_OF */
2721 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2722 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2723 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2724 #endif /* CONFIG_OF */
2725
2726 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2727 pci_device_to_OF_node(const struct pci_dev *pdev)
2728 {
2729 return pdev ? pdev->dev.of_node : NULL;
2730 }
2731
pci_bus_to_OF_node(struct pci_bus * bus)2732 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2733 {
2734 return bus ? bus->dev.of_node : NULL;
2735 }
2736
2737 #ifdef CONFIG_ACPI
2738 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2739
2740 void
2741 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2742 bool pci_pr3_present(struct pci_dev *pdev);
2743 #else
2744 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2745 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2746 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2747 #endif
2748
2749 #if defined(CONFIG_X86) && defined(CONFIG_ACPI)
2750 bool arch_pci_dev_is_removable(struct pci_dev *pdev);
2751 #else
arch_pci_dev_is_removable(struct pci_dev * pdev)2752 static inline bool arch_pci_dev_is_removable(struct pci_dev *pdev) { return false; }
2753 #endif
2754
2755 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2756 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2757 {
2758 return pdev->dev.archdata.edev;
2759 }
2760 #endif
2761
2762 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2763 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2764 int pci_for_each_dma_alias(struct pci_dev *pdev,
2765 int (*fn)(struct pci_dev *pdev,
2766 u16 alias, void *data), void *data);
2767
2768 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2769 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2770 {
2771 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2772 }
pci_clear_dev_assigned(struct pci_dev * pdev)2773 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2774 {
2775 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2776 }
pci_is_dev_assigned(struct pci_dev * pdev)2777 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2778 {
2779 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2780 }
2781
2782 /**
2783 * pci_ari_enabled - query ARI forwarding status
2784 * @bus: the PCI bus
2785 *
2786 * Returns true if ARI forwarding is enabled.
2787 */
pci_ari_enabled(struct pci_bus * bus)2788 static inline bool pci_ari_enabled(struct pci_bus *bus)
2789 {
2790 return bus->self && bus->self->ari_enabled;
2791 }
2792
2793 /**
2794 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2795 * @pdev: PCI device to check
2796 *
2797 * Walk upwards from @pdev and check for each encountered bridge if it's part
2798 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2799 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2800 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2801 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2802 {
2803 struct pci_dev *parent = pdev;
2804
2805 if (pdev->is_thunderbolt)
2806 return true;
2807
2808 while ((parent = pci_upstream_bridge(parent)))
2809 if (parent->is_thunderbolt)
2810 return true;
2811
2812 return false;
2813 }
2814
2815 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) || defined(CONFIG_S390)
2816 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2817 #endif
2818
2819 #include <linux/dma-mapping.h>
2820
2821 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2822 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2823 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2824 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2825 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2826 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
2827 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2828 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2829 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2830
2831 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2832 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2833
2834 #define pci_info_ratelimited(pdev, fmt, arg...) \
2835 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2836
2837 #define pci_WARN(pdev, condition, fmt, arg...) \
2838 WARN(condition, "%s %s: " fmt, \
2839 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2840
2841 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2842 WARN_ONCE(condition, "%s %s: " fmt, \
2843 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2844
2845 #endif /* LINUX_PCI_H */
2846