1 /*-
2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include "igc_api.h"
8
9 static s32 igc_wait_autoneg(struct igc_hw *hw);
10
11 /**
12 * igc_init_phy_ops_generic - Initialize PHY function pointers
13 * @hw: pointer to the HW structure
14 *
15 * Setups up the function pointers to no-op functions
16 **/
igc_init_phy_ops_generic(struct igc_hw * hw)17 void igc_init_phy_ops_generic(struct igc_hw *hw)
18 {
19 struct igc_phy_info *phy = &hw->phy;
20 DEBUGFUNC("igc_init_phy_ops_generic");
21
22 /* Initialize function pointers */
23 phy->ops.init_params = igc_null_ops_generic;
24 phy->ops.acquire = igc_null_ops_generic;
25 phy->ops.check_reset_block = igc_null_ops_generic;
26 phy->ops.force_speed_duplex = igc_null_ops_generic;
27 phy->ops.get_info = igc_null_ops_generic;
28 phy->ops.set_page = igc_null_set_page;
29 phy->ops.read_reg = igc_null_read_reg;
30 phy->ops.read_reg_locked = igc_null_read_reg;
31 phy->ops.read_reg_page = igc_null_read_reg;
32 phy->ops.release = igc_null_phy_generic;
33 phy->ops.reset = igc_null_ops_generic;
34 phy->ops.set_d0_lplu_state = igc_null_lplu_state;
35 phy->ops.set_d3_lplu_state = igc_null_lplu_state;
36 phy->ops.write_reg = igc_null_write_reg;
37 phy->ops.write_reg_locked = igc_null_write_reg;
38 phy->ops.write_reg_page = igc_null_write_reg;
39 phy->ops.power_up = igc_null_phy_generic;
40 phy->ops.power_down = igc_null_phy_generic;
41 }
42
43 /**
44 * igc_null_set_page - No-op function, return 0
45 * @hw: pointer to the HW structure
46 * @data: dummy variable
47 **/
igc_null_set_page(struct igc_hw IGC_UNUSEDARG * hw,u16 IGC_UNUSEDARG data)48 s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw,
49 u16 IGC_UNUSEDARG data)
50 {
51 DEBUGFUNC("igc_null_set_page");
52 return IGC_SUCCESS;
53 }
54
55 /**
56 * igc_null_read_reg - No-op function, return 0
57 * @hw: pointer to the HW structure
58 * @offset: dummy variable
59 * @data: dummy variable
60 **/
igc_null_read_reg(struct igc_hw IGC_UNUSEDARG * hw,u32 IGC_UNUSEDARG offset,u16 IGC_UNUSEDARG * data)61 s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw,
62 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG *data)
63 {
64 DEBUGFUNC("igc_null_read_reg");
65 return IGC_SUCCESS;
66 }
67
68 /**
69 * igc_null_phy_generic - No-op function, return void
70 * @hw: pointer to the HW structure
71 **/
igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG * hw)72 void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw)
73 {
74 DEBUGFUNC("igc_null_phy_generic");
75 return;
76 }
77
78 /**
79 * igc_null_lplu_state - No-op function, return 0
80 * @hw: pointer to the HW structure
81 * @active: dummy variable
82 **/
igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG * hw,bool IGC_UNUSEDARG active)83 s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw,
84 bool IGC_UNUSEDARG active)
85 {
86 DEBUGFUNC("igc_null_lplu_state");
87 return IGC_SUCCESS;
88 }
89
90 /**
91 * igc_null_write_reg - No-op function, return 0
92 * @hw: pointer to the HW structure
93 * @offset: dummy variable
94 * @data: dummy variable
95 **/
igc_null_write_reg(struct igc_hw IGC_UNUSEDARG * hw,u32 IGC_UNUSEDARG offset,u16 IGC_UNUSEDARG data)96 s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw,
97 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data)
98 {
99 DEBUGFUNC("igc_null_write_reg");
100 return IGC_SUCCESS;
101 }
102
103 /**
104 * igc_check_reset_block_generic - Check if PHY reset is blocked
105 * @hw: pointer to the HW structure
106 *
107 * Read the PHY management control register and check whether a PHY reset
108 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise
109 * return IGC_BLK_PHY_RESET (12).
110 **/
igc_check_reset_block_generic(struct igc_hw * hw)111 s32 igc_check_reset_block_generic(struct igc_hw *hw)
112 {
113 u32 manc;
114
115 DEBUGFUNC("igc_check_reset_block");
116
117 manc = IGC_READ_REG(hw, IGC_MANC);
118
119 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
120 IGC_BLK_PHY_RESET : IGC_SUCCESS;
121 }
122
123 /**
124 * igc_get_phy_id - Retrieve the PHY ID and revision
125 * @hw: pointer to the HW structure
126 *
127 * Reads the PHY registers and stores the PHY ID and possibly the PHY
128 * revision in the hardware structure.
129 **/
igc_get_phy_id(struct igc_hw * hw)130 s32 igc_get_phy_id(struct igc_hw *hw)
131 {
132 struct igc_phy_info *phy = &hw->phy;
133 s32 ret_val = IGC_SUCCESS;
134 u16 phy_id;
135
136 DEBUGFUNC("igc_get_phy_id");
137
138 if (!phy->ops.read_reg)
139 return IGC_SUCCESS;
140
141 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
142 if (ret_val)
143 return ret_val;
144
145 phy->id = (u32)(phy_id << 16);
146 usec_delay(200);
147 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
148 if (ret_val)
149 return ret_val;
150
151 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
152 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
153
154 return IGC_SUCCESS;
155 }
156
157 /**
158 * igc_read_phy_reg_mdic - Read MDI control register
159 * @hw: pointer to the HW structure
160 * @offset: register offset to be read
161 * @data: pointer to the read data
162 *
163 * Reads the MDI control register in the PHY at offset and stores the
164 * information read to data.
165 **/
igc_read_phy_reg_mdic(struct igc_hw * hw,u32 offset,u16 * data)166 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
167 {
168 struct igc_phy_info *phy = &hw->phy;
169 u32 i, mdic = 0;
170
171 DEBUGFUNC("igc_read_phy_reg_mdic");
172
173 if (offset > MAX_PHY_REG_ADDRESS) {
174 DEBUGOUT1("PHY Address %d is out of range\n", offset);
175 return -IGC_ERR_PARAM;
176 }
177
178 /* Set up Op-code, Phy Address, and register offset in the MDI
179 * Control register. The MAC will take care of interfacing with the
180 * PHY to retrieve the desired data.
181 */
182 mdic = ((offset << IGC_MDIC_REG_SHIFT) |
183 (phy->addr << IGC_MDIC_PHY_SHIFT) |
184 (IGC_MDIC_OP_READ));
185
186 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
187
188 /* Poll the ready bit to see if the MDI read completed
189 * Increasing the time out as testing showed failures with
190 * the lower time out
191 */
192 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
193 usec_delay_irq(50);
194 mdic = IGC_READ_REG(hw, IGC_MDIC);
195 if (mdic & IGC_MDIC_READY)
196 break;
197 }
198 if (!(mdic & IGC_MDIC_READY)) {
199 DEBUGOUT("MDI Read did not complete\n");
200 return -IGC_ERR_PHY;
201 }
202 if (mdic & IGC_MDIC_ERROR) {
203 DEBUGOUT("MDI Error\n");
204 return -IGC_ERR_PHY;
205 }
206 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
207 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
208 offset,
209 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
210 return -IGC_ERR_PHY;
211 }
212 *data = (u16) mdic;
213
214 return IGC_SUCCESS;
215 }
216
217 /**
218 * igc_write_phy_reg_mdic - Write MDI control register
219 * @hw: pointer to the HW structure
220 * @offset: register offset to write to
221 * @data: data to write to register at offset
222 *
223 * Writes data to MDI control register in the PHY at offset.
224 **/
igc_write_phy_reg_mdic(struct igc_hw * hw,u32 offset,u16 data)225 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
226 {
227 struct igc_phy_info *phy = &hw->phy;
228 u32 i, mdic = 0;
229
230 DEBUGFUNC("igc_write_phy_reg_mdic");
231
232 if (offset > MAX_PHY_REG_ADDRESS) {
233 DEBUGOUT1("PHY Address %d is out of range\n", offset);
234 return -IGC_ERR_PARAM;
235 }
236
237 /* Set up Op-code, Phy Address, and register offset in the MDI
238 * Control register. The MAC will take care of interfacing with the
239 * PHY to retrieve the desired data.
240 */
241 mdic = (((u32)data) |
242 (offset << IGC_MDIC_REG_SHIFT) |
243 (phy->addr << IGC_MDIC_PHY_SHIFT) |
244 (IGC_MDIC_OP_WRITE));
245
246 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
247
248 /* Poll the ready bit to see if the MDI read completed
249 * Increasing the time out as testing showed failures with
250 * the lower time out
251 */
252 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
253 usec_delay_irq(50);
254 mdic = IGC_READ_REG(hw, IGC_MDIC);
255 if (mdic & IGC_MDIC_READY)
256 break;
257 }
258 if (!(mdic & IGC_MDIC_READY)) {
259 DEBUGOUT("MDI Write did not complete\n");
260 return -IGC_ERR_PHY;
261 }
262 if (mdic & IGC_MDIC_ERROR) {
263 DEBUGOUT("MDI Error\n");
264 return -IGC_ERR_PHY;
265 }
266 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
267 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
268 offset,
269 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
270 return -IGC_ERR_PHY;
271 }
272
273 return IGC_SUCCESS;
274 }
275
276 /**
277 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
278 * @hw: pointer to the HW structure
279 *
280 * Reads the MII auto-neg advertisement register and/or the 1000T control
281 * register and if the PHY is already setup for auto-negotiation, then
282 * return successful. Otherwise, setup advertisement and flow control to
283 * the appropriate values for the wanted auto-negotiation.
284 **/
igc_phy_setup_autoneg(struct igc_hw * hw)285 static s32 igc_phy_setup_autoneg(struct igc_hw *hw)
286 {
287 struct igc_phy_info *phy = &hw->phy;
288 s32 ret_val;
289 u16 mii_autoneg_adv_reg;
290 u16 mii_1000t_ctrl_reg = 0;
291 u16 aneg_multigbt_an_ctrl = 0;
292
293 DEBUGFUNC("igc_phy_setup_autoneg");
294
295 phy->autoneg_advertised &= phy->autoneg_mask;
296
297 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
298 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
299 if (ret_val)
300 return ret_val;
301
302 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
303 /* Read the MII 1000Base-T Control Register (Address 9). */
304 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
305 &mii_1000t_ctrl_reg);
306 if (ret_val)
307 return ret_val;
308 }
309
310 if (phy->autoneg_mask & ADVERTISE_2500_FULL) {
311 /* Read the MULTI GBT AN Control Register - reg 7.32 */
312 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
313 MMD_DEVADDR_SHIFT) |
314 ANEG_MULTIGBT_AN_CTRL,
315 &aneg_multigbt_an_ctrl);
316
317 if (ret_val)
318 return ret_val;
319 }
320
321 /* Need to parse both autoneg_advertised and fc and set up
322 * the appropriate PHY registers. First we will parse for
323 * autoneg_advertised software override. Since we can advertise
324 * a plethora of combinations, we need to check each bit
325 * individually.
326 */
327
328 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
329 * Advertisement Register (Address 4) and the 1000 mb speed bits in
330 * the 1000Base-T Control Register (Address 9).
331 */
332 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
333 NWAY_AR_100TX_HD_CAPS |
334 NWAY_AR_10T_FD_CAPS |
335 NWAY_AR_10T_HD_CAPS);
336 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
337
338 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
339
340 /* Do we want to advertise 10 Mb Half Duplex? */
341 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
342 DEBUGOUT("Advertise 10mb Half duplex\n");
343 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
344 }
345
346 /* Do we want to advertise 10 Mb Full Duplex? */
347 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
348 DEBUGOUT("Advertise 10mb Full duplex\n");
349 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
350 }
351
352 /* Do we want to advertise 100 Mb Half Duplex? */
353 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
354 DEBUGOUT("Advertise 100mb Half duplex\n");
355 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
356 }
357
358 /* Do we want to advertise 100 Mb Full Duplex? */
359 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
360 DEBUGOUT("Advertise 100mb Full duplex\n");
361 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
362 }
363
364 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
365 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
366 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
367
368 /* Do we want to advertise 1000 Mb Full Duplex? */
369 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
370 DEBUGOUT("Advertise 1000mb Full duplex\n");
371 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
372 }
373
374 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */
375 if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
376 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n");
377
378 /* Do we want to advertise 2500 Mb Full Duplex? */
379 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
380 DEBUGOUT("Advertise 2500mb Full duplex\n");
381 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;
382 } else {
383 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;
384 }
385
386 /* Check for a software override of the flow control settings, and
387 * setup the PHY advertisement registers accordingly. If
388 * auto-negotiation is enabled, then software will have to set the
389 * "PAUSE" bits to the correct value in the Auto-Negotiation
390 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
391 * negotiation.
392 *
393 * The possible values of the "fc" parameter are:
394 * 0: Flow control is completely disabled
395 * 1: Rx flow control is enabled (we can receive pause frames
396 * but not send pause frames).
397 * 2: Tx flow control is enabled (we can send pause frames
398 * but we do not support receiving pause frames).
399 * 3: Both Rx and Tx flow control (symmetric) are enabled.
400 * other: No software override. The flow control configuration
401 * in the EEPROM is used.
402 */
403 switch (hw->fc.current_mode) {
404 case igc_fc_none:
405 /* Flow control (Rx & Tx) is completely disabled by a
406 * software over-ride.
407 */
408 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
409 break;
410 case igc_fc_rx_pause:
411 /* Rx Flow control is enabled, and Tx Flow control is
412 * disabled, by a software over-ride.
413 *
414 * Since there really isn't a way to advertise that we are
415 * capable of Rx Pause ONLY, we will advertise that we
416 * support both symmetric and asymmetric Rx PAUSE. Later
417 * (in igc_config_fc_after_link_up) we will disable the
418 * hw's ability to send PAUSE frames.
419 */
420 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
421 break;
422 case igc_fc_tx_pause:
423 /* Tx Flow control is enabled, and Rx Flow control is
424 * disabled, by a software over-ride.
425 */
426 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
427 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
428 break;
429 case igc_fc_full:
430 /* Flow control (both Rx and Tx) is enabled by a software
431 * over-ride.
432 */
433 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
434 break;
435 default:
436 DEBUGOUT("Flow control param set incorrectly\n");
437 return -IGC_ERR_CONFIG;
438 }
439
440 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
441 if (ret_val)
442 return ret_val;
443
444 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
445
446 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
447 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
448 mii_1000t_ctrl_reg);
449
450 if (phy->autoneg_mask & ADVERTISE_2500_FULL)
451 ret_val = phy->ops.write_reg(hw,
452 (STANDARD_AN_REG_MASK <<
453 MMD_DEVADDR_SHIFT) |
454 ANEG_MULTIGBT_AN_CTRL,
455 aneg_multigbt_an_ctrl);
456
457 return ret_val;
458 }
459
460 /**
461 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link
462 * @hw: pointer to the HW structure
463 *
464 * Performs initial bounds checking on autoneg advertisement parameter, then
465 * configure to advertise the full capability. Setup the PHY to autoneg
466 * and restart the negotiation process between the link partner. If
467 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
468 **/
igc_copper_link_autoneg(struct igc_hw * hw)469 static s32 igc_copper_link_autoneg(struct igc_hw *hw)
470 {
471 struct igc_phy_info *phy = &hw->phy;
472 s32 ret_val;
473 u16 phy_ctrl;
474
475 DEBUGFUNC("igc_copper_link_autoneg");
476
477 /* Perform some bounds checking on the autoneg advertisement
478 * parameter.
479 */
480 phy->autoneg_advertised &= phy->autoneg_mask;
481
482 /* If autoneg_advertised is zero, we assume it was not defaulted
483 * by the calling code so we set to advertise full capability.
484 */
485 if (!phy->autoneg_advertised)
486 phy->autoneg_advertised = phy->autoneg_mask;
487
488 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
489 ret_val = igc_phy_setup_autoneg(hw);
490 if (ret_val) {
491 DEBUGOUT("Error Setting up Auto-Negotiation\n");
492 return ret_val;
493 }
494 DEBUGOUT("Restarting Auto-Neg\n");
495
496 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
497 * the Auto Neg Restart bit in the PHY control register.
498 */
499 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
500 if (ret_val)
501 return ret_val;
502
503 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
504 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
505 if (ret_val)
506 return ret_val;
507
508 /* Does the user want to wait for Auto-Neg to complete here, or
509 * check at a later time (for example, callback routine).
510 */
511 if (phy->autoneg_wait_to_complete) {
512 ret_val = igc_wait_autoneg(hw);
513 if (ret_val) {
514 DEBUGOUT("Error while waiting for autoneg to complete\n");
515 return ret_val;
516 }
517 }
518
519 hw->mac.get_link_status = true;
520
521 return ret_val;
522 }
523
524 /**
525 * igc_setup_copper_link_generic - Configure copper link settings
526 * @hw: pointer to the HW structure
527 *
528 * Calls the appropriate function to configure the link for auto-neg or forced
529 * speed and duplex. Then we check for link, once link is established calls
530 * to configure collision distance and flow control are called. If link is
531 * not established, we return -IGC_ERR_PHY (-2).
532 **/
igc_setup_copper_link_generic(struct igc_hw * hw)533 s32 igc_setup_copper_link_generic(struct igc_hw *hw)
534 {
535 s32 ret_val;
536 bool link;
537
538 DEBUGFUNC("igc_setup_copper_link_generic");
539
540 if (hw->mac.autoneg) {
541 /* Setup autoneg and flow control advertisement and perform
542 * autonegotiation.
543 */
544 ret_val = igc_copper_link_autoneg(hw);
545 if (ret_val)
546 return ret_val;
547 } else {
548 /* PHY will be set to 10H, 10F, 100H or 100F
549 * depending on user settings.
550 */
551 DEBUGOUT("Forcing Speed and Duplex\n");
552 ret_val = hw->phy.ops.force_speed_duplex(hw);
553 if (ret_val) {
554 DEBUGOUT("Error Forcing Speed and Duplex\n");
555 return ret_val;
556 }
557 }
558
559 /* Check link status. Wait up to 100 microseconds for link to become
560 * valid.
561 */
562 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
563 &link);
564 if (ret_val)
565 return ret_val;
566
567 if (link) {
568 DEBUGOUT("Valid link established!!!\n");
569 hw->mac.ops.config_collision_dist(hw);
570 ret_val = igc_config_fc_after_link_up_generic(hw);
571 } else {
572 DEBUGOUT("Unable to establish link!!!\n");
573 }
574
575 return ret_val;
576 }
577
578 /**
579 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
580 * @hw: pointer to the HW structure
581 * @phy_ctrl: pointer to current value of PHY_CONTROL
582 *
583 * Forces speed and duplex on the PHY by doing the following: disable flow
584 * control, force speed/duplex on the MAC, disable auto speed detection,
585 * disable auto-negotiation, configure duplex, configure speed, configure
586 * the collision distance, write configuration to CTRL register. The
587 * caller must write to the PHY_CONTROL register for these settings to
588 * take effect.
589 **/
igc_phy_force_speed_duplex_setup(struct igc_hw * hw,u16 * phy_ctrl)590 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl)
591 {
592 struct igc_mac_info *mac = &hw->mac;
593 u32 ctrl;
594
595 DEBUGFUNC("igc_phy_force_speed_duplex_setup");
596
597 /* Turn off flow control when forcing speed/duplex */
598 hw->fc.current_mode = igc_fc_none;
599
600 /* Force speed/duplex on the mac */
601 ctrl = IGC_READ_REG(hw, IGC_CTRL);
602 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
603 ctrl &= ~IGC_CTRL_SPD_SEL;
604
605 /* Disable Auto Speed Detection */
606 ctrl &= ~IGC_CTRL_ASDE;
607
608 /* Disable autoneg on the phy */
609 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
610
611 /* Forcing Full or Half Duplex? */
612 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) {
613 ctrl &= ~IGC_CTRL_FD;
614 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
615 DEBUGOUT("Half Duplex\n");
616 } else {
617 ctrl |= IGC_CTRL_FD;
618 *phy_ctrl |= MII_CR_FULL_DUPLEX;
619 DEBUGOUT("Full Duplex\n");
620 }
621
622 /* Forcing 10mb or 100mb? */
623 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) {
624 ctrl |= IGC_CTRL_SPD_100;
625 *phy_ctrl |= MII_CR_SPEED_100;
626 *phy_ctrl &= ~MII_CR_SPEED_1000;
627 DEBUGOUT("Forcing 100mb\n");
628 } else {
629 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);
630 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
631 DEBUGOUT("Forcing 10mb\n");
632 }
633
634 hw->mac.ops.config_collision_dist(hw);
635
636 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
637 }
638
639 /**
640 * igc_set_d3_lplu_state_generic - Sets low power link up state for D3
641 * @hw: pointer to the HW structure
642 * @active: boolean used to enable/disable lplu
643 *
644 * Success returns 0, Failure returns 1
645 *
646 * The low power link up (lplu) state is set to the power management level D3
647 * and SmartSpeed is disabled when active is true, else clear lplu for D3
648 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
649 * is used during Dx states where the power conservation is most important.
650 * During driver activity, SmartSpeed should be enabled so performance is
651 * maintained.
652 **/
igc_set_d3_lplu_state_generic(struct igc_hw * hw,bool active)653 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active)
654 {
655 struct igc_phy_info *phy = &hw->phy;
656 s32 ret_val;
657 u16 data;
658
659 DEBUGFUNC("igc_set_d3_lplu_state_generic");
660
661 if (!hw->phy.ops.read_reg)
662 return IGC_SUCCESS;
663
664 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
665 if (ret_val)
666 return ret_val;
667
668 if (!active) {
669 data &= ~IGP02IGC_PM_D3_LPLU;
670 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
671 data);
672 if (ret_val)
673 return ret_val;
674 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
675 * during Dx states where the power conservation is most
676 * important. During driver activity we should enable
677 * SmartSpeed, so performance is maintained.
678 */
679 if (phy->smart_speed == igc_smart_speed_on) {
680 ret_val = phy->ops.read_reg(hw,
681 IGP01IGC_PHY_PORT_CONFIG,
682 &data);
683 if (ret_val)
684 return ret_val;
685
686 data |= IGP01IGC_PSCFR_SMART_SPEED;
687 ret_val = phy->ops.write_reg(hw,
688 IGP01IGC_PHY_PORT_CONFIG,
689 data);
690 if (ret_val)
691 return ret_val;
692 } else if (phy->smart_speed == igc_smart_speed_off) {
693 ret_val = phy->ops.read_reg(hw,
694 IGP01IGC_PHY_PORT_CONFIG,
695 &data);
696 if (ret_val)
697 return ret_val;
698
699 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
700 ret_val = phy->ops.write_reg(hw,
701 IGP01IGC_PHY_PORT_CONFIG,
702 data);
703 if (ret_val)
704 return ret_val;
705 }
706 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||
707 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||
708 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) {
709 data |= IGP02IGC_PM_D3_LPLU;
710 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
711 data);
712 if (ret_val)
713 return ret_val;
714
715 /* When LPLU is enabled, we should disable SmartSpeed */
716 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
717 &data);
718 if (ret_val)
719 return ret_val;
720
721 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
722 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
723 data);
724 }
725
726 return ret_val;
727 }
728
729 /**
730 * igc_check_downshift_generic - Checks whether a downshift in speed occurred
731 * @hw: pointer to the HW structure
732 *
733 * Success returns 0, Failure returns 1
734 *
735 * A downshift is detected by querying the PHY link health.
736 **/
igc_check_downshift_generic(struct igc_hw * hw)737 s32 igc_check_downshift_generic(struct igc_hw *hw)
738 {
739 struct igc_phy_info *phy = &hw->phy;
740 s32 ret_val;
741
742 DEBUGFUNC("igc_check_downshift_generic");
743
744 switch (phy->type) {
745 case igc_phy_i225:
746 default:
747 /* speed downshift not supported */
748 phy->speed_downgraded = false;
749 return IGC_SUCCESS;
750 }
751
752 return ret_val;
753 }
754
755 /**
756 * igc_wait_autoneg - Wait for auto-neg completion
757 * @hw: pointer to the HW structure
758 *
759 * Waits for auto-negotiation to complete or for the auto-negotiation time
760 * limit to expire, which ever happens first.
761 **/
igc_wait_autoneg(struct igc_hw * hw)762 static s32 igc_wait_autoneg(struct igc_hw *hw)
763 {
764 s32 ret_val = IGC_SUCCESS;
765 u16 i, phy_status;
766
767 DEBUGFUNC("igc_wait_autoneg");
768
769 if (!hw->phy.ops.read_reg)
770 return IGC_SUCCESS;
771
772 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
773 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
774 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
775 if (ret_val)
776 break;
777 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
778 if (ret_val)
779 break;
780 if (phy_status & MII_SR_AUTONEG_COMPLETE)
781 break;
782 msec_delay(100);
783 }
784
785 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
786 * has completed.
787 */
788 return ret_val;
789 }
790
791 /**
792 * igc_phy_has_link_generic - Polls PHY for link
793 * @hw: pointer to the HW structure
794 * @iterations: number of times to poll for link
795 * @usec_interval: delay between polling attempts
796 * @success: pointer to whether polling was successful or not
797 *
798 * Polls the PHY status register for link, 'iterations' number of times.
799 **/
igc_phy_has_link_generic(struct igc_hw * hw,u32 iterations,u32 usec_interval,bool * success)800 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
801 u32 usec_interval, bool *success)
802 {
803 s32 ret_val = IGC_SUCCESS;
804 u16 i, phy_status;
805
806 DEBUGFUNC("igc_phy_has_link_generic");
807
808 if (!hw->phy.ops.read_reg)
809 return IGC_SUCCESS;
810
811 for (i = 0; i < iterations; i++) {
812 /* Some PHYs require the PHY_STATUS register to be read
813 * twice due to the link bit being sticky. No harm doing
814 * it across the board.
815 */
816 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
817 if (ret_val) {
818 /* If the first read fails, another entity may have
819 * ownership of the resources, wait and try again to
820 * see if they have relinquished the resources yet.
821 */
822 if (usec_interval >= 1000)
823 msec_delay(usec_interval/1000);
824 else
825 usec_delay(usec_interval);
826 }
827 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
828 if (ret_val)
829 break;
830 if (phy_status & MII_SR_LINK_STATUS)
831 break;
832 if (usec_interval >= 1000)
833 msec_delay(usec_interval/1000);
834 else
835 usec_delay(usec_interval);
836 }
837
838 *success = (i < iterations);
839
840 return ret_val;
841 }
842
843 /**
844 * igc_phy_hw_reset_generic - PHY hardware reset
845 * @hw: pointer to the HW structure
846 *
847 * Verify the reset block is not blocking us from resetting. Acquire
848 * semaphore (if necessary) and read/set/write the device control reset
849 * bit in the PHY. Wait the appropriate delay time for the device to
850 * reset and release the semaphore (if necessary).
851 **/
igc_phy_hw_reset_generic(struct igc_hw * hw)852 s32 igc_phy_hw_reset_generic(struct igc_hw *hw)
853 {
854 struct igc_phy_info *phy = &hw->phy;
855 s32 ret_val;
856 u32 ctrl, timeout = 10000, phpm = 0;
857
858 DEBUGFUNC("igc_phy_hw_reset_generic");
859
860 if (phy->ops.check_reset_block) {
861 ret_val = phy->ops.check_reset_block(hw);
862 if (ret_val)
863 return IGC_SUCCESS;
864 }
865
866 ret_val = phy->ops.acquire(hw);
867 if (ret_val)
868 return ret_val;
869
870 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
871
872 ctrl = IGC_READ_REG(hw, IGC_CTRL);
873 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
874 IGC_WRITE_FLUSH(hw);
875
876 usec_delay(phy->reset_delay_us);
877
878 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
879 IGC_WRITE_FLUSH(hw);
880
881 usec_delay(150);
882
883 do {
884 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
885 timeout--;
886 usec_delay(1);
887 } while (!(phpm & IGC_I225_PHPM_RST_COMPL) && timeout);
888
889 if (!timeout)
890 DEBUGOUT("Timeout expired after a phy reset\n");
891
892 phy->ops.release(hw);
893
894 return ret_val;
895 }
896
897 /**
898 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
899 * @hw: pointer to the HW structure
900 *
901 * In the case of a PHY power down to save power, or to turn off link during a
902 * driver unload, or wake on lan is not enabled, restore the link to previous
903 * settings.
904 **/
igc_power_up_phy_copper(struct igc_hw * hw)905 void igc_power_up_phy_copper(struct igc_hw *hw)
906 {
907 u16 mii_reg = 0;
908
909 /* The PHY will retain its settings across a power down/up cycle */
910 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
911 mii_reg &= ~MII_CR_POWER_DOWN;
912 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
913 usec_delay(300);
914 }
915
916 /**
917 * igc_power_down_phy_copper - Restore copper link in case of PHY power down
918 * @hw: pointer to the HW structure
919 *
920 * In the case of a PHY power down to save power, or to turn off link during a
921 * driver unload, or wake on lan is not enabled, restore the link to previous
922 * settings.
923 **/
igc_power_down_phy_copper(struct igc_hw * hw)924 void igc_power_down_phy_copper(struct igc_hw *hw)
925 {
926 u16 mii_reg = 0;
927
928 /* The PHY will retain its settings across a power down/up cycle */
929 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
930 mii_reg |= MII_CR_POWER_DOWN;
931 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
932 msec_delay(1);
933 }
934 /**
935 * igc_write_phy_reg_gpy - Write GPY PHY register
936 * @hw: pointer to the HW structure
937 * @offset: register offset to write to
938 * @data: data to write at register offset
939 *
940 * Acquires semaphore, if necessary, then writes the data to PHY register
941 * at the offset. Release any acquired semaphores before exiting.
942 **/
igc_write_phy_reg_gpy(struct igc_hw * hw,u32 offset,u16 data)943 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
944 {
945 s32 ret_val;
946 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
947
948 DEBUGFUNC("igc_write_phy_reg_gpy");
949
950 offset = offset & GPY_REG_MASK;
951
952 if (!dev_addr) {
953 ret_val = hw->phy.ops.acquire(hw);
954 if (ret_val)
955 return ret_val;
956 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
957 if (ret_val)
958 return ret_val;
959 hw->phy.ops.release(hw);
960 } else {
961 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
962 data);
963 }
964 return ret_val;
965 }
966
967 /**
968 * igc_read_phy_reg_gpy - Read GPY PHY register
969 * @hw: pointer to the HW structure
970 * @offset: lower half is register offset to read to
971 * upper half is MMD to use.
972 * @data: data to read at register offset
973 *
974 * Acquires semaphore, if necessary, then reads the data in the PHY register
975 * at the offset. Release any acquired semaphores before exiting.
976 **/
igc_read_phy_reg_gpy(struct igc_hw * hw,u32 offset,u16 * data)977 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
978 {
979 s32 ret_val;
980 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
981
982 DEBUGFUNC("igc_read_phy_reg_gpy");
983
984 offset = offset & GPY_REG_MASK;
985
986 if (!dev_addr) {
987 ret_val = hw->phy.ops.acquire(hw);
988 if (ret_val)
989 return ret_val;
990 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
991 if (ret_val)
992 return ret_val;
993 hw->phy.ops.release(hw);
994 } else {
995 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
996 data);
997 }
998 return ret_val;
999 }
1000
1001
1002 /**
1003 * __igc_access_xmdio_reg - Read/write XMDIO register
1004 * @hw: pointer to the HW structure
1005 * @address: XMDIO address to program
1006 * @dev_addr: device address to program
1007 * @data: pointer to value to read/write from/to the XMDIO address
1008 * @read: boolean flag to indicate read or write
1009 **/
__igc_access_xmdio_reg(struct igc_hw * hw,u16 address,u8 dev_addr,u16 * data,bool read)1010 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
1011 u8 dev_addr, u16 *data, bool read)
1012 {
1013 s32 ret_val;
1014
1015 DEBUGFUNC("__igc_access_xmdio_reg");
1016
1017 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
1018 if (ret_val)
1019 return ret_val;
1020
1021 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
1022 if (ret_val)
1023 return ret_val;
1024
1025 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
1026 dev_addr);
1027 if (ret_val)
1028 return ret_val;
1029
1030 if (read)
1031 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
1032 else
1033 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
1034 if (ret_val)
1035 return ret_val;
1036
1037 /* Recalibrate the device back to 0 */
1038 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
1039 if (ret_val)
1040 return ret_val;
1041
1042 return ret_val;
1043 }
1044
1045 /**
1046 * igc_read_xmdio_reg - Read XMDIO register
1047 * @hw: pointer to the HW structure
1048 * @addr: XMDIO address to program
1049 * @dev_addr: device address to program
1050 * @data: value to be read from the EMI address
1051 **/
igc_read_xmdio_reg(struct igc_hw * hw,u16 addr,u8 dev_addr,u16 * data)1052 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data)
1053 {
1054 DEBUGFUNC("igc_read_xmdio_reg");
1055
1056 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
1057 }
1058
1059 /**
1060 * igc_write_xmdio_reg - Write XMDIO register
1061 * @hw: pointer to the HW structure
1062 * @addr: XMDIO address to program
1063 * @dev_addr: device address to program
1064 * @data: value to be written to the XMDIO address
1065 **/
igc_write_xmdio_reg(struct igc_hw * hw,u16 addr,u8 dev_addr,u16 data)1066 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data)
1067 {
1068 DEBUGFUNC("igc_write_xmdio_reg");
1069
1070 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);
1071 }
1072