1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io>
5 * All rights reserved.
6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate)
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "if_igc.h"
32
33 #ifdef RSS
34 #include <net/rss_config.h>
35 #include <netinet/in_rss.h>
36 #endif
37
38 #ifdef VERBOSE_DEBUG
39 #define DPRINTF device_printf
40 #else
41 #define DPRINTF(...)
42 #endif
43
44 /*********************************************************************
45 * Local Function prototypes
46 *********************************************************************/
47 static int igc_isc_txd_encap(void *, if_pkt_info_t);
48 static void igc_isc_txd_flush(void *, uint16_t, qidx_t);
49 static int igc_isc_txd_credits_update(void *, uint16_t, bool);
50
51 static void igc_isc_rxd_refill(void *, if_rxd_update_t);
52
53 static void igc_isc_rxd_flush(void *, uint16_t, uint8_t, qidx_t);
54 static int igc_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t);
55
56 static int igc_isc_rxd_pkt_get(void *, if_rxd_info_t);
57
58 static int igc_tx_ctx_setup(struct tx_ring *, if_pkt_info_t, uint32_t *,
59 uint32_t *);
60 static int igc_tso_setup(struct tx_ring *, if_pkt_info_t, uint32_t *,
61 uint32_t *);
62
63 static void igc_rx_checksum(uint32_t, if_rxd_info_t, uint32_t);
64 static int igc_determine_rsstype(uint16_t);
65
66 extern void igc_if_enable_intr(if_ctx_t);
67 extern int igc_intr(void *);
68
69 struct if_txrx igc_txrx = {
70 .ift_txd_encap = igc_isc_txd_encap,
71 .ift_txd_flush = igc_isc_txd_flush,
72 .ift_txd_credits_update = igc_isc_txd_credits_update,
73 .ift_rxd_available = igc_isc_rxd_available,
74 .ift_rxd_pkt_get = igc_isc_rxd_pkt_get,
75 .ift_rxd_refill = igc_isc_rxd_refill,
76 .ift_rxd_flush = igc_isc_rxd_flush,
77 .ift_legacy_intr = igc_intr
78 };
79
80 void
igc_dump_rs(struct igc_softc * sc)81 igc_dump_rs(struct igc_softc *sc)
82 {
83 if_softc_ctx_t scctx = sc->shared;
84 struct igc_tx_queue *que;
85 struct tx_ring *txr;
86 qidx_t i, ntxd, qid, cur;
87 int16_t rs_cidx;
88 uint8_t status;
89
90 printf("\n");
91 ntxd = scctx->isc_ntxd[0];
92 for (qid = 0; qid < sc->tx_num_queues; qid++) {
93 que = &sc->tx_queues[qid];
94 txr = &que->txr;
95 rs_cidx = txr->tx_rs_cidx;
96 if (rs_cidx != txr->tx_rs_pidx) {
97 cur = txr->tx_rsq[rs_cidx];
98 status = txr->tx_base[cur].upper.fields.status;
99 if (!(status & IGC_TXD_STAT_DD))
100 printf("qid[%d]->tx_rsq[%d]: %d clear ", qid, rs_cidx, cur);
101 } else {
102 rs_cidx = (rs_cidx-1)&(ntxd-1);
103 cur = txr->tx_rsq[rs_cidx];
104 printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ", qid, rs_cidx, cur);
105 }
106 printf("cidx_prev=%d rs_pidx=%d ",txr->tx_cidx_processed, txr->tx_rs_pidx);
107 for (i = 0; i < ntxd; i++) {
108 if (txr->tx_base[i].upper.fields.status & IGC_TXD_STAT_DD)
109 printf("%d set ", i);
110 }
111 printf("\n");
112 }
113 }
114
115 /**********************************************************************
116 *
117 * Setup work for hardware segmentation offload (TSO) on
118 * adapters using advanced tx descriptors
119 *
120 **********************************************************************/
121 static int
igc_tso_setup(struct tx_ring * txr,if_pkt_info_t pi,uint32_t * cmd_type_len,uint32_t * olinfo_status)122 igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
123 uint32_t *olinfo_status)
124 {
125 struct igc_adv_tx_context_desc *TXD;
126 uint32_t type_tucmd_mlhl = 0, vlan_macip_lens = 0;
127 uint32_t mss_l4len_idx = 0;
128 uint32_t paylen;
129
130 switch(pi->ipi_etype) {
131 case ETHERTYPE_IPV6:
132 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6;
133 break;
134 case ETHERTYPE_IP:
135 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4;
136 /* Tell transmit desc to also do IPv4 checksum. */
137 *olinfo_status |= IGC_TXD_POPTS_IXSM << 8;
138 break;
139 default:
140 panic("%s: CSUM_TSO but no supported IP version (0x%04x)",
141 __func__, ntohs(pi->ipi_etype));
142 break;
143 }
144
145 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
146
147 /* This is used in the transmit desc in encap */
148 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen;
149
150 /* VLAN MACLEN IPLEN */
151 if (pi->ipi_mflags & M_VLANTAG) {
152 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT);
153 }
154
155 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT;
156 vlan_macip_lens |= pi->ipi_ip_hlen;
157 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
158
159 /* ADV DTYPE TUCMD */
160 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
161 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP;
162 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
163
164 /* MSS L4LEN IDX */
165 mss_l4len_idx |= (pi->ipi_tso_segsz << IGC_ADVTXD_MSS_SHIFT);
166 mss_l4len_idx |= (pi->ipi_tcp_hlen << IGC_ADVTXD_L4LEN_SHIFT);
167 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
168
169 TXD->seqnum_seed = htole32(0);
170 *cmd_type_len |= IGC_ADVTXD_DCMD_TSE;
171 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
172 *olinfo_status |= paylen << IGC_ADVTXD_PAYLEN_SHIFT;
173
174 return (1);
175 }
176
177 /*********************************************************************
178 *
179 * Advanced Context Descriptor setup for VLAN, CSUM or TSO
180 *
181 **********************************************************************/
182 static int
igc_tx_ctx_setup(struct tx_ring * txr,if_pkt_info_t pi,uint32_t * cmd_type_len,uint32_t * olinfo_status)183 igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
184 uint32_t *olinfo_status)
185 {
186 struct igc_adv_tx_context_desc *TXD;
187 uint32_t vlan_macip_lens, type_tucmd_mlhl;
188 uint32_t mss_l4len_idx;
189 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0;
190
191 /* First check if TSO is to be used */
192 if (pi->ipi_csum_flags & CSUM_TSO)
193 return (igc_tso_setup(txr, pi, cmd_type_len, olinfo_status));
194
195 /* Indicate the whole packet as payload when not doing TSO */
196 *olinfo_status |= pi->ipi_len << IGC_ADVTXD_PAYLEN_SHIFT;
197
198 /* Now ready a context descriptor */
199 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
200
201 /*
202 ** In advanced descriptors the vlan tag must
203 ** be placed into the context descriptor. Hence
204 ** we need to make one even if not doing offloads.
205 */
206 if (pi->ipi_mflags & M_VLANTAG) {
207 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT);
208 } else if ((pi->ipi_csum_flags & IGC_CSUM_OFFLOAD) == 0) {
209 return (0);
210 }
211
212 /* Set the ether header length */
213 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT;
214
215 switch(pi->ipi_etype) {
216 case ETHERTYPE_IP:
217 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4;
218 break;
219 case ETHERTYPE_IPV6:
220 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6;
221 break;
222 default:
223 break;
224 }
225
226 vlan_macip_lens |= pi->ipi_ip_hlen;
227 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
228
229 switch (pi->ipi_ipproto) {
230 case IPPROTO_TCP:
231 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) {
232 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP;
233 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
234 }
235 break;
236 case IPPROTO_UDP:
237 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) {
238 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_UDP;
239 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
240 }
241 break;
242 case IPPROTO_SCTP:
243 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) {
244 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_SCTP;
245 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
246 }
247 break;
248 default:
249 break;
250 }
251
252 /* Now copy bits into descriptor */
253 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
254 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
255 TXD->seqnum_seed = htole32(0);
256 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
257
258 return (1);
259 }
260
261 static int
igc_isc_txd_encap(void * arg,if_pkt_info_t pi)262 igc_isc_txd_encap(void *arg, if_pkt_info_t pi)
263 {
264 struct igc_softc *sc = arg;
265 if_softc_ctx_t scctx = sc->shared;
266 struct igc_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx];
267 struct tx_ring *txr = &que->txr;
268 int nsegs = pi->ipi_nsegs;
269 bus_dma_segment_t *segs = pi->ipi_segs;
270 union igc_adv_tx_desc *txd = NULL;
271 int i, j, pidx_last;
272 uint32_t olinfo_status, cmd_type_len, txd_flags;
273 qidx_t ntxd;
274
275 pidx_last = olinfo_status = 0;
276 /* Basic descriptor defines */
277 cmd_type_len = (IGC_ADVTXD_DTYP_DATA |
278 IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DCMD_DEXT);
279
280 if (pi->ipi_mflags & M_VLANTAG)
281 cmd_type_len |= IGC_ADVTXD_DCMD_VLE;
282
283 i = pi->ipi_pidx;
284 ntxd = scctx->isc_ntxd[0];
285 txd_flags = pi->ipi_flags & IPI_TX_INTR ? IGC_ADVTXD_DCMD_RS : 0;
286 /* Consume the first descriptor */
287 i += igc_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status);
288 if (i == scctx->isc_ntxd[0])
289 i = 0;
290
291 for (j = 0; j < nsegs; j++) {
292 bus_size_t seglen;
293 bus_addr_t segaddr;
294
295 txd = (union igc_adv_tx_desc *)&txr->tx_base[i];
296 seglen = segs[j].ds_len;
297 segaddr = htole64(segs[j].ds_addr);
298
299 txd->read.buffer_addr = segaddr;
300 txd->read.cmd_type_len = htole32(IGC_ADVTXD_DCMD_IFCS |
301 cmd_type_len | seglen);
302 txd->read.olinfo_status = htole32(olinfo_status);
303 pidx_last = i;
304 if (++i == scctx->isc_ntxd[0]) {
305 i = 0;
306 }
307 }
308 if (txd_flags) {
309 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last;
310 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1);
311 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx);
312 }
313
314 txd->read.cmd_type_len |= htole32(IGC_ADVTXD_DCMD_EOP | txd_flags);
315 pi->ipi_new_pidx = i;
316
317 /* Sent data accounting for AIM */
318 txr->tx_bytes += pi->ipi_len;
319 ++txr->tx_packets;
320
321 return (0);
322 }
323
324 static void
igc_isc_txd_flush(void * arg,uint16_t txqid,qidx_t pidx)325 igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
326 {
327 struct igc_softc *sc = arg;
328 struct igc_tx_queue *que = &sc->tx_queues[txqid];
329 struct tx_ring *txr = &que->txr;
330
331 IGC_WRITE_REG(&sc->hw, IGC_TDT(txr->me), pidx);
332 }
333
334 static int
igc_isc_txd_credits_update(void * arg,uint16_t txqid,bool clear)335 igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
336 {
337 struct igc_softc *sc = arg;
338 if_softc_ctx_t scctx = sc->shared;
339 struct igc_tx_queue *que = &sc->tx_queues[txqid];
340 struct tx_ring *txr = &que->txr;
341
342 qidx_t processed = 0;
343 int updated;
344 qidx_t cur, prev, ntxd, rs_cidx;
345 int32_t delta;
346 uint8_t status;
347
348 rs_cidx = txr->tx_rs_cidx;
349 if (rs_cidx == txr->tx_rs_pidx)
350 return (0);
351 cur = txr->tx_rsq[rs_cidx];
352 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status;
353 updated = !!(status & IGC_TXD_STAT_DD);
354
355 if (!updated)
356 return (0);
357
358 /* If clear is false just let caller know that there
359 * are descriptors to reclaim */
360 if (!clear)
361 return (1);
362
363 prev = txr->tx_cidx_processed;
364 ntxd = scctx->isc_ntxd[0];
365 do {
366 MPASS(prev != cur);
367 delta = (int32_t)cur - (int32_t)prev;
368 if (delta < 0)
369 delta += ntxd;
370 MPASS(delta > 0);
371
372 processed += delta;
373 prev = cur;
374 rs_cidx = (rs_cidx + 1) & (ntxd-1);
375 if (rs_cidx == txr->tx_rs_pidx)
376 break;
377 cur = txr->tx_rsq[rs_cidx];
378 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status;
379 } while ((status & IGC_TXD_STAT_DD));
380
381 txr->tx_rs_cidx = rs_cidx;
382 txr->tx_cidx_processed = prev;
383 return (processed);
384 }
385
386 static void
igc_isc_rxd_refill(void * arg,if_rxd_update_t iru)387 igc_isc_rxd_refill(void *arg, if_rxd_update_t iru)
388 {
389 struct igc_softc *sc = arg;
390 if_softc_ctx_t scctx = sc->shared;
391 uint16_t rxqid = iru->iru_qsidx;
392 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
393 union igc_adv_rx_desc *rxd;
394 struct rx_ring *rxr = &que->rxr;
395 uint64_t *paddrs;
396 uint32_t next_pidx, pidx;
397 uint16_t count;
398 int i;
399
400 paddrs = iru->iru_paddrs;
401 pidx = iru->iru_pidx;
402 count = iru->iru_count;
403
404 for (i = 0, next_pidx = pidx; i < count; i++) {
405 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[next_pidx];
406
407 rxd->read.pkt_addr = htole64(paddrs[i]);
408 if (++next_pidx == scctx->isc_nrxd[0])
409 next_pidx = 0;
410 }
411 }
412
413 static void
igc_isc_rxd_flush(void * arg,uint16_t rxqid,uint8_t flid __unused,qidx_t pidx)414 igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx)
415 {
416 struct igc_softc *sc = arg;
417 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
418 struct rx_ring *rxr = &que->rxr;
419
420 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), pidx);
421 }
422
423 static int
igc_isc_rxd_available(void * arg,uint16_t rxqid,qidx_t idx,qidx_t budget)424 igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget)
425 {
426 struct igc_softc *sc = arg;
427 if_softc_ctx_t scctx = sc->shared;
428 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
429 struct rx_ring *rxr = &que->rxr;
430 union igc_adv_rx_desc *rxd;
431 uint32_t staterr = 0;
432 int cnt, i;
433
434 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) {
435 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[i];
436 staterr = le32toh(rxd->wb.upper.status_error);
437
438 if ((staterr & IGC_RXD_STAT_DD) == 0)
439 break;
440 if (++i == scctx->isc_nrxd[0])
441 i = 0;
442 if (staterr & IGC_RXD_STAT_EOP)
443 cnt++;
444 }
445 return (cnt);
446 }
447
448 /****************************************************************
449 * Routine sends data which has been dma'ed into host memory
450 * to upper layer. Initialize ri structure.
451 *
452 * Returns 0 upon success, errno on failure
453 ***************************************************************/
454
455 static int
igc_isc_rxd_pkt_get(void * arg,if_rxd_info_t ri)456 igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
457 {
458 struct igc_softc *sc = arg;
459 if_softc_ctx_t scctx = sc->shared;
460 struct igc_rx_queue *que = &sc->rx_queues[ri->iri_qsidx];
461 struct rx_ring *rxr = &que->rxr;
462 union igc_adv_rx_desc *rxd;
463
464 uint16_t pkt_info, len;
465 uint32_t ptype, staterr;
466 int i, cidx;
467 bool eop;
468
469 staterr = i = 0;
470 cidx = ri->iri_cidx;
471
472 do {
473 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[cidx];
474 staterr = le32toh(rxd->wb.upper.status_error);
475 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info);
476
477 MPASS ((staterr & IGC_RXD_STAT_DD) != 0);
478
479 len = le16toh(rxd->wb.upper.length);
480 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGC_PKTTYPE_MASK;
481
482 ri->iri_len += len;
483 rxr->rx_bytes += ri->iri_len;
484
485 rxd->wb.upper.status_error = 0;
486 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP);
487
488 /* Make sure bad packets are discarded */
489 if (eop && ((staterr & IGC_RXDEXT_STATERR_RXE) != 0)) {
490 sc->dropped_pkts++;
491 ++rxr->rx_discarded;
492 return (EBADMSG);
493 }
494 ri->iri_frags[i].irf_flid = 0;
495 ri->iri_frags[i].irf_idx = cidx;
496 ri->iri_frags[i].irf_len = len;
497
498 if (++cidx == scctx->isc_nrxd[0])
499 cidx = 0;
500 #ifdef notyet
501 if (rxr->hdr_split == true) {
502 ri->iri_frags[i].irf_flid = 1;
503 ri->iri_frags[i].irf_idx = cidx;
504 if (++cidx == scctx->isc_nrxd[0])
505 cidx = 0;
506 }
507 #endif
508 i++;
509 } while (!eop);
510
511 rxr->rx_packets++;
512
513 if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0)
514 igc_rx_checksum(staterr, ri, ptype);
515
516 if (staterr & IGC_RXD_STAT_VP) {
517 ri->iri_vtag = le16toh(rxd->wb.upper.vlan);
518 ri->iri_flags |= M_VLANTAG;
519 }
520
521 ri->iri_flowid =
522 le32toh(rxd->wb.lower.hi_dword.rss);
523 ri->iri_rsstype = igc_determine_rsstype(pkt_info);
524 ri->iri_nfrags = i;
525
526 return (0);
527 }
528
529 /*********************************************************************
530 *
531 * Verify that the hardware indicated that the checksum is valid.
532 * Inform the stack about the status of checksum so that stack
533 * doesn't spend time verifying the checksum.
534 *
535 *********************************************************************/
536 static void
igc_rx_checksum(uint32_t staterr,if_rxd_info_t ri,uint32_t ptype)537 igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype)
538 {
539 uint16_t status = (uint16_t)staterr;
540 uint8_t errors = (uint8_t)(staterr >> 24);
541
542 if (__predict_false(status & IGC_RXD_STAT_IXSM))
543 return;
544
545 /* If there is a layer 3 or 4 error we are done */
546 if (__predict_false(errors & (IGC_RXD_ERR_IPE | IGC_RXD_ERR_TCPE)))
547 return;
548
549 /* IP Checksum Good */
550 if (status & IGC_RXD_STAT_IPCS)
551 ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID);
552
553 /* Valid L4E checksum */
554 if (__predict_true(status &
555 (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS))) {
556 /* SCTP header present */
557 if (__predict_false((ptype & IGC_RXDADV_PKTTYPE_ETQF) == 0 &&
558 (ptype & IGC_RXDADV_PKTTYPE_SCTP) != 0)) {
559 ri->iri_csum_flags |= CSUM_SCTP_VALID;
560 } else {
561 ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
562 ri->iri_csum_data = htons(0xffff);
563 }
564 }
565 }
566
567 /********************************************************************
568 *
569 * Parse the packet type to determine the appropriate hash
570 *
571 ******************************************************************/
572 static int
igc_determine_rsstype(uint16_t pkt_info)573 igc_determine_rsstype(uint16_t pkt_info)
574 {
575 switch (pkt_info & IGC_RXDADV_RSSTYPE_MASK) {
576 case IGC_RXDADV_RSSTYPE_IPV4_TCP:
577 return M_HASHTYPE_RSS_TCP_IPV4;
578 case IGC_RXDADV_RSSTYPE_IPV4:
579 return M_HASHTYPE_RSS_IPV4;
580 case IGC_RXDADV_RSSTYPE_IPV6_TCP:
581 return M_HASHTYPE_RSS_TCP_IPV6;
582 case IGC_RXDADV_RSSTYPE_IPV6_EX:
583 return M_HASHTYPE_RSS_IPV6_EX;
584 case IGC_RXDADV_RSSTYPE_IPV6:
585 return M_HASHTYPE_RSS_IPV6;
586 case IGC_RXDADV_RSSTYPE_IPV6_TCP_EX:
587 return M_HASHTYPE_RSS_TCP_IPV6_EX;
588 default:
589 return M_HASHTYPE_OPAQUE;
590 }
591 }
592