1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io>
5 * All rights reserved.
6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate)
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "if_igc.h"
32
33 #ifdef RSS
34 #include <net/rss_config.h>
35 #include <netinet/in_rss.h>
36 #endif
37
38 #ifdef VERBOSE_DEBUG
39 #define DPRINTF device_printf
40 #else
41 #define DPRINTF(...)
42 #endif
43
44 /*********************************************************************
45 * Local Function prototypes
46 *********************************************************************/
47 static int igc_isc_txd_encap(void *, if_pkt_info_t);
48 static void igc_isc_txd_flush(void *, uint16_t, qidx_t);
49 static int igc_isc_txd_credits_update(void *, uint16_t, bool);
50
51 static void igc_isc_rxd_refill(void *, if_rxd_update_t);
52
53 static void igc_isc_rxd_flush(void *, uint16_t, uint8_t, qidx_t);
54 static int igc_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t);
55
56 static int igc_isc_rxd_pkt_get(void *, if_rxd_info_t);
57
58 static int igc_tx_ctx_setup(struct tx_ring *, if_pkt_info_t, uint32_t *,
59 uint32_t *);
60 static int igc_tso_setup(struct tx_ring *, if_pkt_info_t, uint32_t *,
61 uint32_t *);
62
63 static void igc_rx_checksum(uint32_t, if_rxd_info_t, uint32_t);
64 static int igc_determine_rsstype(uint16_t);
65
66 extern void igc_if_enable_intr(if_ctx_t);
67 extern int igc_intr(void *);
68
69 struct if_txrx igc_txrx = {
70 .ift_txd_encap = igc_isc_txd_encap,
71 .ift_txd_flush = igc_isc_txd_flush,
72 .ift_txd_credits_update = igc_isc_txd_credits_update,
73 .ift_rxd_available = igc_isc_rxd_available,
74 .ift_rxd_pkt_get = igc_isc_rxd_pkt_get,
75 .ift_rxd_refill = igc_isc_rxd_refill,
76 .ift_rxd_flush = igc_isc_rxd_flush,
77 .ift_legacy_intr = igc_intr
78 };
79
80 void
igc_dump_rs(struct igc_softc * sc)81 igc_dump_rs(struct igc_softc *sc)
82 {
83 if_softc_ctx_t scctx = sc->shared;
84 struct igc_tx_queue *que;
85 struct tx_ring *txr;
86 qidx_t i, ntxd, qid, cur;
87 int16_t rs_cidx;
88 uint8_t status;
89
90 printf("\n");
91 ntxd = scctx->isc_ntxd[0];
92 for (qid = 0; qid < sc->tx_num_queues; qid++) {
93 que = &sc->tx_queues[qid];
94 txr = &que->txr;
95 rs_cidx = txr->tx_rs_cidx;
96 if (rs_cidx != txr->tx_rs_pidx) {
97 cur = txr->tx_rsq[rs_cidx];
98 status = txr->tx_base[cur].upper.fields.status;
99 if (!(status & IGC_TXD_STAT_DD))
100 printf("qid[%d]->tx_rsq[%d]: %d clear ",
101 qid, rs_cidx, cur);
102 } else {
103 rs_cidx = (rs_cidx-1)&(ntxd-1);
104 cur = txr->tx_rsq[rs_cidx];
105 printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ",
106 qid, rs_cidx, cur);
107 }
108 printf("cidx_prev=%d rs_pidx=%d ",txr->tx_cidx_processed,
109 txr->tx_rs_pidx);
110 for (i = 0; i < ntxd; i++) {
111 if (txr->tx_base[i].upper.fields.status &
112 IGC_TXD_STAT_DD)
113 printf("%d set ", i);
114 }
115 printf("\n");
116 }
117 }
118
119 /**********************************************************************
120 *
121 * Setup work for hardware segmentation offload (TSO) on
122 * adapters using advanced tx descriptors
123 *
124 **********************************************************************/
125 static int
igc_tso_setup(struct tx_ring * txr,if_pkt_info_t pi,uint32_t * cmd_type_len,uint32_t * olinfo_status)126 igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
127 uint32_t *olinfo_status)
128 {
129 struct igc_adv_tx_context_desc *TXD;
130 uint32_t type_tucmd_mlhl = 0, vlan_macip_lens = 0;
131 uint32_t mss_l4len_idx = 0;
132 uint32_t paylen;
133
134 switch(pi->ipi_etype) {
135 case ETHERTYPE_IPV6:
136 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6;
137 break;
138 case ETHERTYPE_IP:
139 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4;
140 /* Tell transmit desc to also do IPv4 checksum. */
141 *olinfo_status |= IGC_TXD_POPTS_IXSM << 8;
142 break;
143 default:
144 panic("%s: CSUM_TSO but no supported IP version (0x%04x)",
145 __func__, ntohs(pi->ipi_etype));
146 break;
147 }
148
149 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
150
151 /* This is used in the transmit desc in encap */
152 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen -
153 pi->ipi_tcp_hlen;
154
155 /* VLAN MACLEN IPLEN */
156 if (pi->ipi_mflags & M_VLANTAG) {
157 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT);
158 }
159
160 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT;
161 vlan_macip_lens |= pi->ipi_ip_hlen;
162 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
163
164 /* ADV DTYPE TUCMD */
165 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
166 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP;
167 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
168
169 /* MSS L4LEN IDX */
170 mss_l4len_idx |= (pi->ipi_tso_segsz << IGC_ADVTXD_MSS_SHIFT);
171 mss_l4len_idx |= (pi->ipi_tcp_hlen << IGC_ADVTXD_L4LEN_SHIFT);
172 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
173
174 TXD->seqnum_seed = htole32(0);
175 *cmd_type_len |= IGC_ADVTXD_DCMD_TSE;
176 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
177 *olinfo_status |= paylen << IGC_ADVTXD_PAYLEN_SHIFT;
178
179 return (1);
180 }
181
182 /*********************************************************************
183 *
184 * Advanced Context Descriptor setup for VLAN, CSUM or TSO
185 *
186 **********************************************************************/
187 static int
igc_tx_ctx_setup(struct tx_ring * txr,if_pkt_info_t pi,uint32_t * cmd_type_len,uint32_t * olinfo_status)188 igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi,
189 uint32_t *cmd_type_len, uint32_t *olinfo_status)
190 {
191 struct igc_adv_tx_context_desc *TXD;
192 uint32_t vlan_macip_lens, type_tucmd_mlhl;
193 uint32_t mss_l4len_idx;
194 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0;
195
196 /* First check if TSO is to be used */
197 if (pi->ipi_csum_flags & CSUM_TSO)
198 return (igc_tso_setup(txr, pi, cmd_type_len, olinfo_status));
199
200 /* Indicate the whole packet as payload when not doing TSO */
201 *olinfo_status |= pi->ipi_len << IGC_ADVTXD_PAYLEN_SHIFT;
202
203 /* Now ready a context descriptor */
204 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
205
206 /*
207 ** In advanced descriptors the vlan tag must
208 ** be placed into the context descriptor. Hence
209 ** we need to make one even if not doing offloads.
210 */
211 if (pi->ipi_mflags & M_VLANTAG) {
212 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT);
213 } else if ((pi->ipi_csum_flags & IGC_CSUM_OFFLOAD) == 0) {
214 return (0);
215 }
216
217 /* Set the ether header length */
218 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT;
219
220 switch(pi->ipi_etype) {
221 case ETHERTYPE_IP:
222 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4;
223 break;
224 case ETHERTYPE_IPV6:
225 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6;
226 break;
227 default:
228 break;
229 }
230
231 vlan_macip_lens |= pi->ipi_ip_hlen;
232 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT;
233
234 switch (pi->ipi_ipproto) {
235 case IPPROTO_TCP:
236 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) {
237 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP;
238 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
239 }
240 break;
241 case IPPROTO_UDP:
242 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) {
243 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_UDP;
244 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
245 }
246 break;
247 case IPPROTO_SCTP:
248 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) {
249 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_SCTP;
250 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8;
251 }
252 break;
253 default:
254 break;
255 }
256
257 /* Now copy bits into descriptor */
258 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
259 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
260 TXD->seqnum_seed = htole32(0);
261 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
262
263 return (1);
264 }
265
266 static int
igc_isc_txd_encap(void * arg,if_pkt_info_t pi)267 igc_isc_txd_encap(void *arg, if_pkt_info_t pi)
268 {
269 struct igc_softc *sc = arg;
270 if_softc_ctx_t scctx = sc->shared;
271 struct igc_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx];
272 struct tx_ring *txr = &que->txr;
273 int nsegs = pi->ipi_nsegs;
274 bus_dma_segment_t *segs = pi->ipi_segs;
275 union igc_adv_tx_desc *txd = NULL;
276 int i, j, pidx_last;
277 uint32_t olinfo_status, cmd_type_len, txd_flags;
278 qidx_t ntxd;
279
280 pidx_last = olinfo_status = 0;
281 /* Basic descriptor defines */
282 cmd_type_len = (IGC_ADVTXD_DTYP_DATA |
283 IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DCMD_DEXT);
284
285 if (pi->ipi_mflags & M_VLANTAG)
286 cmd_type_len |= IGC_ADVTXD_DCMD_VLE;
287
288 i = pi->ipi_pidx;
289 ntxd = scctx->isc_ntxd[0];
290 txd_flags = pi->ipi_flags & IPI_TX_INTR ? IGC_ADVTXD_DCMD_RS : 0;
291 /* Consume the first descriptor */
292 i += igc_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status);
293 if (i == scctx->isc_ntxd[0])
294 i = 0;
295
296 for (j = 0; j < nsegs; j++) {
297 bus_size_t seglen;
298 bus_addr_t segaddr;
299
300 txd = (union igc_adv_tx_desc *)&txr->tx_base[i];
301 seglen = segs[j].ds_len;
302 segaddr = htole64(segs[j].ds_addr);
303
304 txd->read.buffer_addr = segaddr;
305 txd->read.cmd_type_len = htole32(IGC_ADVTXD_DCMD_IFCS |
306 cmd_type_len | seglen);
307 txd->read.olinfo_status = htole32(olinfo_status);
308 pidx_last = i;
309 if (++i == scctx->isc_ntxd[0]) {
310 i = 0;
311 }
312 }
313 if (txd_flags) {
314 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last;
315 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1);
316 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx);
317 }
318
319 txd->read.cmd_type_len |= htole32(IGC_ADVTXD_DCMD_EOP | txd_flags);
320 pi->ipi_new_pidx = i;
321
322 /* Sent data accounting for AIM */
323 txr->tx_bytes += pi->ipi_len;
324 ++txr->tx_packets;
325
326 return (0);
327 }
328
329 static void
igc_isc_txd_flush(void * arg,uint16_t txqid,qidx_t pidx)330 igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
331 {
332 struct igc_softc *sc = arg;
333 struct igc_tx_queue *que = &sc->tx_queues[txqid];
334 struct tx_ring *txr = &que->txr;
335
336 IGC_WRITE_REG(&sc->hw, IGC_TDT(txr->me), pidx);
337 }
338
339 static int
igc_isc_txd_credits_update(void * arg,uint16_t txqid,bool clear)340 igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
341 {
342 struct igc_softc *sc = arg;
343 if_softc_ctx_t scctx = sc->shared;
344 struct igc_tx_queue *que = &sc->tx_queues[txqid];
345 struct tx_ring *txr = &que->txr;
346
347 qidx_t processed = 0;
348 int updated;
349 qidx_t cur, prev, ntxd, rs_cidx;
350 int32_t delta;
351 uint8_t status;
352
353 rs_cidx = txr->tx_rs_cidx;
354 if (rs_cidx == txr->tx_rs_pidx)
355 return (0);
356 cur = txr->tx_rsq[rs_cidx];
357 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status;
358 updated = !!(status & IGC_TXD_STAT_DD);
359
360 if (!updated)
361 return (0);
362
363 /* If clear is false just let caller know that there
364 * are descriptors to reclaim */
365 if (!clear)
366 return (1);
367
368 prev = txr->tx_cidx_processed;
369 ntxd = scctx->isc_ntxd[0];
370 do {
371 MPASS(prev != cur);
372 delta = (int32_t)cur - (int32_t)prev;
373 if (delta < 0)
374 delta += ntxd;
375 MPASS(delta > 0);
376
377 processed += delta;
378 prev = cur;
379 rs_cidx = (rs_cidx + 1) & (ntxd-1);
380 if (rs_cidx == txr->tx_rs_pidx)
381 break;
382 cur = txr->tx_rsq[rs_cidx];
383 status =
384 ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status;
385 } while ((status & IGC_TXD_STAT_DD));
386
387 txr->tx_rs_cidx = rs_cidx;
388 txr->tx_cidx_processed = prev;
389 return (processed);
390 }
391
392 static void
igc_isc_rxd_refill(void * arg,if_rxd_update_t iru)393 igc_isc_rxd_refill(void *arg, if_rxd_update_t iru)
394 {
395 struct igc_softc *sc = arg;
396 if_softc_ctx_t scctx = sc->shared;
397 uint16_t rxqid = iru->iru_qsidx;
398 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
399 union igc_adv_rx_desc *rxd;
400 struct rx_ring *rxr = &que->rxr;
401 uint64_t *paddrs;
402 uint32_t next_pidx, pidx;
403 uint16_t count;
404 int i;
405
406 paddrs = iru->iru_paddrs;
407 pidx = iru->iru_pidx;
408 count = iru->iru_count;
409
410 for (i = 0, next_pidx = pidx; i < count; i++) {
411 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[next_pidx];
412
413 rxd->read.pkt_addr = htole64(paddrs[i]);
414 if (++next_pidx == scctx->isc_nrxd[0])
415 next_pidx = 0;
416 }
417 }
418
419 static void
igc_isc_rxd_flush(void * arg,uint16_t rxqid,uint8_t flid __unused,qidx_t pidx)420 igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused,
421 qidx_t pidx)
422 {
423 struct igc_softc *sc = arg;
424 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
425 struct rx_ring *rxr = &que->rxr;
426
427 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), pidx);
428 }
429
430 static int
igc_isc_rxd_available(void * arg,uint16_t rxqid,qidx_t idx,qidx_t budget)431 igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget)
432 {
433 struct igc_softc *sc = arg;
434 if_softc_ctx_t scctx = sc->shared;
435 struct igc_rx_queue *que = &sc->rx_queues[rxqid];
436 struct rx_ring *rxr = &que->rxr;
437 union igc_adv_rx_desc *rxd;
438 uint32_t staterr = 0;
439 int cnt, i;
440
441 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) {
442 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[i];
443 staterr = le32toh(rxd->wb.upper.status_error);
444
445 if ((staterr & IGC_RXD_STAT_DD) == 0)
446 break;
447 if (++i == scctx->isc_nrxd[0])
448 i = 0;
449 if (staterr & IGC_RXD_STAT_EOP)
450 cnt++;
451 }
452 return (cnt);
453 }
454
455 /****************************************************************
456 * Routine sends data which has been dma'ed into host memory
457 * to upper layer. Initialize ri structure.
458 *
459 * Returns 0 upon success, errno on failure
460 ***************************************************************/
461
462 static int
igc_isc_rxd_pkt_get(void * arg,if_rxd_info_t ri)463 igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
464 {
465 struct igc_softc *sc = arg;
466 if_softc_ctx_t scctx = sc->shared;
467 struct igc_rx_queue *que = &sc->rx_queues[ri->iri_qsidx];
468 struct rx_ring *rxr = &que->rxr;
469 union igc_adv_rx_desc *rxd;
470
471 uint16_t pkt_info, len;
472 uint32_t ptype, staterr;
473 int i, cidx;
474 bool eop;
475
476 staterr = i = 0;
477 cidx = ri->iri_cidx;
478
479 do {
480 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[cidx];
481 staterr = le32toh(rxd->wb.upper.status_error);
482 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info);
483
484 MPASS ((staterr & IGC_RXD_STAT_DD) != 0);
485
486 len = le16toh(rxd->wb.upper.length);
487 ptype =
488 le32toh(rxd->wb.lower.lo_dword.data) & IGC_PKTTYPE_MASK;
489
490 ri->iri_len += len;
491 rxr->rx_bytes += ri->iri_len;
492
493 rxd->wb.upper.status_error = 0;
494 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP);
495
496 /* Make sure bad packets are discarded */
497 if (eop && ((staterr & IGC_RXDEXT_STATERR_RXE) != 0)) {
498 sc->dropped_pkts++;
499 ++rxr->rx_discarded;
500 return (EBADMSG);
501 }
502 ri->iri_frags[i].irf_flid = 0;
503 ri->iri_frags[i].irf_idx = cidx;
504 ri->iri_frags[i].irf_len = len;
505
506 if (++cidx == scctx->isc_nrxd[0])
507 cidx = 0;
508 #ifdef notyet
509 if (rxr->hdr_split == true) {
510 ri->iri_frags[i].irf_flid = 1;
511 ri->iri_frags[i].irf_idx = cidx;
512 if (++cidx == scctx->isc_nrxd[0])
513 cidx = 0;
514 }
515 #endif
516 i++;
517 } while (!eop);
518
519 rxr->rx_packets++;
520
521 if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0)
522 igc_rx_checksum(staterr, ri, ptype);
523
524 if (staterr & IGC_RXD_STAT_VP) {
525 ri->iri_vtag = le16toh(rxd->wb.upper.vlan);
526 ri->iri_flags |= M_VLANTAG;
527 }
528
529 ri->iri_flowid =
530 le32toh(rxd->wb.lower.hi_dword.rss);
531 ri->iri_rsstype = igc_determine_rsstype(pkt_info);
532 ri->iri_nfrags = i;
533
534 return (0);
535 }
536
537 /*********************************************************************
538 *
539 * Verify that the hardware indicated that the checksum is valid.
540 * Inform the stack about the status of checksum so that stack
541 * doesn't spend time verifying the checksum.
542 *
543 *********************************************************************/
544 static void
igc_rx_checksum(uint32_t staterr,if_rxd_info_t ri,uint32_t ptype)545 igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype)
546 {
547 uint16_t status = (uint16_t)staterr;
548 uint8_t errors = (uint8_t)(staterr >> 24);
549
550 if (__predict_false(status & IGC_RXD_STAT_IXSM))
551 return;
552
553 /* If there is a layer 3 or 4 error we are done */
554 if (__predict_false(errors & (IGC_RXD_ERR_IPE | IGC_RXD_ERR_TCPE)))
555 return;
556
557 /* IP Checksum Good */
558 if (status & IGC_RXD_STAT_IPCS)
559 ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID);
560
561 /* Valid L4E checksum */
562 if (__predict_true(status &
563 (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS))) {
564 /* SCTP header present */
565 if (__predict_false((ptype & IGC_RXDADV_PKTTYPE_ETQF) == 0 &&
566 (ptype & IGC_RXDADV_PKTTYPE_SCTP) != 0)) {
567 ri->iri_csum_flags |= CSUM_SCTP_VALID;
568 } else {
569 ri->iri_csum_flags |=
570 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
571 ri->iri_csum_data = htons(0xffff);
572 }
573 }
574 }
575
576 /********************************************************************
577 *
578 * Parse the packet type to determine the appropriate hash
579 *
580 ******************************************************************/
581 static int
igc_determine_rsstype(uint16_t pkt_info)582 igc_determine_rsstype(uint16_t pkt_info)
583 {
584 switch (pkt_info & IGC_RXDADV_RSSTYPE_MASK) {
585 case IGC_RXDADV_RSSTYPE_IPV4_TCP:
586 return M_HASHTYPE_RSS_TCP_IPV4;
587 case IGC_RXDADV_RSSTYPE_IPV4:
588 return M_HASHTYPE_RSS_IPV4;
589 case IGC_RXDADV_RSSTYPE_IPV6_TCP:
590 return M_HASHTYPE_RSS_TCP_IPV6;
591 case IGC_RXDADV_RSSTYPE_IPV6_EX:
592 return M_HASHTYPE_RSS_IPV6_EX;
593 case IGC_RXDADV_RSSTYPE_IPV6:
594 return M_HASHTYPE_RSS_IPV6;
595 case IGC_RXDADV_RSSTYPE_IPV6_TCP_EX:
596 return M_HASHTYPE_RSS_TCP_IPV6_EX;
597 default:
598 return M_HASHTYPE_OPAQUE;
599 }
600 }
601