1 /*-
2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include "igc_api.h"
8
9 static void igc_config_collision_dist_generic(struct igc_hw *hw);
10
11 /**
12 * igc_init_mac_ops_generic - Initialize MAC function pointers
13 * @hw: pointer to the HW structure
14 *
15 * Setups up the function pointers to no-op functions
16 **/
igc_init_mac_ops_generic(struct igc_hw * hw)17 void igc_init_mac_ops_generic(struct igc_hw *hw)
18 {
19 struct igc_mac_info *mac = &hw->mac;
20 DEBUGFUNC("igc_init_mac_ops_generic");
21
22 /* General Setup */
23 mac->ops.init_params = igc_null_ops_generic;
24 mac->ops.config_collision_dist = igc_config_collision_dist_generic;
25 mac->ops.rar_set = igc_rar_set_generic;
26 }
27
28 /**
29 * igc_null_ops_generic - No-op function, returns 0
30 * @hw: pointer to the HW structure
31 **/
igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG * hw)32 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw)
33 {
34 DEBUGFUNC("igc_null_ops_generic");
35 return IGC_SUCCESS;
36 }
37
38 /**
39 * igc_null_mac_generic - No-op function, return void
40 * @hw: pointer to the HW structure
41 **/
igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG * hw)42 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw)
43 {
44 DEBUGFUNC("igc_null_mac_generic");
45 return;
46 }
47
48 /**
49 * igc_null_link_info - No-op function, return 0
50 * @hw: pointer to the HW structure
51 * @s: dummy variable
52 * @d: dummy variable
53 **/
igc_null_link_info(struct igc_hw IGC_UNUSEDARG * hw,u16 IGC_UNUSEDARG * s,u16 IGC_UNUSEDARG * d)54 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw,
55 u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d)
56 {
57 DEBUGFUNC("igc_null_link_info");
58 return IGC_SUCCESS;
59 }
60
61 /**
62 * igc_null_mng_mode - No-op function, return false
63 * @hw: pointer to the HW structure
64 **/
igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG * hw)65 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw)
66 {
67 DEBUGFUNC("igc_null_mng_mode");
68 return false;
69 }
70
71 /**
72 * igc_null_update_mc - No-op function, return void
73 * @hw: pointer to the HW structure
74 * @h: dummy variable
75 * @a: dummy variable
76 **/
igc_null_update_mc(struct igc_hw IGC_UNUSEDARG * hw,u8 IGC_UNUSEDARG * h,u32 IGC_UNUSEDARG a)77 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw,
78 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a)
79 {
80 DEBUGFUNC("igc_null_update_mc");
81 return;
82 }
83
84 /**
85 * igc_null_write_vfta - No-op function, return void
86 * @hw: pointer to the HW structure
87 * @a: dummy variable
88 * @b: dummy variable
89 **/
igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG * hw,u32 IGC_UNUSEDARG a,u32 IGC_UNUSEDARG b)90 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw,
91 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b)
92 {
93 DEBUGFUNC("igc_null_write_vfta");
94 return;
95 }
96
97 /**
98 * igc_null_rar_set - No-op function, return 0
99 * @hw: pointer to the HW structure
100 * @h: dummy variable
101 * @a: dummy variable
102 **/
igc_null_rar_set(struct igc_hw IGC_UNUSEDARG * hw,u8 IGC_UNUSEDARG * h,u32 IGC_UNUSEDARG a)103 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw,
104 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a)
105 {
106 DEBUGFUNC("igc_null_rar_set");
107 return IGC_SUCCESS;
108 }
109
110 /**
111 * igc_set_lan_id_single_port - Set LAN id for a single port device
112 * @hw: pointer to the HW structure
113 *
114 * Sets the LAN function id to zero for a single port device.
115 **/
igc_set_lan_id_single_port(struct igc_hw * hw)116 void igc_set_lan_id_single_port(struct igc_hw *hw)
117 {
118 struct igc_bus_info *bus = &hw->bus;
119
120 bus->func = 0;
121 }
122
123 /**
124 * igc_clear_vfta_generic - Clear VLAN filter table
125 * @hw: pointer to the HW structure
126 *
127 * Clears the register array which contains the VLAN filter table by
128 * setting all the values to 0.
129 **/
igc_clear_vfta_generic(struct igc_hw * hw)130 void igc_clear_vfta_generic(struct igc_hw *hw)
131 {
132 u32 offset;
133
134 DEBUGFUNC("igc_clear_vfta_generic");
135
136 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) {
137 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0);
138 IGC_WRITE_FLUSH(hw);
139 }
140 }
141
142 /**
143 * igc_write_vfta_generic - Write value to VLAN filter table
144 * @hw: pointer to the HW structure
145 * @offset: register offset in VLAN filter table
146 * @value: register value written to VLAN filter table
147 *
148 * Writes value at the given offset in the register array which stores
149 * the VLAN filter table.
150 **/
igc_write_vfta_generic(struct igc_hw * hw,u32 offset,u32 value)151 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value)
152 {
153 DEBUGFUNC("igc_write_vfta_generic");
154
155 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);
156 IGC_WRITE_FLUSH(hw);
157 }
158
159 /**
160 * igc_init_rx_addrs_generic - Initialize receive address's
161 * @hw: pointer to the HW structure
162 * @rar_count: receive address registers
163 *
164 * Setup the receive address registers by setting the base receive address
165 * register to the devices MAC address and clearing all the other receive
166 * address registers to 0.
167 **/
igc_init_rx_addrs_generic(struct igc_hw * hw,u16 rar_count)168 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count)
169 {
170 u32 i;
171 u8 mac_addr[ETH_ADDR_LEN] = {0};
172
173 DEBUGFUNC("igc_init_rx_addrs_generic");
174
175 /* Setup the receive address */
176 DEBUGOUT("Programming MAC Address into RAR[0]\n");
177
178 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
179
180 /* Zero out the other (rar_entry_count - 1) receive addresses */
181 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
182 for (i = 1; i < rar_count; i++)
183 hw->mac.ops.rar_set(hw, mac_addr, i);
184 }
185
186 /**
187 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr
188 * @hw: pointer to the HW structure
189 *
190 * Checks the nvm for an alternate MAC address. An alternate MAC address
191 * can be setup by pre-boot software and must be treated like a permanent
192 * address and must override the actual permanent MAC address. If an
193 * alternate MAC address is found it is programmed into RAR0, replacing
194 * the permanent address that was installed into RAR0 by the Si on reset.
195 * This function will return SUCCESS unless it encounters an error while
196 * reading the EEPROM.
197 **/
igc_check_alt_mac_addr_generic(struct igc_hw * hw)198 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw)
199 {
200 u32 i;
201 s32 ret_val;
202 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
203 u8 alt_mac_addr[ETH_ADDR_LEN];
204
205 DEBUGFUNC("igc_check_alt_mac_addr_generic");
206
207 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
208 if (ret_val)
209 return ret_val;
210
211
212 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
213 &nvm_alt_mac_addr_offset);
214 if (ret_val) {
215 DEBUGOUT("NVM Read Error\n");
216 return ret_val;
217 }
218
219 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
220 (nvm_alt_mac_addr_offset == 0x0000))
221 /* There is no Alternate MAC Address */
222 return IGC_SUCCESS;
223
224 if (hw->bus.func == IGC_FUNC_1)
225 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1;
226 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
227 offset = nvm_alt_mac_addr_offset + (i >> 1);
228 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
229 if (ret_val) {
230 DEBUGOUT("NVM Read Error\n");
231 return ret_val;
232 }
233
234 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
235 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
236 }
237
238 /* if multicast bit is set, the alternate address will not be used */
239 if (alt_mac_addr[0] & 0x01) {
240 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
241 return IGC_SUCCESS;
242 }
243
244 /* We have a valid alternate MAC address, and we want to treat it the
245 * same as the normal permanent MAC address stored by the HW into the
246 * RAR. Do this by mapping this address into RAR0.
247 */
248 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
249
250 return IGC_SUCCESS;
251 }
252
253 /**
254 * igc_rar_set_generic - Set receive address register
255 * @hw: pointer to the HW structure
256 * @addr: pointer to the receive address
257 * @index: receive address array register
258 *
259 * Sets the receive address array register at index to the address passed
260 * in by addr.
261 **/
igc_rar_set_generic(struct igc_hw * hw,u8 * addr,u32 index)262 int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)
263 {
264 u32 rar_low, rar_high;
265
266 DEBUGFUNC("igc_rar_set_generic");
267
268 /* HW expects these in little endian so we reverse the byte order
269 * from network order (big endian) to little endian
270 */
271 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
272 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
273
274 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
275
276 /* If MAC address zero, no need to set the AV bit */
277 if (rar_low || rar_high)
278 rar_high |= IGC_RAH_AV;
279
280 /* Some bridges will combine consecutive 32-bit writes into
281 * a single burst write, which will malfunction on some parts.
282 * The flushes avoid this.
283 */
284 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
285 IGC_WRITE_FLUSH(hw);
286 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
287 IGC_WRITE_FLUSH(hw);
288
289 return IGC_SUCCESS;
290 }
291
292 /**
293 * igc_hash_mc_addr_generic - Generate a multicast hash value
294 * @hw: pointer to the HW structure
295 * @mc_addr: pointer to a multicast address
296 *
297 * Generates a multicast address hash value which is used to determine
298 * the multicast filter table array address and new table value.
299 **/
igc_hash_mc_addr_generic(struct igc_hw * hw,u8 * mc_addr)300 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr)
301 {
302 u32 hash_value, hash_mask;
303 u8 bit_shift = 0;
304
305 DEBUGFUNC("igc_hash_mc_addr_generic");
306
307 /* Register count multiplied by bits per register */
308 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
309
310 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
311 * where 0xFF would still fall within the hash mask.
312 */
313 while (hash_mask >> bit_shift != 0xFF)
314 bit_shift++;
315
316 /* The portion of the address that is used for the hash table
317 * is determined by the mc_filter_type setting.
318 * The algorithm is such that there is a total of 8 bits of shifting.
319 * The bit_shift for a mc_filter_type of 0 represents the number of
320 * left-shifts where the MSB of mc_addr[5] would still fall within
321 * the hash_mask. Case 0 does this exactly. Since there are a total
322 * of 8 bits of shifting, then mc_addr[4] will shift right the
323 * remaining number of bits. Thus 8 - bit_shift. The rest of the
324 * cases are a variation of this algorithm...essentially raising the
325 * number of bits to shift mc_addr[5] left, while still keeping the
326 * 8-bit shifting total.
327 *
328 * For example, given the following Destination MAC Address and an
329 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
330 * we can see that the bit_shift for case 0 is 4. These are the hash
331 * values resulting from each mc_filter_type...
332 * [0] [1] [2] [3] [4] [5]
333 * 01 AA 00 12 34 56
334 * LSB MSB
335 *
336 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
337 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
338 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
339 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
340 */
341 switch (hw->mac.mc_filter_type) {
342 default:
343 case 0:
344 break;
345 case 1:
346 bit_shift += 1;
347 break;
348 case 2:
349 bit_shift += 2;
350 break;
351 case 3:
352 bit_shift += 4;
353 break;
354 }
355
356 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
357 (((u16) mc_addr[5]) << bit_shift)));
358
359 return hash_value;
360 }
361
362 /**
363 * igc_update_mc_addr_list_generic - Update Multicast addresses
364 * @hw: pointer to the HW structure
365 * @mc_addr_list: array of multicast addresses to program
366 * @mc_addr_count: number of multicast addresses to program
367 *
368 * Updates entire Multicast Table Array.
369 * The caller must have a packed mc_addr_list of multicast addresses.
370 **/
igc_update_mc_addr_list_generic(struct igc_hw * hw,u8 * mc_addr_list,u32 mc_addr_count)371 void igc_update_mc_addr_list_generic(struct igc_hw *hw,
372 u8 *mc_addr_list, u32 mc_addr_count)
373 {
374 u32 hash_value, hash_bit, hash_reg;
375 int i;
376
377 DEBUGFUNC("igc_update_mc_addr_list_generic");
378
379 /* clear mta_shadow */
380 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
381
382 /* update mta_shadow from mc_addr_list */
383 for (i = 0; (u32) i < mc_addr_count; i++) {
384 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);
385
386 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
387 hash_bit = hash_value & 0x1F;
388
389 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
390 mc_addr_list += (ETH_ADDR_LEN);
391 }
392
393 /* replace the entire MTA table */
394 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
395 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);
396 IGC_WRITE_FLUSH(hw);
397 }
398
399 /**
400 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters
401 * @hw: pointer to the HW structure
402 *
403 * Clears the base hardware counters by reading the counter registers.
404 **/
igc_clear_hw_cntrs_base_generic(struct igc_hw * hw)405 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)
406 {
407 DEBUGFUNC("igc_clear_hw_cntrs_base_generic");
408
409 IGC_READ_REG(hw, IGC_CRCERRS);
410 IGC_READ_REG(hw, IGC_MPC);
411 IGC_READ_REG(hw, IGC_SCC);
412 IGC_READ_REG(hw, IGC_ECOL);
413 IGC_READ_REG(hw, IGC_MCC);
414 IGC_READ_REG(hw, IGC_LATECOL);
415 IGC_READ_REG(hw, IGC_COLC);
416 IGC_READ_REG(hw, IGC_RERC);
417 IGC_READ_REG(hw, IGC_DC);
418 IGC_READ_REG(hw, IGC_RLEC);
419 IGC_READ_REG(hw, IGC_XONRXC);
420 IGC_READ_REG(hw, IGC_XONTXC);
421 IGC_READ_REG(hw, IGC_XOFFRXC);
422 IGC_READ_REG(hw, IGC_XOFFTXC);
423 IGC_READ_REG(hw, IGC_FCRUC);
424 IGC_READ_REG(hw, IGC_GPRC);
425 IGC_READ_REG(hw, IGC_BPRC);
426 IGC_READ_REG(hw, IGC_MPRC);
427 IGC_READ_REG(hw, IGC_GPTC);
428 IGC_READ_REG(hw, IGC_GORCL);
429 IGC_READ_REG(hw, IGC_GORCH);
430 IGC_READ_REG(hw, IGC_GOTCL);
431 IGC_READ_REG(hw, IGC_GOTCH);
432 IGC_READ_REG(hw, IGC_RNBC);
433 IGC_READ_REG(hw, IGC_RUC);
434 IGC_READ_REG(hw, IGC_RFC);
435 IGC_READ_REG(hw, IGC_ROC);
436 IGC_READ_REG(hw, IGC_RJC);
437 IGC_READ_REG(hw, IGC_TORL);
438 IGC_READ_REG(hw, IGC_TORH);
439 IGC_READ_REG(hw, IGC_TOTL);
440 IGC_READ_REG(hw, IGC_TOTH);
441 IGC_READ_REG(hw, IGC_TPR);
442 IGC_READ_REG(hw, IGC_TPT);
443 IGC_READ_REG(hw, IGC_MPTC);
444 IGC_READ_REG(hw, IGC_BPTC);
445 IGC_READ_REG(hw, IGC_TLPIC);
446 IGC_READ_REG(hw, IGC_RLPIC);
447 IGC_READ_REG(hw, IGC_RXDMTC);
448 }
449
450 /**
451 * igc_check_for_copper_link_generic - Check for link (Copper)
452 * @hw: pointer to the HW structure
453 *
454 * Checks to see of the link status of the hardware has changed. If a
455 * change in link status has been detected, then we read the PHY registers
456 * to get the current speed/duplex if link exists.
457 **/
igc_check_for_copper_link_generic(struct igc_hw * hw)458 s32 igc_check_for_copper_link_generic(struct igc_hw *hw)
459 {
460 struct igc_mac_info *mac = &hw->mac;
461 s32 ret_val;
462 bool link = false;
463
464 DEBUGFUNC("igc_check_for_copper_link");
465
466 /* We only want to go out to the PHY registers to see if Auto-Neg
467 * has completed and/or if our link status has changed. The
468 * get_link_status flag is set upon receiving a Link Status
469 * Change or Rx Sequence Error interrupt.
470 */
471 if (!mac->get_link_status)
472 return IGC_SUCCESS;
473
474 /* First we want to see if the MII Status Register reports
475 * link. If so, then we want to get the current speed/duplex
476 * of the PHY.
477 */
478 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
479 if (ret_val)
480 return ret_val;
481
482 if (!link)
483 return IGC_SUCCESS; /* No link detected */
484
485 mac->get_link_status = false;
486
487 /* Check if there was DownShift, must be checked
488 * immediately after link-up
489 */
490 igc_check_downshift_generic(hw);
491
492 /* If we are forcing speed/duplex, then we simply return since
493 * we have already determined whether we have link or not.
494 */
495 if (!mac->autoneg)
496 return -IGC_ERR_CONFIG;
497
498 /* Auto-Neg is enabled. Auto Speed Detection takes care
499 * of MAC speed/duplex configuration. So we only need to
500 * configure Collision Distance in the MAC.
501 */
502 mac->ops.config_collision_dist(hw);
503
504 /* Configure Flow Control now that Auto-Neg has completed.
505 * First, we need to restore the desired flow control
506 * settings because we may have had to re-autoneg with a
507 * different link partner.
508 */
509 ret_val = igc_config_fc_after_link_up_generic(hw);
510 if (ret_val)
511 DEBUGOUT("Error configuring flow control\n");
512
513 return ret_val;
514 }
515
516 /**
517 * igc_setup_link_generic - Setup flow control and link settings
518 * @hw: pointer to the HW structure
519 *
520 * Determines which flow control settings to use, then configures flow
521 * control. Calls the appropriate media-specific link configuration
522 * function. Assuming the adapter has a valid link partner, a valid link
523 * should be established. Assumes the hardware has previously been reset
524 * and the transmitter and receiver are not enabled.
525 **/
igc_setup_link_generic(struct igc_hw * hw)526 s32 igc_setup_link_generic(struct igc_hw *hw)
527 {
528 s32 ret_val;
529
530 DEBUGFUNC("igc_setup_link_generic");
531
532 /* In the case of the phy reset being blocked, we already have a link.
533 * We do not need to set it up again.
534 */
535 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
536 return IGC_SUCCESS;
537
538 /* If requested flow control is set to default, set flow control
539 * for both 'rx' and 'tx' pause frames.
540 */
541 if (hw->fc.requested_mode == igc_fc_default) {
542 hw->fc.requested_mode = igc_fc_full;
543 }
544
545 /* Save off the requested flow control mode for use later. Depending
546 * on the link partner's capabilities, we may or may not use this mode.
547 */
548 hw->fc.current_mode = hw->fc.requested_mode;
549
550 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
551 hw->fc.current_mode);
552
553 /* Call the necessary media_type subroutine to configure the link. */
554 ret_val = hw->mac.ops.setup_physical_interface(hw);
555 if (ret_val)
556 return ret_val;
557
558 /* Initialize the flow control address, type, and PAUSE timer
559 * registers to their default values. This is done even if flow
560 * control is disabled, because it does not hurt anything to
561 * initialize these registers.
562 */
563 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
564 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);
565 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
566 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
567
568 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);
569
570 return igc_set_fc_watermarks_generic(hw);
571 }
572
573 /**
574 * igc_config_collision_dist_generic - Configure collision distance
575 * @hw: pointer to the HW structure
576 *
577 * Configures the collision distance to the default value and is used
578 * during link setup.
579 **/
igc_config_collision_dist_generic(struct igc_hw * hw)580 static void igc_config_collision_dist_generic(struct igc_hw *hw)
581 {
582 u32 tctl;
583
584 DEBUGFUNC("igc_config_collision_dist_generic");
585
586 tctl = IGC_READ_REG(hw, IGC_TCTL);
587
588 tctl &= ~IGC_TCTL_COLD;
589 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
590
591 IGC_WRITE_REG(hw, IGC_TCTL, tctl);
592 IGC_WRITE_FLUSH(hw);
593 }
594
595 /**
596 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks
597 * @hw: pointer to the HW structure
598 *
599 * Sets the flow control high/low threshold (watermark) registers. If
600 * flow control XON frame transmission is enabled, then set XON frame
601 * transmission as well.
602 **/
igc_set_fc_watermarks_generic(struct igc_hw * hw)603 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw)
604 {
605 u32 fcrtl = 0, fcrth = 0;
606
607 DEBUGFUNC("igc_set_fc_watermarks_generic");
608
609 /* Set the flow control receive threshold registers. Normally,
610 * these registers will be set to a default threshold that may be
611 * adjusted later by the driver's runtime code. However, if the
612 * ability to transmit pause frames is not enabled, then these
613 * registers will be set to 0.
614 */
615 if (hw->fc.current_mode & igc_fc_tx_pause) {
616 /* We need to set up the Receive Threshold high and low water
617 * marks as well as (optionally) enabling the transmission of
618 * XON frames.
619 */
620 fcrtl = hw->fc.low_water;
621 if (hw->fc.send_xon)
622 fcrtl |= IGC_FCRTL_XONE;
623
624 fcrth = hw->fc.high_water;
625 }
626 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);
627 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);
628
629 return IGC_SUCCESS;
630 }
631
632 /**
633 * igc_force_mac_fc_generic - Force the MAC's flow control settings
634 * @hw: pointer to the HW structure
635 *
636 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
637 * device control register to reflect the adapter settings. TFCE and RFCE
638 * need to be explicitly set by software when a copper PHY is used because
639 * autonegotiation is managed by the PHY rather than the MAC. Software must
640 * also configure these bits when link is forced on a fiber connection.
641 **/
igc_force_mac_fc_generic(struct igc_hw * hw)642 s32 igc_force_mac_fc_generic(struct igc_hw *hw)
643 {
644 u32 ctrl;
645
646 DEBUGFUNC("igc_force_mac_fc_generic");
647
648 ctrl = IGC_READ_REG(hw, IGC_CTRL);
649
650 /* Because we didn't get link via the internal auto-negotiation
651 * mechanism (we either forced link or we got link via PHY
652 * auto-neg), we have to manually enable/disable transmit an
653 * receive flow control.
654 *
655 * The "Case" statement below enables/disable flow control
656 * according to the "hw->fc.current_mode" parameter.
657 *
658 * The possible values of the "fc" parameter are:
659 * 0: Flow control is completely disabled
660 * 1: Rx flow control is enabled (we can receive pause
661 * frames but not send pause frames).
662 * 2: Tx flow control is enabled (we can send pause frames
663 * frames but we do not receive pause frames).
664 * 3: Both Rx and Tx flow control (symmetric) is enabled.
665 * other: No other values should be possible at this point.
666 */
667 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
668
669 switch (hw->fc.current_mode) {
670 case igc_fc_none:
671 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
672 break;
673 case igc_fc_rx_pause:
674 ctrl &= (~IGC_CTRL_TFCE);
675 ctrl |= IGC_CTRL_RFCE;
676 break;
677 case igc_fc_tx_pause:
678 ctrl &= (~IGC_CTRL_RFCE);
679 ctrl |= IGC_CTRL_TFCE;
680 break;
681 case igc_fc_full:
682 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
683 break;
684 default:
685 DEBUGOUT("Flow control param set incorrectly\n");
686 return -IGC_ERR_CONFIG;
687 }
688
689 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
690
691 return IGC_SUCCESS;
692 }
693
694 /**
695 * igc_config_fc_after_link_up_generic - Configures flow control after link
696 * @hw: pointer to the HW structure
697 *
698 * Checks the status of auto-negotiation after link up to ensure that the
699 * speed and duplex were not forced. If the link needed to be forced, then
700 * flow control needs to be forced also. If auto-negotiation is enabled
701 * and did not fail, then we configure flow control based on our link
702 * partner.
703 **/
igc_config_fc_after_link_up_generic(struct igc_hw * hw)704 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw)
705 {
706 struct igc_mac_info *mac = &hw->mac;
707 s32 ret_val = IGC_SUCCESS;
708 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
709 u16 speed, duplex;
710
711 DEBUGFUNC("igc_config_fc_after_link_up_generic");
712
713 if (ret_val) {
714 DEBUGOUT("Error forcing flow control settings\n");
715 return ret_val;
716 }
717
718 /* Check for the case where we have copper media and auto-neg is
719 * enabled. In this case, we need to check and see if Auto-Neg
720 * has completed, and if so, how the PHY and link partner has
721 * flow control configured.
722 */
723 if (mac->autoneg) {
724 /* Read the MII Status Register and check to see if AutoNeg
725 * has completed. We read this twice because this reg has
726 * some "sticky" (latched) bits.
727 */
728 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
729 if (ret_val)
730 return ret_val;
731 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
732 if (ret_val)
733 return ret_val;
734
735 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
736 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
737 return ret_val;
738 }
739
740 /* The AutoNeg process has completed, so we now need to
741 * read both the Auto Negotiation Advertisement
742 * Register (Address 4) and the Auto_Negotiation Base
743 * Page Ability Register (Address 5) to determine how
744 * flow control was negotiated.
745 */
746 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
747 &mii_nway_adv_reg);
748 if (ret_val)
749 return ret_val;
750 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
751 &mii_nway_lp_ability_reg);
752 if (ret_val)
753 return ret_val;
754
755 /* Two bits in the Auto Negotiation Advertisement Register
756 * (Address 4) and two bits in the Auto Negotiation Base
757 * Page Ability Register (Address 5) determine flow control
758 * for both the PHY and the link partner. The following
759 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
760 * 1999, describes these PAUSE resolution bits and how flow
761 * control is determined based upon these settings.
762 * NOTE: DC = Don't Care
763 *
764 * LOCAL DEVICE | LINK PARTNER
765 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
766 *-------|---------|-------|---------|--------------------
767 * 0 | 0 | DC | DC | igc_fc_none
768 * 0 | 1 | 0 | DC | igc_fc_none
769 * 0 | 1 | 1 | 0 | igc_fc_none
770 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
771 * 1 | 0 | 0 | DC | igc_fc_none
772 * 1 | DC | 1 | DC | igc_fc_full
773 * 1 | 1 | 0 | 0 | igc_fc_none
774 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
775 *
776 * Are both PAUSE bits set to 1? If so, this implies
777 * Symmetric Flow Control is enabled at both ends. The
778 * ASM_DIR bits are irrelevant per the spec.
779 *
780 * For Symmetric Flow Control:
781 *
782 * LOCAL DEVICE | LINK PARTNER
783 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
784 *-------|---------|-------|---------|--------------------
785 * 1 | DC | 1 | DC | IGC_fc_full
786 *
787 */
788 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
789 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
790 /* Now we need to check if the user selected Rx ONLY
791 * of pause frames. In this case, we had to advertise
792 * FULL flow control because we could not advertise Rx
793 * ONLY. Hence, we must now check to see if we need to
794 * turn OFF the TRANSMISSION of PAUSE frames.
795 */
796 if (hw->fc.requested_mode == igc_fc_full) {
797 hw->fc.current_mode = igc_fc_full;
798 DEBUGOUT("Flow Control = FULL.\n");
799 } else {
800 hw->fc.current_mode = igc_fc_rx_pause;
801 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
802 }
803 }
804 /* For receiving PAUSE frames ONLY.
805 *
806 * LOCAL DEVICE | LINK PARTNER
807 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
808 *-------|---------|-------|---------|--------------------
809 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
810 */
811 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
812 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
813 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
814 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
815 hw->fc.current_mode = igc_fc_tx_pause;
816 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
817 }
818 /* For transmitting PAUSE frames ONLY.
819 *
820 * LOCAL DEVICE | LINK PARTNER
821 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
822 *-------|---------|-------|---------|--------------------
823 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
824 */
825 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
826 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
827 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
828 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
829 hw->fc.current_mode = igc_fc_rx_pause;
830 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
831 } else {
832 /* Per the IEEE spec, at this point flow control
833 * should be disabled.
834 */
835 hw->fc.current_mode = igc_fc_none;
836 DEBUGOUT("Flow Control = NONE.\n");
837 }
838
839 /* Now we need to do one last check... If we auto-
840 * negotiated to HALF DUPLEX, flow control should not be
841 * enabled per IEEE 802.3 spec.
842 */
843 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
844 if (ret_val) {
845 DEBUGOUT("Error getting link speed and duplex\n");
846 return ret_val;
847 }
848
849 if (duplex == HALF_DUPLEX)
850 hw->fc.current_mode = igc_fc_none;
851
852 /* Now we call a subroutine to actually force the MAC
853 * controller to use the correct flow control settings.
854 */
855 ret_val = igc_force_mac_fc_generic(hw);
856 if (ret_val) {
857 DEBUGOUT("Error forcing flow control settings\n");
858 return ret_val;
859 }
860 }
861
862 return IGC_SUCCESS;
863 }
864
865 /**
866 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
867 * @hw: pointer to the HW structure
868 * @speed: stores the current speed
869 * @duplex: stores the current duplex
870 *
871 * Read the status register for the current speed/duplex and store the current
872 * speed and duplex for copper connections.
873 **/
igc_get_speed_and_duplex_copper_generic(struct igc_hw * hw,u16 * speed,u16 * duplex)874 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,
875 u16 *duplex)
876 {
877 u32 status;
878
879 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic");
880
881 status = IGC_READ_REG(hw, IGC_STATUS);
882 if (status & IGC_STATUS_SPEED_1000) {
883 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
884 * and 2.5 Gbps link modes. An additional bit is used
885 * to differentiate between 1 Gbps and 2.5 Gbps.
886 */
887 if ((hw->mac.type == igc_i225) &&
888 (status & IGC_STATUS_SPEED_2500)) {
889 *speed = SPEED_2500;
890 DEBUGOUT("2500 Mbs, ");
891 } else {
892 *speed = SPEED_1000;
893 DEBUGOUT("1000 Mbs, ");
894 }
895 } else if (status & IGC_STATUS_SPEED_100) {
896 *speed = SPEED_100;
897 DEBUGOUT("100 Mbs, ");
898 } else {
899 *speed = SPEED_10;
900 DEBUGOUT("10 Mbs, ");
901 }
902
903 if (status & IGC_STATUS_FD) {
904 *duplex = FULL_DUPLEX;
905 DEBUGOUT("Full Duplex\n");
906 } else {
907 *duplex = HALF_DUPLEX;
908 DEBUGOUT("Half Duplex\n");
909 }
910
911 return IGC_SUCCESS;
912 }
913
914 /**
915 * igc_get_hw_semaphore_generic - Acquire hardware semaphore
916 * @hw: pointer to the HW structure
917 *
918 * Acquire the HW semaphore to access the PHY or NVM
919 **/
igc_get_hw_semaphore_generic(struct igc_hw * hw)920 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw)
921 {
922 u32 swsm;
923 s32 timeout = hw->nvm.word_size + 1;
924 s32 i = 0;
925
926 DEBUGFUNC("igc_get_hw_semaphore_generic");
927
928 /* Get the SW semaphore */
929 while (i < timeout) {
930 swsm = IGC_READ_REG(hw, IGC_SWSM);
931 if (!(swsm & IGC_SWSM_SMBI))
932 break;
933
934 usec_delay(50);
935 i++;
936 }
937
938 if (i == timeout) {
939 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
940 return -IGC_ERR_NVM;
941 }
942
943 /* Get the FW semaphore. */
944 for (i = 0; i < timeout; i++) {
945 swsm = IGC_READ_REG(hw, IGC_SWSM);
946 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
947
948 /* Semaphore acquired if bit latched */
949 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
950 break;
951
952 usec_delay(50);
953 }
954
955 if (i == timeout) {
956 /* Release semaphores */
957 igc_put_hw_semaphore_generic(hw);
958 DEBUGOUT("Driver can't access the NVM\n");
959 return -IGC_ERR_NVM;
960 }
961
962 return IGC_SUCCESS;
963 }
964
965 /**
966 * igc_put_hw_semaphore_generic - Release hardware semaphore
967 * @hw: pointer to the HW structure
968 *
969 * Release hardware semaphore used to access the PHY or NVM
970 **/
igc_put_hw_semaphore_generic(struct igc_hw * hw)971 void igc_put_hw_semaphore_generic(struct igc_hw *hw)
972 {
973 u32 swsm;
974
975 DEBUGFUNC("igc_put_hw_semaphore_generic");
976
977 swsm = IGC_READ_REG(hw, IGC_SWSM);
978
979 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
980
981 IGC_WRITE_REG(hw, IGC_SWSM, swsm);
982 }
983
984 /**
985 * igc_get_auto_rd_done_generic - Check for auto read completion
986 * @hw: pointer to the HW structure
987 *
988 * Check EEPROM for Auto Read done bit.
989 **/
igc_get_auto_rd_done_generic(struct igc_hw * hw)990 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw)
991 {
992 s32 i = 0;
993
994 DEBUGFUNC("igc_get_auto_rd_done_generic");
995
996 while (i < AUTO_READ_DONE_TIMEOUT) {
997 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)
998 break;
999 msec_delay(1);
1000 i++;
1001 }
1002
1003 if (i == AUTO_READ_DONE_TIMEOUT) {
1004 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1005 return -IGC_ERR_RESET;
1006 }
1007
1008 return IGC_SUCCESS;
1009 }
1010
1011 /**
1012 * igc_disable_pcie_master_generic - Disables PCI-express master access
1013 * @hw: pointer to the HW structure
1014 *
1015 * Returns IGC_SUCCESS if successful, else returns -10
1016 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1017 * the master requests to be disabled.
1018 *
1019 * Disables PCI-Express master access and verifies there are no pending
1020 * requests.
1021 **/
igc_disable_pcie_master_generic(struct igc_hw * hw)1022 s32 igc_disable_pcie_master_generic(struct igc_hw *hw)
1023 {
1024 u32 ctrl;
1025 s32 timeout = MASTER_DISABLE_TIMEOUT;
1026
1027 DEBUGFUNC("igc_disable_pcie_master_generic");
1028
1029 ctrl = IGC_READ_REG(hw, IGC_CTRL);
1030 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
1031 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1032
1033 while (timeout) {
1034 if (!(IGC_READ_REG(hw, IGC_STATUS) &
1035 IGC_STATUS_GIO_MASTER_ENABLE))
1036 break;
1037 usec_delay(100);
1038 timeout--;
1039 }
1040
1041 if (!timeout) {
1042 DEBUGOUT("Master requests are pending.\n");
1043 return -IGC_ERR_MASTER_REQUESTS_PENDING;
1044 }
1045
1046 return IGC_SUCCESS;
1047 }
1048