1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2001-2024, Intel Corporation
5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate)
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "if_igc.h"
32 #include <sys/sbuf.h>
33 #include <machine/_inttypes.h>
34
35 #ifdef RSS
36 #include <net/rss_config.h>
37 #include <netinet/in_rss.h>
38 #endif
39
40 /*********************************************************************
41 * PCI Device ID Table
42 *
43 * Used by probe to select devices to load on
44 * Last entry must be all 0s
45 *
46 * { Vendor ID, Device ID, String }
47 *********************************************************************/
48
49 static const pci_vendor_info_t igc_vendor_info_array[] =
50 {
51 /* Intel(R) PRO/1000 Network Connection - igc */
52 PVID(0x8086, IGC_DEV_ID_I225_LM,
53 "Intel(R) Ethernet Controller I225-LM"),
54 PVID(0x8086, IGC_DEV_ID_I225_V,
55 "Intel(R) Ethernet Controller I225-V"),
56 PVID(0x8086, IGC_DEV_ID_I225_K,
57 "Intel(R) Ethernet Controller I225-K"),
58 PVID(0x8086, IGC_DEV_ID_I225_I,
59 "Intel(R) Ethernet Controller I225-IT"),
60 PVID(0x8086, IGC_DEV_ID_I220_V,
61 "Intel(R) Ethernet Controller I220-V"),
62 PVID(0x8086, IGC_DEV_ID_I225_K2,
63 "Intel(R) Ethernet Controller I225-K(2)"),
64 PVID(0x8086, IGC_DEV_ID_I225_LMVP,
65 "Intel(R) Ethernet Controller I225-LMvP(2)"),
66 PVID(0x8086, IGC_DEV_ID_I226_K,
67 "Intel(R) Ethernet Controller I226-K"),
68 PVID(0x8086, IGC_DEV_ID_I226_LMVP,
69 "Intel(R) Ethernet Controller I226-LMvP"),
70 PVID(0x8086, IGC_DEV_ID_I225_IT,
71 "Intel(R) Ethernet Controller I225-IT(2)"),
72 PVID(0x8086, IGC_DEV_ID_I226_LM,
73 "Intel(R) Ethernet Controller I226-LM"),
74 PVID(0x8086, IGC_DEV_ID_I226_V,
75 "Intel(R) Ethernet Controller I226-V"),
76 PVID(0x8086, IGC_DEV_ID_I226_IT,
77 "Intel(R) Ethernet Controller I226-IT"),
78 PVID(0x8086, IGC_DEV_ID_I221_V,
79 "Intel(R) Ethernet Controller I221-V"),
80 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM,
81 "Intel(R) Ethernet Controller I226(blankNVM)"),
82 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM,
83 "Intel(R) Ethernet Controller I225(blankNVM)"),
84 /* required last entry */
85 PVID_END
86 };
87
88 /*********************************************************************
89 * Function prototypes
90 *********************************************************************/
91 static void *igc_register(device_t);
92 static int igc_if_attach_pre(if_ctx_t);
93 static int igc_if_attach_post(if_ctx_t);
94 static int igc_if_detach(if_ctx_t);
95 static int igc_if_shutdown(if_ctx_t);
96 static int igc_if_suspend(if_ctx_t);
97 static int igc_if_resume(if_ctx_t);
98
99 static int igc_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
100 int);
101 static int igc_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
102 int);
103 static void igc_if_queues_free(if_ctx_t);
104
105 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter);
106 static void igc_if_init(if_ctx_t);
107 static void igc_if_stop(if_ctx_t);
108 static void igc_if_media_status(if_ctx_t, struct ifmediareq *);
109 static int igc_if_media_change(if_ctx_t);
110 static int igc_if_mtu_set(if_ctx_t, uint32_t);
111 static void igc_if_timer(if_ctx_t, uint16_t);
112 static void igc_if_watchdog_reset(if_ctx_t);
113 static bool igc_if_needs_restart(if_ctx_t, enum iflib_restart_event);
114
115 static void igc_identify_hardware(if_ctx_t);
116 static int igc_allocate_pci_resources(if_ctx_t);
117 static void igc_free_pci_resources(if_ctx_t);
118 static void igc_reset(if_ctx_t);
119 static int igc_setup_interface(if_ctx_t);
120 static int igc_setup_msix(if_ctx_t);
121
122 static void igc_initialize_transmit_unit(if_ctx_t);
123 static void igc_initialize_receive_unit(if_ctx_t);
124
125 static void igc_if_intr_enable(if_ctx_t);
126 static void igc_if_intr_disable(if_ctx_t);
127 static int igc_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
128 static int igc_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
129 static void igc_if_multi_set(if_ctx_t);
130 static void igc_if_update_admin_status(if_ctx_t);
131 static void igc_if_debug(if_ctx_t);
132 static void igc_update_stats_counters(struct igc_softc *);
133 static void igc_add_hw_stats(struct igc_softc *);
134 static int igc_if_set_promisc(if_ctx_t, int);
135 static void igc_setup_vlan_hw_support(if_ctx_t);
136 static void igc_fw_version(struct igc_softc *);
137 static void igc_sbuf_fw_version(struct igc_fw_version *, struct sbuf *);
138 static void igc_print_fw_version(struct igc_softc *);
139 static int igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS);
140 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS);
141 static void igc_print_nvm_info(struct igc_softc *);
142 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
143 static int igc_get_rs(SYSCTL_HANDLER_ARGS);
144 static void igc_print_debug_info(struct igc_softc *);
145 static int igc_is_valid_ether_addr(u8 *);
146 static void igc_neweitr(struct igc_softc *, struct igc_rx_queue *,
147 struct tx_ring *, struct rx_ring *);
148 static int igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS);
149 /* Management and WOL Support */
150 static void igc_get_hw_control(struct igc_softc *);
151 static void igc_release_hw_control(struct igc_softc *);
152 static void igc_get_wakeup(if_ctx_t);
153 static void igc_enable_wakeup(if_ctx_t);
154
155 int igc_intr(void *);
156
157 /* MSI-X handlers */
158 static int igc_if_msix_intr_assign(if_ctx_t, int);
159 static int igc_msix_link(void *);
160 static void igc_handle_link(void *context);
161
162 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS);
163 static int igc_sysctl_dmac(SYSCTL_HANDLER_ARGS);
164 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS);
165
166 static int igc_get_regs(SYSCTL_HANDLER_ARGS);
167
168 static void igc_configure_queues(struct igc_softc *);
169
170
171 /*********************************************************************
172 * FreeBSD Device Interface Entry Points
173 *********************************************************************/
174 static device_method_t igc_methods[] = {
175 /* Device interface */
176 DEVMETHOD(device_register, igc_register),
177 DEVMETHOD(device_probe, iflib_device_probe),
178 DEVMETHOD(device_attach, iflib_device_attach),
179 DEVMETHOD(device_detach, iflib_device_detach),
180 DEVMETHOD(device_shutdown, iflib_device_shutdown),
181 DEVMETHOD(device_suspend, iflib_device_suspend),
182 DEVMETHOD(device_resume, iflib_device_resume),
183 DEVMETHOD_END
184 };
185
186 static driver_t igc_driver = {
187 "igc", igc_methods, sizeof(struct igc_softc),
188 };
189
190 DRIVER_MODULE(igc, pci, igc_driver, 0, 0);
191
192 MODULE_DEPEND(igc, pci, 1, 1, 1);
193 MODULE_DEPEND(igc, ether, 1, 1, 1);
194 MODULE_DEPEND(igc, iflib, 1, 1, 1);
195
196 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array);
197
198 static device_method_t igc_if_methods[] = {
199 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre),
200 DEVMETHOD(ifdi_attach_post, igc_if_attach_post),
201 DEVMETHOD(ifdi_detach, igc_if_detach),
202 DEVMETHOD(ifdi_shutdown, igc_if_shutdown),
203 DEVMETHOD(ifdi_suspend, igc_if_suspend),
204 DEVMETHOD(ifdi_resume, igc_if_resume),
205 DEVMETHOD(ifdi_init, igc_if_init),
206 DEVMETHOD(ifdi_stop, igc_if_stop),
207 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign),
208 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable),
209 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable),
210 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc),
211 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc),
212 DEVMETHOD(ifdi_queues_free, igc_if_queues_free),
213 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status),
214 DEVMETHOD(ifdi_multi_set, igc_if_multi_set),
215 DEVMETHOD(ifdi_media_status, igc_if_media_status),
216 DEVMETHOD(ifdi_media_change, igc_if_media_change),
217 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set),
218 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc),
219 DEVMETHOD(ifdi_timer, igc_if_timer),
220 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset),
221 DEVMETHOD(ifdi_get_counter, igc_if_get_counter),
222 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable),
223 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable),
224 DEVMETHOD(ifdi_debug, igc_if_debug),
225 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart),
226 DEVMETHOD_END
227 };
228
229 static driver_t igc_if_driver = {
230 "igc_if", igc_if_methods, sizeof(struct igc_softc)
231 };
232
233 /*********************************************************************
234 * Tunable default values.
235 *********************************************************************/
236
237 /* Allow common code without TSO */
238 #ifndef CSUM_TSO
239 #define CSUM_TSO 0
240 #endif
241
242 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
243 "igc driver parameters");
244
245 static int igc_disable_crc_stripping = 0;
246 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
247 &igc_disable_crc_stripping, 0, "Disable CRC Stripping");
248
249 static int igc_smart_pwr_down = false;
250 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN,
251 &igc_smart_pwr_down,
252 0, "Set to true to leave smart power down enabled on newer adapters");
253
254 /* Controls whether promiscuous also shows bad packets */
255 static int igc_debug_sbp = false;
256 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0,
257 "Show bad packets in promiscuous mode");
258
259 /* Energy efficient ethernet - default to OFF */
260 static int igc_eee_setting = 1;
261 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0,
262 "Enable Energy Efficient Ethernet");
263
264 /*
265 * AIM: Adaptive Interrupt Moderation
266 * which means that the interrupt rate is varied over time based on the
267 * traffic for that interrupt vector
268 */
269 static int igc_enable_aim = 1;
270 SYSCTL_INT(_hw_igc, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &igc_enable_aim,
271 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)");
272
273 /*
274 ** Tuneable Interrupt rate
275 */
276 static int igc_max_interrupt_rate = IGC_INTS_DEFAULT;
277 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
278 &igc_max_interrupt_rate, 0, "Maximum interrupts per second");
279
280 extern struct if_txrx igc_txrx;
281
282 static struct if_shared_ctx igc_sctx_init = {
283 .isc_magic = IFLIB_MAGIC,
284 .isc_q_align = PAGE_SIZE,
285 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header),
286 .isc_tx_maxsegsize = PAGE_SIZE,
287 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header),
288 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE,
289 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE,
290 .isc_rx_nsegments = 1,
291 .isc_rx_maxsegsize = MJUM9BYTES,
292 .isc_nfl = 1,
293 .isc_nrxqs = 1,
294 .isc_ntxqs = 1,
295 .isc_admin_intrcnt = 1,
296 .isc_vendor_info = igc_vendor_info_array,
297 .isc_driver_version = "1",
298 .isc_driver = &igc_if_driver,
299 .isc_flags =
300 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
301
302 .isc_nrxd_min = {IGC_MIN_RXD},
303 .isc_ntxd_min = {IGC_MIN_TXD},
304 .isc_nrxd_max = {IGC_MAX_RXD},
305 .isc_ntxd_max = {IGC_MAX_TXD},
306 .isc_nrxd_default = {IGC_DEFAULT_RXD},
307 .isc_ntxd_default = {IGC_DEFAULT_TXD},
308 };
309
310 /*****************************************************************
311 *
312 * Dump Registers
313 *
314 ****************************************************************/
315 #define IGC_REGS_LEN 739
316
igc_get_regs(SYSCTL_HANDLER_ARGS)317 static int igc_get_regs(SYSCTL_HANDLER_ARGS)
318 {
319 struct igc_softc *sc = (struct igc_softc *)arg1;
320 struct igc_hw *hw = &sc->hw;
321 struct sbuf *sb;
322 u32 *regs_buff;
323 int rc;
324
325 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK);
326 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32));
327
328 rc = sysctl_wire_old_buffer(req, 0);
329 MPASS(rc == 0);
330 if (rc != 0) {
331 free(regs_buff, M_DEVBUF);
332 return (rc);
333 }
334
335 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req);
336 MPASS(sb != NULL);
337 if (sb == NULL) {
338 free(regs_buff, M_DEVBUF);
339 return (ENOMEM);
340 }
341
342 /* General Registers */
343 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL);
344 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS);
345 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT);
346 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR);
347 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL);
348 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0));
349 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0));
350 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0));
351 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0));
352 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0));
353 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0));
354 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL);
355 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0));
356 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0));
357 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0));
358 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0));
359 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0));
360 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0));
361
362 sbuf_printf(sb, "General Registers\n");
363 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]);
364 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]);
365 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]);
366
367 sbuf_printf(sb, "Interrupt Registers\n");
368 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]);
369
370 sbuf_printf(sb, "RX Registers\n");
371 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]);
372 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]);
373 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]);
374 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]);
375 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]);
376 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]);
377 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]);
378
379 sbuf_printf(sb, "TX Registers\n");
380 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]);
381 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]);
382 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]);
383 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]);
384 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]);
385 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]);
386 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]);
387 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]);
388 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]);
389 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]);
390 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]);
391
392 free(regs_buff, M_DEVBUF);
393
394 #ifdef DUMP_DESCS
395 {
396 if_softc_ctx_t scctx = sc->shared;
397 struct rx_ring *rxr = &rx_que->rxr;
398 struct tx_ring *txr = &tx_que->txr;
399 int ntxd = scctx->isc_ntxd[0];
400 int nrxd = scctx->isc_nrxd[0];
401 int j;
402
403 for (j = 0; j < nrxd; j++) {
404 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
405 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
406 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08"
407 PRIx64 " Error:%d Length:%d\n",
408 j, rxr->rx_base[j].read.buffer_addr, staterr, length);
409 }
410
411 for (j = 0; j < min(ntxd, 256); j++) {
412 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
413
414 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x"
415 "[3]: %08x eop: %d DD=%d\n",
416 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
417 buf->eop != -1 ?
418 txr->tx_base[buf->eop].upper.fields.status &
419 IGC_TXD_STAT_DD : 0);
420
421 }
422 }
423 #endif
424
425 rc = sbuf_finish(sb);
426 sbuf_delete(sb);
427 return(rc);
428 }
429
430 static void *
igc_register(device_t dev)431 igc_register(device_t dev)
432 {
433 return (&igc_sctx_init);
434 }
435
436 static int
igc_set_num_queues(if_ctx_t ctx)437 igc_set_num_queues(if_ctx_t ctx)
438 {
439 int maxqueues;
440
441 maxqueues = 4;
442
443 return (maxqueues);
444 }
445
446 #define IGC_CAPS \
447 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
448 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_TSO4 | IFCAP_LRO | \
449 IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | IFCAP_TSO6
450
451 /*********************************************************************
452 * Device initialization routine
453 *
454 * The attach entry point is called when the driver is being loaded.
455 * This routine identifies the type of hardware, allocates all resources
456 * and initializes the hardware.
457 *
458 * return 0 on success, positive on failure
459 *********************************************************************/
460 static int
igc_if_attach_pre(if_ctx_t ctx)461 igc_if_attach_pre(if_ctx_t ctx)
462 {
463 struct igc_softc *sc;
464 if_softc_ctx_t scctx;
465 device_t dev;
466 struct igc_hw *hw;
467 int error = 0;
468
469 INIT_DEBUGOUT("igc_if_attach_pre: begin");
470 dev = iflib_get_dev(ctx);
471 sc = iflib_get_softc(ctx);
472
473 sc->ctx = sc->osdep.ctx = ctx;
474 sc->dev = sc->osdep.dev = dev;
475 scctx = sc->shared = iflib_get_softc_ctx(ctx);
476 sc->media = iflib_get_media(ctx);
477 hw = &sc->hw;
478
479 /* SYSCTL stuff */
480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
481 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
482 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
483 sc, 0, igc_sysctl_nvm_info, "I", "NVM Information");
484
485 sc->enable_aim = igc_enable_aim;
486 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
487 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
488 OID_AUTO, "enable_aim", CTLFLAG_RW,
489 &sc->enable_aim, 0,
490 "Interrupt Moderation (1=normal, 2=lowlatency)");
491
492 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
493 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
494 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD,
495 sc, 0, igc_sysctl_print_fw_version, "A",
496 "Prints FW/NVM Versions");
497
498 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
499 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
500 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
501 sc, 0, igc_sysctl_debug_info, "I", "Debug Information");
502
503 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
505 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
506 sc, 0, igc_set_flowcntl, "I", "Flow Control");
507
508 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
509 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
510 OID_AUTO, "reg_dump",
511 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
512 igc_get_regs, "A", "Dump Registers");
513
514 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
515 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
516 OID_AUTO, "rs_dump",
517 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
518 igc_get_rs, "I", "Dump RS indexes");
519
520 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
521 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
522 OID_AUTO, "dmac",
523 CTLTYPE_INT | CTLFLAG_RW, sc, 0,
524 igc_sysctl_dmac, "I", "DMA Coalesce");
525
526 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
527 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
528 OID_AUTO, "tso_tcp_flags_mask_first_segment",
529 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
530 sc, 0, igc_sysctl_tso_tcp_flags_mask, "IU",
531 "TSO TCP flags mask for first segment");
532
533 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
534 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
535 OID_AUTO, "tso_tcp_flags_mask_middle_segment",
536 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
537 sc, 1, igc_sysctl_tso_tcp_flags_mask, "IU",
538 "TSO TCP flags mask for middle segment");
539
540 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
542 OID_AUTO, "tso_tcp_flags_mask_last_segment",
543 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
544 sc, 2, igc_sysctl_tso_tcp_flags_mask, "IU",
545 "TSO TCP flags mask for last segment");
546
547 /* Determine hardware and mac info */
548 igc_identify_hardware(ctx);
549
550 scctx->isc_tx_nsegments = IGC_MAX_SCATTER;
551 scctx->isc_nrxqsets_max =
552 scctx->isc_ntxqsets_max = igc_set_num_queues(ctx);
553 if (bootverbose)
554 device_printf(dev, "attach_pre capping queues at %d\n",
555 scctx->isc_ntxqsets_max);
556
557 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
558 sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN);
559 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
560 sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN);
561 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc);
562 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc);
563 scctx->isc_txrx = &igc_txrx;
564 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER;
565 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE;
566 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE;
567 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS;
568 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
569 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP;
570
571 /*
572 ** Some new devices, as with ixgbe, now may
573 ** use a different BAR, so we need to keep
574 ** track of which is used.
575 */
576 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR);
577 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0)
578 scctx->isc_msix_bar += 4;
579
580 /* Setup PCI resources */
581 if (igc_allocate_pci_resources(ctx)) {
582 device_printf(dev, "Allocation of PCI resources failed\n");
583 error = ENXIO;
584 goto err_pci;
585 }
586
587 /* Do Shared Code initialization */
588 error = igc_setup_init_funcs(hw, true);
589 if (error) {
590 device_printf(dev, "Setup of Shared code failed, error %d\n",
591 error);
592 error = ENXIO;
593 goto err_pci;
594 }
595
596 igc_setup_msix(ctx);
597 igc_get_bus_info(hw);
598
599 hw->mac.autoneg = DO_AUTO_NEG;
600 hw->phy.autoneg_wait_to_complete = false;
601 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
602
603 /* Copper options */
604 if (hw->phy.media_type == igc_media_type_copper) {
605 hw->phy.mdix = AUTO_ALL_MODES;
606 }
607
608 /*
609 * Set the frame limits assuming
610 * standard ethernet sized frames.
611 */
612 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
613 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE;
614
615 /* Allocate multicast array memory. */
616 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
617 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
618 if (sc->mta == NULL) {
619 device_printf(dev,
620 "Can not allocate multicast setup array\n");
621 error = ENOMEM;
622 goto err_late;
623 }
624
625 /* Check SOL/IDER usage */
626 if (igc_check_reset_block(hw))
627 device_printf(dev, "PHY reset is blocked"
628 " due to SOL/IDER session.\n");
629
630 /* Sysctl for setting Energy Efficient Ethernet */
631 sc->hw.dev_spec._i225.eee_disable = igc_eee_setting;
632 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
633 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
634 OID_AUTO, "eee_control",
635 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
636 sc, 0, igc_sysctl_eee, "I",
637 "Disable Energy Efficient Ethernet");
638
639 /*
640 ** Start from a known state, this is
641 ** important in reading the nvm and
642 ** mac from that.
643 */
644 igc_reset_hw(hw);
645
646 /* Make sure we have a good EEPROM before we read from it */
647 if (igc_validate_nvm_checksum(hw) < 0) {
648 /*
649 ** Some PCI-E parts fail the first check due to
650 ** the link being in sleep state, call it again,
651 ** if it fails a second time its a real issue.
652 */
653 if (igc_validate_nvm_checksum(hw) < 0) {
654 device_printf(dev,
655 "The EEPROM Checksum Is Not Valid\n");
656 error = EIO;
657 goto err_late;
658 }
659 }
660
661 /* Copy the permanent MAC address out of the EEPROM */
662 if (igc_read_mac_addr(hw) < 0) {
663 device_printf(dev, "EEPROM read error while reading MAC"
664 " address\n");
665 error = EIO;
666 goto err_late;
667 }
668
669 if (!igc_is_valid_ether_addr(hw->mac.addr)) {
670 device_printf(dev, "Invalid MAC address\n");
671 error = EIO;
672 goto err_late;
673 }
674
675 /* Save the EEPROM/NVM versions */
676 igc_fw_version(sc);
677
678 igc_print_fw_version(sc);
679
680 /*
681 * Get Wake-on-Lan and Management info for later use
682 */
683 igc_get_wakeup(ctx);
684
685 /* Enable only WOL MAGIC by default */
686 scctx->isc_capenable &= ~IFCAP_WOL;
687 if (sc->wol != 0)
688 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
689
690 iflib_set_mac(ctx, hw->mac.addr);
691
692 return (0);
693
694 err_late:
695 igc_release_hw_control(sc);
696 err_pci:
697 igc_free_pci_resources(ctx);
698 free(sc->mta, M_DEVBUF);
699
700 return (error);
701 }
702
703 static int
igc_if_attach_post(if_ctx_t ctx)704 igc_if_attach_post(if_ctx_t ctx)
705 {
706 struct igc_softc *sc = iflib_get_softc(ctx);
707 struct igc_hw *hw = &sc->hw;
708 int error = 0;
709
710 /* Setup OS specific network interface */
711 error = igc_setup_interface(ctx);
712 if (error != 0) {
713 goto err_late;
714 }
715
716 igc_reset(ctx);
717
718 /* Initialize statistics */
719 igc_update_stats_counters(sc);
720 hw->mac.get_link_status = true;
721 igc_if_update_admin_status(ctx);
722 igc_add_hw_stats(sc);
723
724 /* the driver can now take control from firmware */
725 igc_get_hw_control(sc);
726
727 INIT_DEBUGOUT("igc_if_attach_post: end");
728
729 return (error);
730
731 err_late:
732 igc_release_hw_control(sc);
733 igc_free_pci_resources(ctx);
734 igc_if_queues_free(ctx);
735 free(sc->mta, M_DEVBUF);
736
737 return (error);
738 }
739
740 /*********************************************************************
741 * Device removal routine
742 *
743 * The detach entry point is called when the driver is being removed.
744 * This routine stops the adapter and deallocates all the resources
745 * that were allocated for driver operation.
746 *
747 * return 0 on success, positive on failure
748 *********************************************************************/
749 static int
igc_if_detach(if_ctx_t ctx)750 igc_if_detach(if_ctx_t ctx)
751 {
752 struct igc_softc *sc = iflib_get_softc(ctx);
753
754 INIT_DEBUGOUT("igc_if_detach: begin");
755
756 igc_phy_hw_reset(&sc->hw);
757
758 igc_release_hw_control(sc);
759 igc_free_pci_resources(ctx);
760
761 return (0);
762 }
763
764 /*********************************************************************
765 *
766 * Shutdown entry point
767 *
768 **********************************************************************/
769
770 static int
igc_if_shutdown(if_ctx_t ctx)771 igc_if_shutdown(if_ctx_t ctx)
772 {
773 return igc_if_suspend(ctx);
774 }
775
776 /*
777 * Suspend/resume device methods.
778 */
779 static int
igc_if_suspend(if_ctx_t ctx)780 igc_if_suspend(if_ctx_t ctx)
781 {
782 struct igc_softc *sc = iflib_get_softc(ctx);
783
784 igc_release_hw_control(sc);
785 igc_enable_wakeup(ctx);
786 return (0);
787 }
788
789 static int
igc_if_resume(if_ctx_t ctx)790 igc_if_resume(if_ctx_t ctx)
791 {
792 igc_if_init(ctx);
793
794 return(0);
795 }
796
797 static int
igc_if_mtu_set(if_ctx_t ctx,uint32_t mtu)798 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
799 {
800 int max_frame_size;
801 struct igc_softc *sc = iflib_get_softc(ctx);
802 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx);
803
804 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
805
806 /* 9K Jumbo Frame size */
807 max_frame_size = 9234;
808
809 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
810 return (EINVAL);
811 }
812
813 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
814 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
815 return (0);
816 }
817
818 /*********************************************************************
819 * Init entry point
820 *
821 * This routine is used in two ways. It is used by the stack as
822 * init entry point in network interface structure. It is also used
823 * by the driver as a hw/sw initialization routine to get to a
824 * consistent state.
825 *
826 **********************************************************************/
827 static void
igc_if_init(if_ctx_t ctx)828 igc_if_init(if_ctx_t ctx)
829 {
830 struct igc_softc *sc = iflib_get_softc(ctx);
831 if_softc_ctx_t scctx = sc->shared;
832 if_t ifp = iflib_get_ifp(ctx);
833 struct igc_tx_queue *tx_que;
834 int i;
835
836 INIT_DEBUGOUT("igc_if_init: begin");
837
838 /* Get the latest mac address, User can use a LAA */
839 bcopy(if_getlladdr(ifp), sc->hw.mac.addr,
840 ETHER_ADDR_LEN);
841
842 /* Put the address into the Receive Address Array */
843 igc_rar_set(&sc->hw, sc->hw.mac.addr, 0);
844
845 /* Initialize the hardware */
846 igc_reset(ctx);
847 igc_if_update_admin_status(ctx);
848
849 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues;
850 i++, tx_que++) {
851 struct tx_ring *txr = &tx_que->txr;
852
853 txr->tx_rs_cidx = txr->tx_rs_pidx;
854
855 /* Initialize the last processed descriptor to be the end of
856 * the ring, rather than the start, so that we avoid an
857 * off-by-one error when calculating how many descriptors are
858 * done in the credits_update function.
859 */
860 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
861 }
862
863 /* Setup VLAN support, basic and offload if available */
864 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN);
865
866 /* Prepare transmit descriptors and buffers */
867 igc_initialize_transmit_unit(ctx);
868
869 /* Setup Multicast table */
870 igc_if_multi_set(ctx);
871
872 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
873 igc_initialize_receive_unit(ctx);
874
875 /* Set up VLAN support */
876 igc_setup_vlan_hw_support(ctx);
877
878 /* Don't lose promiscuous settings */
879 igc_if_set_promisc(ctx, if_getflags(ifp));
880 igc_clear_hw_cntrs_base_generic(&sc->hw);
881
882 if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
883 igc_configure_queues(sc);
884
885 /* this clears any pending interrupts */
886 IGC_READ_REG(&sc->hw, IGC_ICR);
887 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC);
888
889 /* the driver can now take control from firmware */
890 igc_get_hw_control(sc);
891
892 /* Set Energy Efficient Ethernet */
893 igc_set_eee_i225(&sc->hw, true, true, true);
894 }
895
896 enum eitr_latency_target {
897 eitr_latency_disabled = 0,
898 eitr_latency_lowest = 1,
899 eitr_latency_low = 2,
900 eitr_latency_bulk = 3
901 };
902 /*********************************************************************
903 *
904 * Helper to calculate next EITR value for AIM
905 *
906 *********************************************************************/
907 static void
igc_neweitr(struct igc_softc * sc,struct igc_rx_queue * que,struct tx_ring * txr,struct rx_ring * rxr)908 igc_neweitr(struct igc_softc *sc, struct igc_rx_queue *que,
909 struct tx_ring *txr, struct rx_ring *rxr)
910 {
911 struct igc_hw *hw = &sc->hw;
912 u32 neweitr;
913 u32 bytes;
914 u32 bytes_packets;
915 u32 packets;
916 u8 nextlatency;
917
918 /* Idle, do nothing */
919 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0))
920 return;
921
922 neweitr = 0;
923
924 if (sc->enable_aim) {
925 nextlatency = rxr->rx_nextlatency;
926
927 /* Use half default (4K) ITR if sub-gig */
928 if (sc->link_speed < 1000) {
929 neweitr = IGC_INTS_4K;
930 goto igc_set_next_eitr;
931 }
932 /* Want at least enough packet buffer for two frames to AIM */
933 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) {
934 neweitr = igc_max_interrupt_rate;
935 sc->enable_aim = 0;
936 goto igc_set_next_eitr;
937 }
938
939 /* Get largest values from the associated tx and rx ring */
940 if (txr->tx_bytes && txr->tx_packets) {
941 bytes = txr->tx_bytes;
942 bytes_packets = txr->tx_bytes/txr->tx_packets;
943 packets = txr->tx_packets;
944 }
945 if (rxr->rx_bytes && rxr->rx_packets) {
946 bytes = max(bytes, rxr->rx_bytes);
947 bytes_packets = max(bytes_packets,
948 rxr->rx_bytes/rxr->rx_packets);
949 packets = max(packets, rxr->rx_packets);
950 }
951
952 /* Latency state machine */
953 switch (nextlatency) {
954 case eitr_latency_disabled: /* Bootstrapping */
955 nextlatency = eitr_latency_low;
956 break;
957 case eitr_latency_lowest: /* 70k ints/s */
958 /* TSO and jumbo frames */
959 if (bytes_packets > 8000)
960 nextlatency = eitr_latency_bulk;
961 else if ((packets < 5) && (bytes > 512))
962 nextlatency = eitr_latency_low;
963 break;
964 case eitr_latency_low: /* 20k ints/s */
965 if (bytes > 10000) {
966 /* Handle TSO */
967 if (bytes_packets > 8000)
968 nextlatency = eitr_latency_bulk;
969 else if ((packets < 10) ||
970 (bytes_packets > 1200))
971 nextlatency = eitr_latency_bulk;
972 else if (packets > 35)
973 nextlatency = eitr_latency_lowest;
974 } else if (bytes_packets > 2000) {
975 nextlatency = eitr_latency_bulk;
976 } else if (packets < 3 && bytes < 512) {
977 nextlatency = eitr_latency_lowest;
978 }
979 break;
980 case eitr_latency_bulk: /* 4k ints/s */
981 if (bytes > 25000) {
982 if (packets > 35)
983 nextlatency = eitr_latency_low;
984 } else if (bytes < 1500)
985 nextlatency = eitr_latency_low;
986 break;
987 default:
988 nextlatency = eitr_latency_low;
989 device_printf(sc->dev,
990 "Unexpected neweitr transition %d\n",
991 nextlatency);
992 break;
993 }
994
995 /* Trim itr_latency_lowest for default AIM setting */
996 if (sc->enable_aim == 1 && nextlatency == eitr_latency_lowest)
997 nextlatency = eitr_latency_low;
998
999 /* Request new latency */
1000 rxr->rx_nextlatency = nextlatency;
1001 } else {
1002 /* We may have toggled to AIM disabled */
1003 nextlatency = eitr_latency_disabled;
1004 rxr->rx_nextlatency = nextlatency;
1005 }
1006
1007 /* ITR state machine */
1008 switch(nextlatency) {
1009 case eitr_latency_lowest:
1010 neweitr = IGC_INTS_70K;
1011 break;
1012 case eitr_latency_low:
1013 neweitr = IGC_INTS_20K;
1014 break;
1015 case eitr_latency_bulk:
1016 neweitr = IGC_INTS_4K;
1017 break;
1018 case eitr_latency_disabled:
1019 default:
1020 neweitr = igc_max_interrupt_rate;
1021 break;
1022 }
1023
1024 igc_set_next_eitr:
1025 neweitr = IGC_INTS_TO_EITR(neweitr);
1026
1027 neweitr |= IGC_EITR_CNT_IGNR;
1028
1029 if (neweitr != que->eitr_setting) {
1030 que->eitr_setting = neweitr;
1031 IGC_WRITE_REG(hw, IGC_EITR(que->msix), que->eitr_setting);
1032 }
1033 }
1034
1035 /*********************************************************************
1036 *
1037 * Fast Legacy/MSI Combined Interrupt Service routine
1038 *
1039 *********************************************************************/
1040 int
igc_intr(void * arg)1041 igc_intr(void *arg)
1042 {
1043 struct igc_softc *sc = arg;
1044 struct igc_hw *hw = &sc->hw;
1045 struct igc_rx_queue *que = &sc->rx_queues[0];
1046 struct tx_ring *txr = &sc->tx_queues[0].txr;
1047 struct rx_ring *rxr = &que->rxr;
1048 if_ctx_t ctx = sc->ctx;
1049 u32 reg_icr;
1050
1051 reg_icr = IGC_READ_REG(hw, IGC_ICR);
1052
1053 /* Hot eject? */
1054 if (reg_icr == 0xffffffff)
1055 return FILTER_STRAY;
1056
1057 /* Definitely not our interrupt. */
1058 if (reg_icr == 0x0)
1059 return FILTER_STRAY;
1060
1061 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0)
1062 return FILTER_STRAY;
1063
1064 /*
1065 * Only MSI-X interrupts have one-shot behavior by taking advantage
1066 * of the EIAC register. Thus, explicitly disable interrupts. This
1067 * also works around the MSI message reordering errata on certain
1068 * systems.
1069 */
1070 IFDI_INTR_DISABLE(ctx);
1071
1072 /* Link status change */
1073 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC))
1074 igc_handle_link(ctx);
1075
1076 if (reg_icr & IGC_ICR_RXO)
1077 sc->rx_overruns++;
1078
1079 igc_neweitr(sc, que, txr, rxr);
1080
1081 /* Reset state */
1082 txr->tx_bytes = 0;
1083 txr->tx_packets = 0;
1084 rxr->rx_bytes = 0;
1085 rxr->rx_packets = 0;
1086
1087 return (FILTER_SCHEDULE_THREAD);
1088 }
1089
1090 static int
igc_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t rxqid)1091 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
1092 {
1093 struct igc_softc *sc = iflib_get_softc(ctx);
1094 struct igc_rx_queue *rxq = &sc->rx_queues[rxqid];
1095
1096 IGC_WRITE_REG(&sc->hw, IGC_EIMS, rxq->eims);
1097 return (0);
1098 }
1099
1100 static int
igc_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t txqid)1101 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid)
1102 {
1103 struct igc_softc *sc = iflib_get_softc(ctx);
1104 struct igc_tx_queue *txq = &sc->tx_queues[txqid];
1105
1106 IGC_WRITE_REG(&sc->hw, IGC_EIMS, txq->eims);
1107 return (0);
1108 }
1109
1110 /*********************************************************************
1111 *
1112 * MSI-X RX Interrupt Service routine
1113 *
1114 **********************************************************************/
1115 static int
igc_msix_que(void * arg)1116 igc_msix_que(void *arg)
1117 {
1118 struct igc_rx_queue *que = arg;
1119 struct igc_softc *sc = que->sc;
1120 struct tx_ring *txr = &sc->tx_queues[que->msix].txr;
1121 struct rx_ring *rxr = &que->rxr;
1122
1123 ++que->irqs;
1124
1125 igc_neweitr(sc, que, txr, rxr);
1126
1127 /* Reset state */
1128 txr->tx_bytes = 0;
1129 txr->tx_packets = 0;
1130 rxr->rx_bytes = 0;
1131 rxr->rx_packets = 0;
1132
1133 return (FILTER_SCHEDULE_THREAD);
1134 }
1135
1136 /*********************************************************************
1137 *
1138 * MSI-X Link Fast Interrupt Service routine
1139 *
1140 **********************************************************************/
1141 static int
igc_msix_link(void * arg)1142 igc_msix_link(void *arg)
1143 {
1144 struct igc_softc *sc = arg;
1145 u32 reg_icr;
1146
1147 ++sc->link_irq;
1148 MPASS(sc->hw.back != NULL);
1149 reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR);
1150
1151 if (reg_icr & IGC_ICR_RXO)
1152 sc->rx_overruns++;
1153
1154 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) {
1155 igc_handle_link(sc->ctx);
1156 }
1157
1158 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC);
1159 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->link_mask);
1160
1161 return (FILTER_HANDLED);
1162 }
1163
1164 static void
igc_handle_link(void * context)1165 igc_handle_link(void *context)
1166 {
1167 if_ctx_t ctx = context;
1168 struct igc_softc *sc = iflib_get_softc(ctx);
1169
1170 sc->hw.mac.get_link_status = true;
1171 iflib_admin_intr_deferred(ctx);
1172 }
1173
1174 /*********************************************************************
1175 *
1176 * Media Ioctl callback
1177 *
1178 * This routine is called whenever the user queries the status of
1179 * the interface using ifconfig.
1180 *
1181 **********************************************************************/
1182 static void
igc_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)1183 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
1184 {
1185 struct igc_softc *sc = iflib_get_softc(ctx);
1186
1187 INIT_DEBUGOUT("igc_if_media_status: begin");
1188
1189 iflib_admin_intr_deferred(ctx);
1190
1191 ifmr->ifm_status = IFM_AVALID;
1192 ifmr->ifm_active = IFM_ETHER;
1193
1194 if (!sc->link_active) {
1195 return;
1196 }
1197
1198 ifmr->ifm_status |= IFM_ACTIVE;
1199
1200 switch (sc->link_speed) {
1201 case 10:
1202 ifmr->ifm_active |= IFM_10_T;
1203 break;
1204 case 100:
1205 ifmr->ifm_active |= IFM_100_TX;
1206 break;
1207 case 1000:
1208 ifmr->ifm_active |= IFM_1000_T;
1209 break;
1210 case 2500:
1211 ifmr->ifm_active |= IFM_2500_T;
1212 break;
1213 }
1214
1215 if (sc->link_duplex == FULL_DUPLEX)
1216 ifmr->ifm_active |= IFM_FDX;
1217 else
1218 ifmr->ifm_active |= IFM_HDX;
1219 }
1220
1221 /*********************************************************************
1222 *
1223 * Media Ioctl callback
1224 *
1225 * This routine is called when the user changes speed/duplex using
1226 * media/mediopt option with ifconfig.
1227 *
1228 **********************************************************************/
1229 static int
igc_if_media_change(if_ctx_t ctx)1230 igc_if_media_change(if_ctx_t ctx)
1231 {
1232 struct igc_softc *sc = iflib_get_softc(ctx);
1233 struct ifmedia *ifm = iflib_get_media(ctx);
1234
1235 INIT_DEBUGOUT("igc_if_media_change: begin");
1236
1237 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1238 return (EINVAL);
1239
1240 sc->hw.mac.autoneg = DO_AUTO_NEG;
1241
1242 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1243 case IFM_AUTO:
1244 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1245 break;
1246 case IFM_2500_T:
1247 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL;
1248 break;
1249 case IFM_1000_T:
1250 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1251 break;
1252 case IFM_100_TX:
1253 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1254 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;
1255 else
1256 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;
1257 break;
1258 case IFM_10_T:
1259 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1260 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;
1261 else
1262 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;
1263 break;
1264 default:
1265 device_printf(sc->dev, "Unsupported media type\n");
1266 }
1267
1268 igc_if_init(ctx);
1269
1270 return (0);
1271 }
1272
1273 static int
igc_if_set_promisc(if_ctx_t ctx,int flags)1274 igc_if_set_promisc(if_ctx_t ctx, int flags)
1275 {
1276 struct igc_softc *sc = iflib_get_softc(ctx);
1277 if_t ifp = iflib_get_ifp(ctx);
1278 u32 reg_rctl;
1279 int mcnt = 0;
1280
1281 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL);
1282 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE);
1283 if (flags & IFF_ALLMULTI)
1284 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1285 else
1286 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
1287
1288 /* Don't disable if in MAX groups */
1289 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1290 reg_rctl &= (~IGC_RCTL_MPE);
1291 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1292
1293 if (flags & IFF_PROMISC) {
1294 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE);
1295 /* Turn this on if you want to see bad packets */
1296 if (igc_debug_sbp)
1297 reg_rctl |= IGC_RCTL_SBP;
1298 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1299 } else if (flags & IFF_ALLMULTI) {
1300 reg_rctl |= IGC_RCTL_MPE;
1301 reg_rctl &= ~IGC_RCTL_UPE;
1302 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1303 }
1304 return (0);
1305 }
1306
1307 static u_int
igc_copy_maddr(void * arg,struct sockaddr_dl * sdl,u_int idx)1308 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx)
1309 {
1310 u8 *mta = arg;
1311
1312 if (idx == MAX_NUM_MULTICAST_ADDRESSES)
1313 return (0);
1314
1315 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1316
1317 return (1);
1318 }
1319
1320 /*********************************************************************
1321 * Multicast Update
1322 *
1323 * This routine is called whenever multicast address list is updated.
1324 *
1325 **********************************************************************/
1326
1327 static void
igc_if_multi_set(if_ctx_t ctx)1328 igc_if_multi_set(if_ctx_t ctx)
1329 {
1330 struct igc_softc *sc = iflib_get_softc(ctx);
1331 if_t ifp = iflib_get_ifp(ctx);
1332 u8 *mta; /* Multicast array memory */
1333 u32 reg_rctl = 0;
1334 int mcnt = 0;
1335
1336 IOCTL_DEBUGOUT("igc_set_multi: begin");
1337
1338 mta = sc->mta;
1339 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1340
1341 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta);
1342
1343 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL);
1344
1345 if (if_getflags(ifp) & IFF_PROMISC) {
1346 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE);
1347 /* Turn this on if you want to see bad packets */
1348 if (igc_debug_sbp)
1349 reg_rctl |= IGC_RCTL_SBP;
1350 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES ||
1351 if_getflags(ifp) & IFF_ALLMULTI) {
1352 reg_rctl |= IGC_RCTL_MPE;
1353 reg_rctl &= ~IGC_RCTL_UPE;
1354 } else
1355 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE);
1356
1357 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
1358 igc_update_mc_addr_list(&sc->hw, mta, mcnt);
1359
1360 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1361 }
1362
1363 /*********************************************************************
1364 * Timer routine
1365 *
1366 * This routine schedules igc_if_update_admin_status() to check for
1367 * link status and to gather statistics as well as to perform some
1368 * controller-specific hardware patting.
1369 *
1370 **********************************************************************/
1371 static void
igc_if_timer(if_ctx_t ctx,uint16_t qid)1372 igc_if_timer(if_ctx_t ctx, uint16_t qid)
1373 {
1374
1375 if (qid != 0)
1376 return;
1377
1378 iflib_admin_intr_deferred(ctx);
1379 }
1380
1381 static void
igc_if_update_admin_status(if_ctx_t ctx)1382 igc_if_update_admin_status(if_ctx_t ctx)
1383 {
1384 struct igc_softc *sc = iflib_get_softc(ctx);
1385 struct igc_hw *hw = &sc->hw;
1386 device_t dev = iflib_get_dev(ctx);
1387 u32 link_check, thstat, ctrl;
1388
1389 link_check = thstat = ctrl = 0;
1390 /* Get the cached link value or read phy for real */
1391 switch (hw->phy.media_type) {
1392 case igc_media_type_copper:
1393 if (hw->mac.get_link_status == true) {
1394 /* Do the work to read phy */
1395 igc_check_for_link(hw);
1396 link_check = !hw->mac.get_link_status;
1397 } else
1398 link_check = true;
1399 break;
1400 case igc_media_type_unknown:
1401 igc_check_for_link(hw);
1402 link_check = !hw->mac.get_link_status;
1403 /* FALLTHROUGH */
1404 default:
1405 break;
1406 }
1407
1408 /* Now check for a transition */
1409 if (link_check && (sc->link_active == 0)) {
1410 igc_get_speed_and_duplex(hw, &sc->link_speed,
1411 &sc->link_duplex);
1412 if (bootverbose)
1413 device_printf(dev, "Link is up %d Mbps %s\n",
1414 sc->link_speed,
1415 ((sc->link_duplex == FULL_DUPLEX) ?
1416 "Full Duplex" : "Half Duplex"));
1417 sc->link_active = 1;
1418 iflib_link_state_change(ctx, LINK_STATE_UP,
1419 IF_Mbps(sc->link_speed));
1420 } else if (!link_check && (sc->link_active == 1)) {
1421 sc->link_speed = 0;
1422 sc->link_duplex = 0;
1423 sc->link_active = 0;
1424 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
1425 }
1426 igc_update_stats_counters(sc);
1427 }
1428
1429 static void
igc_if_watchdog_reset(if_ctx_t ctx)1430 igc_if_watchdog_reset(if_ctx_t ctx)
1431 {
1432 struct igc_softc *sc = iflib_get_softc(ctx);
1433
1434 /*
1435 * Just count the event; iflib(4) will already trigger a
1436 * sufficient reset of the controller.
1437 */
1438 sc->watchdog_events++;
1439 }
1440
1441 /*********************************************************************
1442 *
1443 * This routine disables all traffic on the adapter by issuing a
1444 * global reset on the MAC.
1445 *
1446 **********************************************************************/
1447 static void
igc_if_stop(if_ctx_t ctx)1448 igc_if_stop(if_ctx_t ctx)
1449 {
1450 struct igc_softc *sc = iflib_get_softc(ctx);
1451
1452 INIT_DEBUGOUT("igc_if_stop: begin");
1453
1454 igc_reset_hw(&sc->hw);
1455 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0);
1456 }
1457
1458 /*********************************************************************
1459 *
1460 * Determine hardware revision.
1461 *
1462 **********************************************************************/
1463 static void
igc_identify_hardware(if_ctx_t ctx)1464 igc_identify_hardware(if_ctx_t ctx)
1465 {
1466 device_t dev = iflib_get_dev(ctx);
1467 struct igc_softc *sc = iflib_get_softc(ctx);
1468
1469 /* Make sure our PCI config space has the necessary stuff set */
1470 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1471
1472 /* Save off the information about this board */
1473 sc->hw.vendor_id = pci_get_vendor(dev);
1474 sc->hw.device_id = pci_get_device(dev);
1475 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
1476 sc->hw.subsystem_vendor_id =
1477 pci_read_config(dev, PCIR_SUBVEND_0, 2);
1478 sc->hw.subsystem_device_id =
1479 pci_read_config(dev, PCIR_SUBDEV_0, 2);
1480
1481 /* Do Shared Code Init and Setup */
1482 if (igc_set_mac_type(&sc->hw)) {
1483 device_printf(dev, "Setup init failure\n");
1484 return;
1485 }
1486 }
1487
1488 static int
igc_allocate_pci_resources(if_ctx_t ctx)1489 igc_allocate_pci_resources(if_ctx_t ctx)
1490 {
1491 struct igc_softc *sc = iflib_get_softc(ctx);
1492 device_t dev = iflib_get_dev(ctx);
1493 int rid;
1494
1495 rid = PCIR_BAR(0);
1496 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1497 &rid, RF_ACTIVE);
1498 if (sc->memory == NULL) {
1499 device_printf(dev,
1500 "Unable to allocate bus resource: memory\n");
1501 return (ENXIO);
1502 }
1503 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
1504 sc->osdep.mem_bus_space_handle =
1505 rman_get_bushandle(sc->memory);
1506 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
1507
1508 sc->hw.back = &sc->osdep;
1509
1510 return (0);
1511 }
1512
1513 /*********************************************************************
1514 *
1515 * Set up the MSI-X Interrupt handlers
1516 *
1517 **********************************************************************/
1518 static int
igc_if_msix_intr_assign(if_ctx_t ctx,int msix)1519 igc_if_msix_intr_assign(if_ctx_t ctx, int msix)
1520 {
1521 struct igc_softc *sc = iflib_get_softc(ctx);
1522 struct igc_rx_queue *rx_que = sc->rx_queues;
1523 struct igc_tx_queue *tx_que = sc->tx_queues;
1524 int error, rid, i, vector = 0, rx_vectors;
1525 char buf[16];
1526
1527 /* First set up ring resources */
1528 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
1529 rid = vector + 1;
1530 snprintf(buf, sizeof(buf), "rxq%d", i);
1531 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
1532 IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf);
1533 if (error) {
1534 device_printf(iflib_get_dev(ctx),
1535 "Failed to allocate que int %d err: %d",
1536 i, error);
1537 sc->rx_num_queues = i + 1;
1538 goto fail;
1539 }
1540
1541 rx_que->msix = vector;
1542
1543 /*
1544 * Set the bit to enable interrupt
1545 * in IGC_IMS -- bits 20 and 21
1546 * are for RX0 and RX1, note this has
1547 * NOTHING to do with the MSI-X vector
1548 */
1549 rx_que->eims = 1 << vector;
1550 }
1551 rx_vectors = vector;
1552
1553 vector = 0;
1554 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) {
1555 snprintf(buf, sizeof(buf), "txq%d", i);
1556 tx_que = &sc->tx_queues[i];
1557 iflib_softirq_alloc_generic(ctx,
1558 &sc->rx_queues[i % sc->rx_num_queues].que_irq,
1559 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
1560
1561 tx_que->msix = (vector % sc->rx_num_queues);
1562
1563 /*
1564 * Set the bit to enable interrupt
1565 * in IGC_IMS -- bits 22 and 23
1566 * are for TX0 and TX1, note this has
1567 * NOTHING to do with the MSI-X vector
1568 */
1569 tx_que->eims = 1 << i;
1570 }
1571
1572 /* Link interrupt */
1573 rid = rx_vectors + 1;
1574 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN,
1575 igc_msix_link, sc, 0, "aq");
1576
1577 if (error) {
1578 device_printf(iflib_get_dev(ctx),
1579 "Failed to register admin handler");
1580 goto fail;
1581 }
1582 sc->linkvec = rx_vectors;
1583 return (0);
1584 fail:
1585 iflib_irq_free(ctx, &sc->irq);
1586 rx_que = sc->rx_queues;
1587 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++)
1588 iflib_irq_free(ctx, &rx_que->que_irq);
1589 return (error);
1590 }
1591
1592 static void
igc_configure_queues(struct igc_softc * sc)1593 igc_configure_queues(struct igc_softc *sc)
1594 {
1595 struct igc_hw *hw = &sc->hw;
1596 struct igc_rx_queue *rx_que;
1597 struct igc_tx_queue *tx_que;
1598 u32 ivar = 0, newitr = 0;
1599
1600 /* First turn on RSS capability */
1601 IGC_WRITE_REG(hw, IGC_GPIE,
1602 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA |
1603 IGC_GPIE_NSICR);
1604
1605 /* Turn on MSI-X */
1606 /* RX entries */
1607 for (int i = 0; i < sc->rx_num_queues; i++) {
1608 u32 index = i >> 1;
1609 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index);
1610 rx_que = &sc->rx_queues[i];
1611 if (i & 1) {
1612 ivar &= 0xFF00FFFF;
1613 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16;
1614 } else {
1615 ivar &= 0xFFFFFF00;
1616 ivar |= rx_que->msix | IGC_IVAR_VALID;
1617 }
1618 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar);
1619 }
1620 /* TX entries */
1621 for (int i = 0; i < sc->tx_num_queues; i++) {
1622 u32 index = i >> 1;
1623 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index);
1624 tx_que = &sc->tx_queues[i];
1625 if (i & 1) {
1626 ivar &= 0x00FFFFFF;
1627 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24;
1628 } else {
1629 ivar &= 0xFFFF00FF;
1630 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8;
1631 }
1632 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar);
1633 sc->que_mask |= tx_que->eims;
1634 }
1635
1636 /* And for the link interrupt */
1637 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8;
1638 sc->link_mask = 1 << sc->linkvec;
1639 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar);
1640
1641 /* Set the starting interrupt rate */
1642 if (igc_max_interrupt_rate > 0)
1643 newitr = IGC_INTS_TO_EITR(igc_max_interrupt_rate);
1644
1645 newitr |= IGC_EITR_CNT_IGNR;
1646
1647 for (int i = 0; i < sc->rx_num_queues; i++) {
1648 rx_que = &sc->rx_queues[i];
1649 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr);
1650 }
1651
1652 return;
1653 }
1654
1655 static void
igc_free_pci_resources(if_ctx_t ctx)1656 igc_free_pci_resources(if_ctx_t ctx)
1657 {
1658 struct igc_softc *sc = iflib_get_softc(ctx);
1659 struct igc_rx_queue *que = sc->rx_queues;
1660 device_t dev = iflib_get_dev(ctx);
1661
1662 /* Release all MSI-X queue resources */
1663 if (sc->intr_type == IFLIB_INTR_MSIX)
1664 iflib_irq_free(ctx, &sc->irq);
1665
1666 for (int i = 0; i < sc->rx_num_queues; i++, que++) {
1667 iflib_irq_free(ctx, &que->que_irq);
1668 }
1669
1670 if (sc->memory != NULL) {
1671 bus_release_resource(dev, SYS_RES_MEMORY,
1672 rman_get_rid(sc->memory), sc->memory);
1673 sc->memory = NULL;
1674 }
1675
1676 if (sc->flash != NULL) {
1677 bus_release_resource(dev, SYS_RES_MEMORY,
1678 rman_get_rid(sc->flash), sc->flash);
1679 sc->flash = NULL;
1680 }
1681
1682 if (sc->ioport != NULL) {
1683 bus_release_resource(dev, SYS_RES_IOPORT,
1684 rman_get_rid(sc->ioport), sc->ioport);
1685 sc->ioport = NULL;
1686 }
1687 }
1688
1689 /* Set up MSI or MSI-X */
1690 static int
igc_setup_msix(if_ctx_t ctx)1691 igc_setup_msix(if_ctx_t ctx)
1692 {
1693 return (0);
1694 }
1695
1696 /*********************************************************************
1697 *
1698 * Initialize the DMA Coalescing feature
1699 *
1700 **********************************************************************/
1701 static void
igc_init_dmac(struct igc_softc * sc,u32 pba)1702 igc_init_dmac(struct igc_softc *sc, u32 pba)
1703 {
1704 device_t dev = sc->dev;
1705 struct igc_hw *hw = &sc->hw;
1706 u32 dmac, reg = ~IGC_DMACR_DMAC_EN;
1707 u16 hwm;
1708 u16 max_frame_size;
1709 int status;
1710
1711 max_frame_size = sc->shared->isc_max_frame_size;
1712
1713 if (sc->dmac == 0) { /* Disabling it */
1714 IGC_WRITE_REG(hw, IGC_DMACR, reg);
1715 return;
1716 } else
1717 device_printf(dev, "DMA Coalescing enabled\n");
1718
1719 /* Set starting threshold */
1720 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0);
1721
1722 hwm = 64 * pba - max_frame_size / 16;
1723 if (hwm < 64 * (pba - 6))
1724 hwm = 64 * (pba - 6);
1725 reg = IGC_READ_REG(hw, IGC_FCRTC);
1726 reg &= ~IGC_FCRTC_RTH_COAL_MASK;
1727 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT)
1728 & IGC_FCRTC_RTH_COAL_MASK);
1729 IGC_WRITE_REG(hw, IGC_FCRTC, reg);
1730
1731 dmac = pba - max_frame_size / 512;
1732 if (dmac < pba - 10)
1733 dmac = pba - 10;
1734 reg = IGC_READ_REG(hw, IGC_DMACR);
1735 reg &= ~IGC_DMACR_DMACTHR_MASK;
1736 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT)
1737 & IGC_DMACR_DMACTHR_MASK);
1738
1739 /* transition to L0x or L1 if available..*/
1740 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK);
1741
1742 /* Check if status is 2.5Gb backplane connection
1743 * before configuration of watchdog timer, which is
1744 * in msec values in 12.8usec intervals
1745 * watchdog timer= msec values in 32usec intervals
1746 * for non 2.5Gb connection
1747 */
1748 status = IGC_READ_REG(hw, IGC_STATUS);
1749 if ((status & IGC_STATUS_2P5_SKU) &&
1750 (!(status & IGC_STATUS_2P5_SKU_OVER)))
1751 reg |= ((sc->dmac * 5) >> 6);
1752 else
1753 reg |= (sc->dmac >> 5);
1754
1755 IGC_WRITE_REG(hw, IGC_DMACR, reg);
1756
1757 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0);
1758
1759 /* Set the interval before transition */
1760 reg = IGC_READ_REG(hw, IGC_DMCTLX);
1761 reg |= IGC_DMCTLX_DCFLUSH_DIS;
1762
1763 /*
1764 ** in 2.5Gb connection, TTLX unit is 0.4 usec
1765 ** which is 0x4*2 = 0xA. But delay is still 4 usec
1766 */
1767 status = IGC_READ_REG(hw, IGC_STATUS);
1768 if ((status & IGC_STATUS_2P5_SKU) &&
1769 (!(status & IGC_STATUS_2P5_SKU_OVER)))
1770 reg |= 0xA;
1771 else
1772 reg |= 0x4;
1773
1774 IGC_WRITE_REG(hw, IGC_DMCTLX, reg);
1775
1776 /* free space in tx packet buffer to wake from DMA coal */
1777 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE -
1778 (2 * max_frame_size)) >> 6);
1779
1780 /* make low power state decision controlled by DMA coal */
1781 reg = IGC_READ_REG(hw, IGC_PCIEMISC);
1782 reg &= ~IGC_PCIEMISC_LX_DECISION;
1783 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg);
1784 }
1785
1786 /*********************************************************************
1787 *
1788 * Initialize the hardware to a configuration as specified by the
1789 * softc structure.
1790 *
1791 **********************************************************************/
1792 static void
igc_reset(if_ctx_t ctx)1793 igc_reset(if_ctx_t ctx)
1794 {
1795 device_t dev = iflib_get_dev(ctx);
1796 struct igc_softc *sc = iflib_get_softc(ctx);
1797 struct igc_hw *hw = &sc->hw;
1798 u32 rx_buffer_size;
1799 u32 pba;
1800
1801 INIT_DEBUGOUT("igc_reset: begin");
1802 /* Let the firmware know the OS is in control */
1803 igc_get_hw_control(sc);
1804
1805 /*
1806 * Packet Buffer Allocation (PBA)
1807 * Writing PBA sets the receive portion of the buffer
1808 * the remainder is used for the transmit buffer.
1809 */
1810 pba = IGC_PBA_34K;
1811
1812 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba);
1813
1814 /*
1815 * These parameters control the automatic generation (Tx) and
1816 * response (Rx) to Ethernet PAUSE frames.
1817 * - High water mark should allow for at least two frames to be
1818 * received after sending an XOFF.
1819 * - Low water mark works best when it is very near the high water
1820 * mark.
1821 * This allows the receiver to restart by sending XON when it has
1822 * drained a bit. Here we use an arbitrary value of 1500 which will
1823 * restart after one full frame is pulled from the buffer. There
1824 * could be several smaller frames in the buffer and if so they will
1825 * not trigger the XON until their total number reduces the buffer
1826 * by 1500.
1827 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1828 */
1829 rx_buffer_size = (pba & 0xffff) << 10;
1830 hw->fc.high_water = rx_buffer_size -
1831 roundup2(sc->hw.mac.max_frame_size, 1024);
1832 /* 16-byte granularity */
1833 hw->fc.low_water = hw->fc.high_water - 16;
1834
1835 if (sc->fc) /* locally set flow control value? */
1836 hw->fc.requested_mode = sc->fc;
1837 else
1838 hw->fc.requested_mode = igc_fc_full;
1839
1840 hw->fc.pause_time = IGC_FC_PAUSE_TIME;
1841
1842 hw->fc.send_xon = true;
1843
1844 /* Issue a global reset */
1845 igc_reset_hw(hw);
1846 IGC_WRITE_REG(hw, IGC_WUC, 0);
1847
1848 /* and a re-init */
1849 if (igc_init_hw(hw) < 0) {
1850 device_printf(dev, "Hardware Initialization Failed\n");
1851 return;
1852 }
1853
1854 /* Setup DMA Coalescing */
1855 igc_init_dmac(sc, pba);
1856
1857 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */
1858 sc->pba = pba;
1859
1860 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN);
1861 igc_get_phy_info(hw);
1862 igc_check_for_link(hw);
1863 }
1864
1865 /*
1866 * Initialise the RSS mapping for NICs that support multiple transmit/
1867 * receive rings.
1868 */
1869
1870 #define RSSKEYLEN 10
1871 static void
igc_initialize_rss_mapping(struct igc_softc * sc)1872 igc_initialize_rss_mapping(struct igc_softc *sc)
1873 {
1874 struct igc_hw *hw = &sc->hw;
1875 int i;
1876 int queue_id;
1877 u32 reta;
1878 u32 rss_key[RSSKEYLEN], mrqc, shift = 0;
1879
1880 /*
1881 * The redirection table controls which destination
1882 * queue each bucket redirects traffic to.
1883 * Each DWORD represents four queues, with the LSB
1884 * being the first queue in the DWORD.
1885 *
1886 * This just allocates buckets to queues using round-robin
1887 * allocation.
1888 *
1889 * NOTE: It Just Happens to line up with the default
1890 * RSS allocation method.
1891 */
1892
1893 /* Warning FM follows */
1894 reta = 0;
1895 for (i = 0; i < 128; i++) {
1896 #ifdef RSS
1897 queue_id = rss_get_indirection_to_bucket(i);
1898 /*
1899 * If we have more queues than buckets, we'll
1900 * end up mapping buckets to a subset of the
1901 * queues.
1902 *
1903 * If we have more buckets than queues, we'll
1904 * end up instead assigning multiple buckets
1905 * to queues.
1906 *
1907 * Both are suboptimal, but we need to handle
1908 * the case so we don't go out of bounds
1909 * indexing arrays and such.
1910 */
1911 queue_id = queue_id % sc->rx_num_queues;
1912 #else
1913 queue_id = (i % sc->rx_num_queues);
1914 #endif
1915 /* Adjust if required */
1916 queue_id = queue_id << shift;
1917
1918 /*
1919 * The low 8 bits are for hash value (n+0);
1920 * The next 8 bits are for hash value (n+1), etc.
1921 */
1922 reta = reta >> 8;
1923 reta = reta | ( ((uint32_t) queue_id) << 24);
1924 if ((i & 3) == 3) {
1925 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta);
1926 reta = 0;
1927 }
1928 }
1929
1930 /* Now fill in hash table */
1931
1932 /*
1933 * MRQC: Multiple Receive Queues Command
1934 * Set queuing to RSS control, number depends on the device.
1935 */
1936 mrqc = IGC_MRQC_ENABLE_RSS_4Q;
1937
1938 #ifdef RSS
1939 /* XXX ew typecasting */
1940 rss_getkey((uint8_t *) &rss_key);
1941 #else
1942 arc4rand(&rss_key, sizeof(rss_key), 0);
1943 #endif
1944 for (i = 0; i < RSSKEYLEN; i++)
1945 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]);
1946
1947 /*
1948 * Configure the RSS fields to hash upon.
1949 */
1950 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 |
1951 IGC_MRQC_RSS_FIELD_IPV4_TCP);
1952 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 |
1953 IGC_MRQC_RSS_FIELD_IPV6_TCP);
1954 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP |
1955 IGC_MRQC_RSS_FIELD_IPV6_UDP);
1956 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX |
1957 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX);
1958
1959 IGC_WRITE_REG(hw, IGC_MRQC, mrqc);
1960 }
1961
1962 /*********************************************************************
1963 *
1964 * Setup networking device structure and register interface media.
1965 *
1966 **********************************************************************/
1967 static int
igc_setup_interface(if_ctx_t ctx)1968 igc_setup_interface(if_ctx_t ctx)
1969 {
1970 if_t ifp = iflib_get_ifp(ctx);
1971 struct igc_softc *sc = iflib_get_softc(ctx);
1972 if_softc_ctx_t scctx = sc->shared;
1973
1974 INIT_DEBUGOUT("igc_setup_interface: begin");
1975
1976 /* Single Queue */
1977 if (sc->tx_num_queues == 1) {
1978 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
1979 if_setsendqready(ifp);
1980 }
1981
1982 /*
1983 * Specify the media types supported by this adapter and register
1984 * callbacks to update media and link information
1985 */
1986 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1987 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1988 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1989 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1990 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1991 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1992 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL);
1993
1994 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1995 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1996 return (0);
1997 }
1998
1999 static int
igc_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int ntxqs,int ntxqsets)2000 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
2001 int ntxqs, int ntxqsets)
2002 {
2003 struct igc_softc *sc = iflib_get_softc(ctx);
2004 if_softc_ctx_t scctx = sc->shared;
2005 int error = IGC_SUCCESS;
2006 struct igc_tx_queue *que;
2007 int i, j;
2008
2009 MPASS(sc->tx_num_queues > 0);
2010 MPASS(sc->tx_num_queues == ntxqsets);
2011
2012 /* First allocate the top level queue structs */
2013 if (!(sc->tx_queues =
2014 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) *
2015 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2016 device_printf(iflib_get_dev(ctx),
2017 "Unable to allocate queue memory\n");
2018 return(ENOMEM);
2019 }
2020
2021 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) {
2022 /* Set up some basics */
2023
2024 struct tx_ring *txr = &que->txr;
2025 txr->sc = que->sc = sc;
2026 que->me = txr->me = i;
2027
2028 /* Allocate report status array */
2029 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) *
2030 scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
2031 device_printf(iflib_get_dev(ctx),
2032 "failed to allocate rs_idxs memory\n");
2033 error = ENOMEM;
2034 goto fail;
2035 }
2036 for (j = 0; j < scctx->isc_ntxd[0]; j++)
2037 txr->tx_rsq[j] = QIDX_INVALID;
2038 /* get virtual and physical address of the hardware queues */
2039 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs];
2040 txr->tx_paddr = paddrs[i*ntxqs];
2041 }
2042
2043 if (bootverbose)
2044 device_printf(iflib_get_dev(ctx),
2045 "allocated for %d tx_queues\n", sc->tx_num_queues);
2046 return (0);
2047 fail:
2048 igc_if_queues_free(ctx);
2049 return (error);
2050 }
2051
2052 static int
igc_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * vaddrs,uint64_t * paddrs,int nrxqs,int nrxqsets)2053 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
2054 int nrxqs, int nrxqsets)
2055 {
2056 struct igc_softc *sc = iflib_get_softc(ctx);
2057 int error = IGC_SUCCESS;
2058 struct igc_rx_queue *que;
2059 int i;
2060
2061 MPASS(sc->rx_num_queues > 0);
2062 MPASS(sc->rx_num_queues == nrxqsets);
2063
2064 /* First allocate the top level queue structs */
2065 if (!(sc->rx_queues =
2066 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) *
2067 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
2068 device_printf(iflib_get_dev(ctx),
2069 "Unable to allocate queue memory\n");
2070 error = ENOMEM;
2071 goto fail;
2072 }
2073
2074 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
2075 /* Set up some basics */
2076 struct rx_ring *rxr = &que->rxr;
2077 rxr->sc = que->sc = sc;
2078 rxr->que = que;
2079 que->me = rxr->me = i;
2080
2081 /* get virtual and physical address of the hardware queues */
2082 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs];
2083 rxr->rx_paddr = paddrs[i*nrxqs];
2084 }
2085
2086 if (bootverbose)
2087 device_printf(iflib_get_dev(ctx),
2088 "allocated for %d rx_queues\n", sc->rx_num_queues);
2089
2090 return (0);
2091 fail:
2092 igc_if_queues_free(ctx);
2093 return (error);
2094 }
2095
2096 static void
igc_if_queues_free(if_ctx_t ctx)2097 igc_if_queues_free(if_ctx_t ctx)
2098 {
2099 struct igc_softc *sc = iflib_get_softc(ctx);
2100 struct igc_tx_queue *tx_que = sc->tx_queues;
2101 struct igc_rx_queue *rx_que = sc->rx_queues;
2102
2103 if (tx_que != NULL) {
2104 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
2105 struct tx_ring *txr = &tx_que->txr;
2106 if (txr->tx_rsq == NULL)
2107 break;
2108
2109 free(txr->tx_rsq, M_DEVBUF);
2110 txr->tx_rsq = NULL;
2111 }
2112 free(sc->tx_queues, M_DEVBUF);
2113 sc->tx_queues = NULL;
2114 }
2115
2116 if (rx_que != NULL) {
2117 free(sc->rx_queues, M_DEVBUF);
2118 sc->rx_queues = NULL;
2119 }
2120
2121 if (sc->mta != NULL) {
2122 free(sc->mta, M_DEVBUF);
2123 }
2124 }
2125
2126 /*********************************************************************
2127 *
2128 * Enable transmit unit.
2129 *
2130 **********************************************************************/
2131 static void
igc_initialize_transmit_unit(if_ctx_t ctx)2132 igc_initialize_transmit_unit(if_ctx_t ctx)
2133 {
2134 struct igc_softc *sc = iflib_get_softc(ctx);
2135 if_softc_ctx_t scctx = sc->shared;
2136 struct igc_tx_queue *que;
2137 struct tx_ring *txr;
2138 struct igc_hw *hw = &sc->hw;
2139 u32 tctl, txdctl = 0;
2140
2141 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin");
2142
2143 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
2144 u64 bus_addr;
2145 caddr_t offp, endp;
2146
2147 que = &sc->tx_queues[i];
2148 txr = &que->txr;
2149 bus_addr = txr->tx_paddr;
2150
2151 /* Clear checksum offload context. */
2152 offp = (caddr_t)&txr->csum_flags;
2153 endp = (caddr_t)(txr + 1);
2154 bzero(offp, endp - offp);
2155
2156 /* Base and Len of TX Ring */
2157 IGC_WRITE_REG(hw, IGC_TDLEN(i),
2158 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc));
2159 IGC_WRITE_REG(hw, IGC_TDBAH(i),
2160 (u32)(bus_addr >> 32));
2161 IGC_WRITE_REG(hw, IGC_TDBAL(i),
2162 (u32)bus_addr);
2163 /* Init the HEAD/TAIL indices */
2164 IGC_WRITE_REG(hw, IGC_TDT(i), 0);
2165 IGC_WRITE_REG(hw, IGC_TDH(i), 0);
2166
2167 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2168 IGC_READ_REG(&sc->hw, IGC_TDBAL(i)),
2169 IGC_READ_REG(&sc->hw, IGC_TDLEN(i)));
2170
2171 txdctl = 0; /* clear txdctl */
2172 txdctl |= 0x1f; /* PTHRESH */
2173 txdctl |= 1 << 8; /* HTHRESH */
2174 txdctl |= 1 << 16;/* WTHRESH */
2175 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2176 txdctl |= IGC_TXDCTL_GRAN;
2177 txdctl |= 1 << 25; /* LWTHRESH */
2178
2179 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl);
2180 }
2181
2182 /* Program the Transmit Control Register */
2183 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL);
2184 tctl &= ~IGC_TCTL_CT;
2185 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN |
2186 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT));
2187
2188 /* This write will effectively turn on the transmit unit. */
2189 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl);
2190 }
2191
2192 /*********************************************************************
2193 *
2194 * Enable receive unit.
2195 *
2196 **********************************************************************/
2197 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1)
2198
2199 static void
igc_initialize_receive_unit(if_ctx_t ctx)2200 igc_initialize_receive_unit(if_ctx_t ctx)
2201 {
2202 struct igc_softc *sc = iflib_get_softc(ctx);
2203 if_softc_ctx_t scctx = sc->shared;
2204 if_t ifp = iflib_get_ifp(ctx);
2205 struct igc_hw *hw = &sc->hw;
2206 struct igc_rx_queue *que;
2207 int i;
2208 u32 psize, rctl, rxcsum, srrctl = 0;
2209
2210 INIT_DEBUGOUT("igc_initialize_receive_units: begin");
2211
2212 /*
2213 * Make sure receives are disabled while setting
2214 * up the descriptor ring
2215 */
2216 rctl = IGC_READ_REG(hw, IGC_RCTL);
2217 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN);
2218
2219 /* Setup the Receive Control Register */
2220 rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
2221 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM |
2222 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF |
2223 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
2224
2225 /* Do not store bad packets */
2226 rctl &= ~IGC_RCTL_SBP;
2227
2228 /* Enable Long Packet receive */
2229 if (if_getmtu(ifp) > ETHERMTU)
2230 rctl |= IGC_RCTL_LPE;
2231 else
2232 rctl &= ~IGC_RCTL_LPE;
2233
2234 /* Strip the CRC */
2235 if (!igc_disable_crc_stripping)
2236 rctl |= IGC_RCTL_SECRC;
2237
2238 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM);
2239 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
2240 rxcsum |= IGC_RXCSUM_CRCOFL;
2241 if (sc->tx_num_queues > 1)
2242 rxcsum |= IGC_RXCSUM_PCSD;
2243 else
2244 rxcsum |= IGC_RXCSUM_IPPCSE;
2245 } else {
2246 if (sc->tx_num_queues > 1)
2247 rxcsum |= IGC_RXCSUM_PCSD;
2248 else
2249 rxcsum &= ~IGC_RXCSUM_TUOFL;
2250 }
2251 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum);
2252
2253 if (sc->rx_num_queues > 1)
2254 igc_initialize_rss_mapping(sc);
2255
2256 if (if_getmtu(ifp) > ETHERMTU) {
2257 psize = scctx->isc_max_frame_size;
2258 /* are we on a vlan? */
2259 if (if_vlantrunkinuse(ifp))
2260 psize += VLAN_TAG_SIZE;
2261 IGC_WRITE_REG(&sc->hw, IGC_RLPML, psize);
2262 }
2263
2264 /* Set maximum packet buffer len */
2265 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
2266 IGC_SRRCTL_BSIZEPKT_SHIFT;
2267 /* srrctl above overrides this but set the register to a sane value */
2268 rctl |= IGC_RCTL_SZ_2048;
2269
2270 /*
2271 * If TX flow control is disabled and there's >1 queue defined,
2272 * enable DROP.
2273 *
2274 * This drops frames rather than hanging the RX MAC for all queues.
2275 */
2276 if ((sc->rx_num_queues > 1) &&
2277 (sc->fc == igc_fc_none ||
2278 sc->fc == igc_fc_rx_pause)) {
2279 srrctl |= IGC_SRRCTL_DROP_EN;
2280 }
2281
2282 /* Setup the Base and Length of the Rx Descriptor Rings */
2283 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
2284 struct rx_ring *rxr = &que->rxr;
2285 u64 bus_addr = rxr->rx_paddr;
2286 u32 rxdctl;
2287
2288 #ifdef notyet
2289 /* Configure for header split? -- ignore for now */
2290 rxr->hdr_split = igc_header_split;
2291 #else
2292 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;
2293 #endif
2294
2295 IGC_WRITE_REG(hw, IGC_RDLEN(i),
2296 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc));
2297 IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32));
2298 IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr);
2299 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl);
2300 /* Setup the Head and Tail Descriptor Pointers */
2301 IGC_WRITE_REG(hw, IGC_RDH(i), 0);
2302 IGC_WRITE_REG(hw, IGC_RDT(i), 0);
2303 /* Enable this Queue */
2304 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i));
2305 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;
2306 rxdctl &= 0xFFF00000;
2307 rxdctl |= IGC_RX_PTHRESH;
2308 rxdctl |= IGC_RX_HTHRESH << 8;
2309 rxdctl |= IGC_RX_WTHRESH << 16;
2310 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl);
2311 }
2312
2313 /* Make sure VLAN Filters are off */
2314 rctl &= ~IGC_RCTL_VFE;
2315
2316 /* Write out the settings */
2317 IGC_WRITE_REG(hw, IGC_RCTL, rctl);
2318
2319 return;
2320 }
2321
2322 static void
igc_setup_vlan_hw_support(if_ctx_t ctx)2323 igc_setup_vlan_hw_support(if_ctx_t ctx)
2324 {
2325 struct igc_softc *sc = iflib_get_softc(ctx);
2326 struct igc_hw *hw = &sc->hw;
2327 struct ifnet *ifp = iflib_get_ifp(ctx);
2328 u32 reg;
2329
2330 /* igc hardware doesn't seem to implement VFTA for HWFILTER */
2331
2332 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
2333 !igc_disable_crc_stripping) {
2334 reg = IGC_READ_REG(hw, IGC_CTRL);
2335 reg |= IGC_CTRL_VME;
2336 IGC_WRITE_REG(hw, IGC_CTRL, reg);
2337 } else {
2338 reg = IGC_READ_REG(hw, IGC_CTRL);
2339 reg &= ~IGC_CTRL_VME;
2340 IGC_WRITE_REG(hw, IGC_CTRL, reg);
2341 }
2342 }
2343
2344 static void
igc_if_intr_enable(if_ctx_t ctx)2345 igc_if_intr_enable(if_ctx_t ctx)
2346 {
2347 struct igc_softc *sc = iflib_get_softc(ctx);
2348 struct igc_hw *hw = &sc->hw;
2349 u32 mask;
2350
2351 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
2352 mask = (sc->que_mask | sc->link_mask);
2353 IGC_WRITE_REG(hw, IGC_EIAC, mask);
2354 IGC_WRITE_REG(hw, IGC_EIAM, mask);
2355 IGC_WRITE_REG(hw, IGC_EIMS, mask);
2356 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC);
2357 } else
2358 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK);
2359 IGC_WRITE_FLUSH(hw);
2360 }
2361
2362 static void
igc_if_intr_disable(if_ctx_t ctx)2363 igc_if_intr_disable(if_ctx_t ctx)
2364 {
2365 struct igc_softc *sc = iflib_get_softc(ctx);
2366 struct igc_hw *hw = &sc->hw;
2367
2368 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
2369 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff);
2370 IGC_WRITE_REG(hw, IGC_EIAC, 0);
2371 }
2372 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
2373 IGC_WRITE_FLUSH(hw);
2374 }
2375
2376 /*
2377 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
2378 * For ASF and Pass Through versions of f/w this means
2379 * that the driver is loaded. For AMT version type f/w
2380 * this means that the network i/f is open.
2381 */
2382 static void
igc_get_hw_control(struct igc_softc * sc)2383 igc_get_hw_control(struct igc_softc *sc)
2384 {
2385 u32 ctrl_ext;
2386
2387 if (sc->vf_ifp)
2388 return;
2389
2390 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT);
2391 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT,
2392 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
2393 }
2394
2395 /*
2396 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
2397 * For ASF and Pass Through versions of f/w this means that
2398 * the driver is no longer loaded. For AMT versions of the
2399 * f/w this means that the network i/f is closed.
2400 */
2401 static void
igc_release_hw_control(struct igc_softc * sc)2402 igc_release_hw_control(struct igc_softc *sc)
2403 {
2404 u32 ctrl_ext;
2405
2406 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT);
2407 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT,
2408 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
2409 return;
2410 }
2411
2412 static int
igc_is_valid_ether_addr(u8 * addr)2413 igc_is_valid_ether_addr(u8 *addr)
2414 {
2415 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
2416
2417 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
2418 return (false);
2419 }
2420
2421 return (true);
2422 }
2423
2424 /*
2425 ** Parse the interface capabilities with regard
2426 ** to both system management and wake-on-lan for
2427 ** later use.
2428 */
2429 static void
igc_get_wakeup(if_ctx_t ctx)2430 igc_get_wakeup(if_ctx_t ctx)
2431 {
2432 struct igc_softc *sc = iflib_get_softc(ctx);
2433 u16 eeprom_data = 0, apme_mask;
2434
2435 apme_mask = IGC_WUC_APME;
2436 eeprom_data = IGC_READ_REG(&sc->hw, IGC_WUC);
2437
2438 if (eeprom_data & apme_mask)
2439 sc->wol = IGC_WUFC_LNKC;
2440 }
2441
2442
2443 /*
2444 * Enable PCI Wake On Lan capability
2445 */
2446 static void
igc_enable_wakeup(if_ctx_t ctx)2447 igc_enable_wakeup(if_ctx_t ctx)
2448 {
2449 struct igc_softc *sc = iflib_get_softc(ctx);
2450 device_t dev = iflib_get_dev(ctx);
2451 if_t ifp = iflib_get_ifp(ctx);
2452 int error = 0;
2453 u32 pmc, ctrl, rctl;
2454 u16 status;
2455
2456 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
2457 return;
2458
2459 /*
2460 * Determine type of Wakeup: note that wol
2461 * is set with all bits on by default.
2462 */
2463 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0)
2464 sc->wol &= ~IGC_WUFC_MAG;
2465
2466 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0)
2467 sc->wol &= ~IGC_WUFC_EX;
2468
2469 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0)
2470 sc->wol &= ~IGC_WUFC_MC;
2471 else {
2472 rctl = IGC_READ_REG(&sc->hw, IGC_RCTL);
2473 rctl |= IGC_RCTL_MPE;
2474 IGC_WRITE_REG(&sc->hw, IGC_RCTL, rctl);
2475 }
2476
2477 if (!(sc->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC)))
2478 goto pme;
2479
2480 /* Advertise the wakeup capability */
2481 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL);
2482 ctrl |= IGC_CTRL_ADVD3WUC;
2483 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl);
2484
2485 /* Enable wakeup by the MAC */
2486 IGC_WRITE_REG(&sc->hw, IGC_WUC, IGC_WUC_PME_EN);
2487 IGC_WRITE_REG(&sc->hw, IGC_WUFC, sc->wol);
2488
2489 pme:
2490 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
2491 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2492 if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
2493 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2494 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
2495
2496 return;
2497 }
2498
2499 /**********************************************************************
2500 *
2501 * Update the board statistics counters.
2502 *
2503 **********************************************************************/
2504 static void
igc_update_stats_counters(struct igc_softc * sc)2505 igc_update_stats_counters(struct igc_softc *sc)
2506 {
2507 u64 prev_xoffrxc = sc->stats.xoffrxc;
2508
2509 sc->stats.crcerrs += IGC_READ_REG(&sc->hw, IGC_CRCERRS);
2510 sc->stats.mpc += IGC_READ_REG(&sc->hw, IGC_MPC);
2511 sc->stats.scc += IGC_READ_REG(&sc->hw, IGC_SCC);
2512 sc->stats.ecol += IGC_READ_REG(&sc->hw, IGC_ECOL);
2513
2514 sc->stats.mcc += IGC_READ_REG(&sc->hw, IGC_MCC);
2515 sc->stats.latecol += IGC_READ_REG(&sc->hw, IGC_LATECOL);
2516 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_COLC);
2517 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_RERC);
2518 sc->stats.dc += IGC_READ_REG(&sc->hw, IGC_DC);
2519 sc->stats.rlec += IGC_READ_REG(&sc->hw, IGC_RLEC);
2520 sc->stats.xonrxc += IGC_READ_REG(&sc->hw, IGC_XONRXC);
2521 sc->stats.xontxc += IGC_READ_REG(&sc->hw, IGC_XONTXC);
2522 sc->stats.xoffrxc += IGC_READ_REG(&sc->hw, IGC_XOFFRXC);
2523 /*
2524 * For watchdog management we need to know if we have been
2525 * paused during the last interval, so capture that here.
2526 */
2527 if (sc->stats.xoffrxc != prev_xoffrxc)
2528 sc->shared->isc_pause_frames = 1;
2529 sc->stats.xofftxc += IGC_READ_REG(&sc->hw, IGC_XOFFTXC);
2530 sc->stats.fcruc += IGC_READ_REG(&sc->hw, IGC_FCRUC);
2531 sc->stats.prc64 += IGC_READ_REG(&sc->hw, IGC_PRC64);
2532 sc->stats.prc127 += IGC_READ_REG(&sc->hw, IGC_PRC127);
2533 sc->stats.prc255 += IGC_READ_REG(&sc->hw, IGC_PRC255);
2534 sc->stats.prc511 += IGC_READ_REG(&sc->hw, IGC_PRC511);
2535 sc->stats.prc1023 += IGC_READ_REG(&sc->hw, IGC_PRC1023);
2536 sc->stats.prc1522 += IGC_READ_REG(&sc->hw, IGC_PRC1522);
2537 sc->stats.tlpic += IGC_READ_REG(&sc->hw, IGC_TLPIC);
2538 sc->stats.rlpic += IGC_READ_REG(&sc->hw, IGC_RLPIC);
2539 sc->stats.gprc += IGC_READ_REG(&sc->hw, IGC_GPRC);
2540 sc->stats.bprc += IGC_READ_REG(&sc->hw, IGC_BPRC);
2541 sc->stats.mprc += IGC_READ_REG(&sc->hw, IGC_MPRC);
2542 sc->stats.gptc += IGC_READ_REG(&sc->hw, IGC_GPTC);
2543
2544 /* For the 64-bit byte counters the low dword must be read first. */
2545 /* Both registers clear on the read of the high dword */
2546
2547 sc->stats.gorc += IGC_READ_REG(&sc->hw, IGC_GORCL) +
2548 ((u64)IGC_READ_REG(&sc->hw, IGC_GORCH) << 32);
2549 sc->stats.gotc += IGC_READ_REG(&sc->hw, IGC_GOTCL) +
2550 ((u64)IGC_READ_REG(&sc->hw, IGC_GOTCH) << 32);
2551
2552 sc->stats.rnbc += IGC_READ_REG(&sc->hw, IGC_RNBC);
2553 sc->stats.ruc += IGC_READ_REG(&sc->hw, IGC_RUC);
2554 sc->stats.rfc += IGC_READ_REG(&sc->hw, IGC_RFC);
2555 sc->stats.roc += IGC_READ_REG(&sc->hw, IGC_ROC);
2556 sc->stats.rjc += IGC_READ_REG(&sc->hw, IGC_RJC);
2557
2558 sc->stats.mgprc += IGC_READ_REG(&sc->hw, IGC_MGTPRC);
2559 sc->stats.mgpdc += IGC_READ_REG(&sc->hw, IGC_MGTPDC);
2560 sc->stats.mgptc += IGC_READ_REG(&sc->hw, IGC_MGTPTC);
2561
2562 sc->stats.tor += IGC_READ_REG(&sc->hw, IGC_TORH);
2563 sc->stats.tot += IGC_READ_REG(&sc->hw, IGC_TOTH);
2564
2565 sc->stats.tpr += IGC_READ_REG(&sc->hw, IGC_TPR);
2566 sc->stats.tpt += IGC_READ_REG(&sc->hw, IGC_TPT);
2567 sc->stats.ptc64 += IGC_READ_REG(&sc->hw, IGC_PTC64);
2568 sc->stats.ptc127 += IGC_READ_REG(&sc->hw, IGC_PTC127);
2569 sc->stats.ptc255 += IGC_READ_REG(&sc->hw, IGC_PTC255);
2570 sc->stats.ptc511 += IGC_READ_REG(&sc->hw, IGC_PTC511);
2571 sc->stats.ptc1023 += IGC_READ_REG(&sc->hw, IGC_PTC1023);
2572 sc->stats.ptc1522 += IGC_READ_REG(&sc->hw, IGC_PTC1522);
2573 sc->stats.mptc += IGC_READ_REG(&sc->hw, IGC_MPTC);
2574 sc->stats.bptc += IGC_READ_REG(&sc->hw, IGC_BPTC);
2575
2576 /* Interrupt Counts */
2577 sc->stats.iac += IGC_READ_REG(&sc->hw, IGC_IAC);
2578 sc->stats.rxdmtc += IGC_READ_REG(&sc->hw, IGC_RXDMTC);
2579
2580 sc->stats.algnerrc += IGC_READ_REG(&sc->hw, IGC_ALGNERRC);
2581 sc->stats.tncrs += IGC_READ_REG(&sc->hw, IGC_TNCRS);
2582 sc->stats.htdpmc += IGC_READ_REG(&sc->hw, IGC_HTDPMC);
2583 sc->stats.tsctc += IGC_READ_REG(&sc->hw, IGC_TSCTC);
2584 }
2585
2586 static uint64_t
igc_if_get_counter(if_ctx_t ctx,ift_counter cnt)2587 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2588 {
2589 struct igc_softc *sc = iflib_get_softc(ctx);
2590 if_t ifp = iflib_get_ifp(ctx);
2591
2592 switch (cnt) {
2593 case IFCOUNTER_COLLISIONS:
2594 return (sc->stats.colc);
2595 case IFCOUNTER_IERRORS:
2596 return (sc->dropped_pkts + sc->stats.rxerrc +
2597 sc->stats.crcerrs + sc->stats.algnerrc +
2598 sc->stats.ruc + sc->stats.roc +
2599 sc->stats.mpc + sc->stats.htdpmc);
2600 case IFCOUNTER_OERRORS:
2601 return (sc->stats.ecol + sc->stats.latecol +
2602 sc->watchdog_events);
2603 default:
2604 return (if_get_counter_default(ifp, cnt));
2605 }
2606 }
2607
2608 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized
2609 * @ctx: iflib context
2610 * @event: event code to check
2611 *
2612 * Defaults to returning false for unknown events.
2613 *
2614 * @returns true if iflib needs to reinit the interface
2615 */
2616 static bool
igc_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)2617 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
2618 {
2619 switch (event) {
2620 case IFLIB_RESTART_VLAN_CONFIG:
2621 default:
2622 return (false);
2623 }
2624 }
2625
2626 /* Export a single 32-bit register via a read-only sysctl. */
2627 static int
igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)2628 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
2629 {
2630 struct igc_softc *sc;
2631 u_int val;
2632
2633 sc = oidp->oid_arg1;
2634 val = IGC_READ_REG(&sc->hw, oidp->oid_arg2);
2635 return (sysctl_handle_int(oidp, &val, 0, req));
2636 }
2637
2638 /* Per queue holdoff interrupt rate handler */
2639 static int
igc_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)2640 igc_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)
2641 {
2642 struct igc_rx_queue *rque;
2643 struct igc_tx_queue *tque;
2644 struct igc_hw *hw;
2645 int error;
2646 u32 reg, usec, rate;
2647
2648 bool tx = oidp->oid_arg2;
2649
2650 if (tx) {
2651 tque = oidp->oid_arg1;
2652 hw = &tque->sc->hw;
2653 reg = IGC_READ_REG(hw, IGC_EITR(tque->me));
2654 } else {
2655 rque = oidp->oid_arg1;
2656 hw = &rque->sc->hw;
2657 reg = IGC_READ_REG(hw, IGC_EITR(rque->msix));
2658 }
2659
2660 usec = (reg & IGC_QVECTOR_MASK);
2661 if (usec > 0)
2662 rate = IGC_INTS_TO_EITR(usec);
2663 else
2664 rate = 0;
2665
2666 error = sysctl_handle_int(oidp, &rate, 0, req);
2667 if (error || !req->newptr)
2668 return error;
2669 return 0;
2670 }
2671
2672 /*
2673 * Add sysctl variables, one per statistic, to the system.
2674 */
2675 static void
igc_add_hw_stats(struct igc_softc * sc)2676 igc_add_hw_stats(struct igc_softc *sc)
2677 {
2678 device_t dev = iflib_get_dev(sc->ctx);
2679 struct igc_tx_queue *tx_que = sc->tx_queues;
2680 struct igc_rx_queue *rx_que = sc->rx_queues;
2681
2682 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
2683 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
2684 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
2685 struct igc_hw_stats *stats = &sc->stats;
2686
2687 struct sysctl_oid *stat_node, *queue_node, *int_node;
2688 struct sysctl_oid_list *stat_list, *queue_list, *int_list;
2689
2690 #define QUEUE_NAME_LEN 32
2691 char namebuf[QUEUE_NAME_LEN];
2692
2693 /* Driver Statistics */
2694 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
2695 CTLFLAG_RD, &sc->dropped_pkts,
2696 "Driver dropped packets");
2697 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
2698 CTLFLAG_RD, &sc->link_irq,
2699 "Link MSI-X IRQ Handled");
2700 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
2701 CTLFLAG_RD, &sc->rx_overruns,
2702 "RX overruns");
2703 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
2704 CTLFLAG_RD, &sc->watchdog_events,
2705 "Watchdog timeouts");
2706 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
2707 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
2708 sc, IGC_CTRL, igc_sysctl_reg_handler, "IU",
2709 "Device Control Register");
2710 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
2711 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
2712 sc, IGC_RCTL, igc_sysctl_reg_handler, "IU",
2713 "Receiver Control Register");
2714 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
2715 CTLFLAG_RD, &sc->hw.fc.high_water, 0,
2716 "Flow Control High Watermark");
2717 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
2718 CTLFLAG_RD, &sc->hw.fc.low_water, 0,
2719 "Flow Control Low Watermark");
2720
2721 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
2722 struct tx_ring *txr = &tx_que->txr;
2723 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i);
2724 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2725 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
2726 queue_list = SYSCTL_CHILDREN(queue_node);
2727
2728 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
2729 CTLTYPE_UINT | CTLFLAG_RD, tx_que,
2730 true, igc_sysctl_interrupt_rate_handler, "IU",
2731 "Interrupt Rate");
2732 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
2733 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2734 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU",
2735 "Transmit Descriptor Head");
2736 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
2737 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2738 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU",
2739 "Transmit Descriptor Tail");
2740 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
2741 CTLFLAG_RD, &txr->tx_irq,
2742 "Queue MSI-X Transmit Interrupts");
2743 }
2744
2745 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
2746 struct rx_ring *rxr = &rx_que->rxr;
2747 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j);
2748 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
2749 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
2750 queue_list = SYSCTL_CHILDREN(queue_node);
2751
2752 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
2753 CTLTYPE_UINT | CTLFLAG_RD, rx_que,
2754 false, igc_sysctl_interrupt_rate_handler, "IU",
2755 "Interrupt Rate");
2756 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
2757 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2758 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU",
2759 "Receive Descriptor Head");
2760 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
2761 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
2762 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU",
2763 "Receive Descriptor Tail");
2764 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
2765 CTLFLAG_RD, &rxr->rx_irq,
2766 "Queue MSI-X Receive Interrupts");
2767 }
2768
2769 /* MAC stats get their own sub node */
2770 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
2771 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
2772 stat_list = SYSCTL_CHILDREN(stat_node);
2773
2774 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
2775 CTLFLAG_RD, &stats->ecol,
2776 "Excessive collisions");
2777 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
2778 CTLFLAG_RD, &stats->scc,
2779 "Single collisions");
2780 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
2781 CTLFLAG_RD, &stats->mcc,
2782 "Multiple collisions");
2783 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
2784 CTLFLAG_RD, &stats->latecol,
2785 "Late collisions");
2786 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
2787 CTLFLAG_RD, &stats->colc,
2788 "Collision Count");
2789 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
2790 CTLFLAG_RD, &sc->stats.symerrs,
2791 "Symbol Errors");
2792 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
2793 CTLFLAG_RD, &sc->stats.sec,
2794 "Sequence Errors");
2795 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
2796 CTLFLAG_RD, &sc->stats.dc,
2797 "Defer Count");
2798 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
2799 CTLFLAG_RD, &sc->stats.mpc,
2800 "Missed Packets");
2801 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors",
2802 CTLFLAG_RD, &sc->stats.rlec,
2803 "Receive Length Errors");
2804 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
2805 CTLFLAG_RD, &sc->stats.rnbc,
2806 "Receive No Buffers");
2807 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
2808 CTLFLAG_RD, &sc->stats.ruc,
2809 "Receive Undersize");
2810 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
2811 CTLFLAG_RD, &sc->stats.rfc,
2812 "Fragmented Packets Received ");
2813 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
2814 CTLFLAG_RD, &sc->stats.roc,
2815 "Oversized Packets Received");
2816 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
2817 CTLFLAG_RD, &sc->stats.rjc,
2818 "Recevied Jabber");
2819 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
2820 CTLFLAG_RD, &sc->stats.rxerrc,
2821 "Receive Errors");
2822 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
2823 CTLFLAG_RD, &sc->stats.crcerrs,
2824 "CRC errors");
2825 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
2826 CTLFLAG_RD, &sc->stats.algnerrc,
2827 "Alignment Errors");
2828 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
2829 CTLFLAG_RD, &sc->stats.xonrxc,
2830 "XON Received");
2831 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
2832 CTLFLAG_RD, &sc->stats.xontxc,
2833 "XON Transmitted");
2834 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
2835 CTLFLAG_RD, &sc->stats.xoffrxc,
2836 "XOFF Received");
2837 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
2838 CTLFLAG_RD, &sc->stats.xofftxc,
2839 "XOFF Transmitted");
2840 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd",
2841 CTLFLAG_RD, &sc->stats.fcruc,
2842 "Unsupported Flow Control Received");
2843 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd",
2844 CTLFLAG_RD, &sc->stats.mgprc,
2845 "Management Packets Received");
2846 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop",
2847 CTLFLAG_RD, &sc->stats.mgpdc,
2848 "Management Packets Dropped");
2849 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd",
2850 CTLFLAG_RD, &sc->stats.mgptc,
2851 "Management Packets Transmitted");
2852
2853 /* Packet Reception Stats */
2854 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
2855 CTLFLAG_RD, &sc->stats.tpr,
2856 "Total Packets Received ");
2857 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
2858 CTLFLAG_RD, &sc->stats.gprc,
2859 "Good Packets Received");
2860 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
2861 CTLFLAG_RD, &sc->stats.bprc,
2862 "Broadcast Packets Received");
2863 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
2864 CTLFLAG_RD, &sc->stats.mprc,
2865 "Multicast Packets Received");
2866 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
2867 CTLFLAG_RD, &sc->stats.prc64,
2868 "64 byte frames received ");
2869 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
2870 CTLFLAG_RD, &sc->stats.prc127,
2871 "65-127 byte frames received");
2872 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
2873 CTLFLAG_RD, &sc->stats.prc255,
2874 "128-255 byte frames received");
2875 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
2876 CTLFLAG_RD, &sc->stats.prc511,
2877 "256-511 byte frames received");
2878 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
2879 CTLFLAG_RD, &sc->stats.prc1023,
2880 "512-1023 byte frames received");
2881 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
2882 CTLFLAG_RD, &sc->stats.prc1522,
2883 "1023-1522 byte frames received");
2884 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
2885 CTLFLAG_RD, &sc->stats.gorc,
2886 "Good Octets Received");
2887
2888 /* Packet Transmission Stats */
2889 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
2890 CTLFLAG_RD, &sc->stats.gotc,
2891 "Good Octets Transmitted");
2892 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
2893 CTLFLAG_RD, &sc->stats.tpt,
2894 "Total Packets Transmitted");
2895 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
2896 CTLFLAG_RD, &sc->stats.gptc,
2897 "Good Packets Transmitted");
2898 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
2899 CTLFLAG_RD, &sc->stats.bptc,
2900 "Broadcast Packets Transmitted");
2901 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
2902 CTLFLAG_RD, &sc->stats.mptc,
2903 "Multicast Packets Transmitted");
2904 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
2905 CTLFLAG_RD, &sc->stats.ptc64,
2906 "64 byte frames transmitted ");
2907 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
2908 CTLFLAG_RD, &sc->stats.ptc127,
2909 "65-127 byte frames transmitted");
2910 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
2911 CTLFLAG_RD, &sc->stats.ptc255,
2912 "128-255 byte frames transmitted");
2913 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
2914 CTLFLAG_RD, &sc->stats.ptc511,
2915 "256-511 byte frames transmitted");
2916 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
2917 CTLFLAG_RD, &sc->stats.ptc1023,
2918 "512-1023 byte frames transmitted");
2919 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
2920 CTLFLAG_RD, &sc->stats.ptc1522,
2921 "1024-1522 byte frames transmitted");
2922 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
2923 CTLFLAG_RD, &sc->stats.tsctc,
2924 "TSO Contexts Transmitted");
2925
2926 /* Interrupt Stats */
2927 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
2928 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
2929 int_list = SYSCTL_CHILDREN(int_node);
2930
2931 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
2932 CTLFLAG_RD, &sc->stats.iac,
2933 "Interrupt Assertion Count");
2934
2935 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
2936 CTLFLAG_RD, &sc->stats.rxdmtc,
2937 "Rx Desc Min Thresh Count");
2938 }
2939
2940 static void
igc_fw_version(struct igc_softc * sc)2941 igc_fw_version(struct igc_softc *sc)
2942 {
2943 struct igc_hw *hw = &sc->hw;
2944 struct igc_fw_version *fw_ver = &sc->fw_ver;
2945
2946 *fw_ver = (struct igc_fw_version){0};
2947
2948 igc_get_fw_version(hw, fw_ver);
2949 }
2950
2951 static void
igc_sbuf_fw_version(struct igc_fw_version * fw_ver,struct sbuf * buf)2952 igc_sbuf_fw_version(struct igc_fw_version *fw_ver, struct sbuf *buf)
2953 {
2954 const char *space = "";
2955
2956 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) {
2957 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major,
2958 fw_ver->eep_minor, fw_ver->eep_build);
2959 space = " ";
2960 }
2961
2962 if (fw_ver->invm_major || fw_ver->invm_minor ||
2963 fw_ver->invm_img_type) {
2964 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d",
2965 space, fw_ver->invm_major, fw_ver->invm_minor,
2966 fw_ver->invm_img_type);
2967 space = " ";
2968 }
2969
2970 if (fw_ver->or_valid) {
2971 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
2972 space, fw_ver->or_major, fw_ver->or_build,
2973 fw_ver->or_patch);
2974 space = " ";
2975 }
2976
2977 if (fw_ver->etrack_id)
2978 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id);
2979 }
2980
2981 static void
igc_print_fw_version(struct igc_softc * sc)2982 igc_print_fw_version(struct igc_softc *sc )
2983 {
2984 device_t dev = sc->dev;
2985 struct sbuf *buf;
2986 int error = 0;
2987
2988 buf = sbuf_new_auto();
2989 if (!buf) {
2990 device_printf(dev, "Could not allocate sbuf for output.\n");
2991 return;
2992 }
2993
2994 igc_sbuf_fw_version(&sc->fw_ver, buf);
2995
2996 error = sbuf_finish(buf);
2997 if (error)
2998 device_printf(dev, "Error finishing sbuf: %d\n", error);
2999 else if (sbuf_len(buf))
3000 device_printf(dev, "%s\n", sbuf_data(buf));
3001
3002 sbuf_delete(buf);
3003 }
3004
3005 static int
igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)3006 igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS)
3007 {
3008 struct igc_softc *sc = (struct igc_softc *)arg1;
3009 device_t dev = sc->dev;
3010 struct sbuf *buf;
3011 int error = 0;
3012
3013 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
3014 if (!buf) {
3015 device_printf(dev, "Could not allocate sbuf for output.\n");
3016 return (ENOMEM);
3017 }
3018
3019 igc_sbuf_fw_version(&sc->fw_ver, buf);
3020
3021 error = sbuf_finish(buf);
3022 if (error)
3023 device_printf(dev, "Error finishing sbuf: %d\n", error);
3024
3025 sbuf_delete(buf);
3026
3027 return (0);
3028 }
3029
3030 /**********************************************************************
3031 *
3032 * This routine provides a way to dump out the adapter eeprom,
3033 * often a useful debug/service tool. This only dumps the first
3034 * 32 words, stuff that matters is in that extent.
3035 *
3036 **********************************************************************/
3037 static int
igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)3038 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
3039 {
3040 struct igc_softc *sc = (struct igc_softc *)arg1;
3041 int error;
3042 int result;
3043
3044 result = -1;
3045 error = sysctl_handle_int(oidp, &result, 0, req);
3046
3047 if (error || !req->newptr)
3048 return (error);
3049
3050 /*
3051 * This value will cause a hex dump of the
3052 * first 32 16-bit words of the EEPROM to
3053 * the screen.
3054 */
3055 if (result == 1)
3056 igc_print_nvm_info(sc);
3057
3058 return (error);
3059 }
3060
3061 static void
igc_print_nvm_info(struct igc_softc * sc)3062 igc_print_nvm_info(struct igc_softc *sc)
3063 {
3064 u16 eeprom_data;
3065 int i, j, row = 0;
3066
3067 /* Its a bit crude, but it gets the job done */
3068 printf("\nInterface EEPROM Dump:\n");
3069 printf("Offset\n0x0000 ");
3070 for (i = 0, j = 0; i < 32; i++, j++) {
3071 if (j == 8) { /* Make the offset block */
3072 j = 0; ++row;
3073 printf("\n0x00%x0 ",row);
3074 }
3075 igc_read_nvm(&sc->hw, i, 1, &eeprom_data);
3076 printf("%04x ", eeprom_data);
3077 }
3078 printf("\n");
3079 }
3080
3081 static int
igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)3082 igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)
3083 {
3084 struct igc_softc *sc;
3085 u32 reg, val, shift;
3086 int error, mask;
3087
3088 sc = oidp->oid_arg1;
3089 switch (oidp->oid_arg2) {
3090 case 0:
3091 reg = IGC_DTXTCPFLGL;
3092 shift = 0;
3093 break;
3094 case 1:
3095 reg = IGC_DTXTCPFLGL;
3096 shift = 16;
3097 break;
3098 case 2:
3099 reg = IGC_DTXTCPFLGH;
3100 shift = 0;
3101 break;
3102 default:
3103 return (EINVAL);
3104 break;
3105 }
3106 val = IGC_READ_REG(&sc->hw, reg);
3107 mask = (val >> shift) & 0xfff;
3108 error = sysctl_handle_int(oidp, &mask, 0, req);
3109 if (error != 0 || req->newptr == NULL)
3110 return (error);
3111 if (mask < 0 || mask > 0xfff)
3112 return (EINVAL);
3113 val = (val & ~(0xfff << shift)) | (mask << shift);
3114 IGC_WRITE_REG(&sc->hw, reg, val);
3115 return (0);
3116 }
3117
3118 /*
3119 * Set flow control using sysctl:
3120 * Flow control values:
3121 * 0 - off
3122 * 1 - rx pause
3123 * 2 - tx pause
3124 * 3 - full
3125 */
3126 static int
igc_set_flowcntl(SYSCTL_HANDLER_ARGS)3127 igc_set_flowcntl(SYSCTL_HANDLER_ARGS)
3128 {
3129 int error;
3130 static int input = 3; /* default is full */
3131 struct igc_softc *sc = (struct igc_softc *) arg1;
3132
3133 error = sysctl_handle_int(oidp, &input, 0, req);
3134
3135 if ((error) || (req->newptr == NULL))
3136 return (error);
3137
3138 if (input == sc->fc) /* no change? */
3139 return (error);
3140
3141 switch (input) {
3142 case igc_fc_rx_pause:
3143 case igc_fc_tx_pause:
3144 case igc_fc_full:
3145 case igc_fc_none:
3146 sc->hw.fc.requested_mode = input;
3147 sc->fc = input;
3148 break;
3149 default:
3150 /* Do nothing */
3151 return (error);
3152 }
3153
3154 sc->hw.fc.current_mode = sc->hw.fc.requested_mode;
3155 igc_force_mac_fc(&sc->hw);
3156 return (error);
3157 }
3158
3159 /*
3160 * Manage DMA Coalesce:
3161 * Control values:
3162 * 0/1 - off/on
3163 * Legal timer values are:
3164 * 250,500,1000-10000 in thousands
3165 */
3166 static int
igc_sysctl_dmac(SYSCTL_HANDLER_ARGS)3167 igc_sysctl_dmac(SYSCTL_HANDLER_ARGS)
3168 {
3169 struct igc_softc *sc = (struct igc_softc *) arg1;
3170 int error;
3171
3172 error = sysctl_handle_int(oidp, &sc->dmac, 0, req);
3173
3174 if ((error) || (req->newptr == NULL))
3175 return (error);
3176
3177 switch (sc->dmac) {
3178 case 0:
3179 /* Disabling */
3180 break;
3181 case 1: /* Just enable and use default */
3182 sc->dmac = 1000;
3183 break;
3184 case 250:
3185 case 500:
3186 case 1000:
3187 case 2000:
3188 case 3000:
3189 case 4000:
3190 case 5000:
3191 case 6000:
3192 case 7000:
3193 case 8000:
3194 case 9000:
3195 case 10000:
3196 /* Legal values - allow */
3197 break;
3198 default:
3199 /* Do nothing, illegal value */
3200 sc->dmac = 0;
3201 return (EINVAL);
3202 }
3203 /* Reinit the interface */
3204 igc_if_init(sc->ctx);
3205 return (error);
3206 }
3207
3208 /*
3209 * Manage Energy Efficient Ethernet:
3210 * Control values:
3211 * 0/1 - enabled/disabled
3212 */
3213 static int
igc_sysctl_eee(SYSCTL_HANDLER_ARGS)3214 igc_sysctl_eee(SYSCTL_HANDLER_ARGS)
3215 {
3216 struct igc_softc *sc = (struct igc_softc *) arg1;
3217 int error, value;
3218
3219 value = sc->hw.dev_spec._i225.eee_disable;
3220 error = sysctl_handle_int(oidp, &value, 0, req);
3221 if (error || req->newptr == NULL)
3222 return (error);
3223
3224 sc->hw.dev_spec._i225.eee_disable = (value != 0);
3225 igc_if_init(sc->ctx);
3226
3227 return (0);
3228 }
3229
3230 static int
igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS)3231 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3232 {
3233 struct igc_softc *sc;
3234 int error;
3235 int result;
3236
3237 result = -1;
3238 error = sysctl_handle_int(oidp, &result, 0, req);
3239
3240 if (error || !req->newptr)
3241 return (error);
3242
3243 if (result == 1) {
3244 sc = (struct igc_softc *) arg1;
3245 igc_print_debug_info(sc);
3246 }
3247
3248 return (error);
3249 }
3250
3251 static int
igc_get_rs(SYSCTL_HANDLER_ARGS)3252 igc_get_rs(SYSCTL_HANDLER_ARGS)
3253 {
3254 struct igc_softc *sc = (struct igc_softc *) arg1;
3255 int error;
3256 int result;
3257
3258 result = 0;
3259 error = sysctl_handle_int(oidp, &result, 0, req);
3260
3261 if (error || !req->newptr || result != 1)
3262 return (error);
3263 igc_dump_rs(sc);
3264
3265 return (error);
3266 }
3267
3268 static void
igc_if_debug(if_ctx_t ctx)3269 igc_if_debug(if_ctx_t ctx)
3270 {
3271 igc_dump_rs(iflib_get_softc(ctx));
3272 }
3273
3274 /*
3275 * This routine is meant to be fluid, add whatever is
3276 * needed for debugging a problem. -jfv
3277 */
3278 static void
igc_print_debug_info(struct igc_softc * sc)3279 igc_print_debug_info(struct igc_softc *sc)
3280 {
3281 device_t dev = iflib_get_dev(sc->ctx);
3282 if_t ifp = iflib_get_ifp(sc->ctx);
3283 struct tx_ring *txr = &sc->tx_queues->txr;
3284 struct rx_ring *rxr = &sc->rx_queues->rxr;
3285
3286 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
3287 printf("Interface is RUNNING ");
3288 else
3289 printf("Interface is NOT RUNNING\n");
3290
3291 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
3292 printf("and INACTIVE\n");
3293 else
3294 printf("and ACTIVE\n");
3295
3296 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
3297 device_printf(dev, "TX Queue %d ------\n", i);
3298 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3299 IGC_READ_REG(&sc->hw, IGC_TDH(i)),
3300 IGC_READ_REG(&sc->hw, IGC_TDT(i)));
3301
3302 }
3303 for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
3304 device_printf(dev, "RX Queue %d ------\n", j);
3305 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3306 IGC_READ_REG(&sc->hw, IGC_RDH(j)),
3307 IGC_READ_REG(&sc->hw, IGC_RDT(j)));
3308 }
3309 }
3310