1 /*-
2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Neither the name of Matthew Macy nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include "opt_inet.h"
30 #include "opt_inet6.h"
31 #include "opt_acpi.h"
32
33 #include <sys/param.h>
34 #include <sys/types.h>
35 #include <sys/bus.h>
36 #include <sys/eventhandler.h>
37 #include <sys/kernel.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/module.h>
41 #include <sys/kobj.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/sbuf.h>
45 #include <sys/sched.h>
46 #include <sys/smp.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/sysctl.h>
50 #include <sys/syslog.h>
51 #include <sys/taskqueue.h>
52 #include <sys/limits.h>
53
54 #include <net/if.h>
55 #include <net/if_var.h>
56 #include <net/if_private.h>
57 #include <net/if_types.h>
58 #include <net/if_media.h>
59 #include <net/bpf.h>
60 #include <net/ethernet.h>
61 #include <net/mp_ring.h>
62 #include <net/debugnet.h>
63 #include <net/pfil.h>
64 #include <net/vnet.h>
65
66 #include <netinet/in.h>
67 #include <netinet/in_pcb.h>
68 #include <netinet/tcp_lro.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/if_ether.h>
71 #include <netinet/ip.h>
72 #include <netinet/ip6.h>
73 #include <netinet/tcp.h>
74 #include <netinet/udp.h>
75 #include <netinet/ip_var.h>
76 #include <netinet6/ip6_var.h>
77
78 #include <machine/bus.h>
79 #include <machine/in_cksum.h>
80
81 #include <vm/vm.h>
82 #include <vm/pmap.h>
83
84 #include <dev/led/led.h>
85 #include <dev/pci/pcireg.h>
86 #include <dev/pci/pcivar.h>
87 #include <dev/pci/pci_private.h>
88
89 #include <net/iflib.h>
90
91 #include "ifdi_if.h"
92
93 #ifdef PCI_IOV
94 #include <dev/pci/pci_iov.h>
95 #endif
96
97 #include <sys/bitstring.h>
98 /*
99 * enable accounting of every mbuf as it comes in to and goes out of
100 * iflib's software descriptor references
101 */
102 #define MEMORY_LOGGING 0
103 /*
104 * Enable mbuf vectors for compressing long mbuf chains
105 */
106
107 /*
108 * NB:
109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * we prefetch needs to be determined by the time spent in m_free vis a vis
111 * the cost of a prefetch. This will of course vary based on the workload:
112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
113 * is quite expensive, thus suggesting very little prefetch.
114 * - small packet forwarding which is just returning a single mbuf to
115 * UMA will typically be very fast vis a vis the cost of a memory
116 * access.
117 */
118
119 /*
120 * File organization:
121 * - private structures
122 * - iflib private utility functions
123 * - ifnet functions
124 * - vlan registry and other exported functions
125 * - iflib public core functions
126 *
127 *
128 */
129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library");
130
131 #define IFLIB_RXEOF_MORE (1U << 0)
132 #define IFLIB_RXEOF_EMPTY (2U << 0)
133
134 struct iflib_txq;
135 typedef struct iflib_txq *iflib_txq_t;
136 struct iflib_rxq;
137 typedef struct iflib_rxq *iflib_rxq_t;
138 struct iflib_fl;
139 typedef struct iflib_fl *iflib_fl_t;
140
141 struct iflib_ctx;
142
143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid);
144 static void iflib_timer(void *arg);
145 static void iflib_tqg_detach(if_ctx_t ctx);
146 #ifndef ALTQ
147 static int iflib_simple_transmit(if_t ifp, struct mbuf *m);
148 #endif
149
150 typedef struct iflib_filter_info {
151 driver_filter_t *ifi_filter;
152 void *ifi_filter_arg;
153 struct grouptask *ifi_task;
154 void *ifi_ctx;
155 } *iflib_filter_info_t;
156
157 struct iflib_ctx {
158 KOBJ_FIELDS;
159 /*
160 * Pointer to hardware driver's softc
161 */
162 void *ifc_softc;
163 device_t ifc_dev;
164 if_t ifc_ifp;
165
166 cpuset_t ifc_cpus;
167 if_shared_ctx_t ifc_sctx;
168 struct if_softc_ctx ifc_softc_ctx;
169
170 struct sx ifc_ctx_sx;
171 struct mtx ifc_state_mtx;
172
173 iflib_txq_t ifc_txqs;
174 iflib_rxq_t ifc_rxqs;
175 uint32_t ifc_if_flags;
176 uint32_t ifc_flags;
177 uint32_t ifc_max_fl_buf_size;
178 uint32_t ifc_rx_mbuf_sz;
179
180 int ifc_link_state;
181 int ifc_watchdog_events;
182 struct cdev *ifc_led_dev;
183 struct resource *ifc_msix_mem;
184
185 struct if_irq ifc_legacy_irq;
186 struct task ifc_admin_task;
187 struct task ifc_vflr_task;
188 struct taskqueue *ifc_tq;
189 struct iflib_filter_info ifc_filter_info;
190 struct ifmedia ifc_media;
191 struct ifmedia *ifc_mediap;
192
193 struct sysctl_oid *ifc_sysctl_node;
194 uint16_t ifc_sysctl_ntxqs;
195 uint16_t ifc_sysctl_nrxqs;
196 uint16_t ifc_sysctl_qs_eq_override;
197 uint16_t ifc_sysctl_rx_budget;
198 uint16_t ifc_sysctl_tx_abdicate;
199 uint16_t ifc_sysctl_core_offset;
200 #define CORE_OFFSET_UNSPECIFIED 0xffff
201 uint8_t ifc_sysctl_separate_txrx;
202 uint8_t ifc_sysctl_use_logical_cores;
203 uint16_t ifc_sysctl_extra_msix_vectors;
204 bool ifc_cpus_are_physical_cores;
205 bool ifc_sysctl_simple_tx;
206 bool ifc_sysctl_tx_defer_mfree;
207 uint16_t ifc_sysctl_tx_reclaim_thresh;
208 uint16_t ifc_sysctl_tx_reclaim_ticks;
209
210 qidx_t ifc_sysctl_ntxds[8];
211 qidx_t ifc_sysctl_nrxds[8];
212 struct if_txrx ifc_txrx;
213 #define isc_txd_encap ifc_txrx.ift_txd_encap
214 #define isc_txd_flush ifc_txrx.ift_txd_flush
215 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update
216 #define isc_rxd_available ifc_txrx.ift_rxd_available
217 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get
218 #define isc_rxd_refill ifc_txrx.ift_rxd_refill
219 #define isc_rxd_flush ifc_txrx.ift_rxd_flush
220 #define isc_legacy_intr ifc_txrx.ift_legacy_intr
221 #define isc_txq_select ifc_txrx.ift_txq_select
222 #define isc_txq_select_v2 ifc_txrx.ift_txq_select_v2
223
224 eventhandler_tag ifc_vlan_attach_event;
225 eventhandler_tag ifc_vlan_detach_event;
226 struct ether_addr ifc_mac;
227 };
228
229 void *
iflib_get_softc(if_ctx_t ctx)230 iflib_get_softc(if_ctx_t ctx)
231 {
232
233 return (ctx->ifc_softc);
234 }
235
236 device_t
iflib_get_dev(if_ctx_t ctx)237 iflib_get_dev(if_ctx_t ctx)
238 {
239
240 return (ctx->ifc_dev);
241 }
242
243 if_t
iflib_get_ifp(if_ctx_t ctx)244 iflib_get_ifp(if_ctx_t ctx)
245 {
246
247 return (ctx->ifc_ifp);
248 }
249
250 struct ifmedia *
iflib_get_media(if_ctx_t ctx)251 iflib_get_media(if_ctx_t ctx)
252 {
253
254 return (ctx->ifc_mediap);
255 }
256
257 void
iflib_set_mac(if_ctx_t ctx,uint8_t mac[ETHER_ADDR_LEN])258 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN])
259 {
260
261 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN);
262 }
263
264 if_softc_ctx_t
iflib_get_softc_ctx(if_ctx_t ctx)265 iflib_get_softc_ctx(if_ctx_t ctx)
266 {
267
268 return (&ctx->ifc_softc_ctx);
269 }
270
271 if_shared_ctx_t
iflib_get_sctx(if_ctx_t ctx)272 iflib_get_sctx(if_ctx_t ctx)
273 {
274
275 return (ctx->ifc_sctx);
276 }
277
278 uint16_t
iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx)279 iflib_get_extra_msix_vectors_sysctl(if_ctx_t ctx)
280 {
281
282 return (ctx->ifc_sysctl_extra_msix_vectors);
283 }
284
285 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2)
286 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE / sizeof(void *))
287 #define CACHE_PTR_NEXT(ptr) ((void *)(roundup2(ptr, CACHE_LINE_SIZE)))
288
289 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP)
290 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF)
291
292 typedef struct iflib_sw_rx_desc_array {
293 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
294 struct mbuf **ifsd_m; /* pkthdr mbufs */
295 caddr_t *ifsd_cl; /* direct cluster pointer for rx */
296 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */
297 } iflib_rxsd_array_t;
298
299 typedef struct iflib_sw_tx_desc_array {
300 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */
301 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */
302 struct mbuf **ifsd_m; /* pkthdr mbufs */
303 struct mbuf **ifsd_m_defer; /* deferred mbuf ptr */
304 struct mbuf **ifsd_m_deferb;/* deferred mbuf backing ptr */
305 } if_txsd_vec_t;
306
307 /* magic number that should be high enough for any hardware */
308 #define IFLIB_MAX_TX_SEGS 128
309 #define IFLIB_RX_COPY_THRESH 128
310 #define IFLIB_MAX_RX_REFRESH 32
311 /* The minimum descriptors per second before we start coalescing */
312 #define IFLIB_MIN_DESC_SEC 16384
313 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16
314 #define IFLIB_QUEUE_IDLE 0
315 #define IFLIB_QUEUE_HUNG 1
316 #define IFLIB_QUEUE_WORKING 2
317 /* maximum number of txqs that can share an rx interrupt */
318 #define IFLIB_MAX_TX_SHARED_INTR 4
319
320 /* this should really scale with ring size - this is a fairly arbitrary value */
321 #define TX_BATCH_SIZE 32
322
323 #define IFLIB_RESTART_BUDGET 8
324
325
326 /*
327 * Encode TSO or !TSO in the low bits of the tx ifsd_m pointer so as
328 * to avoid defref'ing the mbuf to determine the correct busdma resources
329 * to release
330 */
331 #define IFLIB_TSO (1ULL << 0)
332 #define IFLIB_NO_TSO (2ULL << 0)
333 #define IFLIB_FLAGS_MASK (0x3ULL)
334 #define IFLIB_SAVE_MBUF(mbuf, flags) ((void *)(((uintptr_t)mbuf) | flags))
335 #define IFLIB_GET_FLAGS(a) ((uintptr_t)a & IFLIB_FLAGS_MASK)
336 #define IFLIB_GET_MBUF(a) ((struct mbuf *)((uintptr_t)a & ~IFLIB_FLAGS_MASK))
337
338
339 #define IFC_LEGACY 0x001
340 #define IFC_QFLUSH 0x002
341 #define IFC_MULTISEG 0x004
342 #define IFC_SPARE1 0x008
343 #define IFC_SC_ALLOCATED 0x010
344 #define IFC_INIT_DONE 0x020
345 #define IFC_PREFETCH 0x040
346 #define IFC_DO_RESET 0x080
347 #define IFC_DO_WATCHDOG 0x100
348 #define IFC_SPARE0 0x200
349 #define IFC_SPARE2 0x400
350 #define IFC_IN_DETACH 0x800
351
352 #define IFC_NETMAP_TX_IRQ 0x80000000
353
354 #define CSUM_OFFLOAD (CSUM_IP_TSO | CSUM_IP6_TSO | CSUM_IP | \
355 CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_SCTP | \
356 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_SCTP)
357
358 struct iflib_txq {
359 qidx_t ift_in_use;
360 qidx_t ift_cidx;
361 qidx_t ift_cidx_processed;
362 qidx_t ift_pidx;
363 uint8_t ift_gen;
364 uint8_t ift_br_offset:1,
365 ift_defer_mfree:1,
366 ift_spare_bits0:6;
367 uint16_t ift_npending;
368 uint16_t ift_db_pending;
369 uint16_t ift_rs_pending;
370 uint32_t ift_last_reclaim;
371 uint16_t ift_reclaim_thresh;
372 uint16_t ift_reclaim_ticks;
373 uint8_t ift_txd_size[8];
374 uint64_t ift_processed;
375 uint64_t ift_cleaned;
376 uint64_t ift_cleaned_prev;
377 #if MEMORY_LOGGING
378 uint64_t ift_enqueued;
379 uint64_t ift_dequeued;
380 #endif
381 uint64_t ift_no_tx_dma_setup;
382 uint64_t ift_no_desc_avail;
383 uint64_t ift_mbuf_defrag_failed;
384 uint64_t ift_mbuf_defrag;
385 uint64_t ift_map_failed;
386 uint64_t ift_txd_encap_efbig;
387 uint64_t ift_pullups;
388 uint64_t ift_last_timer_tick;
389
390 struct mtx ift_mtx;
391 struct mtx ift_db_mtx;
392
393 /* constant values */
394 if_ctx_t ift_ctx;
395 struct ifmp_ring *ift_br;
396 struct grouptask ift_task;
397 qidx_t ift_size;
398 qidx_t ift_pad;
399 uint16_t ift_id;
400 struct callout ift_timer;
401 #ifdef DEV_NETMAP
402 struct callout ift_netmap_timer;
403 #endif /* DEV_NETMAP */
404
405 if_txsd_vec_t ift_sds;
406 uint8_t ift_qstatus;
407 uint8_t ift_closed;
408 uint8_t ift_update_freq;
409 struct iflib_filter_info ift_filter_info;
410 bus_dma_tag_t ift_buf_tag;
411 bus_dma_tag_t ift_tso_buf_tag;
412 iflib_dma_info_t ift_ifdi;
413 #define MTX_NAME_LEN 32
414 char ift_mtx_name[MTX_NAME_LEN];
415 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE);
416 #ifdef IFLIB_DIAGNOSTICS
417 uint64_t ift_cpu_exec_count[256];
418 #endif
419 } __aligned(CACHE_LINE_SIZE);
420
421 struct iflib_fl {
422 qidx_t ifl_cidx;
423 qidx_t ifl_pidx;
424 qidx_t ifl_credits;
425 uint8_t ifl_gen;
426 uint8_t ifl_rxd_size;
427 #if MEMORY_LOGGING
428 uint64_t ifl_m_enqueued;
429 uint64_t ifl_m_dequeued;
430 uint64_t ifl_cl_enqueued;
431 uint64_t ifl_cl_dequeued;
432 #endif
433 /* implicit pad */
434 bitstr_t *ifl_rx_bitmap;
435 qidx_t ifl_fragidx;
436 /* constant */
437 qidx_t ifl_size;
438 uint16_t ifl_buf_size;
439 uint16_t ifl_cltype;
440 uma_zone_t ifl_zone;
441 iflib_rxsd_array_t ifl_sds;
442 iflib_rxq_t ifl_rxq;
443 uint8_t ifl_id;
444 bus_dma_tag_t ifl_buf_tag;
445 iflib_dma_info_t ifl_ifdi;
446 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE);
447 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH];
448 } __aligned(CACHE_LINE_SIZE);
449
450 static inline qidx_t
get_inuse(int size,qidx_t cidx,qidx_t pidx,uint8_t gen)451 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen)
452 {
453 qidx_t used;
454
455 if (pidx > cidx)
456 used = pidx - cidx;
457 else if (pidx < cidx)
458 used = size - cidx + pidx;
459 else if (gen == 0 && pidx == cidx)
460 used = 0;
461 else if (gen == 1 && pidx == cidx)
462 used = size;
463 else
464 panic("bad state");
465
466 return (used);
467 }
468
469 #define TXQ_AVAIL(txq) ((txq->ift_size - txq->ift_pad) -\
470 get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen))
471
472 #define IDXDIFF(head, tail, wrap) \
473 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
474
475 struct iflib_rxq {
476 if_ctx_t ifr_ctx;
477 iflib_fl_t ifr_fl;
478 uint64_t ifr_rx_irq;
479 struct pfil_head *pfil;
480 /*
481 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is
482 * the completion queue consumer index. Otherwise it's unused.
483 */
484 qidx_t ifr_cq_cidx;
485 uint16_t ifr_id;
486 uint8_t ifr_nfl;
487 uint8_t ifr_ntxqirq;
488 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR];
489 uint8_t ifr_fl_offset;
490 struct lro_ctrl ifr_lc;
491 struct grouptask ifr_task;
492 struct callout ifr_watchdog;
493 struct iflib_filter_info ifr_filter_info;
494 iflib_dma_info_t ifr_ifdi;
495
496 /* dynamically allocate if any drivers need a value substantially larger than this */
497 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE);
498 #ifdef IFLIB_DIAGNOSTICS
499 uint64_t ifr_cpu_exec_count[256];
500 #endif
501 } __aligned(CACHE_LINE_SIZE);
502
503 typedef struct if_rxsd {
504 caddr_t *ifsd_cl;
505 iflib_fl_t ifsd_fl;
506 } *if_rxsd_t;
507
508 /*
509 * Only allow a single packet to take up most 1/nth of the tx ring
510 */
511 #define MAX_SINGLE_PACKET_FRACTION 12
512 #define IF_BAD_DMA ((bus_addr_t)-1)
513
514 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING))
515
516 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock")
517 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx)
518 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx)
519 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx)
520
521 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF)
522 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx)
523 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx)
524 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx)
525
526 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx)
527 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx)
528
529 /* Our boot-time initialization hook */
530 static int iflib_module_event_handler(module_t, int, void *);
531
532 static moduledata_t iflib_moduledata = {
533 "iflib",
534 iflib_module_event_handler,
535 NULL
536 };
537
538 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY);
539 MODULE_VERSION(iflib, 1);
540
541 MODULE_DEPEND(iflib, pci, 1, 1, 1);
542 MODULE_DEPEND(iflib, ether, 1, 1, 1);
543
544 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1);
545 TASKQGROUP_DEFINE(if_config_tqg, 1, 1);
546
547 #ifndef IFLIB_DEBUG_COUNTERS
548 #ifdef INVARIANTS
549 #define IFLIB_DEBUG_COUNTERS 1
550 #else
551 #define IFLIB_DEBUG_COUNTERS 0
552 #endif /* !INVARIANTS */
553 #endif
554
555 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
556 "iflib driver parameters");
557
558 /*
559 * XXX need to ensure that this can't accidentally cause the head to be moved backwards
560 */
561 static int iflib_min_tx_latency = 0;
562 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW,
563 &iflib_min_tx_latency, 0,
564 "minimize transmit latency at the possible expense of throughput");
565 static int iflib_no_tx_batch = 0;
566 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW,
567 &iflib_no_tx_batch, 0,
568 "minimize transmit latency at the possible expense of throughput");
569 static int iflib_timer_default = 1000;
570 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW,
571 &iflib_timer_default, 0, "number of ticks between iflib_timer calls");
572
573
574 #if IFLIB_DEBUG_COUNTERS
575
576 static int iflib_tx_seen;
577 static int iflib_tx_sent;
578 static int iflib_tx_encap;
579 static int iflib_rx_allocs;
580 static int iflib_fl_refills;
581 static int iflib_fl_refills_large;
582 static int iflib_tx_frees;
583
584 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, &iflib_tx_seen, 0,
585 "# TX mbufs seen");
586 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, &iflib_tx_sent, 0,
587 "# TX mbufs sent");
588 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, &iflib_tx_encap, 0,
589 "# TX mbufs encapped");
590 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, &iflib_tx_frees, 0,
591 "# TX frees");
592 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, &iflib_rx_allocs, 0,
593 "# RX allocations");
594 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, &iflib_fl_refills, 0,
595 "# refills");
596 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD,
597 &iflib_fl_refills_large, 0, "# large refills");
598
599 static int iflib_txq_drain_flushing;
600 static int iflib_txq_drain_oactive;
601 static int iflib_txq_drain_notready;
602
603 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD,
604 &iflib_txq_drain_flushing, 0, "# drain flushes");
605 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD,
606 &iflib_txq_drain_oactive, 0, "# drain oactives");
607 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD,
608 &iflib_txq_drain_notready, 0, "# drain notready");
609
610 static int iflib_encap_load_mbuf_fail;
611 static int iflib_encap_pad_mbuf_fail;
612 static int iflib_encap_txq_avail_fail;
613 static int iflib_encap_txd_encap_fail;
614
615 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD,
616 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures");
617 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD,
618 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures");
619 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD,
620 &iflib_encap_txq_avail_fail, 0, "# txq avail failures");
621 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD,
622 &iflib_encap_txd_encap_fail, 0, "# driver encap failures");
623
624 static int iflib_task_fn_rxs;
625 static int iflib_rx_intr_enables;
626 static int iflib_fast_intrs;
627 static int iflib_rx_unavail;
628 static int iflib_rx_ctx_inactive;
629 static int iflib_rx_if_input;
630 static int iflib_rxd_flush;
631
632 static int iflib_verbose_debug;
633
634 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, &iflib_task_fn_rxs, 0,
635 "# task_fn_rx calls");
636 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD,
637 &iflib_rx_intr_enables, 0, "# RX intr enables");
638 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, &iflib_fast_intrs, 0,
639 "# fast_intr calls");
640 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, &iflib_rx_unavail, 0,
641 "# times rxeof called with no available data");
642 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD,
643 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context");
644 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, &iflib_rx_if_input,
645 0, "# times rxeof called if_input");
646 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, &iflib_rxd_flush, 0,
647 "# times rxd_flush called");
648 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW,
649 &iflib_verbose_debug, 0, "enable verbose debugging");
650
651 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1)
652 static void
iflib_debug_reset(void)653 iflib_debug_reset(void)
654 {
655 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs =
656 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees =
657 iflib_txq_drain_flushing = iflib_txq_drain_oactive =
658 iflib_txq_drain_notready =
659 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail =
660 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail =
661 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs =
662 iflib_rx_unavail =
663 iflib_rx_ctx_inactive = iflib_rx_if_input =
664 iflib_rxd_flush = 0;
665 }
666
667 #else
668 #define DBG_COUNTER_INC(name)
iflib_debug_reset(void)669 static void iflib_debug_reset(void) {}
670 #endif
671
672 #define IFLIB_DEBUG 0
673
674 static void iflib_tx_structures_free(if_ctx_t ctx);
675 static void iflib_rx_structures_free(if_ctx_t ctx);
676 static int iflib_queues_alloc(if_ctx_t ctx);
677 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq);
678 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget);
679 static int iflib_qset_structures_setup(if_ctx_t ctx);
680 static int iflib_msix_init(if_ctx_t ctx);
681 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str);
682 static void iflib_txq_check_drain(iflib_txq_t txq, int budget);
683 static uint32_t iflib_txq_can_drain(struct ifmp_ring *);
684 #ifdef ALTQ
685 static void iflib_altq_if_start(if_t ifp);
686 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m);
687 #endif
688 static void iflib_register(if_ctx_t);
689 static void iflib_deregister(if_ctx_t);
690 static void iflib_unregister_vlan_handlers(if_ctx_t ctx);
691 static uint16_t iflib_get_mbuf_size_for(unsigned int size);
692 static void iflib_init_locked(if_ctx_t ctx);
693 static void iflib_add_device_sysctl_pre(if_ctx_t ctx);
694 static void iflib_add_device_sysctl_post(if_ctx_t ctx);
695 static void iflib_ifmp_purge(iflib_txq_t txq);
696 static void _iflib_pre_assert(if_softc_ctx_t scctx);
697 static void iflib_stop(if_ctx_t ctx);
698 static void iflib_if_init_locked(if_ctx_t ctx);
699 static void iflib_free_intr_mem(if_ctx_t ctx);
700 #ifndef __NO_STRICT_ALIGNMENT
701 static struct mbuf *iflib_fixup_rx(struct mbuf *m);
702 #endif
703 static __inline int iflib_completed_tx_reclaim(iflib_txq_t txq,
704 struct mbuf **m_defer);
705
706 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets =
707 SLIST_HEAD_INITIALIZER(cpu_offsets);
708 struct cpu_offset {
709 SLIST_ENTRY(cpu_offset) entries;
710 cpuset_t set;
711 unsigned int refcount;
712 uint16_t next_cpuid;
713 };
714 static struct mtx cpu_offset_mtx;
715 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock",
716 MTX_DEF);
717
718 DEBUGNET_DEFINE(iflib);
719
720 static int
iflib_num_rx_descs(if_ctx_t ctx)721 iflib_num_rx_descs(if_ctx_t ctx)
722 {
723 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
724 if_shared_ctx_t sctx = ctx->ifc_sctx;
725 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0;
726
727 return (scctx->isc_nrxd[first_rxq]);
728 }
729
730 static int
iflib_num_tx_descs(if_ctx_t ctx)731 iflib_num_tx_descs(if_ctx_t ctx)
732 {
733 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
734 if_shared_ctx_t sctx = ctx->ifc_sctx;
735 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0;
736
737 return (scctx->isc_ntxd[first_txq]);
738 }
739
740 #ifdef DEV_NETMAP
741 #include <sys/selinfo.h>
742 #include <net/netmap.h>
743 #include <dev/netmap/netmap_kern.h>
744
745 MODULE_DEPEND(iflib, netmap, 1, 1, 1);
746
747 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init);
748 static void iflib_netmap_timer(void *arg);
749
750 /*
751 * device-specific sysctl variables:
752 *
753 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it.
754 * During regular operations the CRC is stripped, but on some
755 * hardware reception of frames not multiple of 64 is slower,
756 * so using crcstrip=0 helps in benchmarks.
757 *
758 * iflib_rx_miss, iflib_rx_miss_bufs:
759 * count packets that might be missed due to lost interrupts.
760 */
761 SYSCTL_DECL(_dev_netmap);
762 /*
763 * The xl driver by default strips CRCs and we do not override it.
764 */
765
766 int iflib_crcstrip = 1;
767 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip,
768 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames");
769
770 int iflib_rx_miss, iflib_rx_miss_bufs;
771 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss,
772 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr");
773 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs,
774 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs");
775
776 /*
777 * Register/unregister. We are already under netmap lock.
778 * Only called on the first register or the last unregister.
779 */
780 static int
iflib_netmap_register(struct netmap_adapter * na,int onoff)781 iflib_netmap_register(struct netmap_adapter *na, int onoff)
782 {
783 if_t ifp = na->ifp;
784 if_ctx_t ctx = if_getsoftc(ifp);
785 int status;
786
787 CTX_LOCK(ctx);
788 if (!CTX_IS_VF(ctx))
789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip);
790
791 iflib_stop(ctx);
792
793 /*
794 * Enable (or disable) netmap flags, and intercept (or restore)
795 * ifp->if_transmit. This is done once the device has been stopped
796 * to prevent race conditions. Also, this must be done after
797 * calling netmap_disable_all_rings() and before calling
798 * netmap_enable_all_rings(), so that these two functions see the
799 * updated state of the NAF_NETMAP_ON bit.
800 */
801 if (onoff) {
802 nm_set_native_flags(na);
803 } else {
804 nm_clear_native_flags(na);
805 }
806
807 iflib_init_locked(ctx);
808 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ?
809 status = if_getdrvflags(ifp) & IFF_DRV_RUNNING ? 0 : 1;
810 if (status)
811 nm_clear_native_flags(na);
812 CTX_UNLOCK(ctx);
813 return (status);
814 }
815
816 static int
iflib_netmap_config(struct netmap_adapter * na,struct nm_config_info * info)817 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info)
818 {
819 if_t ifp = na->ifp;
820 if_ctx_t ctx = if_getsoftc(ifp);
821 iflib_rxq_t rxq = &ctx->ifc_rxqs[0];
822 iflib_fl_t fl = &rxq->ifr_fl[0];
823
824 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
825 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
826 info->num_tx_descs = iflib_num_tx_descs(ctx);
827 info->num_rx_descs = iflib_num_rx_descs(ctx);
828 info->rx_buf_maxsize = fl->ifl_buf_size;
829 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u",
830 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs,
831 info->num_rx_descs, info->rx_buf_maxsize);
832
833 return (0);
834 }
835
836 static int
netmap_fl_refill(iflib_rxq_t rxq,struct netmap_kring * kring,bool init)837 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init)
838 {
839 struct netmap_adapter *na = kring->na;
840 u_int const lim = kring->nkr_num_slots - 1;
841 struct netmap_ring *ring = kring->ring;
842 bus_dmamap_t *map;
843 struct if_rxd_update iru;
844 if_ctx_t ctx = rxq->ifr_ctx;
845 iflib_fl_t fl = &rxq->ifr_fl[0];
846 u_int nic_i_first, nic_i;
847 u_int nm_i;
848 int i, n;
849 #if IFLIB_DEBUG_COUNTERS
850 int rf_count = 0;
851 #endif
852
853 /*
854 * This function is used both at initialization and in rxsync.
855 * At initialization we need to prepare (with isc_rxd_refill())
856 * all the netmap buffers currently owned by the kernel, in
857 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync
858 * (except for kring->nkr_hwofs). These may be less than
859 * kring->nkr_num_slots if netmap_reset() was called while
860 * an application using the kring that still owned some
861 * buffers.
862 * At rxsync time, both indexes point to the next buffer to be
863 * refilled.
864 * In any case we publish (with isc_rxd_flush()) up to
865 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod
866 * pointer to overrun the head/cons pointer, although this is
867 * not necessary for some NICs (e.g. vmx).
868 */
869 if (__predict_false(init)) {
870 n = kring->nkr_num_slots - nm_kr_rxspace(kring);
871 } else {
872 n = kring->rhead - kring->nr_hwcur;
873 if (n == 0)
874 return (0); /* Nothing to do. */
875 if (n < 0)
876 n += kring->nkr_num_slots;
877 }
878
879 iru_init(&iru, rxq, 0 /* flid */);
880 map = fl->ifl_sds.ifsd_map;
881 nic_i = fl->ifl_pidx;
882 nm_i = netmap_idx_n2k(kring, nic_i);
883 if (__predict_false(init)) {
884 /*
885 * On init/reset, nic_i must be 0, and we must
886 * start to refill from hwtail (see netmap_reset()).
887 */
888 MPASS(nic_i == 0);
889 MPASS(nm_i == kring->nr_hwtail);
890 } else
891 MPASS(nm_i == kring->nr_hwcur);
892 DBG_COUNTER_INC(fl_refills);
893 while (n > 0) {
894 #if IFLIB_DEBUG_COUNTERS
895 if (++rf_count == 9)
896 DBG_COUNTER_INC(fl_refills_large);
897 #endif
898 nic_i_first = nic_i;
899 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) {
900 struct netmap_slot *slot = &ring->slot[nm_i];
901 uint64_t paddr;
902 void *addr = PNMB(na, slot, &paddr);
903
904 MPASS(i < IFLIB_MAX_RX_REFRESH);
905
906 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */
907 return (netmap_ring_reinit(kring));
908
909 fl->ifl_bus_addrs[i] = paddr +
910 nm_get_offset(kring, slot);
911 fl->ifl_rxd_idxs[i] = nic_i;
912
913 if (__predict_false(init)) {
914 netmap_load_map(na, fl->ifl_buf_tag,
915 map[nic_i], addr);
916 } else if (slot->flags & NS_BUF_CHANGED) {
917 /* buffer has changed, reload map */
918 netmap_reload_map(na, fl->ifl_buf_tag,
919 map[nic_i], addr);
920 }
921 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i],
922 BUS_DMASYNC_PREREAD);
923 slot->flags &= ~NS_BUF_CHANGED;
924
925 nm_i = nm_next(nm_i, lim);
926 nic_i = nm_next(nic_i, lim);
927 }
928
929 iru.iru_pidx = nic_i_first;
930 iru.iru_count = i;
931 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
932 }
933 fl->ifl_pidx = nic_i;
934 /*
935 * At the end of the loop we must have refilled everything
936 * we could possibly refill.
937 */
938 MPASS(nm_i == kring->rhead);
939 kring->nr_hwcur = nm_i;
940
941 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
942 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
943 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id,
944 nm_prev(nic_i, lim));
945 DBG_COUNTER_INC(rxd_flush);
946
947 return (0);
948 }
949
950 #define NETMAP_TX_TIMER_US 90
951
952 /*
953 * Reconcile kernel and user view of the transmit ring.
954 *
955 * All information is in the kring.
956 * Userspace wants to send packets up to the one before kring->rhead,
957 * kernel knows kring->nr_hwcur is the first unsent packet.
958 *
959 * Here we push packets out (as many as possible), and possibly
960 * reclaim buffers from previously completed transmission.
961 *
962 * The caller (netmap) guarantees that there is only one instance
963 * running at any time. Any interference with other driver
964 * methods should be handled by the individual drivers.
965 */
966 static int
iflib_netmap_txsync(struct netmap_kring * kring,int flags)967 iflib_netmap_txsync(struct netmap_kring *kring, int flags)
968 {
969 struct netmap_adapter *na = kring->na;
970 if_t ifp = na->ifp;
971 struct netmap_ring *ring = kring->ring;
972 u_int nm_i; /* index into the netmap kring */
973 u_int nic_i; /* index into the NIC ring */
974 u_int const lim = kring->nkr_num_slots - 1;
975 u_int const head = kring->rhead;
976 struct if_pkt_info pi;
977 int tx_pkts = 0, tx_bytes = 0;
978
979 /*
980 * interrupts on every tx packet are expensive so request
981 * them every half ring, or where NS_REPORT is set
982 */
983 u_int report_frequency = kring->nkr_num_slots >> 1;
984 /* device-specific */
985 if_ctx_t ctx = if_getsoftc(ifp);
986 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id];
987
988 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
989 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
990
991 /*
992 * First part: process new packets to send.
993 * nm_i is the current index in the netmap kring,
994 * nic_i is the corresponding index in the NIC ring.
995 *
996 * If we have packets to send (nm_i != head)
997 * iterate over the netmap ring, fetch length and update
998 * the corresponding slot in the NIC ring. Some drivers also
999 * need to update the buffer's physical address in the NIC slot
1000 * even NS_BUF_CHANGED is not set (PNMB computes the addresses).
1001 *
1002 * The netmap_reload_map() calls is especially expensive,
1003 * even when (as in this case) the tag is 0, so do only
1004 * when the buffer has actually changed.
1005 *
1006 * If possible do not set the report/intr bit on all slots,
1007 * but only a few times per ring or when NS_REPORT is set.
1008 *
1009 * Finally, on 10G and faster drivers, it might be useful
1010 * to prefetch the next slot and txr entry.
1011 */
1012
1013 nm_i = kring->nr_hwcur;
1014 if (nm_i != head) { /* we have new packets to send */
1015 uint32_t pkt_len = 0, seg_idx = 0;
1016 int nic_i_start = -1, flags = 0;
1017 memset(&pi, 0, sizeof(pi));
1018 pi.ipi_segs = txq->ift_segs;
1019 pi.ipi_qsidx = kring->ring_id;
1020 nic_i = netmap_idx_k2n(kring, nm_i);
1021
1022 __builtin_prefetch(&ring->slot[nm_i]);
1023 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]);
1024 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]);
1025
1026 while (nm_i != head) {
1027 struct netmap_slot *slot = &ring->slot[nm_i];
1028 uint64_t offset = nm_get_offset(kring, slot);
1029 u_int len = slot->len;
1030 uint64_t paddr;
1031 void *addr = PNMB(na, slot, &paddr);
1032
1033 flags |= (slot->flags & NS_REPORT ||
1034 nic_i == 0 || nic_i == report_frequency) ?
1035 IPI_TX_INTR : 0;
1036
1037 /*
1038 * If this is the first packet fragment, save the
1039 * index of the first NIC slot for later.
1040 */
1041 if (nic_i_start < 0)
1042 nic_i_start = nic_i;
1043
1044 pi.ipi_segs[seg_idx].ds_addr = paddr + offset;
1045 pi.ipi_segs[seg_idx].ds_len = len;
1046 if (len) {
1047 pkt_len += len;
1048 seg_idx++;
1049 }
1050
1051 if (!(slot->flags & NS_MOREFRAG)) {
1052 pi.ipi_len = pkt_len;
1053 pi.ipi_nsegs = seg_idx;
1054 pi.ipi_pidx = nic_i_start;
1055 pi.ipi_ndescs = 0;
1056 pi.ipi_flags = flags;
1057
1058 /* Prepare the NIC TX ring. */
1059 ctx->isc_txd_encap(ctx->ifc_softc, &pi);
1060 DBG_COUNTER_INC(tx_encap);
1061
1062 /* Update transmit counters */
1063 tx_bytes += pi.ipi_len;
1064 tx_pkts++;
1065
1066 /* Reinit per-packet info for the next one. */
1067 flags = seg_idx = pkt_len = 0;
1068 nic_i_start = -1;
1069 }
1070
1071 /* prefetch for next round */
1072 __builtin_prefetch(&ring->slot[nm_i + 1]);
1073 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]);
1074 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]);
1075
1076 NM_CHECK_ADDR_LEN_OFF(na, len, offset);
1077
1078 if (slot->flags & NS_BUF_CHANGED) {
1079 /* buffer has changed, reload map */
1080 netmap_reload_map(na, txq->ift_buf_tag,
1081 txq->ift_sds.ifsd_map[nic_i], addr);
1082 }
1083 /* make sure changes to the buffer are synced */
1084 bus_dmamap_sync(txq->ift_buf_tag,
1085 txq->ift_sds.ifsd_map[nic_i],
1086 BUS_DMASYNC_PREWRITE);
1087
1088 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG);
1089 nm_i = nm_next(nm_i, lim);
1090 nic_i = nm_next(nic_i, lim);
1091 }
1092 kring->nr_hwcur = nm_i;
1093
1094 /* synchronize the NIC ring */
1095 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1096 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1097
1098 /* (re)start the tx unit up to slot nic_i (excluded) */
1099 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i);
1100 }
1101
1102 /*
1103 * Second part: reclaim buffers for completed transmissions.
1104 *
1105 * If there are unclaimed buffers, attempt to reclaim them.
1106 * If we don't manage to reclaim them all, and TX IRQs are not in use,
1107 * trigger a per-tx-queue timer to try again later.
1108 */
1109 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1110 if (iflib_tx_credits_update(ctx, txq)) {
1111 /* some tx completed, increment avail */
1112 nic_i = txq->ift_cidx_processed;
1113 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim);
1114 }
1115 }
1116
1117 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ))
1118 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) {
1119 callout_reset_sbt_on(&txq->ift_netmap_timer,
1120 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US,
1121 iflib_netmap_timer, txq,
1122 txq->ift_netmap_timer.c_cpu, 0);
1123 }
1124
1125 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes);
1126 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts);
1127
1128 return (0);
1129 }
1130
1131 /*
1132 * Reconcile kernel and user view of the receive ring.
1133 * Same as for the txsync, this routine must be efficient.
1134 * The caller guarantees a single invocations, but races against
1135 * the rest of the driver should be handled here.
1136 *
1137 * On call, kring->rhead is the first packet that userspace wants
1138 * to keep, and kring->rcur is the wakeup point.
1139 * The kernel has previously reported packets up to kring->rtail.
1140 *
1141 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective
1142 * of whether or not we received an interrupt.
1143 */
1144 static int
iflib_netmap_rxsync(struct netmap_kring * kring,int flags)1145 iflib_netmap_rxsync(struct netmap_kring *kring, int flags)
1146 {
1147 struct netmap_adapter *na = kring->na;
1148 struct netmap_ring *ring = kring->ring;
1149 if_t ifp = na->ifp;
1150 uint32_t nm_i; /* index into the netmap ring */
1151 uint32_t nic_i; /* index into the NIC ring */
1152 u_int n;
1153 u_int const lim = kring->nkr_num_slots - 1;
1154 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1155 int i = 0, rx_bytes = 0, rx_pkts = 0;
1156
1157 if_ctx_t ctx = if_getsoftc(ifp);
1158 if_shared_ctx_t sctx = ctx->ifc_sctx;
1159 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1160 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id];
1161 iflib_fl_t fl = &rxq->ifr_fl[0];
1162 struct if_rxd_info ri;
1163 qidx_t *cidxp;
1164
1165 /*
1166 * netmap only uses free list 0, to avoid out of order consumption
1167 * of receive buffers
1168 */
1169
1170 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
1171 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1172
1173 /*
1174 * First part: import newly received packets.
1175 *
1176 * nm_i is the index of the next free slot in the netmap ring,
1177 * nic_i is the index of the next received packet in the NIC ring
1178 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may
1179 * differ in case if_init() has been called while
1180 * in netmap mode. For the receive ring we have
1181 *
1182 * nic_i = fl->ifl_cidx;
1183 * nm_i = kring->nr_hwtail (previous)
1184 * and
1185 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1186 *
1187 * fl->ifl_cidx is set to 0 on a ring reinit
1188 */
1189 if (netmap_no_pendintr || force_update) {
1190 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim);
1191 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ;
1192 int crclen = iflib_crcstrip ? 0 : 4;
1193 int error, avail;
1194
1195 /*
1196 * For the free list consumer index, we use the same
1197 * logic as in iflib_rxeof().
1198 */
1199 if (have_rxcq)
1200 cidxp = &rxq->ifr_cq_cidx;
1201 else
1202 cidxp = &fl->ifl_cidx;
1203 avail = ctx->isc_rxd_available(ctx->ifc_softc,
1204 rxq->ifr_id, *cidxp, USHRT_MAX);
1205
1206 nic_i = fl->ifl_cidx;
1207 nm_i = netmap_idx_n2k(kring, nic_i);
1208 MPASS(nm_i == kring->nr_hwtail);
1209 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) {
1210 memset(&ri, 0, sizeof(ri));
1211 ri.iri_frags = rxq->ifr_frags;
1212 ri.iri_qsidx = kring->ring_id;
1213 ri.iri_ifp = ctx->ifc_ifp;
1214 ri.iri_cidx = *cidxp;
1215
1216 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
1217 for (i = 0; i < ri.iri_nfrags; i++) {
1218 if (error) {
1219 ring->slot[nm_i].len = 0;
1220 ring->slot[nm_i].flags = 0;
1221 } else {
1222 ring->slot[nm_i].len = ri.iri_frags[i].irf_len;
1223 if (i == (ri.iri_nfrags - 1)) {
1224 ring->slot[nm_i].len -= crclen;
1225 ring->slot[nm_i].flags = 0;
1226
1227 /* Update receive counters */
1228 rx_bytes += ri.iri_len;
1229 rx_pkts++;
1230 } else
1231 ring->slot[nm_i].flags = NS_MOREFRAG;
1232 }
1233
1234 bus_dmamap_sync(fl->ifl_buf_tag,
1235 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD);
1236 nm_i = nm_next(nm_i, lim);
1237 fl->ifl_cidx = nic_i = nm_next(nic_i, lim);
1238 }
1239
1240 if (have_rxcq) {
1241 *cidxp = ri.iri_cidx;
1242 while (*cidxp >= scctx->isc_nrxd[0])
1243 *cidxp -= scctx->isc_nrxd[0];
1244 }
1245
1246 }
1247 if (n) { /* update the state variables */
1248 if (netmap_no_pendintr && !force_update) {
1249 /* diagnostics */
1250 iflib_rx_miss++;
1251 iflib_rx_miss_bufs += n;
1252 }
1253 kring->nr_hwtail = nm_i;
1254 }
1255 kring->nr_kflags &= ~NKR_PENDINTR;
1256 }
1257 /*
1258 * Second part: skip past packets that userspace has released.
1259 * (kring->nr_hwcur to head excluded),
1260 * and make the buffers available for reception.
1261 * As usual nm_i is the index in the netmap ring,
1262 * nic_i is the index in the NIC ring, and
1263 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size
1264 */
1265 netmap_fl_refill(rxq, kring, false);
1266
1267 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
1268 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
1269
1270 return (0);
1271 }
1272
1273 static void
iflib_netmap_intr(struct netmap_adapter * na,int onoff)1274 iflib_netmap_intr(struct netmap_adapter *na, int onoff)
1275 {
1276 if_ctx_t ctx = if_getsoftc(na->ifp);
1277
1278 CTX_LOCK(ctx);
1279 if (onoff) {
1280 IFDI_INTR_ENABLE(ctx);
1281 } else {
1282 IFDI_INTR_DISABLE(ctx);
1283 }
1284 CTX_UNLOCK(ctx);
1285 }
1286
1287 static int
iflib_netmap_attach(if_ctx_t ctx)1288 iflib_netmap_attach(if_ctx_t ctx)
1289 {
1290 struct netmap_adapter na;
1291
1292 bzero(&na, sizeof(na));
1293
1294 na.ifp = ctx->ifc_ifp;
1295 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS;
1296 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets);
1297 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets);
1298
1299 na.num_tx_desc = iflib_num_tx_descs(ctx);
1300 na.num_rx_desc = iflib_num_rx_descs(ctx);
1301 na.nm_txsync = iflib_netmap_txsync;
1302 na.nm_rxsync = iflib_netmap_rxsync;
1303 na.nm_register = iflib_netmap_register;
1304 na.nm_intr = iflib_netmap_intr;
1305 na.nm_config = iflib_netmap_config;
1306 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets;
1307 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets;
1308 return (netmap_attach(&na));
1309 }
1310
1311 static int
iflib_netmap_txq_init(if_ctx_t ctx,iflib_txq_t txq)1312 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq)
1313 {
1314 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1315 struct netmap_slot *slot;
1316
1317 slot = netmap_reset(na, NR_TX, txq->ift_id, 0);
1318 if (slot == NULL)
1319 return (0);
1320 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) {
1321 /*
1322 * In netmap mode, set the map for the packet buffer.
1323 * NOTE: Some drivers (not this one) also need to set
1324 * the physical buffer address in the NIC ring.
1325 * netmap_idx_n2k() maps a nic index, i, into the corresponding
1326 * netmap slot index, si
1327 */
1328 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i);
1329 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i],
1330 NMB(na, slot + si));
1331 }
1332 return (1);
1333 }
1334
1335 static int
iflib_netmap_rxq_init(if_ctx_t ctx,iflib_rxq_t rxq)1336 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq)
1337 {
1338 struct netmap_adapter *na = NA(ctx->ifc_ifp);
1339 struct netmap_kring *kring;
1340 struct netmap_slot *slot;
1341
1342 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0);
1343 if (slot == NULL)
1344 return (0);
1345 kring = na->rx_rings[rxq->ifr_id];
1346 netmap_fl_refill(rxq, kring, true);
1347 return (1);
1348 }
1349
1350 static void
iflib_netmap_timer(void * arg)1351 iflib_netmap_timer(void *arg)
1352 {
1353 iflib_txq_t txq = arg;
1354 if_ctx_t ctx = txq->ift_ctx;
1355
1356 /*
1357 * Wake up the netmap application, to give it a chance to
1358 * call txsync and reclaim more completed TX buffers.
1359 */
1360 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id);
1361 }
1362
1363 #define iflib_netmap_detach(ifp) netmap_detach(ifp)
1364
1365 #else
1366 #define iflib_netmap_txq_init(ctx, txq) (0)
1367 #define iflib_netmap_rxq_init(ctx, rxq) (0)
1368 #define iflib_netmap_detach(ifp)
1369 #define netmap_enable_all_rings(ifp)
1370 #define netmap_disable_all_rings(ifp)
1371
1372 #define iflib_netmap_attach(ctx) (0)
1373 #define netmap_rx_irq(ifp, qid, budget) (0)
1374 #endif
1375
1376 #if defined(__i386__) || defined(__amd64__)
1377 static __inline void
prefetch(void * x)1378 prefetch(void *x)
1379 {
1380 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1381 }
1382
1383 static __inline void
prefetch2cachelines(void * x)1384 prefetch2cachelines(void *x)
1385 {
1386 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1387 #if (CACHE_LINE_SIZE < 128)
1388 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x) + CACHE_LINE_SIZE / (sizeof(unsigned long)))));
1389 #endif
1390 }
1391 #else
1392 static __inline void
prefetch(void * x)1393 prefetch(void *x)
1394 {
1395 }
1396
1397 static __inline void
prefetch2cachelines(void * x)1398 prefetch2cachelines(void *x)
1399 {
1400 }
1401 #endif
1402
1403 static void
iru_init(if_rxd_update_t iru,iflib_rxq_t rxq,uint8_t flid)1404 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid)
1405 {
1406 iflib_fl_t fl;
1407
1408 fl = &rxq->ifr_fl[flid];
1409 iru->iru_paddrs = fl->ifl_bus_addrs;
1410 iru->iru_idxs = fl->ifl_rxd_idxs;
1411 iru->iru_qsidx = rxq->ifr_id;
1412 iru->iru_buf_size = fl->ifl_buf_size;
1413 iru->iru_flidx = fl->ifl_id;
1414 }
1415
1416 static void
_iflib_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int err)1417 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
1418 {
1419 if (err)
1420 return;
1421 *(bus_addr_t *) arg = segs[0].ds_addr;
1422 }
1423
1424 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \
1425 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \
1426 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL)
1427
1428 int
iflib_dma_alloc_align(if_ctx_t ctx,int size,int align,iflib_dma_info_t dma,int mapflags)1429 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags)
1430 {
1431 int err;
1432 device_t dev = ctx->ifc_dev;
1433 bus_addr_t lowaddr;
1434
1435 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width);
1436
1437 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1438 align, 0, /* alignment, bounds */
1439 lowaddr, /* lowaddr */
1440 BUS_SPACE_MAXADDR, /* highaddr */
1441 NULL, NULL, /* filter, filterarg */
1442 size, /* maxsize */
1443 1, /* nsegments */
1444 size, /* maxsegsize */
1445 BUS_DMA_ALLOCNOW, /* flags */
1446 NULL, /* lockfunc */
1447 NULL, /* lockarg */
1448 &dma->idi_tag);
1449 if (err) {
1450 device_printf(dev,
1451 "%s: bus_dma_tag_create failed: %d (size=%d, align=%d)\n",
1452 __func__, err, size, align);
1453 goto fail_0;
1454 }
1455
1456 err = bus_dmamem_alloc(dma->idi_tag, (void **)&dma->idi_vaddr,
1457 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map);
1458 if (err) {
1459 device_printf(dev,
1460 "%s: bus_dmamem_alloc(%ju) failed: %d\n",
1461 __func__, (uintmax_t)size, err);
1462 goto fail_1;
1463 }
1464
1465 dma->idi_paddr = IF_BAD_DMA;
1466 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr,
1467 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT);
1468 if (err || dma->idi_paddr == IF_BAD_DMA) {
1469 device_printf(dev,
1470 "%s: bus_dmamap_load failed: %d\n",
1471 __func__, err);
1472 goto fail_2;
1473 }
1474
1475 dma->idi_size = size;
1476 return (0);
1477
1478 fail_2:
1479 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1480 fail_1:
1481 bus_dma_tag_destroy(dma->idi_tag);
1482 fail_0:
1483 dma->idi_tag = NULL;
1484
1485 return (err);
1486 }
1487
1488 int
iflib_dma_alloc(if_ctx_t ctx,int size,iflib_dma_info_t dma,int mapflags)1489 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags)
1490 {
1491 if_shared_ctx_t sctx = ctx->ifc_sctx;
1492
1493 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized"));
1494
1495 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags));
1496 }
1497
1498 int
iflib_dma_alloc_multi(if_ctx_t ctx,int * sizes,iflib_dma_info_t * dmalist,int mapflags,int count)1499 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count)
1500 {
1501 int i, err;
1502 iflib_dma_info_t *dmaiter;
1503
1504 dmaiter = dmalist;
1505 for (i = 0; i < count; i++, dmaiter++) {
1506 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0)
1507 break;
1508 }
1509 if (err)
1510 iflib_dma_free_multi(dmalist, i);
1511 return (err);
1512 }
1513
1514 void
iflib_dma_free(iflib_dma_info_t dma)1515 iflib_dma_free(iflib_dma_info_t dma)
1516 {
1517 if (dma->idi_tag == NULL)
1518 return;
1519 if (dma->idi_paddr != IF_BAD_DMA) {
1520 bus_dmamap_sync(dma->idi_tag, dma->idi_map,
1521 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1522 bus_dmamap_unload(dma->idi_tag, dma->idi_map);
1523 dma->idi_paddr = IF_BAD_DMA;
1524 }
1525 if (dma->idi_vaddr != NULL) {
1526 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map);
1527 dma->idi_vaddr = NULL;
1528 }
1529 bus_dma_tag_destroy(dma->idi_tag);
1530 dma->idi_tag = NULL;
1531 }
1532
1533 void
iflib_dma_free_multi(iflib_dma_info_t * dmalist,int count)1534 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count)
1535 {
1536 int i;
1537 iflib_dma_info_t *dmaiter = dmalist;
1538
1539 for (i = 0; i < count; i++, dmaiter++)
1540 iflib_dma_free(*dmaiter);
1541 }
1542
1543 static int
iflib_fast_intr(void * arg)1544 iflib_fast_intr(void *arg)
1545 {
1546 iflib_filter_info_t info = arg;
1547 struct grouptask *gtask = info->ifi_task;
1548 int result;
1549
1550 DBG_COUNTER_INC(fast_intrs);
1551 if (info->ifi_filter != NULL) {
1552 result = info->ifi_filter(info->ifi_filter_arg);
1553 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1554 return (result);
1555 }
1556
1557 GROUPTASK_ENQUEUE(gtask);
1558 return (FILTER_HANDLED);
1559 }
1560
1561 static int
iflib_fast_intr_rxtx(void * arg)1562 iflib_fast_intr_rxtx(void *arg)
1563 {
1564 iflib_filter_info_t info = arg;
1565 struct grouptask *gtask = info->ifi_task;
1566 if_ctx_t ctx;
1567 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx;
1568 iflib_txq_t txq;
1569 void *sc;
1570 int i, cidx, result;
1571 qidx_t txqid;
1572 bool intr_enable, intr_legacy;
1573
1574 DBG_COUNTER_INC(fast_intrs);
1575 if (info->ifi_filter != NULL) {
1576 result = info->ifi_filter(info->ifi_filter_arg);
1577 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1578 return (result);
1579 }
1580
1581 ctx = rxq->ifr_ctx;
1582 sc = ctx->ifc_softc;
1583 intr_enable = false;
1584 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY);
1585 MPASS(rxq->ifr_ntxqirq);
1586 for (i = 0; i < rxq->ifr_ntxqirq; i++) {
1587 txqid = rxq->ifr_txqid[i];
1588 txq = &ctx->ifc_txqs[txqid];
1589 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
1590 BUS_DMASYNC_POSTREAD);
1591 if (!ctx->isc_txd_credits_update(sc, txqid, false)) {
1592 if (intr_legacy)
1593 intr_enable = true;
1594 else
1595 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid);
1596 continue;
1597 }
1598 GROUPTASK_ENQUEUE(&txq->ift_task);
1599 }
1600 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ)
1601 cidx = rxq->ifr_cq_cidx;
1602 else
1603 cidx = rxq->ifr_fl[0].ifl_cidx;
1604 if (iflib_rxd_avail(ctx, rxq, cidx, 1))
1605 GROUPTASK_ENQUEUE(gtask);
1606 else {
1607 if (intr_legacy)
1608 intr_enable = true;
1609 else
1610 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
1611 DBG_COUNTER_INC(rx_intr_enables);
1612 }
1613 if (intr_enable)
1614 IFDI_INTR_ENABLE(ctx);
1615 return (FILTER_HANDLED);
1616 }
1617
1618 static int
iflib_fast_intr_ctx(void * arg)1619 iflib_fast_intr_ctx(void *arg)
1620 {
1621 iflib_filter_info_t info = arg;
1622 if_ctx_t ctx = info->ifi_ctx;
1623 int result;
1624
1625 DBG_COUNTER_INC(fast_intrs);
1626 if (info->ifi_filter != NULL) {
1627 result = info->ifi_filter(info->ifi_filter_arg);
1628 if ((result & FILTER_SCHEDULE_THREAD) == 0)
1629 return (result);
1630 }
1631
1632 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task);
1633 return (FILTER_HANDLED);
1634 }
1635
1636 static int
_iflib_irq_alloc(if_ctx_t ctx,if_irq_t irq,int rid,driver_filter_t filter,driver_intr_t handler,void * arg,const char * name)1637 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
1638 driver_filter_t filter, driver_intr_t handler, void *arg,
1639 const char *name)
1640 {
1641 struct resource *res;
1642 void *tag = NULL;
1643 device_t dev = ctx->ifc_dev;
1644 int flags, i, rc;
1645
1646 flags = RF_ACTIVE;
1647 if (ctx->ifc_flags & IFC_LEGACY)
1648 flags |= RF_SHAREABLE;
1649 MPASS(rid < 512);
1650 i = rid;
1651 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags);
1652 if (res == NULL) {
1653 device_printf(dev,
1654 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
1655 return (ENOMEM);
1656 }
1657 irq->ii_res = res;
1658 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL"));
1659 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET,
1660 filter, handler, arg, &tag);
1661 if (rc != 0) {
1662 device_printf(dev,
1663 "failed to setup interrupt for rid %d, name %s: %d\n",
1664 rid, name ? name : "unknown", rc);
1665 return (rc);
1666 } else if (name)
1667 bus_describe_intr(dev, res, tag, "%s", name);
1668
1669 irq->ii_tag = tag;
1670 return (0);
1671 }
1672
1673 /*********************************************************************
1674 *
1675 * Allocate DMA resources for TX buffers as well as memory for the TX
1676 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a
1677 * iflib_sw_tx_desc_array structure, storing all the information that
1678 * is needed to transmit a packet on the wire. This is called only
1679 * once at attach, setup is done every reset.
1680 *
1681 **********************************************************************/
1682 static int
iflib_txsd_alloc(iflib_txq_t txq)1683 iflib_txsd_alloc(iflib_txq_t txq)
1684 {
1685 if_ctx_t ctx = txq->ift_ctx;
1686 if_shared_ctx_t sctx = ctx->ifc_sctx;
1687 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1688 device_t dev = ctx->ifc_dev;
1689 bus_size_t tsomaxsize;
1690 bus_addr_t lowaddr;
1691 int err, nsegments, ntsosegments;
1692 bool tso;
1693
1694 nsegments = scctx->isc_tx_nsegments;
1695 ntsosegments = scctx->isc_tx_tso_segments_max;
1696 tsomaxsize = scctx->isc_tx_tso_size_max;
1697 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU)
1698 tsomaxsize += sizeof(struct ether_vlan_header);
1699 MPASS(scctx->isc_ntxd[0] > 0);
1700 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0);
1701 MPASS(nsegments > 0);
1702 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) {
1703 MPASS(ntsosegments > 0);
1704 MPASS(sctx->isc_tso_maxsize >= tsomaxsize);
1705 }
1706
1707 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1708
1709 /*
1710 * Set up DMA tags for TX buffers.
1711 */
1712 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev),
1713 1, 0, /* alignment, bounds */
1714 lowaddr, /* lowaddr */
1715 BUS_SPACE_MAXADDR, /* highaddr */
1716 NULL, NULL, /* filter, filterarg */
1717 sctx->isc_tx_maxsize, /* maxsize */
1718 nsegments, /* nsegments */
1719 sctx->isc_tx_maxsegsize, /* maxsegsize */
1720 0, /* flags */
1721 NULL, /* lockfunc */
1722 NULL, /* lockfuncarg */
1723 &txq->ift_buf_tag))) {
1724 device_printf(dev, "Unable to allocate TX DMA tag: %d\n", err);
1725 device_printf(dev, "maxsize: %ju nsegments: %d maxsegsize: %ju\n",
1726 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize);
1727 goto fail;
1728 }
1729 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0;
1730 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev),
1731 1, 0, /* alignment, bounds */
1732 lowaddr, /* lowaddr */
1733 BUS_SPACE_MAXADDR, /* highaddr */
1734 NULL, NULL, /* filter, filterarg */
1735 tsomaxsize, /* maxsize */
1736 ntsosegments, /* nsegments */
1737 sctx->isc_tso_maxsegsize, /* maxsegsize */
1738 0, /* flags */
1739 NULL, /* lockfunc */
1740 NULL, /* lockfuncarg */
1741 &txq->ift_tso_buf_tag))) {
1742 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n",
1743 err);
1744 goto fail;
1745 }
1746
1747 /* Allocate memory for the TX mbuf map. */
1748 if (!(txq->ift_sds.ifsd_m =
1749 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1750 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1751 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1752 err = ENOMEM;
1753 goto fail;
1754 }
1755 if (ctx->ifc_sysctl_simple_tx) {
1756 if (!(txq->ift_sds.ifsd_m_defer =
1757 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1758 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1759 device_printf(dev, "Unable to allocate TX mbuf map memory\n");
1760 err = ENOMEM;
1761 goto fail;
1762 }
1763 }
1764 txq->ift_sds.ifsd_m_deferb = txq->ift_sds.ifsd_m_defer;
1765 /*
1766 * Create the DMA maps for TX buffers.
1767 */
1768 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc(
1769 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1770 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1771 device_printf(dev,
1772 "Unable to allocate TX buffer DMA map memory\n");
1773 err = ENOMEM;
1774 goto fail;
1775 }
1776 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc(
1777 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset],
1778 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
1779 device_printf(dev,
1780 "Unable to allocate TSO TX buffer map memory\n");
1781 err = ENOMEM;
1782 goto fail;
1783 }
1784 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) {
1785 err = bus_dmamap_create(txq->ift_buf_tag, 0,
1786 &txq->ift_sds.ifsd_map[i]);
1787 if (err != 0) {
1788 device_printf(dev, "Unable to create TX DMA map\n");
1789 goto fail;
1790 }
1791 if (!tso)
1792 continue;
1793 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0,
1794 &txq->ift_sds.ifsd_tso_map[i]);
1795 if (err != 0) {
1796 device_printf(dev, "Unable to create TSO TX DMA map\n");
1797 goto fail;
1798 }
1799 }
1800 return (0);
1801 fail:
1802 /* We free all, it handles case where we are in the middle */
1803 iflib_tx_structures_free(ctx);
1804 return (err);
1805 }
1806
1807 static void
iflib_txsd_destroy(if_ctx_t ctx,iflib_txq_t txq,int i)1808 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i)
1809 {
1810 bus_dmamap_t map;
1811
1812 if (txq->ift_sds.ifsd_map != NULL) {
1813 map = txq->ift_sds.ifsd_map[i];
1814 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE);
1815 bus_dmamap_unload(txq->ift_buf_tag, map);
1816 bus_dmamap_destroy(txq->ift_buf_tag, map);
1817 txq->ift_sds.ifsd_map[i] = NULL;
1818 }
1819
1820 if (txq->ift_sds.ifsd_tso_map != NULL) {
1821 map = txq->ift_sds.ifsd_tso_map[i];
1822 bus_dmamap_sync(txq->ift_tso_buf_tag, map,
1823 BUS_DMASYNC_POSTWRITE);
1824 bus_dmamap_unload(txq->ift_tso_buf_tag, map);
1825 bus_dmamap_destroy(txq->ift_tso_buf_tag, map);
1826 txq->ift_sds.ifsd_tso_map[i] = NULL;
1827 }
1828 }
1829
1830 static void
iflib_txq_destroy(iflib_txq_t txq)1831 iflib_txq_destroy(iflib_txq_t txq)
1832 {
1833 if_ctx_t ctx = txq->ift_ctx;
1834
1835 for (int i = 0; i < txq->ift_size; i++)
1836 iflib_txsd_destroy(ctx, txq, i);
1837
1838 if (txq->ift_br != NULL) {
1839 ifmp_ring_free(txq->ift_br);
1840 txq->ift_br = NULL;
1841 }
1842
1843 mtx_destroy(&txq->ift_mtx);
1844
1845 if (txq->ift_sds.ifsd_map != NULL) {
1846 free(txq->ift_sds.ifsd_map, M_IFLIB);
1847 txq->ift_sds.ifsd_map = NULL;
1848 }
1849 if (txq->ift_sds.ifsd_tso_map != NULL) {
1850 free(txq->ift_sds.ifsd_tso_map, M_IFLIB);
1851 txq->ift_sds.ifsd_tso_map = NULL;
1852 }
1853 if (txq->ift_sds.ifsd_m != NULL) {
1854 free(txq->ift_sds.ifsd_m, M_IFLIB);
1855 txq->ift_sds.ifsd_m = NULL;
1856 }
1857 if (txq->ift_sds.ifsd_m_defer != NULL) {
1858 free(txq->ift_sds.ifsd_m_defer, M_IFLIB);
1859 txq->ift_sds.ifsd_m_defer = NULL;
1860 }
1861 if (txq->ift_buf_tag != NULL) {
1862 bus_dma_tag_destroy(txq->ift_buf_tag);
1863 txq->ift_buf_tag = NULL;
1864 }
1865 if (txq->ift_tso_buf_tag != NULL) {
1866 bus_dma_tag_destroy(txq->ift_tso_buf_tag);
1867 txq->ift_tso_buf_tag = NULL;
1868 }
1869 if (txq->ift_ifdi != NULL) {
1870 free(txq->ift_ifdi, M_IFLIB);
1871 }
1872 }
1873
1874 static void
iflib_txsd_free(if_ctx_t ctx,iflib_txq_t txq,int i)1875 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i)
1876 {
1877 struct mbuf *m;
1878
1879 m = IFLIB_GET_MBUF(txq->ift_sds.ifsd_m[i]);
1880 if (m == NULL)
1881 return;
1882
1883 if (txq->ift_sds.ifsd_map != NULL) {
1884 bus_dmamap_sync(txq->ift_buf_tag,
1885 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE);
1886 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]);
1887 }
1888 if (txq->ift_sds.ifsd_tso_map != NULL) {
1889 bus_dmamap_sync(txq->ift_tso_buf_tag,
1890 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE);
1891 bus_dmamap_unload(txq->ift_tso_buf_tag,
1892 txq->ift_sds.ifsd_tso_map[i]);
1893 }
1894 txq->ift_sds.ifsd_m[i] = NULL;
1895 m_freem(m);
1896 DBG_COUNTER_INC(tx_frees);
1897 }
1898
1899 static int
iflib_txq_setup(iflib_txq_t txq)1900 iflib_txq_setup(iflib_txq_t txq)
1901 {
1902 if_ctx_t ctx = txq->ift_ctx;
1903 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1904 if_shared_ctx_t sctx = ctx->ifc_sctx;
1905 iflib_dma_info_t di;
1906 int i;
1907
1908 /* Set number of descriptors available */
1909 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
1910 /* XXX make configurable */
1911 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ;
1912
1913 /* Reset indices */
1914 txq->ift_cidx_processed = 0;
1915 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0;
1916 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset];
1917 txq->ift_pad = scctx->isc_tx_pad;
1918
1919 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1920 bzero((void *)di->idi_vaddr, di->idi_size);
1921
1922 IFDI_TXQ_SETUP(ctx, txq->ift_id);
1923 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++)
1924 bus_dmamap_sync(di->idi_tag, di->idi_map,
1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1926 return (0);
1927 }
1928
1929 /*********************************************************************
1930 *
1931 * Allocate DMA resources for RX buffers as well as memory for the RX
1932 * mbuf map, direct RX cluster pointer map and RX cluster bus address
1933 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and
1934 * RX cluster map are kept in a iflib_sw_rx_desc_array structure.
1935 * Since we use use one entry in iflib_sw_rx_desc_array per received
1936 * packet, the maximum number of entries we'll need is equal to the
1937 * number of hardware receive descriptors that we've allocated.
1938 *
1939 **********************************************************************/
1940 static int
iflib_rxsd_alloc(iflib_rxq_t rxq)1941 iflib_rxsd_alloc(iflib_rxq_t rxq)
1942 {
1943 if_ctx_t ctx = rxq->ifr_ctx;
1944 if_shared_ctx_t sctx = ctx->ifc_sctx;
1945 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
1946 device_t dev = ctx->ifc_dev;
1947 iflib_fl_t fl;
1948 bus_addr_t lowaddr;
1949 int err;
1950
1951 MPASS(scctx->isc_nrxd[0] > 0);
1952 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0);
1953
1954 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width);
1955
1956 fl = rxq->ifr_fl;
1957 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) {
1958 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */
1959 /* Set up DMA tag for RX buffers. */
1960 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1961 1, 0, /* alignment, bounds */
1962 lowaddr, /* lowaddr */
1963 BUS_SPACE_MAXADDR, /* highaddr */
1964 NULL, NULL, /* filter, filterarg */
1965 sctx->isc_rx_maxsize, /* maxsize */
1966 sctx->isc_rx_nsegments, /* nsegments */
1967 sctx->isc_rx_maxsegsize, /* maxsegsize */
1968 0, /* flags */
1969 NULL, /* lockfunc */
1970 NULL, /* lockarg */
1971 &fl->ifl_buf_tag);
1972 if (err) {
1973 device_printf(dev,
1974 "Unable to allocate RX DMA tag: %d\n", err);
1975 goto fail;
1976 }
1977
1978 /* Allocate memory for the RX mbuf map. */
1979 if (!(fl->ifl_sds.ifsd_m =
1980 (struct mbuf **) malloc(sizeof(struct mbuf *) *
1981 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1982 device_printf(dev,
1983 "Unable to allocate RX mbuf map memory\n");
1984 err = ENOMEM;
1985 goto fail;
1986 }
1987
1988 /* Allocate memory for the direct RX cluster pointer map. */
1989 if (!(fl->ifl_sds.ifsd_cl =
1990 (caddr_t *) malloc(sizeof(caddr_t) *
1991 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
1992 device_printf(dev,
1993 "Unable to allocate RX cluster map memory\n");
1994 err = ENOMEM;
1995 goto fail;
1996 }
1997
1998 /* Allocate memory for the RX cluster bus address map. */
1999 if (!(fl->ifl_sds.ifsd_ba =
2000 (bus_addr_t *) malloc(sizeof(bus_addr_t) *
2001 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2002 device_printf(dev,
2003 "Unable to allocate RX bus address map memory\n");
2004 err = ENOMEM;
2005 goto fail;
2006 }
2007
2008 /*
2009 * Create the DMA maps for RX buffers.
2010 */
2011 if (!(fl->ifl_sds.ifsd_map =
2012 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) {
2013 device_printf(dev,
2014 "Unable to allocate RX buffer DMA map memory\n");
2015 err = ENOMEM;
2016 goto fail;
2017 }
2018 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) {
2019 err = bus_dmamap_create(fl->ifl_buf_tag, 0,
2020 &fl->ifl_sds.ifsd_map[i]);
2021 if (err != 0) {
2022 device_printf(dev, "Unable to create RX buffer DMA map\n");
2023 goto fail;
2024 }
2025 }
2026 }
2027 return (0);
2028
2029 fail:
2030 iflib_rx_structures_free(ctx);
2031 return (err);
2032 }
2033
2034 /*
2035 * Internal service routines
2036 */
2037
2038 struct rxq_refill_cb_arg {
2039 int error;
2040 bus_dma_segment_t seg;
2041 int nseg;
2042 };
2043
2044 static void
_rxq_refill_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)2045 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2046 {
2047 struct rxq_refill_cb_arg *cb_arg = arg;
2048
2049 cb_arg->error = error;
2050 cb_arg->seg = segs[0];
2051 cb_arg->nseg = nseg;
2052 }
2053
2054 /**
2055 * iflib_fl_refill - refill an rxq free-buffer list
2056 * @ctx: the iflib context
2057 * @fl: the free list to refill
2058 * @count: the number of new buffers to allocate
2059 *
2060 * (Re)populate an rxq free-buffer list with up to @count new packet buffers.
2061 * The caller must assure that @count does not exceed the queue's capacity
2062 * minus one (since we always leave a descriptor unavailable).
2063 */
2064 static uint8_t
iflib_fl_refill(if_ctx_t ctx,iflib_fl_t fl,int count)2065 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count)
2066 {
2067 struct if_rxd_update iru;
2068 struct rxq_refill_cb_arg cb_arg;
2069 struct mbuf *m;
2070 caddr_t cl, *sd_cl;
2071 struct mbuf **sd_m;
2072 bus_dmamap_t *sd_map;
2073 bus_addr_t bus_addr, *sd_ba;
2074 int err, frag_idx, i, idx, n, pidx;
2075 qidx_t credits;
2076
2077 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1);
2078
2079 sd_m = fl->ifl_sds.ifsd_m;
2080 sd_map = fl->ifl_sds.ifsd_map;
2081 sd_cl = fl->ifl_sds.ifsd_cl;
2082 sd_ba = fl->ifl_sds.ifsd_ba;
2083 pidx = fl->ifl_pidx;
2084 idx = pidx;
2085 frag_idx = fl->ifl_fragidx;
2086 credits = fl->ifl_credits;
2087
2088 i = 0;
2089 n = count;
2090 MPASS(n > 0);
2091 MPASS(credits + n <= fl->ifl_size);
2092
2093 if (pidx < fl->ifl_cidx)
2094 MPASS(pidx + n <= fl->ifl_cidx);
2095 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size))
2096 MPASS(fl->ifl_gen == 0);
2097 if (pidx > fl->ifl_cidx)
2098 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx);
2099
2100 DBG_COUNTER_INC(fl_refills);
2101 if (n > 8)
2102 DBG_COUNTER_INC(fl_refills_large);
2103 iru_init(&iru, fl->ifl_rxq, fl->ifl_id);
2104 while (n-- > 0) {
2105 /*
2106 * We allocate an uninitialized mbuf + cluster, mbuf is
2107 * initialized after rx.
2108 *
2109 * If the cluster is still set then we know a minimum sized
2110 * packet was received
2111 */
2112 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size,
2113 &frag_idx);
2114 if (frag_idx < 0)
2115 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx);
2116 MPASS(frag_idx >= 0);
2117 if ((cl = sd_cl[frag_idx]) == NULL) {
2118 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT);
2119 if (__predict_false(cl == NULL))
2120 break;
2121
2122 cb_arg.error = 0;
2123 MPASS(sd_map != NULL);
2124 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx],
2125 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg,
2126 BUS_DMA_NOWAIT);
2127 if (__predict_false(err != 0 || cb_arg.error)) {
2128 uma_zfree(fl->ifl_zone, cl);
2129 break;
2130 }
2131
2132 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr;
2133 sd_cl[frag_idx] = cl;
2134 #if MEMORY_LOGGING
2135 fl->ifl_cl_enqueued++;
2136 #endif
2137 } else {
2138 bus_addr = sd_ba[frag_idx];
2139 }
2140 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx],
2141 BUS_DMASYNC_PREREAD);
2142
2143 if (sd_m[frag_idx] == NULL) {
2144 m = m_gethdr_raw(M_NOWAIT, 0);
2145 if (__predict_false(m == NULL))
2146 break;
2147 sd_m[frag_idx] = m;
2148 }
2149 bit_set(fl->ifl_rx_bitmap, frag_idx);
2150 #if MEMORY_LOGGING
2151 fl->ifl_m_enqueued++;
2152 #endif
2153
2154 DBG_COUNTER_INC(rx_allocs);
2155 fl->ifl_rxd_idxs[i] = frag_idx;
2156 fl->ifl_bus_addrs[i] = bus_addr;
2157 credits++;
2158 i++;
2159 MPASS(credits <= fl->ifl_size);
2160 if (++idx == fl->ifl_size) {
2161 #ifdef INVARIANTS
2162 fl->ifl_gen = 1;
2163 #endif
2164 idx = 0;
2165 }
2166 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) {
2167 iru.iru_pidx = pidx;
2168 iru.iru_count = i;
2169 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2170 fl->ifl_pidx = idx;
2171 fl->ifl_credits = credits;
2172 pidx = idx;
2173 i = 0;
2174 }
2175 }
2176
2177 if (n < count - 1) {
2178 if (i != 0) {
2179 iru.iru_pidx = pidx;
2180 iru.iru_count = i;
2181 ctx->isc_rxd_refill(ctx->ifc_softc, &iru);
2182 fl->ifl_pidx = idx;
2183 fl->ifl_credits = credits;
2184 }
2185 DBG_COUNTER_INC(rxd_flush);
2186 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2187 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2188 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id,
2189 fl->ifl_id, fl->ifl_pidx);
2190 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) {
2191 fl->ifl_fragidx = frag_idx + 1;
2192 if (fl->ifl_fragidx == fl->ifl_size)
2193 fl->ifl_fragidx = 0;
2194 } else {
2195 fl->ifl_fragidx = frag_idx;
2196 }
2197 }
2198
2199 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY);
2200 }
2201
2202 static inline uint8_t
iflib_fl_refill_all(if_ctx_t ctx,iflib_fl_t fl)2203 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl)
2204 {
2205 /*
2206 * We leave an unused descriptor to avoid pidx to catch up with cidx.
2207 * This is important as it confuses most NICs. For instance,
2208 * Intel NICs have (per receive ring) RDH and RDT registers, where
2209 * RDH points to the next receive descriptor to be used by the NIC,
2210 * and RDT for the next receive descriptor to be published by the
2211 * driver to the NIC (RDT - 1 is thus the last valid one).
2212 * The condition RDH == RDT means no descriptors are available to
2213 * the NIC, and thus it would be ambiguous if it also meant that
2214 * all the descriptors are available to the NIC.
2215 */
2216 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1;
2217 #ifdef INVARIANTS
2218 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1;
2219 #endif
2220
2221 MPASS(fl->ifl_credits <= fl->ifl_size);
2222 MPASS(reclaimable == delta);
2223
2224 if (reclaimable > 0)
2225 return (iflib_fl_refill(ctx, fl, reclaimable));
2226 return (0);
2227 }
2228
2229 uint8_t
iflib_in_detach(if_ctx_t ctx)2230 iflib_in_detach(if_ctx_t ctx)
2231 {
2232 bool in_detach;
2233
2234 STATE_LOCK(ctx);
2235 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH);
2236 STATE_UNLOCK(ctx);
2237 return (in_detach);
2238 }
2239
2240 static void
iflib_fl_bufs_free(iflib_fl_t fl)2241 iflib_fl_bufs_free(iflib_fl_t fl)
2242 {
2243 iflib_dma_info_t idi = fl->ifl_ifdi;
2244 bus_dmamap_t sd_map;
2245 uint32_t i;
2246
2247 for (i = 0; i < fl->ifl_size; i++) {
2248 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i];
2249 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i];
2250
2251 if (*sd_cl != NULL) {
2252 sd_map = fl->ifl_sds.ifsd_map[i];
2253 bus_dmamap_sync(fl->ifl_buf_tag, sd_map,
2254 BUS_DMASYNC_POSTREAD);
2255 bus_dmamap_unload(fl->ifl_buf_tag, sd_map);
2256 uma_zfree(fl->ifl_zone, *sd_cl);
2257 *sd_cl = NULL;
2258 if (*sd_m != NULL) {
2259 m_init(*sd_m, M_NOWAIT, MT_DATA, 0);
2260 m_free_raw(*sd_m);
2261 *sd_m = NULL;
2262 }
2263 } else {
2264 MPASS(*sd_m == NULL);
2265 }
2266 #if MEMORY_LOGGING
2267 fl->ifl_m_dequeued++;
2268 fl->ifl_cl_dequeued++;
2269 #endif
2270 }
2271 #ifdef INVARIANTS
2272 for (i = 0; i < fl->ifl_size; i++) {
2273 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL);
2274 MPASS(fl->ifl_sds.ifsd_m[i] == NULL);
2275 }
2276 #endif
2277 /*
2278 * Reset free list values
2279 */
2280 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0;
2281 bzero(idi->idi_vaddr, idi->idi_size);
2282 }
2283
2284 /*********************************************************************
2285 *
2286 * Initialize a free list and its buffers.
2287 *
2288 **********************************************************************/
2289 static int
iflib_fl_setup(iflib_fl_t fl)2290 iflib_fl_setup(iflib_fl_t fl)
2291 {
2292 iflib_rxq_t rxq = fl->ifl_rxq;
2293 if_ctx_t ctx = rxq->ifr_ctx;
2294 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2295 int qidx;
2296
2297 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1);
2298 /*
2299 * Free current RX buffer structs and their mbufs
2300 */
2301 iflib_fl_bufs_free(fl);
2302 /* Now replenish the mbufs */
2303 MPASS(fl->ifl_credits == 0);
2304 qidx = rxq->ifr_fl_offset + fl->ifl_id;
2305 if (scctx->isc_rxd_buf_size[qidx] != 0)
2306 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx];
2307 else
2308 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz;
2309 /*
2310 * ifl_buf_size may be a driver-supplied value, so pull it up
2311 * to the selected mbuf size.
2312 */
2313 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size);
2314 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size)
2315 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size;
2316 fl->ifl_cltype = m_gettype(fl->ifl_buf_size);
2317 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
2318
2319 /*
2320 * Avoid pre-allocating zillions of clusters to an idle card
2321 * potentially speeding up attach. In any case make sure
2322 * to leave a descriptor unavailable. See the comment in
2323 * iflib_fl_refill_all().
2324 */
2325 MPASS(fl->ifl_size > 0);
2326 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1));
2327 if (min(128, fl->ifl_size - 1) != fl->ifl_credits)
2328 return (ENOBUFS);
2329 /*
2330 * handle failure
2331 */
2332 MPASS(rxq != NULL);
2333 MPASS(fl->ifl_ifdi != NULL);
2334 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
2335 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2336 return (0);
2337 }
2338
2339 /*********************************************************************
2340 *
2341 * Free receive ring data structures
2342 *
2343 **********************************************************************/
2344 static void
iflib_rx_sds_free(iflib_rxq_t rxq)2345 iflib_rx_sds_free(iflib_rxq_t rxq)
2346 {
2347 iflib_fl_t fl;
2348 int i, j;
2349
2350 if (rxq->ifr_fl != NULL) {
2351 for (i = 0; i < rxq->ifr_nfl; i++) {
2352 fl = &rxq->ifr_fl[i];
2353 if (fl->ifl_buf_tag != NULL) {
2354 if (fl->ifl_sds.ifsd_map != NULL) {
2355 for (j = 0; j < fl->ifl_size; j++) {
2356 bus_dmamap_sync(
2357 fl->ifl_buf_tag,
2358 fl->ifl_sds.ifsd_map[j],
2359 BUS_DMASYNC_POSTREAD);
2360 bus_dmamap_unload(
2361 fl->ifl_buf_tag,
2362 fl->ifl_sds.ifsd_map[j]);
2363 bus_dmamap_destroy(
2364 fl->ifl_buf_tag,
2365 fl->ifl_sds.ifsd_map[j]);
2366 }
2367 }
2368 bus_dma_tag_destroy(fl->ifl_buf_tag);
2369 fl->ifl_buf_tag = NULL;
2370 }
2371 free(fl->ifl_sds.ifsd_m, M_IFLIB);
2372 free(fl->ifl_sds.ifsd_cl, M_IFLIB);
2373 free(fl->ifl_sds.ifsd_ba, M_IFLIB);
2374 free(fl->ifl_sds.ifsd_map, M_IFLIB);
2375 free(fl->ifl_rx_bitmap, M_IFLIB);
2376 fl->ifl_sds.ifsd_m = NULL;
2377 fl->ifl_sds.ifsd_cl = NULL;
2378 fl->ifl_sds.ifsd_ba = NULL;
2379 fl->ifl_sds.ifsd_map = NULL;
2380 fl->ifl_rx_bitmap = NULL;
2381 }
2382 free(rxq->ifr_fl, M_IFLIB);
2383 rxq->ifr_fl = NULL;
2384 free(rxq->ifr_ifdi, M_IFLIB);
2385 rxq->ifr_ifdi = NULL;
2386 rxq->ifr_cq_cidx = 0;
2387 }
2388 }
2389
2390 /*
2391 * Timer routine
2392 */
2393 static void
iflib_timer(void * arg)2394 iflib_timer(void *arg)
2395 {
2396 iflib_txq_t txq = arg;
2397 if_ctx_t ctx = txq->ift_ctx;
2398 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2399 uint64_t this_tick = ticks;
2400
2401 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))
2402 return;
2403
2404 /*
2405 ** Check on the state of the TX queue(s), this
2406 ** can be done without the lock because its RO
2407 ** and the HUNG state will be static if set.
2408 */
2409 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) {
2410 txq->ift_last_timer_tick = this_tick;
2411 IFDI_TIMER(ctx, txq->ift_id);
2412 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) &&
2413 ((txq->ift_cleaned_prev == txq->ift_cleaned) ||
2414 (sctx->isc_pause_frames == 0)))
2415 goto hung;
2416
2417 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE &&
2418 ifmp_ring_is_stalled(txq->ift_br)) {
2419 KASSERT(ctx->ifc_link_state == LINK_STATE_UP,
2420 ("queue can't be marked as hung if interface is down"));
2421 txq->ift_qstatus = IFLIB_QUEUE_HUNG;
2422 }
2423 txq->ift_cleaned_prev = txq->ift_cleaned;
2424 }
2425 /* handle any laggards */
2426 if (txq->ift_db_pending)
2427 GROUPTASK_ENQUEUE(&txq->ift_task);
2428
2429 sctx->isc_pause_frames = 0;
2430 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)
2431 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer,
2432 txq, txq->ift_timer.c_cpu);
2433 return;
2434
2435 hung:
2436 device_printf(ctx->ifc_dev,
2437 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n",
2438 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx);
2439 STATE_LOCK(ctx);
2440 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2441 ctx->ifc_flags |= (IFC_DO_WATCHDOG | IFC_DO_RESET);
2442 iflib_admin_intr_deferred(ctx);
2443 STATE_UNLOCK(ctx);
2444 }
2445
2446 static uint16_t
iflib_get_mbuf_size_for(unsigned int size)2447 iflib_get_mbuf_size_for(unsigned int size)
2448 {
2449
2450 if (size <= MCLBYTES)
2451 return (MCLBYTES);
2452 else
2453 return (MJUMPAGESIZE);
2454 }
2455
2456 static void
iflib_calc_rx_mbuf_sz(if_ctx_t ctx)2457 iflib_calc_rx_mbuf_sz(if_ctx_t ctx)
2458 {
2459 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
2460
2461 /*
2462 * XXX don't set the max_frame_size to larger
2463 * than the hardware can handle
2464 */
2465 ctx->ifc_rx_mbuf_sz =
2466 iflib_get_mbuf_size_for(sctx->isc_max_frame_size);
2467 }
2468
2469 uint32_t
iflib_get_rx_mbuf_sz(if_ctx_t ctx)2470 iflib_get_rx_mbuf_sz(if_ctx_t ctx)
2471 {
2472
2473 return (ctx->ifc_rx_mbuf_sz);
2474 }
2475
2476 static void
iflib_init_locked(if_ctx_t ctx)2477 iflib_init_locked(if_ctx_t ctx)
2478 {
2479 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2480 if_t ifp = ctx->ifc_ifp;
2481 iflib_fl_t fl;
2482 iflib_txq_t txq;
2483 iflib_rxq_t rxq;
2484 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags;
2485
2486 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2487 IFDI_INTR_DISABLE(ctx);
2488
2489 /*
2490 * See iflib_stop(). Useful in case iflib_init_locked() is
2491 * called without first calling iflib_stop().
2492 */
2493 netmap_disable_all_rings(ifp);
2494
2495 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP);
2496 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP);
2497 /* Set hardware offload abilities */
2498 if_clearhwassist(ifp);
2499 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
2500 if_sethwassistbits(ifp, tx_ip_csum_flags, 0);
2501 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
2502 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0);
2503 if (if_getcapenable(ifp) & IFCAP_TSO4)
2504 if_sethwassistbits(ifp, CSUM_IP_TSO, 0);
2505 if (if_getcapenable(ifp) & IFCAP_TSO6)
2506 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0);
2507
2508 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
2509 CALLOUT_LOCK(txq);
2510 callout_stop(&txq->ift_timer);
2511 #ifdef DEV_NETMAP
2512 callout_stop(&txq->ift_netmap_timer);
2513 #endif /* DEV_NETMAP */
2514 CALLOUT_UNLOCK(txq);
2515 (void)iflib_netmap_txq_init(ctx, txq);
2516 }
2517
2518 /*
2519 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so
2520 * that drivers can use the value when setting up the hardware receive
2521 * buffers.
2522 */
2523 iflib_calc_rx_mbuf_sz(ctx);
2524
2525 #ifdef INVARIANTS
2526 i = if_getdrvflags(ifp);
2527 #endif
2528 IFDI_INIT(ctx);
2529 MPASS(if_getdrvflags(ifp) == i);
2530 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
2531 if (iflib_netmap_rxq_init(ctx, rxq) > 0) {
2532 /* This rxq is in netmap mode. Skip normal init. */
2533 continue;
2534 }
2535 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
2536 if (iflib_fl_setup(fl)) {
2537 device_printf(ctx->ifc_dev,
2538 "setting up free list %d failed - "
2539 "check cluster settings\n", j);
2540 goto done;
2541 }
2542 }
2543 }
2544 done:
2545 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2546 IFDI_INTR_ENABLE(ctx);
2547 txq = ctx->ifc_txqs;
2548 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++)
2549 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
2550 txq->ift_timer.c_cpu);
2551
2552 /* Re-enable txsync/rxsync. */
2553 netmap_enable_all_rings(ifp);
2554 }
2555
2556 static int
iflib_media_change(if_t ifp)2557 iflib_media_change(if_t ifp)
2558 {
2559 if_ctx_t ctx = if_getsoftc(ifp);
2560 int err;
2561
2562 CTX_LOCK(ctx);
2563 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0)
2564 iflib_if_init_locked(ctx);
2565 CTX_UNLOCK(ctx);
2566 return (err);
2567 }
2568
2569 static void
iflib_media_status(if_t ifp,struct ifmediareq * ifmr)2570 iflib_media_status(if_t ifp, struct ifmediareq *ifmr)
2571 {
2572 if_ctx_t ctx = if_getsoftc(ifp);
2573
2574 CTX_LOCK(ctx);
2575 IFDI_UPDATE_ADMIN_STATUS(ctx);
2576 IFDI_MEDIA_STATUS(ctx, ifmr);
2577 CTX_UNLOCK(ctx);
2578 }
2579
2580 static void
iflib_stop(if_ctx_t ctx)2581 iflib_stop(if_ctx_t ctx)
2582 {
2583 iflib_txq_t txq = ctx->ifc_txqs;
2584 iflib_rxq_t rxq = ctx->ifc_rxqs;
2585 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2586 if_shared_ctx_t sctx = ctx->ifc_sctx;
2587 iflib_dma_info_t di;
2588 iflib_fl_t fl;
2589 int i, j;
2590
2591 /* Tell the stack that the interface is no longer active */
2592 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING);
2593
2594 IFDI_INTR_DISABLE(ctx);
2595 DELAY(1000);
2596 IFDI_STOP(ctx);
2597 DELAY(1000);
2598
2599 /*
2600 * Stop any pending txsync/rxsync and prevent new ones
2601 * form starting. Processes blocked in poll() will get
2602 * POLLERR.
2603 */
2604 netmap_disable_all_rings(ctx->ifc_ifp);
2605
2606 iflib_debug_reset();
2607 /* Wait for current tx queue users to exit to disarm watchdog timer. */
2608 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) {
2609 /* make sure all transmitters have completed before proceeding XXX */
2610
2611 CALLOUT_LOCK(txq);
2612 callout_stop(&txq->ift_timer);
2613 #ifdef DEV_NETMAP
2614 callout_stop(&txq->ift_netmap_timer);
2615 #endif /* DEV_NETMAP */
2616 CALLOUT_UNLOCK(txq);
2617
2618 if (!ctx->ifc_sysctl_simple_tx) {
2619 /* clean any enqueued buffers */
2620 iflib_ifmp_purge(txq);
2621 }
2622 /* Free any existing tx buffers. */
2623 for (j = 0; j < txq->ift_size; j++) {
2624 iflib_txsd_free(ctx, txq, j);
2625 }
2626 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0;
2627 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0;
2628 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES)
2629 txq->ift_cidx = txq->ift_pidx;
2630 else
2631 txq->ift_cidx = txq->ift_pidx = 0;
2632
2633 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0;
2634 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0;
2635 txq->ift_pullups = 0;
2636 ifmp_ring_reset_stats(txq->ift_br);
2637 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++)
2638 bzero((void *)di->idi_vaddr, di->idi_size);
2639 }
2640 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) {
2641 if (rxq->ifr_task.gt_taskqueue != NULL)
2642 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue,
2643 &rxq->ifr_task.gt_task);
2644
2645 rxq->ifr_cq_cidx = 0;
2646 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++)
2647 bzero((void *)di->idi_vaddr, di->idi_size);
2648 /* also resets the free lists pidx/cidx */
2649 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
2650 iflib_fl_bufs_free(fl);
2651 }
2652 }
2653
2654 static inline caddr_t
calc_next_rxd(iflib_fl_t fl,int cidx)2655 calc_next_rxd(iflib_fl_t fl, int cidx)
2656 {
2657 qidx_t size;
2658 int nrxd;
2659 caddr_t start, end, cur, next;
2660
2661 nrxd = fl->ifl_size;
2662 size = fl->ifl_rxd_size;
2663 start = fl->ifl_ifdi->idi_vaddr;
2664
2665 if (__predict_false(size == 0))
2666 return (start);
2667 cur = start + size * cidx;
2668 end = start + size * nrxd;
2669 next = CACHE_PTR_NEXT(cur);
2670 return (next < end ? next : start);
2671 }
2672
2673 static inline void
prefetch_pkts(iflib_fl_t fl,int cidx)2674 prefetch_pkts(iflib_fl_t fl, int cidx)
2675 {
2676 int nextptr;
2677 int nrxd = fl->ifl_size;
2678 caddr_t next_rxd;
2679
2680 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd - 1);
2681 prefetch(&fl->ifl_sds.ifsd_m[nextptr]);
2682 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]);
2683 next_rxd = calc_next_rxd(fl, cidx);
2684 prefetch(next_rxd);
2685 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd - 1)]);
2686 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd - 1)]);
2687 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd - 1)]);
2688 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd - 1)]);
2689 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd - 1)]);
2690 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd - 1)]);
2691 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd - 1)]);
2692 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd - 1)]);
2693 }
2694
2695 static struct mbuf *
rxd_frag_to_sd(iflib_rxq_t rxq,if_rxd_frag_t irf,bool unload,if_rxsd_t sd,int * pf_rv,if_rxd_info_t ri)2696 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd,
2697 int *pf_rv, if_rxd_info_t ri)
2698 {
2699 bus_dmamap_t map;
2700 iflib_fl_t fl;
2701 caddr_t payload;
2702 struct mbuf *m;
2703 int flid, cidx, len, next;
2704
2705 map = NULL;
2706 flid = irf->irf_flid;
2707 cidx = irf->irf_idx;
2708 fl = &rxq->ifr_fl[flid];
2709 sd->ifsd_fl = fl;
2710 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx];
2711 fl->ifl_credits--;
2712 #if MEMORY_LOGGING
2713 fl->ifl_m_dequeued++;
2714 #endif
2715 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH)
2716 prefetch_pkts(fl, cidx);
2717 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size - 1);
2718 prefetch(&fl->ifl_sds.ifsd_map[next]);
2719 map = fl->ifl_sds.ifsd_map[cidx];
2720
2721 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD);
2722
2723 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL &&
2724 irf->irf_len != 0) {
2725 payload = *sd->ifsd_cl;
2726 payload += ri->iri_pad;
2727 len = ri->iri_len - ri->iri_pad;
2728 *pf_rv = pfil_mem_in(rxq->pfil, payload, len, ri->iri_ifp, &m);
2729 switch (*pf_rv) {
2730 case PFIL_DROPPED:
2731 case PFIL_CONSUMED:
2732 /*
2733 * The filter ate it. Everything is recycled.
2734 */
2735 m = NULL;
2736 unload = 0;
2737 break;
2738 case PFIL_REALLOCED:
2739 /*
2740 * The filter copied it. Everything is recycled.
2741 * 'm' points at new mbuf.
2742 */
2743 unload = 0;
2744 break;
2745 case PFIL_PASS:
2746 /*
2747 * Filter said it was OK, so receive like
2748 * normal
2749 */
2750 m = fl->ifl_sds.ifsd_m[cidx];
2751 fl->ifl_sds.ifsd_m[cidx] = NULL;
2752 break;
2753 default:
2754 MPASS(0);
2755 }
2756 } else {
2757 m = fl->ifl_sds.ifsd_m[cidx];
2758 fl->ifl_sds.ifsd_m[cidx] = NULL;
2759 if (pf_rv != NULL)
2760 *pf_rv = PFIL_PASS;
2761 }
2762
2763 if (unload && irf->irf_len != 0)
2764 bus_dmamap_unload(fl->ifl_buf_tag, map);
2765 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size - 1);
2766 if (__predict_false(fl->ifl_cidx == 0))
2767 fl->ifl_gen = 0;
2768 bit_clear(fl->ifl_rx_bitmap, cidx);
2769 return (m);
2770 }
2771
2772 static struct mbuf *
assemble_segments(iflib_rxq_t rxq,if_rxd_info_t ri,if_rxsd_t sd,int * pf_rv)2773 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv)
2774 {
2775 struct mbuf *m, *mh, *mt;
2776 caddr_t cl;
2777 int *pf_rv_ptr, flags, i, padlen;
2778 bool consumed;
2779
2780 i = 0;
2781 mh = NULL;
2782 consumed = false;
2783 *pf_rv = PFIL_PASS;
2784 pf_rv_ptr = pf_rv;
2785 do {
2786 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd,
2787 pf_rv_ptr, ri);
2788
2789 MPASS(*sd->ifsd_cl != NULL);
2790
2791 /*
2792 * Exclude zero-length frags & frags from
2793 * packets the filter has consumed or dropped
2794 */
2795 if (ri->iri_frags[i].irf_len == 0 || consumed ||
2796 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) {
2797 if (mh == NULL) {
2798 /* everything saved here */
2799 consumed = true;
2800 pf_rv_ptr = NULL;
2801 continue;
2802 }
2803 /* XXX we can save the cluster here, but not the mbuf */
2804 m_init(m, M_NOWAIT, MT_DATA, 0);
2805 m_free(m);
2806 continue;
2807 }
2808 if (mh == NULL) {
2809 flags = M_PKTHDR | M_EXT;
2810 mh = mt = m;
2811 padlen = ri->iri_pad;
2812 } else {
2813 flags = M_EXT;
2814 mt->m_next = m;
2815 mt = m;
2816 /* assuming padding is only on the first fragment */
2817 padlen = 0;
2818 }
2819 cl = *sd->ifsd_cl;
2820 *sd->ifsd_cl = NULL;
2821
2822 /* Can these two be made one ? */
2823 m_init(m, M_NOWAIT, MT_DATA, flags);
2824 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype);
2825 /*
2826 * These must follow m_init and m_cljset
2827 */
2828 m->m_data += padlen;
2829 ri->iri_len -= padlen;
2830 m->m_len = ri->iri_frags[i].irf_len;
2831 } while (++i < ri->iri_nfrags);
2832
2833 return (mh);
2834 }
2835
2836 /*
2837 * Process one software descriptor
2838 */
2839 static struct mbuf *
iflib_rxd_pkt_get(iflib_rxq_t rxq,if_rxd_info_t ri)2840 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri)
2841 {
2842 struct if_rxsd sd;
2843 struct mbuf *m;
2844 int pf_rv;
2845
2846 /* should I merge this back in now that the two paths are basically duplicated? */
2847 if (ri->iri_nfrags == 1 &&
2848 ri->iri_frags[0].irf_len != 0 &&
2849 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) {
2850 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd,
2851 &pf_rv, ri);
2852 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2853 return (m);
2854 if (pf_rv == PFIL_PASS) {
2855 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR);
2856 #ifndef __NO_STRICT_ALIGNMENT
2857 if (!IP_ALIGNED(m) && ri->iri_pad == 0)
2858 m->m_data += 2;
2859 #endif
2860 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len);
2861 m->m_len = ri->iri_frags[0].irf_len;
2862 m->m_data += ri->iri_pad;
2863 ri->iri_len -= ri->iri_pad;
2864 }
2865 } else {
2866 m = assemble_segments(rxq, ri, &sd, &pf_rv);
2867 if (m == NULL)
2868 return (NULL);
2869 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED)
2870 return (m);
2871 }
2872 m->m_pkthdr.len = ri->iri_len;
2873 m->m_pkthdr.rcvif = ri->iri_ifp;
2874 m->m_flags |= ri->iri_flags;
2875 m->m_pkthdr.ether_vtag = ri->iri_vtag;
2876 m->m_pkthdr.flowid = ri->iri_flowid;
2877 #ifdef NUMA
2878 m->m_pkthdr.numa_domain = if_getnumadomain(ri->iri_ifp);
2879 #endif
2880 M_HASHTYPE_SET(m, ri->iri_rsstype);
2881 m->m_pkthdr.csum_flags = ri->iri_csum_flags;
2882 m->m_pkthdr.csum_data = ri->iri_csum_data;
2883 return (m);
2884 }
2885
2886 static void
_task_fn_rx_watchdog(void * context)2887 _task_fn_rx_watchdog(void *context)
2888 {
2889 iflib_rxq_t rxq = context;
2890
2891 GROUPTASK_ENQUEUE(&rxq->ifr_task);
2892 }
2893
2894 static uint8_t
iflib_rxeof(iflib_rxq_t rxq,qidx_t budget)2895 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget)
2896 {
2897 if_t ifp;
2898 if_ctx_t ctx = rxq->ifr_ctx;
2899 if_shared_ctx_t sctx = ctx->ifc_sctx;
2900 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
2901 int avail, i;
2902 qidx_t *cidxp;
2903 struct if_rxd_info ri;
2904 int err, budget_left, rx_bytes, rx_pkts;
2905 iflib_fl_t fl;
2906 #if defined(INET6) || defined(INET)
2907 int lro_enabled;
2908 #endif
2909 uint8_t retval = 0;
2910
2911 /*
2912 * XXX early demux data packets so that if_input processing only handles
2913 * acks in interrupt context
2914 */
2915 struct mbuf *m, *mh, *mt;
2916
2917 NET_EPOCH_ASSERT();
2918
2919 ifp = ctx->ifc_ifp;
2920 mh = mt = NULL;
2921 MPASS(budget > 0);
2922 rx_pkts = rx_bytes = 0;
2923 if (sctx->isc_flags & IFLIB_HAS_RXCQ)
2924 cidxp = &rxq->ifr_cq_cidx;
2925 else
2926 cidxp = &rxq->ifr_fl[0].ifl_cidx;
2927 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) {
2928 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
2929 retval |= iflib_fl_refill_all(ctx, fl);
2930 DBG_COUNTER_INC(rx_unavail);
2931 return (retval);
2932 }
2933
2934 #if defined(INET6) || defined(INET)
2935 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO);
2936 #endif
2937
2938 /* pfil needs the vnet to be set */
2939 CURVNET_SET_QUIET(if_getvnet(ifp));
2940 for (budget_left = budget; budget_left > 0 && avail > 0;) {
2941 if (__predict_false(!CTX_ACTIVE(ctx))) {
2942 DBG_COUNTER_INC(rx_ctx_inactive);
2943 break;
2944 }
2945 /*
2946 * Reset client set fields to their default values
2947 */
2948 memset(&ri, 0, sizeof(ri));
2949 ri.iri_qsidx = rxq->ifr_id;
2950 ri.iri_cidx = *cidxp;
2951 ri.iri_ifp = ifp;
2952 ri.iri_frags = rxq->ifr_frags;
2953 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri);
2954
2955 if (err)
2956 goto err;
2957 rx_pkts += 1;
2958 rx_bytes += ri.iri_len;
2959 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
2960 *cidxp = ri.iri_cidx;
2961 /* Update our consumer index */
2962 /* XXX NB: shurd - check if this is still safe */
2963 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0])
2964 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0];
2965 /* was this only a completion queue message? */
2966 if (__predict_false(ri.iri_nfrags == 0))
2967 continue;
2968 }
2969 MPASS(ri.iri_nfrags != 0);
2970 MPASS(ri.iri_len != 0);
2971
2972 /* will advance the cidx on the corresponding free lists */
2973 m = iflib_rxd_pkt_get(rxq, &ri);
2974 avail--;
2975 budget_left--;
2976 if (avail == 0 && budget_left)
2977 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left);
2978
2979 if (__predict_false(m == NULL))
2980 continue;
2981
2982 #ifndef __NO_STRICT_ALIGNMENT
2983 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL)
2984 continue;
2985 #endif
2986 #if defined(INET6) || defined(INET)
2987 if (lro_enabled) {
2988 tcp_lro_queue_mbuf(&rxq->ifr_lc, m);
2989 continue;
2990 }
2991 #endif
2992
2993 if (mh == NULL)
2994 mh = mt = m;
2995 else {
2996 mt->m_nextpkt = m;
2997 mt = m;
2998 }
2999 }
3000 CURVNET_RESTORE();
3001 /* make sure that we can refill faster than drain */
3002 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++)
3003 retval |= iflib_fl_refill_all(ctx, fl);
3004
3005 if (mh != NULL) {
3006 if_input(ifp, mh);
3007 DBG_COUNTER_INC(rx_if_input);
3008 }
3009
3010 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes);
3011 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts);
3012
3013 /*
3014 * Flush any outstanding LRO work
3015 */
3016 #if defined(INET6) || defined(INET)
3017 tcp_lro_flush_all(&rxq->ifr_lc);
3018 #endif
3019 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0)
3020 retval |= IFLIB_RXEOF_MORE;
3021 return (retval);
3022 err:
3023 STATE_LOCK(ctx);
3024 ctx->ifc_flags |= IFC_DO_RESET;
3025 iflib_admin_intr_deferred(ctx);
3026 STATE_UNLOCK(ctx);
3027 return (0);
3028 }
3029
3030 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq) - 1)
3031 static inline qidx_t
txq_max_db_deferred(iflib_txq_t txq,qidx_t in_use)3032 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use)
3033 {
3034 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3035 qidx_t minthresh = txq->ift_size / 8;
3036 if (in_use > 4 * minthresh)
3037 return (notify_count);
3038 if (in_use > 2 * minthresh)
3039 return (notify_count >> 1);
3040 if (in_use > minthresh)
3041 return (notify_count >> 3);
3042 return (0);
3043 }
3044
3045 static inline qidx_t
txq_max_rs_deferred(iflib_txq_t txq)3046 txq_max_rs_deferred(iflib_txq_t txq)
3047 {
3048 qidx_t notify_count = TXD_NOTIFY_COUNT(txq);
3049 qidx_t minthresh = txq->ift_size / 8;
3050 if (txq->ift_in_use > 4 * minthresh)
3051 return (notify_count);
3052 if (txq->ift_in_use > 2 * minthresh)
3053 return (notify_count >> 1);
3054 if (txq->ift_in_use > minthresh)
3055 return (notify_count >> 2);
3056 return (2);
3057 }
3058
3059 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags)
3060 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG)
3061
3062 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use))
3063 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq)
3064 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4)
3065
3066 /* forward compatibility for cxgb */
3067 #define FIRST_QSET(ctx) 0
3068 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets)
3069 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets)
3070 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx))
3071 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments))
3072
3073 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \
3074 (ctx)->ifc_softc_ctx.isc_tx_nsegments)
3075
3076 static inline bool
iflib_txd_db_check(iflib_txq_t txq,int ring)3077 iflib_txd_db_check(iflib_txq_t txq, int ring)
3078 {
3079 if_ctx_t ctx = txq->ift_ctx;
3080 qidx_t dbval, max;
3081
3082 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use);
3083
3084 /* force || threshold exceeded || at the edge of the ring */
3085 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx))) {
3086
3087 /*
3088 * 'npending' is used if the card's doorbell is in terms of the number of descriptors
3089 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the
3090 * producer index explicitly (INTC).
3091 */
3092 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx;
3093 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3094 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3095 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval);
3096
3097 /*
3098 * Absent bugs there are zero packets pending so reset pending counts to zero.
3099 */
3100 txq->ift_db_pending = txq->ift_npending = 0;
3101 return (true);
3102 }
3103 return (false);
3104 }
3105
3106 #ifdef PKT_DEBUG
3107 static void
print_pkt(if_pkt_info_t pi)3108 print_pkt(if_pkt_info_t pi)
3109 {
3110 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n",
3111 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx);
3112 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n",
3113 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag);
3114 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n",
3115 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto);
3116 }
3117 #endif
3118
3119 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO)
3120 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO))
3121 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO)
3122 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO))
3123
3124 /**
3125 * Parses out ethernet header information in the given mbuf.
3126 * Returns in pi: ipi_etype (EtherType) and ipi_ehdrlen (Ethernet header length)
3127 *
3128 * This will account for the VLAN header if present.
3129 *
3130 * XXX: This doesn't handle QinQ, which could prevent TX offloads for those
3131 * types of packets.
3132 */
3133 static int
iflib_parse_ether_header(if_pkt_info_t pi,struct mbuf ** mp,uint64_t * pullups)3134 iflib_parse_ether_header(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3135 {
3136 struct ether_vlan_header *eh;
3137 struct mbuf *m;
3138
3139 m = *mp;
3140 if (__predict_false(m->m_len < sizeof(*eh))) {
3141 (*pullups)++;
3142 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL))
3143 return (ENOMEM);
3144 }
3145 eh = mtod(m, struct ether_vlan_header *);
3146 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3147 pi->ipi_etype = ntohs(eh->evl_proto);
3148 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3149 } else {
3150 pi->ipi_etype = ntohs(eh->evl_encap_proto);
3151 pi->ipi_ehdrlen = ETHER_HDR_LEN;
3152 }
3153 *mp = m;
3154
3155 return (0);
3156 }
3157
3158 /**
3159 * Parse up to the L3 header and extract IPv4/IPv6 header information into pi.
3160 * Currently this information includes: IP ToS value, IP header version/presence
3161 *
3162 * This is missing some checks and doesn't edit the packet content as it goes,
3163 * unlike iflib_parse_header(), in order to keep the amount of code here minimal.
3164 */
3165 static int
iflib_parse_header_partial(if_pkt_info_t pi,struct mbuf ** mp,uint64_t * pullups)3166 iflib_parse_header_partial(if_pkt_info_t pi, struct mbuf **mp, uint64_t *pullups)
3167 {
3168 struct mbuf *m;
3169 int err;
3170
3171 *pullups = 0;
3172 m = *mp;
3173 if (!M_WRITABLE(m)) {
3174 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3175 return (ENOMEM);
3176 } else {
3177 m_freem(*mp);
3178 DBG_COUNTER_INC(tx_frees);
3179 *mp = m;
3180 }
3181 }
3182
3183 /* Fills out pi->ipi_etype */
3184 err = iflib_parse_ether_header(pi, mp, pullups);
3185 if (err)
3186 return (err);
3187 m = *mp;
3188
3189 switch (pi->ipi_etype) {
3190 #ifdef INET
3191 case ETHERTYPE_IP:
3192 {
3193 struct mbuf *n;
3194 struct ip *ip = NULL;
3195 int miniplen;
3196
3197 miniplen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip));
3198 if (__predict_false(m->m_len < miniplen)) {
3199 /*
3200 * Check for common case where the first mbuf only contains
3201 * the Ethernet header
3202 */
3203 if (m->m_len == pi->ipi_ehdrlen) {
3204 n = m->m_next;
3205 MPASS(n);
3206 /* If next mbuf contains at least the minimal IP header, then stop */
3207 if (n->m_len >= sizeof(*ip)) {
3208 ip = (struct ip *)n->m_data;
3209 } else {
3210 (*pullups)++;
3211 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3212 return (ENOMEM);
3213 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3214 }
3215 } else {
3216 (*pullups)++;
3217 if (__predict_false((m = m_pullup(m, miniplen)) == NULL))
3218 return (ENOMEM);
3219 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3220 }
3221 } else {
3222 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3223 }
3224
3225 /* Have the IPv4 header w/ no options here */
3226 pi->ipi_ip_hlen = ip->ip_hl << 2;
3227 pi->ipi_ipproto = ip->ip_p;
3228 pi->ipi_ip_tos = ip->ip_tos;
3229 pi->ipi_flags |= IPI_TX_IPV4;
3230
3231 break;
3232 }
3233 #endif
3234 #ifdef INET6
3235 case ETHERTYPE_IPV6:
3236 {
3237 struct ip6_hdr *ip6;
3238
3239 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3240 (*pullups)++;
3241 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3242 return (ENOMEM);
3243 }
3244 ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3245
3246 /* Have the IPv6 fixed header here */
3247 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3248 pi->ipi_ipproto = ip6->ip6_nxt;
3249 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3250 pi->ipi_flags |= IPI_TX_IPV6;
3251
3252 break;
3253 }
3254 #endif
3255 default:
3256 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3257 pi->ipi_ip_hlen = 0;
3258 break;
3259 }
3260 *mp = m;
3261
3262 return (0);
3263
3264 }
3265
3266 static int
iflib_parse_header(iflib_txq_t txq,if_pkt_info_t pi,struct mbuf ** mp)3267 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp)
3268 {
3269 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx;
3270 struct mbuf *m;
3271 int err;
3272
3273 m = *mp;
3274 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) &&
3275 M_WRITABLE(m) == 0) {
3276 if ((m = m_dup(m, M_NOWAIT)) == NULL) {
3277 return (ENOMEM);
3278 } else {
3279 m_freem(*mp);
3280 DBG_COUNTER_INC(tx_frees);
3281 *mp = m;
3282 }
3283 }
3284
3285 /* Fills out pi->ipi_etype */
3286 err = iflib_parse_ether_header(pi, mp, &txq->ift_pullups);
3287 if (__predict_false(err))
3288 return (err);
3289 m = *mp;
3290
3291 switch (pi->ipi_etype) {
3292 #ifdef INET
3293 case ETHERTYPE_IP:
3294 {
3295 struct ip *ip;
3296 struct tcphdr *th;
3297 uint8_t hlen;
3298
3299 hlen = pi->ipi_ehdrlen + sizeof(*ip);
3300 if (__predict_false(m->m_len < hlen)) {
3301 txq->ift_pullups++;
3302 if (__predict_false((m = m_pullup(m, hlen)) == NULL))
3303 return (ENOMEM);
3304 }
3305 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen);
3306 hlen = pi->ipi_ehdrlen + (ip->ip_hl << 2);
3307 if (ip->ip_p == IPPROTO_TCP) {
3308 hlen += sizeof(*th);
3309 th = (struct tcphdr *)((char *)ip + (ip->ip_hl << 2));
3310 } else if (ip->ip_p == IPPROTO_UDP) {
3311 hlen += sizeof(struct udphdr);
3312 }
3313 if (__predict_false(m->m_len < hlen)) {
3314 txq->ift_pullups++;
3315 if ((m = m_pullup(m, hlen)) == NULL)
3316 return (ENOMEM);
3317 }
3318 pi->ipi_ip_hlen = ip->ip_hl << 2;
3319 pi->ipi_ipproto = ip->ip_p;
3320 pi->ipi_ip_tos = ip->ip_tos;
3321 pi->ipi_flags |= IPI_TX_IPV4;
3322
3323 /* TCP checksum offload may require TCP header length */
3324 if (IS_TX_OFFLOAD4(pi)) {
3325 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) {
3326 pi->ipi_tcp_hflags = tcp_get_flags(th);
3327 pi->ipi_tcp_hlen = th->th_off << 2;
3328 pi->ipi_tcp_seq = th->th_seq;
3329 }
3330 if (IS_TSO4(pi)) {
3331 if (__predict_false(ip->ip_p != IPPROTO_TCP))
3332 return (ENXIO);
3333 /*
3334 * TSO always requires hardware checksum offload.
3335 */
3336 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP);
3337 th->th_sum = in_pseudo(ip->ip_src.s_addr,
3338 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3339 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3340 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) {
3341 ip->ip_sum = 0;
3342 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz);
3343 }
3344 }
3345 }
3346 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP))
3347 ip->ip_sum = 0;
3348
3349 break;
3350 }
3351 #endif
3352 #ifdef INET6
3353 case ETHERTYPE_IPV6:
3354 {
3355 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen);
3356 struct tcphdr *th;
3357 pi->ipi_ip_hlen = sizeof(struct ip6_hdr);
3358
3359 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) {
3360 txq->ift_pullups++;
3361 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL))
3362 return (ENOMEM);
3363 }
3364 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen);
3365
3366 /* XXX-BZ this will go badly in case of ext hdrs. */
3367 pi->ipi_ipproto = ip6->ip6_nxt;
3368 pi->ipi_ip_tos = IPV6_TRAFFIC_CLASS(ip6);
3369 pi->ipi_flags |= IPI_TX_IPV6;
3370
3371 /* TCP checksum offload may require TCP header length */
3372 if (IS_TX_OFFLOAD6(pi)) {
3373 if (pi->ipi_ipproto == IPPROTO_TCP) {
3374 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) {
3375 txq->ift_pullups++;
3376 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL))
3377 return (ENOMEM);
3378 }
3379 pi->ipi_tcp_hflags = tcp_get_flags(th);
3380 pi->ipi_tcp_hlen = th->th_off << 2;
3381 pi->ipi_tcp_seq = th->th_seq;
3382 }
3383 if (IS_TSO6(pi)) {
3384 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP))
3385 return (ENXIO);
3386 /*
3387 * TSO always requires hardware checksum offload.
3388 */
3389 pi->ipi_csum_flags |= CSUM_IP6_TCP;
3390 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3391 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz;
3392 }
3393 }
3394 break;
3395 }
3396 #endif
3397 default:
3398 pi->ipi_csum_flags &= ~CSUM_OFFLOAD;
3399 pi->ipi_ip_hlen = 0;
3400 break;
3401 }
3402 *mp = m;
3403
3404 return (0);
3405 }
3406
3407 /*
3408 * If dodgy hardware rejects the scatter gather chain we've handed it
3409 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the
3410 * m_defrag'd mbufs
3411 */
3412 static __noinline struct mbuf *
iflib_remove_mbuf(iflib_txq_t txq)3413 iflib_remove_mbuf(iflib_txq_t txq)
3414 {
3415 int ntxd, pidx;
3416 struct mbuf *m, **ifsd_m;
3417
3418 ifsd_m = txq->ift_sds.ifsd_m;
3419 ntxd = txq->ift_size;
3420 pidx = txq->ift_pidx & (ntxd - 1);
3421 ifsd_m = txq->ift_sds.ifsd_m;
3422 m = IFLIB_GET_MBUF(ifsd_m[pidx]);
3423 ifsd_m[pidx] = NULL;
3424 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]);
3425 if (txq->ift_sds.ifsd_tso_map != NULL)
3426 bus_dmamap_unload(txq->ift_tso_buf_tag,
3427 txq->ift_sds.ifsd_tso_map[pidx]);
3428 #if MEMORY_LOGGING
3429 txq->ift_dequeued++;
3430 #endif
3431 return (m);
3432 }
3433
3434 /*
3435 * Pad an mbuf to ensure a minimum ethernet frame size.
3436 * min_frame_size is the frame size (less CRC) to pad the mbuf to
3437 */
3438 static __noinline int
iflib_ether_pad(device_t dev,struct mbuf ** m_head,uint16_t min_frame_size)3439 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size)
3440 {
3441 /*
3442 * 18 is enough bytes to pad an ARP packet to 46 bytes, and
3443 * and ARP message is the smallest common payload I can think of
3444 */
3445 static char pad[18]; /* just zeros */
3446 int n;
3447 struct mbuf *new_head;
3448
3449 if (!M_WRITABLE(*m_head)) {
3450 new_head = m_dup(*m_head, M_NOWAIT);
3451 if (new_head == NULL) {
3452 m_freem(*m_head);
3453 device_printf(dev, "cannot pad short frame, m_dup() failed");
3454 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3455 DBG_COUNTER_INC(tx_frees);
3456 return (ENOMEM);
3457 }
3458 m_freem(*m_head);
3459 *m_head = new_head;
3460 }
3461
3462 for (n = min_frame_size - (*m_head)->m_pkthdr.len;
3463 n > 0; n -= sizeof(pad))
3464 if (!m_append(*m_head, min(n, sizeof(pad)), pad))
3465 break;
3466
3467 if (n > 0) {
3468 m_freem(*m_head);
3469 device_printf(dev, "cannot pad short frame\n");
3470 DBG_COUNTER_INC(encap_pad_mbuf_fail);
3471 DBG_COUNTER_INC(tx_frees);
3472 return (ENOBUFS);
3473 }
3474
3475 return (0);
3476 }
3477
3478 static int
iflib_encap(iflib_txq_t txq,struct mbuf ** m_headp)3479 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp)
3480 {
3481 if_ctx_t ctx;
3482 if_shared_ctx_t sctx;
3483 if_softc_ctx_t scctx;
3484 bus_dma_tag_t buf_tag;
3485 bus_dma_segment_t *segs;
3486 struct mbuf *m_head, **ifsd_m;
3487 bus_dmamap_t map;
3488 struct if_pkt_info pi;
3489 uintptr_t flags;
3490 int remap = 0;
3491 int err, nsegs, ndesc, max_segs, pidx;
3492
3493 ctx = txq->ift_ctx;
3494 sctx = ctx->ifc_sctx;
3495 scctx = &ctx->ifc_softc_ctx;
3496 segs = txq->ift_segs;
3497 m_head = *m_headp;
3498 map = NULL;
3499
3500 /*
3501 * If we're doing TSO the next descriptor to clean may be quite far ahead
3502 */
3503 pidx = txq->ift_pidx;
3504 map = txq->ift_sds.ifsd_map[pidx];
3505 ifsd_m = txq->ift_sds.ifsd_m;
3506
3507 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3508 buf_tag = txq->ift_tso_buf_tag;
3509 max_segs = scctx->isc_tx_tso_segments_max;
3510 map = txq->ift_sds.ifsd_tso_map[pidx];
3511 MPASS(buf_tag != NULL);
3512 MPASS(max_segs > 0);
3513 flags = IFLIB_TSO;
3514 } else {
3515 buf_tag = txq->ift_buf_tag;
3516 max_segs = scctx->isc_tx_nsegments;
3517 map = txq->ift_sds.ifsd_map[pidx];
3518 flags = IFLIB_NO_TSO;
3519 }
3520 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) &&
3521 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) {
3522 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size);
3523 if (err) {
3524 DBG_COUNTER_INC(encap_txd_encap_fail);
3525 return (err);
3526 }
3527 }
3528 m_head = *m_headp;
3529
3530 memset(&pi, 0, sizeof(pi));
3531 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG | M_BCAST | M_MCAST));
3532 pi.ipi_pidx = pidx;
3533 pi.ipi_qsidx = txq->ift_id;
3534 pi.ipi_len = m_head->m_pkthdr.len;
3535 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags;
3536 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0;
3537
3538 /* deliberate bitwise OR to make one condition */
3539 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) {
3540 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) {
3541 DBG_COUNTER_INC(encap_txd_encap_fail);
3542 return (err);
3543 }
3544 m_head = *m_headp;
3545 }
3546
3547 retry:
3548 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs,
3549 BUS_DMA_NOWAIT);
3550 defrag:
3551 if (__predict_false(err)) {
3552 switch (err) {
3553 case EFBIG:
3554 /* try collapse once and defrag once */
3555 if (remap == 0) {
3556 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs);
3557 /* try defrag if collapsing fails */
3558 if (m_head == NULL)
3559 remap++;
3560 }
3561 if (remap == 1) {
3562 txq->ift_mbuf_defrag++;
3563 m_head = m_defrag(*m_headp, M_NOWAIT);
3564 }
3565 /*
3566 * remap should never be >1 unless bus_dmamap_load_mbuf_sg
3567 * failed to map an mbuf that was run through m_defrag
3568 */
3569 MPASS(remap <= 1);
3570 if (__predict_false(m_head == NULL || remap > 1))
3571 goto defrag_failed;
3572 remap++;
3573 *m_headp = m_head;
3574 goto retry;
3575 break;
3576 case ENOMEM:
3577 txq->ift_no_tx_dma_setup++;
3578 break;
3579 default:
3580 txq->ift_no_tx_dma_setup++;
3581 m_freem(*m_headp);
3582 DBG_COUNTER_INC(tx_frees);
3583 *m_headp = NULL;
3584 break;
3585 }
3586 txq->ift_map_failed++;
3587 DBG_COUNTER_INC(encap_load_mbuf_fail);
3588 DBG_COUNTER_INC(encap_txd_encap_fail);
3589 return (err);
3590 }
3591 ifsd_m[pidx] = IFLIB_SAVE_MBUF(m_head, flags);
3592 if (m_head->m_pkthdr.csum_flags & CSUM_SND_TAG)
3593 pi.ipi_mbuf = m_head;
3594 else
3595 pi.ipi_mbuf = NULL;
3596 /*
3597 * XXX assumes a 1 to 1 relationship between segments and
3598 * descriptors - this does not hold true on all drivers, e.g.
3599 * cxgb
3600 */
3601 if (__predict_false(nsegs > TXQ_AVAIL(txq))) {
3602 (void)iflib_completed_tx_reclaim(txq, NULL);
3603 if (__predict_false(nsegs > TXQ_AVAIL(txq))) {
3604 txq->ift_no_desc_avail++;
3605 bus_dmamap_unload(buf_tag, map);
3606 DBG_COUNTER_INC(encap_txq_avail_fail);
3607 DBG_COUNTER_INC(encap_txd_encap_fail);
3608 if (ctx->ifc_sysctl_simple_tx) {
3609 *m_headp = m_head = iflib_remove_mbuf(txq);
3610 m_freem(*m_headp);
3611 DBG_COUNTER_INC(tx_frees);
3612 *m_headp = NULL;
3613 }
3614 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0)
3615 GROUPTASK_ENQUEUE(&txq->ift_task);
3616 return (ENOBUFS);
3617 }
3618 }
3619 /*
3620 * On Intel cards we can greatly reduce the number of TX interrupts
3621 * we see by only setting report status on every Nth descriptor.
3622 * However, this also means that the driver will need to keep track
3623 * of the descriptors that RS was set on to check them for the DD bit.
3624 */
3625 txq->ift_rs_pending += nsegs + 1;
3626 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) ||
3627 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx)) {
3628 pi.ipi_flags |= IPI_TX_INTR;
3629 txq->ift_rs_pending = 0;
3630 }
3631
3632 pi.ipi_segs = segs;
3633 pi.ipi_nsegs = nsegs;
3634
3635 MPASS(pidx >= 0 && pidx < txq->ift_size);
3636 #ifdef PKT_DEBUG
3637 print_pkt(&pi);
3638 #endif
3639 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) {
3640 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE);
3641 DBG_COUNTER_INC(tx_encap);
3642 MPASS(pi.ipi_new_pidx < txq->ift_size);
3643
3644 ndesc = pi.ipi_new_pidx - pi.ipi_pidx;
3645 if (pi.ipi_new_pidx < pi.ipi_pidx) {
3646 ndesc += txq->ift_size;
3647 txq->ift_gen = 1;
3648 }
3649 /*
3650 * drivers can need up to ift_pad sentinels
3651 */
3652 MPASS(ndesc <= pi.ipi_nsegs + txq->ift_pad);
3653 MPASS(pi.ipi_new_pidx != pidx);
3654 MPASS(ndesc > 0);
3655 txq->ift_in_use += ndesc;
3656 txq->ift_db_pending += ndesc;
3657
3658 /*
3659 * We update the last software descriptor again here because there may
3660 * be a sentinel and/or there may be more mbufs than segments
3661 */
3662 txq->ift_pidx = pi.ipi_new_pidx;
3663 txq->ift_npending += pi.ipi_ndescs;
3664 } else {
3665 *m_headp = m_head = iflib_remove_mbuf(txq);
3666 if (err == EFBIG) {
3667 txq->ift_txd_encap_efbig++;
3668 if (remap < 2) {
3669 remap = 1;
3670 goto defrag;
3671 }
3672 }
3673 goto defrag_failed;
3674 }
3675 /*
3676 * err can't possibly be non-zero here, so we don't neet to test it
3677 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail).
3678 */
3679 return (err);
3680
3681 defrag_failed:
3682 txq->ift_mbuf_defrag_failed++;
3683 txq->ift_map_failed++;
3684 m_freem(*m_headp);
3685 DBG_COUNTER_INC(tx_frees);
3686 *m_headp = NULL;
3687 DBG_COUNTER_INC(encap_txd_encap_fail);
3688 return (ENOMEM);
3689 }
3690
3691 static void
iflib_tx_desc_free(iflib_txq_t txq,int n,struct mbuf ** m_defer)3692 iflib_tx_desc_free(iflib_txq_t txq, int n, struct mbuf **m_defer)
3693 {
3694 uint32_t qsize, cidx, gen;
3695 struct mbuf *m, **ifsd_m;
3696 uintptr_t flags;
3697
3698 cidx = txq->ift_cidx;
3699 gen = txq->ift_gen;
3700 qsize = txq->ift_size;
3701 ifsd_m =txq->ift_sds.ifsd_m;
3702
3703 while (n-- > 0) {
3704 if ((m = IFLIB_GET_MBUF(ifsd_m[cidx])) != NULL) {
3705 flags = IFLIB_GET_FLAGS(ifsd_m[cidx]);
3706 MPASS(flags != 0);
3707 if (flags & IFLIB_TSO) {
3708 bus_dmamap_sync(txq->ift_tso_buf_tag,
3709 txq->ift_sds.ifsd_tso_map[cidx],
3710 BUS_DMASYNC_POSTWRITE);
3711 bus_dmamap_unload(txq->ift_tso_buf_tag,
3712 txq->ift_sds.ifsd_tso_map[cidx]);
3713 } else {
3714 bus_dmamap_sync(txq->ift_buf_tag,
3715 txq->ift_sds.ifsd_map[cidx],
3716 BUS_DMASYNC_POSTWRITE);
3717 bus_dmamap_unload(txq->ift_buf_tag,
3718 txq->ift_sds.ifsd_map[cidx]);
3719 }
3720 /* XXX we don't support any drivers that batch packets yet */
3721 MPASS(m->m_nextpkt == NULL);
3722 if (m_defer == NULL) {
3723 m_freem(m);
3724 } else if (m != NULL) {
3725 *m_defer = m;
3726 m_defer++;
3727 }
3728 ifsd_m[cidx] = NULL;
3729 #if MEMORY_LOGGING
3730 txq->ift_dequeued++;
3731 #endif
3732 DBG_COUNTER_INC(tx_frees);
3733 }
3734 if (__predict_false(++cidx == qsize)) {
3735 cidx = 0;
3736 gen = 0;
3737 }
3738 }
3739 txq->ift_cidx = cidx;
3740 txq->ift_gen = gen;
3741 }
3742
3743 static __inline int
iflib_txq_can_reclaim(iflib_txq_t txq)3744 iflib_txq_can_reclaim(iflib_txq_t txq)
3745 {
3746 int reclaim, thresh;
3747
3748 thresh = txq->ift_reclaim_thresh;
3749 KASSERT(thresh >= 0, ("invalid threshold to reclaim"));
3750 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size);
3751
3752 if (ticks <= (txq->ift_last_reclaim + txq->ift_reclaim_ticks) &&
3753 txq->ift_in_use < thresh)
3754 return (false);
3755 iflib_tx_credits_update(txq->ift_ctx, txq);
3756 reclaim = DESC_RECLAIMABLE(txq);
3757 if (reclaim <= thresh) {
3758 #ifdef INVARIANTS
3759 if (iflib_verbose_debug) {
3760 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __func__,
3761 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments,
3762 reclaim, thresh);
3763 }
3764 #endif
3765 return (0);
3766 }
3767 return (reclaim);
3768 }
3769
3770 static __inline void
_iflib_completed_tx_reclaim(iflib_txq_t txq,struct mbuf ** m_defer,int reclaim)3771 _iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer, int reclaim)
3772 {
3773 txq->ift_last_reclaim = ticks;
3774 iflib_tx_desc_free(txq, reclaim, m_defer);
3775 txq->ift_cleaned += reclaim;
3776 txq->ift_in_use -= reclaim;
3777 }
3778
3779 static __inline int
iflib_completed_tx_reclaim(iflib_txq_t txq,struct mbuf ** m_defer)3780 iflib_completed_tx_reclaim(iflib_txq_t txq, struct mbuf **m_defer)
3781 {
3782 int reclaim;
3783
3784 reclaim = iflib_txq_can_reclaim(txq);
3785 if (reclaim == 0)
3786 return (0);
3787 _iflib_completed_tx_reclaim(txq, m_defer, reclaim);
3788 return (reclaim);
3789 }
3790
3791 static struct mbuf **
_ring_peek_one(struct ifmp_ring * r,int cidx,int offset,int remaining)3792 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining)
3793 {
3794 int next, size;
3795 struct mbuf **items;
3796
3797 size = r->size;
3798 next = (cidx + CACHE_PTR_INCREMENT) & (size - 1);
3799 items = __DEVOLATILE(struct mbuf **, &r->items[0]);
3800
3801 prefetch(items[(cidx + offset) & (size - 1)]);
3802 if (remaining > 1) {
3803 prefetch2cachelines(&items[next]);
3804 prefetch2cachelines(items[(cidx + offset + 1) & (size - 1)]);
3805 prefetch2cachelines(items[(cidx + offset + 2) & (size - 1)]);
3806 prefetch2cachelines(items[(cidx + offset + 3) & (size - 1)]);
3807 }
3808 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size - 1)]));
3809 }
3810
3811 static void
iflib_txq_check_drain(iflib_txq_t txq,int budget)3812 iflib_txq_check_drain(iflib_txq_t txq, int budget)
3813 {
3814
3815 ifmp_ring_check_drainage(txq->ift_br, budget);
3816 }
3817
3818 static uint32_t
iflib_txq_can_drain(struct ifmp_ring * r)3819 iflib_txq_can_drain(struct ifmp_ring *r)
3820 {
3821 iflib_txq_t txq = r->cookie;
3822 if_ctx_t ctx = txq->ift_ctx;
3823
3824 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx))
3825 return (1);
3826 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
3827 BUS_DMASYNC_POSTREAD);
3828 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id,
3829 false));
3830 }
3831
3832 static uint32_t
iflib_txq_drain(struct ifmp_ring * r,uint32_t cidx,uint32_t pidx)3833 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3834 {
3835 iflib_txq_t txq = r->cookie;
3836 if_ctx_t ctx = txq->ift_ctx;
3837 if_t ifp = ctx->ifc_ifp;
3838 struct mbuf *m, **mp;
3839 int avail, bytes_sent, skipped, count, err, i;
3840 int mcast_sent, pkt_sent, reclaimed;
3841 bool do_prefetch, rang, ring;
3842
3843 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) ||
3844 !LINK_ACTIVE(ctx))) {
3845 DBG_COUNTER_INC(txq_drain_notready);
3846 return (0);
3847 }
3848 reclaimed = iflib_completed_tx_reclaim(txq, NULL);
3849 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending);
3850 avail = IDXDIFF(pidx, cidx, r->size);
3851
3852 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) {
3853 /*
3854 * The driver is unloading so we need to free all pending packets.
3855 */
3856 DBG_COUNTER_INC(txq_drain_flushing);
3857 for (i = 0; i < avail; i++) {
3858 if (__predict_true(r->items[(cidx + i) & (r->size - 1)] != (void *)txq))
3859 m_freem(r->items[(cidx + i) & (r->size - 1)]);
3860 r->items[(cidx + i) & (r->size - 1)] = NULL;
3861 }
3862 return (avail);
3863 }
3864
3865 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) {
3866 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3867 CALLOUT_LOCK(txq);
3868 callout_stop(&txq->ift_timer);
3869 CALLOUT_UNLOCK(txq);
3870 DBG_COUNTER_INC(txq_drain_oactive);
3871 return (0);
3872 }
3873
3874 /*
3875 * If we've reclaimed any packets this queue cannot be hung.
3876 */
3877 if (reclaimed)
3878 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3879 skipped = mcast_sent = bytes_sent = pkt_sent = 0;
3880 count = MIN(avail, TX_BATCH_SIZE);
3881 #ifdef INVARIANTS
3882 if (iflib_verbose_debug)
3883 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __func__,
3884 avail, ctx->ifc_flags, TXQ_AVAIL(txq));
3885 #endif
3886 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH);
3887 err = 0;
3888 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx); i++) {
3889 int rem = do_prefetch ? count - i : 0;
3890
3891 mp = _ring_peek_one(r, cidx, i, rem);
3892 MPASS(mp != NULL && *mp != NULL);
3893
3894 /*
3895 * Completion interrupts will use the address of the txq
3896 * as a sentinel to enqueue _something_ in order to acquire
3897 * the lock on the mp_ring (there's no direct lock call).
3898 * We obviously whave to check for these sentinel cases
3899 * and skip them.
3900 */
3901 if (__predict_false(*mp == (struct mbuf *)txq)) {
3902 skipped++;
3903 continue;
3904 }
3905 err = iflib_encap(txq, mp);
3906 if (__predict_false(err)) {
3907 /* no room - bail out */
3908 if (err == ENOBUFS)
3909 break;
3910 skipped++;
3911 /* we can't send this packet - skip it */
3912 continue;
3913 }
3914 pkt_sent++;
3915 m = *mp;
3916 DBG_COUNTER_INC(tx_sent);
3917 bytes_sent += m->m_pkthdr.len;
3918 mcast_sent += !!(m->m_flags & M_MCAST);
3919
3920 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)))
3921 break;
3922 ETHER_BPF_MTAP(ifp, m);
3923 rang = iflib_txd_db_check(txq, false);
3924 }
3925
3926 /* deliberate use of bitwise or to avoid gratuitous short-circuit */
3927 ring = rang ? false : (iflib_min_tx_latency | err | (!!txq->ift_reclaim_thresh));
3928 iflib_txd_db_check(txq, ring);
3929 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
3930 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
3931 if (mcast_sent)
3932 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
3933 #ifdef INVARIANTS
3934 if (iflib_verbose_debug)
3935 printf("consumed=%d\n", skipped + pkt_sent);
3936 #endif
3937 return (skipped + pkt_sent);
3938 }
3939
3940 static uint32_t
iflib_txq_drain_always(struct ifmp_ring * r)3941 iflib_txq_drain_always(struct ifmp_ring *r)
3942 {
3943 return (1);
3944 }
3945
3946 static uint32_t
iflib_txq_drain_free(struct ifmp_ring * r,uint32_t cidx,uint32_t pidx)3947 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx)
3948 {
3949 int i, avail;
3950 struct mbuf **mp;
3951 iflib_txq_t txq;
3952
3953 txq = r->cookie;
3954
3955 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
3956 CALLOUT_LOCK(txq);
3957 callout_stop(&txq->ift_timer);
3958 CALLOUT_UNLOCK(txq);
3959
3960 avail = IDXDIFF(pidx, cidx, r->size);
3961 for (i = 0; i < avail; i++) {
3962 mp = _ring_peek_one(r, cidx, i, avail - i);
3963 if (__predict_false(*mp == (struct mbuf *)txq))
3964 continue;
3965 m_freem(*mp);
3966 DBG_COUNTER_INC(tx_frees);
3967 }
3968 MPASS(ifmp_ring_is_stalled(r) == 0);
3969 return (avail);
3970 }
3971
3972 static void
iflib_ifmp_purge(iflib_txq_t txq)3973 iflib_ifmp_purge(iflib_txq_t txq)
3974 {
3975 struct ifmp_ring *r;
3976
3977 r = txq->ift_br;
3978 r->drain = iflib_txq_drain_free;
3979 r->can_drain = iflib_txq_drain_always;
3980
3981 ifmp_ring_check_drainage(r, r->size);
3982
3983 r->drain = iflib_txq_drain;
3984 r->can_drain = iflib_txq_can_drain;
3985 }
3986
3987 static void
_task_fn_tx(void * context)3988 _task_fn_tx(void *context)
3989 {
3990 iflib_txq_t txq = context;
3991 if_ctx_t ctx = txq->ift_ctx;
3992 if_t ifp = ctx->ifc_ifp;
3993 int abdicate = ctx->ifc_sysctl_tx_abdicate;
3994
3995 #ifdef IFLIB_DIAGNOSTICS
3996 txq->ift_cpu_exec_count[curcpu]++;
3997 #endif
3998 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
3999 return;
4000 #ifdef DEV_NETMAP
4001 if ((if_getcapenable(ifp) & IFCAP_NETMAP) &&
4002 netmap_tx_irq(ifp, txq->ift_id))
4003 goto skip_ifmp;
4004 #endif
4005 if (ctx->ifc_sysctl_simple_tx) {
4006 mtx_lock(&txq->ift_mtx);
4007 (void)iflib_completed_tx_reclaim(txq, NULL);
4008 mtx_unlock(&txq->ift_mtx);
4009 goto skip_ifmp;
4010 }
4011 #ifdef ALTQ
4012 if (if_altq_is_enabled(ifp))
4013 iflib_altq_if_start(ifp);
4014 #endif
4015 if (txq->ift_db_pending)
4016 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate);
4017 else if (!abdicate)
4018 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4019 /*
4020 * When abdicating, we always need to check drainage, not just when we don't enqueue
4021 */
4022 if (abdicate)
4023 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4024
4025 skip_ifmp:
4026 if (ctx->ifc_flags & IFC_LEGACY)
4027 IFDI_INTR_ENABLE(ctx);
4028 else
4029 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id);
4030 }
4031
4032 static void
_task_fn_rx(void * context)4033 _task_fn_rx(void *context)
4034 {
4035 iflib_rxq_t rxq = context;
4036 if_ctx_t ctx = rxq->ifr_ctx;
4037 uint8_t more;
4038 uint16_t budget;
4039 #ifdef DEV_NETMAP
4040 u_int work = 0;
4041 int nmirq;
4042 #endif
4043
4044 #ifdef IFLIB_DIAGNOSTICS
4045 rxq->ifr_cpu_exec_count[curcpu]++;
4046 #endif
4047 DBG_COUNTER_INC(task_fn_rxs);
4048 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4049 return;
4050 #ifdef DEV_NETMAP
4051 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work);
4052 if (nmirq != NM_IRQ_PASS) {
4053 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0;
4054 goto skip_rxeof;
4055 }
4056 #endif
4057 budget = ctx->ifc_sysctl_rx_budget;
4058 if (budget == 0)
4059 budget = 16; /* XXX */
4060 more = iflib_rxeof(rxq, budget);
4061 #ifdef DEV_NETMAP
4062 skip_rxeof:
4063 #endif
4064 if ((more & IFLIB_RXEOF_MORE) == 0) {
4065 if (ctx->ifc_flags & IFC_LEGACY)
4066 IFDI_INTR_ENABLE(ctx);
4067 else
4068 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id);
4069 DBG_COUNTER_INC(rx_intr_enables);
4070 }
4071 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)))
4072 return;
4073
4074 if (more & IFLIB_RXEOF_MORE)
4075 GROUPTASK_ENQUEUE(&rxq->ifr_task);
4076 else if (more & IFLIB_RXEOF_EMPTY)
4077 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq);
4078 }
4079
4080 static void
_task_fn_admin(void * context,int pending)4081 _task_fn_admin(void *context, int pending)
4082 {
4083 if_ctx_t ctx = context;
4084 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx;
4085 iflib_txq_t txq;
4086 int i;
4087 bool oactive, running, do_reset, do_watchdog, in_detach;
4088
4089 STATE_LOCK(ctx);
4090 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING);
4091 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE);
4092 do_reset = (ctx->ifc_flags & IFC_DO_RESET);
4093 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG);
4094 in_detach = (ctx->ifc_flags & IFC_IN_DETACH);
4095 ctx->ifc_flags &= ~(IFC_DO_RESET | IFC_DO_WATCHDOG);
4096 STATE_UNLOCK(ctx);
4097
4098 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4099 return;
4100 if (in_detach)
4101 return;
4102
4103 CTX_LOCK(ctx);
4104 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4105 CALLOUT_LOCK(txq);
4106 callout_stop(&txq->ift_timer);
4107 CALLOUT_UNLOCK(txq);
4108 }
4109 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ)
4110 IFDI_ADMIN_COMPLETION_HANDLE(ctx);
4111 if (do_watchdog) {
4112 ctx->ifc_watchdog_events++;
4113 IFDI_WATCHDOG_RESET(ctx);
4114 }
4115 IFDI_UPDATE_ADMIN_STATUS(ctx);
4116 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) {
4117 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq,
4118 txq->ift_timer.c_cpu);
4119 }
4120 IFDI_LINK_INTR_ENABLE(ctx);
4121 if (do_reset)
4122 iflib_if_init_locked(ctx);
4123 CTX_UNLOCK(ctx);
4124
4125 if (LINK_ACTIVE(ctx) == 0)
4126 return;
4127 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++)
4128 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
4129 }
4130
4131 static void
_task_fn_iov(void * context,int pending)4132 _task_fn_iov(void *context, int pending)
4133 {
4134 if_ctx_t ctx = context;
4135
4136 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) &&
4137 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN))
4138 return;
4139
4140 CTX_LOCK(ctx);
4141 IFDI_VFLR_HANDLE(ctx);
4142 CTX_UNLOCK(ctx);
4143 }
4144
4145 static int
iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)4146 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
4147 {
4148 int err;
4149 if_int_delay_info_t info;
4150 if_ctx_t ctx;
4151
4152 info = (if_int_delay_info_t)arg1;
4153 ctx = info->iidi_ctx;
4154 info->iidi_req = req;
4155 info->iidi_oidp = oidp;
4156 CTX_LOCK(ctx);
4157 err = IFDI_SYSCTL_INT_DELAY(ctx, info);
4158 CTX_UNLOCK(ctx);
4159 return (err);
4160 }
4161
4162 /*********************************************************************
4163 *
4164 * IFNET FUNCTIONS
4165 *
4166 **********************************************************************/
4167
4168 static void
iflib_if_init_locked(if_ctx_t ctx)4169 iflib_if_init_locked(if_ctx_t ctx)
4170 {
4171 iflib_stop(ctx);
4172 iflib_init_locked(ctx);
4173 }
4174
4175 static void
iflib_if_init(void * arg)4176 iflib_if_init(void *arg)
4177 {
4178 if_ctx_t ctx = arg;
4179
4180 CTX_LOCK(ctx);
4181 iflib_if_init_locked(ctx);
4182 CTX_UNLOCK(ctx);
4183 }
4184
4185 static int
iflib_if_transmit(if_t ifp,struct mbuf * m)4186 iflib_if_transmit(if_t ifp, struct mbuf *m)
4187 {
4188 if_ctx_t ctx = if_getsoftc(ifp);
4189 iflib_txq_t txq;
4190 int err, qidx;
4191 int abdicate;
4192
4193 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) {
4194 DBG_COUNTER_INC(tx_frees);
4195 m_freem(m);
4196 return (ENETDOWN);
4197 }
4198
4199 MPASS(m->m_nextpkt == NULL);
4200 /* ALTQ-enabled interfaces always use queue 0. */
4201 qidx = 0;
4202 /* Use driver-supplied queue selection method if it exists */
4203 if (ctx->isc_txq_select_v2) {
4204 struct if_pkt_info pi;
4205 uint64_t early_pullups = 0;
4206 memset(&pi, 0, sizeof(pi));
4207
4208 err = iflib_parse_header_partial(&pi, &m, &early_pullups);
4209 if (__predict_false(err != 0)) {
4210 /* Assign pullups for bad pkts to default queue */
4211 ctx->ifc_txqs[0].ift_pullups += early_pullups;
4212 DBG_COUNTER_INC(encap_txd_encap_fail);
4213 return (err);
4214 }
4215 /* Let driver make queueing decision */
4216 qidx = ctx->isc_txq_select_v2(ctx->ifc_softc, m, &pi);
4217 ctx->ifc_txqs[qidx].ift_pullups += early_pullups;
4218 }
4219 /* Backwards compatibility w/ simpler queue select */
4220 else if (ctx->isc_txq_select)
4221 qidx = ctx->isc_txq_select(ctx->ifc_softc, m);
4222 /* If not, use iflib's standard method */
4223 else if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !if_altq_is_enabled(ifp))
4224 qidx = QIDX(ctx, m);
4225
4226 /* Set TX queue */
4227 txq = &ctx->ifc_txqs[qidx];
4228
4229 #ifdef DRIVER_BACKPRESSURE
4230 if (txq->ift_closed) {
4231 while (m != NULL) {
4232 next = m->m_nextpkt;
4233 m->m_nextpkt = NULL;
4234 m_freem(m);
4235 DBG_COUNTER_INC(tx_frees);
4236 m = next;
4237 }
4238 return (ENOBUFS);
4239 }
4240 #endif
4241 #ifdef notyet
4242 qidx = count = 0;
4243 mp = marr;
4244 next = m;
4245 do {
4246 count++;
4247 next = next->m_nextpkt;
4248 } while (next != NULL);
4249
4250 if (count > nitems(marr))
4251 if ((mp = malloc(count * sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) {
4252 /* XXX check nextpkt */
4253 m_freem(m);
4254 /* XXX simplify for now */
4255 DBG_COUNTER_INC(tx_frees);
4256 return (ENOBUFS);
4257 }
4258 for (next = m, i = 0; next != NULL; i++) {
4259 mp[i] = next;
4260 next = next->m_nextpkt;
4261 mp[i]->m_nextpkt = NULL;
4262 }
4263 #endif
4264 DBG_COUNTER_INC(tx_seen);
4265 abdicate = ctx->ifc_sysctl_tx_abdicate;
4266
4267 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate);
4268
4269 if (abdicate)
4270 GROUPTASK_ENQUEUE(&txq->ift_task);
4271 if (err) {
4272 if (!abdicate)
4273 GROUPTASK_ENQUEUE(&txq->ift_task);
4274 /* support forthcoming later */
4275 #ifdef DRIVER_BACKPRESSURE
4276 txq->ift_closed = TRUE;
4277 #endif
4278 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE);
4279 m_freem(m);
4280 DBG_COUNTER_INC(tx_frees);
4281 if (err == ENOBUFS)
4282 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1);
4283 else
4284 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
4285 }
4286
4287 return (err);
4288 }
4289
4290 #ifdef ALTQ
4291 /*
4292 * The overall approach to integrating iflib with ALTQ is to continue to use
4293 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware
4294 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring
4295 * is redundant/unnecessary, but doing so minimizes the amount of
4296 * ALTQ-specific code required in iflib. It is assumed that the overhead of
4297 * redundantly queueing to an intermediate mp_ring is swamped by the
4298 * performance limitations inherent in using ALTQ.
4299 *
4300 * When ALTQ support is compiled in, all iflib drivers will use a transmit
4301 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the
4302 * given interface. If ALTQ is enabled for an interface, then all
4303 * transmitted packets for that interface will be submitted to the ALTQ
4304 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit()
4305 * implementation because it uses IFQ_HANDOFF(), which will duplicatively
4306 * update stats that the iflib machinery handles, and which is sensitve to
4307 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start()
4308 * will be installed as the start routine for use by ALTQ facilities that
4309 * need to trigger queue drains on a scheduled basis.
4310 *
4311 */
4312 static void
iflib_altq_if_start(if_t ifp)4313 iflib_altq_if_start(if_t ifp)
4314 {
4315 struct ifaltq *ifq = &ifp->if_snd; /* XXX - DRVAPI */
4316 struct mbuf *m;
4317
4318 IFQ_LOCK(ifq);
4319 IFQ_DEQUEUE_NOLOCK(ifq, m);
4320 while (m != NULL) {
4321 iflib_if_transmit(ifp, m);
4322 IFQ_DEQUEUE_NOLOCK(ifq, m);
4323 }
4324 IFQ_UNLOCK(ifq);
4325 }
4326
4327 static int
iflib_altq_if_transmit(if_t ifp,struct mbuf * m)4328 iflib_altq_if_transmit(if_t ifp, struct mbuf *m)
4329 {
4330 int err;
4331
4332 if (if_altq_is_enabled(ifp)) {
4333 IFQ_ENQUEUE(&ifp->if_snd, m, err); /* XXX - DRVAPI */
4334 if (err == 0)
4335 iflib_altq_if_start(ifp);
4336 } else
4337 err = iflib_if_transmit(ifp, m);
4338
4339 return (err);
4340 }
4341 #endif /* ALTQ */
4342
4343 static void
iflib_if_qflush(if_t ifp)4344 iflib_if_qflush(if_t ifp)
4345 {
4346 if_ctx_t ctx = if_getsoftc(ifp);
4347 iflib_txq_t txq = ctx->ifc_txqs;
4348 int i;
4349
4350 STATE_LOCK(ctx);
4351 ctx->ifc_flags |= IFC_QFLUSH;
4352 STATE_UNLOCK(ctx);
4353 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
4354 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br)))
4355 iflib_txq_check_drain(txq, 0);
4356 STATE_LOCK(ctx);
4357 ctx->ifc_flags &= ~IFC_QFLUSH;
4358 STATE_UNLOCK(ctx);
4359
4360 /*
4361 * When ALTQ is enabled, this will also take care of purging the
4362 * ALTQ queue(s).
4363 */
4364 if_qflush(ifp);
4365 }
4366
4367 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \
4368 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \
4369 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \
4370 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG)
4371
4372 static int
iflib_if_ioctl(if_t ifp,u_long command,caddr_t data)4373 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data)
4374 {
4375 if_ctx_t ctx = if_getsoftc(ifp);
4376 struct ifreq *ifr = (struct ifreq *)data;
4377 #if defined(INET) || defined(INET6)
4378 struct ifaddr *ifa = (struct ifaddr *)data;
4379 #endif
4380 bool avoid_reset = false;
4381 int err = 0, reinit = 0, bits;
4382
4383 switch (command) {
4384 case SIOCSIFADDR:
4385 #ifdef INET
4386 if (ifa->ifa_addr->sa_family == AF_INET)
4387 avoid_reset = true;
4388 #endif
4389 #ifdef INET6
4390 if (ifa->ifa_addr->sa_family == AF_INET6)
4391 avoid_reset = true;
4392 #endif
4393 /*
4394 * Calling init results in link renegotiation,
4395 * so we avoid doing it when possible.
4396 */
4397 if (avoid_reset) {
4398 if_setflagbits(ifp, IFF_UP, 0);
4399 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4400 reinit = 1;
4401 #ifdef INET
4402 if (!(if_getflags(ifp) & IFF_NOARP))
4403 arp_ifinit(ifp, ifa);
4404 #endif
4405 } else
4406 err = ether_ioctl(ifp, command, data);
4407 break;
4408 case SIOCSIFMTU:
4409 CTX_LOCK(ctx);
4410 if (ifr->ifr_mtu == if_getmtu(ifp)) {
4411 CTX_UNLOCK(ctx);
4412 break;
4413 }
4414 bits = if_getdrvflags(ifp);
4415 /* stop the driver and free any clusters before proceeding */
4416 iflib_stop(ctx);
4417
4418 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) {
4419 STATE_LOCK(ctx);
4420 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size)
4421 ctx->ifc_flags |= IFC_MULTISEG;
4422 else
4423 ctx->ifc_flags &= ~IFC_MULTISEG;
4424 STATE_UNLOCK(ctx);
4425 err = if_setmtu(ifp, ifr->ifr_mtu);
4426 }
4427 iflib_init_locked(ctx);
4428 STATE_LOCK(ctx);
4429 if_setdrvflags(ifp, bits);
4430 STATE_UNLOCK(ctx);
4431 CTX_UNLOCK(ctx);
4432 break;
4433 case SIOCSIFFLAGS:
4434 CTX_LOCK(ctx);
4435 if (if_getflags(ifp) & IFF_UP) {
4436 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4437 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) &
4438 (IFF_PROMISC | IFF_ALLMULTI)) {
4439 CTX_UNLOCK(ctx);
4440 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp));
4441 CTX_LOCK(ctx);
4442 }
4443 } else
4444 reinit = 1;
4445 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4446 iflib_stop(ctx);
4447 }
4448 ctx->ifc_if_flags = if_getflags(ifp);
4449 CTX_UNLOCK(ctx);
4450 break;
4451 case SIOCADDMULTI:
4452 case SIOCDELMULTI:
4453 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4454 CTX_LOCK(ctx);
4455 IFDI_INTR_DISABLE(ctx);
4456 IFDI_MULTI_SET(ctx);
4457 IFDI_INTR_ENABLE(ctx);
4458 CTX_UNLOCK(ctx);
4459 }
4460 break;
4461 case SIOCSIFMEDIA:
4462 CTX_LOCK(ctx);
4463 IFDI_MEDIA_SET(ctx);
4464 CTX_UNLOCK(ctx);
4465 /* FALLTHROUGH */
4466 case SIOCGIFMEDIA:
4467 case SIOCGIFXMEDIA:
4468 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command);
4469 break;
4470 case SIOCGI2C:
4471 {
4472 struct ifi2creq i2c;
4473
4474 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
4475 if (err != 0)
4476 break;
4477 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
4478 err = EINVAL;
4479 break;
4480 }
4481 if (i2c.len > sizeof(i2c.data)) {
4482 err = EINVAL;
4483 break;
4484 }
4485
4486 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0)
4487 err = copyout(&i2c, ifr_data_get_ptr(ifr),
4488 sizeof(i2c));
4489 break;
4490 }
4491 case SIOCSIFCAP:
4492 {
4493 int mask, setmask, oldmask;
4494
4495 oldmask = if_getcapenable(ifp);
4496 mask = ifr->ifr_reqcap ^ oldmask;
4497 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG;
4498 setmask = 0;
4499 #ifdef TCP_OFFLOAD
4500 setmask |= mask & (IFCAP_TOE4 | IFCAP_TOE6);
4501 #endif
4502 setmask |= (mask & IFCAP_FLAGS);
4503 setmask |= (mask & IFCAP_WOL);
4504
4505 /*
4506 * If any RX csum has changed, change all the ones that
4507 * are supported by the driver.
4508 */
4509 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) {
4510 setmask |= ctx->ifc_softc_ctx.isc_capabilities &
4511 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6);
4512 }
4513
4514 /*
4515 * want to ensure that traffic has stopped before we change any of the flags
4516 */
4517 if (setmask) {
4518 CTX_LOCK(ctx);
4519 bits = if_getdrvflags(ifp);
4520 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4521 iflib_stop(ctx);
4522 STATE_LOCK(ctx);
4523 if_togglecapenable(ifp, setmask);
4524 ctx->ifc_softc_ctx.isc_capenable ^= setmask;
4525 STATE_UNLOCK(ctx);
4526 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL)
4527 iflib_init_locked(ctx);
4528 STATE_LOCK(ctx);
4529 if_setdrvflags(ifp, bits);
4530 STATE_UNLOCK(ctx);
4531 CTX_UNLOCK(ctx);
4532 }
4533 if_vlancap(ifp);
4534 break;
4535 }
4536 case SIOCGPRIVATE_0:
4537 case SIOCSDRVSPEC:
4538 case SIOCGDRVSPEC:
4539 CTX_LOCK(ctx);
4540 err = IFDI_PRIV_IOCTL(ctx, command, data);
4541 CTX_UNLOCK(ctx);
4542 break;
4543 default:
4544 err = ether_ioctl(ifp, command, data);
4545 break;
4546 }
4547 if (reinit)
4548 iflib_if_init(ctx);
4549 return (err);
4550 }
4551
4552 static uint64_t
iflib_if_get_counter(if_t ifp,ift_counter cnt)4553 iflib_if_get_counter(if_t ifp, ift_counter cnt)
4554 {
4555 if_ctx_t ctx = if_getsoftc(ifp);
4556
4557 return (IFDI_GET_COUNTER(ctx, cnt));
4558 }
4559
4560 /*********************************************************************
4561 *
4562 * OTHER FUNCTIONS EXPORTED TO THE STACK
4563 *
4564 **********************************************************************/
4565
4566 static void
iflib_vlan_register(void * arg,if_t ifp,uint16_t vtag)4567 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag)
4568 {
4569 if_ctx_t ctx = if_getsoftc(ifp);
4570
4571 if ((void *)ctx != arg)
4572 return;
4573
4574 if ((vtag == 0) || (vtag > 4095))
4575 return;
4576
4577 if (iflib_in_detach(ctx))
4578 return;
4579
4580 CTX_LOCK(ctx);
4581 /* Driver may need all untagged packets to be flushed */
4582 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4583 iflib_stop(ctx);
4584 IFDI_VLAN_REGISTER(ctx, vtag);
4585 /* Re-init to load the changes, if required */
4586 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4587 iflib_init_locked(ctx);
4588 CTX_UNLOCK(ctx);
4589 }
4590
4591 static void
iflib_vlan_unregister(void * arg,if_t ifp,uint16_t vtag)4592 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag)
4593 {
4594 if_ctx_t ctx = if_getsoftc(ifp);
4595
4596 if ((void *)ctx != arg)
4597 return;
4598
4599 if ((vtag == 0) || (vtag > 4095))
4600 return;
4601
4602 CTX_LOCK(ctx);
4603 /* Driver may need all tagged packets to be flushed */
4604 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4605 iflib_stop(ctx);
4606 IFDI_VLAN_UNREGISTER(ctx, vtag);
4607 /* Re-init to load the changes, if required */
4608 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG))
4609 iflib_init_locked(ctx);
4610 CTX_UNLOCK(ctx);
4611 }
4612
4613 static void
iflib_led_func(void * arg,int onoff)4614 iflib_led_func(void *arg, int onoff)
4615 {
4616 if_ctx_t ctx = arg;
4617
4618 CTX_LOCK(ctx);
4619 IFDI_LED_FUNC(ctx, onoff);
4620 CTX_UNLOCK(ctx);
4621 }
4622
4623 /*********************************************************************
4624 *
4625 * BUS FUNCTION DEFINITIONS
4626 *
4627 **********************************************************************/
4628
4629 int
iflib_device_probe(device_t dev)4630 iflib_device_probe(device_t dev)
4631 {
4632 const pci_vendor_info_t *ent;
4633 if_shared_ctx_t sctx;
4634 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id;
4635 uint16_t pci_vendor_id;
4636
4637 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
4638 return (ENOTSUP);
4639
4640 pci_vendor_id = pci_get_vendor(dev);
4641 pci_device_id = pci_get_device(dev);
4642 pci_subvendor_id = pci_get_subvendor(dev);
4643 pci_subdevice_id = pci_get_subdevice(dev);
4644 pci_rev_id = pci_get_revid(dev);
4645 if (sctx->isc_parse_devinfo != NULL)
4646 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id);
4647
4648 ent = sctx->isc_vendor_info;
4649 while (ent->pvi_vendor_id != 0) {
4650 if (pci_vendor_id != ent->pvi_vendor_id) {
4651 ent++;
4652 continue;
4653 }
4654 if ((pci_device_id == ent->pvi_device_id) &&
4655 ((pci_subvendor_id == ent->pvi_subvendor_id) ||
4656 (ent->pvi_subvendor_id == 0)) &&
4657 ((pci_subdevice_id == ent->pvi_subdevice_id) ||
4658 (ent->pvi_subdevice_id == 0)) &&
4659 ((pci_rev_id == ent->pvi_rev_id) ||
4660 (ent->pvi_rev_id == 0))) {
4661 device_set_desc_copy(dev, ent->pvi_name);
4662 /* this needs to be changed to zero if the bus probing code
4663 * ever stops re-probing on best match because the sctx
4664 * may have its values over written by register calls
4665 * in subsequent probes
4666 */
4667 return (BUS_PROBE_DEFAULT);
4668 }
4669 ent++;
4670 }
4671 return (ENXIO);
4672 }
4673
4674 int
iflib_device_probe_vendor(device_t dev)4675 iflib_device_probe_vendor(device_t dev)
4676 {
4677 int probe;
4678
4679 probe = iflib_device_probe(dev);
4680 if (probe == BUS_PROBE_DEFAULT)
4681 return (BUS_PROBE_VENDOR);
4682 else
4683 return (probe);
4684 }
4685
4686 static void
iflib_reset_qvalues(if_ctx_t ctx)4687 iflib_reset_qvalues(if_ctx_t ctx)
4688 {
4689 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4690 if_shared_ctx_t sctx = ctx->ifc_sctx;
4691 device_t dev = ctx->ifc_dev;
4692 int i;
4693
4694 if (ctx->ifc_sysctl_ntxqs != 0)
4695 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs;
4696 if (ctx->ifc_sysctl_nrxqs != 0)
4697 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs;
4698
4699 for (i = 0; i < sctx->isc_ntxqs; i++) {
4700 if (ctx->ifc_sysctl_ntxds[i] != 0)
4701 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i];
4702 else
4703 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4704 }
4705
4706 for (i = 0; i < sctx->isc_nrxqs; i++) {
4707 if (ctx->ifc_sysctl_nrxds[i] != 0)
4708 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i];
4709 else
4710 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4711 }
4712
4713 for (i = 0; i < sctx->isc_nrxqs; i++) {
4714 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) {
4715 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n",
4716 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]);
4717 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i];
4718 }
4719 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) {
4720 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n",
4721 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]);
4722 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i];
4723 }
4724 if (!powerof2(scctx->isc_nrxd[i])) {
4725 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n",
4726 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]);
4727 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i];
4728 }
4729 }
4730
4731 for (i = 0; i < sctx->isc_ntxqs; i++) {
4732 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) {
4733 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n",
4734 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]);
4735 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i];
4736 }
4737 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) {
4738 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n",
4739 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]);
4740 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i];
4741 }
4742 if (!powerof2(scctx->isc_ntxd[i])) {
4743 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n",
4744 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]);
4745 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i];
4746 }
4747 }
4748 scctx->isc_tx_pad = 2;
4749 }
4750
4751 static void
iflib_add_pfil(if_ctx_t ctx)4752 iflib_add_pfil(if_ctx_t ctx)
4753 {
4754 struct pfil_head *pfil;
4755 struct pfil_head_args pa;
4756 iflib_rxq_t rxq;
4757 int i;
4758
4759 pa.pa_version = PFIL_VERSION;
4760 pa.pa_flags = PFIL_IN;
4761 pa.pa_type = PFIL_TYPE_ETHERNET;
4762 pa.pa_headname = if_name(ctx->ifc_ifp);
4763 pfil = pfil_head_register(&pa);
4764
4765 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
4766 rxq->pfil = pfil;
4767 }
4768 }
4769
4770 static void
iflib_rem_pfil(if_ctx_t ctx)4771 iflib_rem_pfil(if_ctx_t ctx)
4772 {
4773 struct pfil_head *pfil;
4774 iflib_rxq_t rxq;
4775 int i;
4776
4777 rxq = ctx->ifc_rxqs;
4778 pfil = rxq->pfil;
4779 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) {
4780 rxq->pfil = NULL;
4781 }
4782 pfil_head_unregister(pfil);
4783 }
4784
4785
4786 /*
4787 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from
4788 * cpuid and wrapping as necessary.
4789 */
4790 static unsigned int
cpuid_advance(if_ctx_t ctx,unsigned int cpuid,unsigned int n)4791 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n)
4792 {
4793 unsigned int first_valid;
4794 unsigned int last_valid;
4795
4796 /* cpuid should always be in the valid set */
4797 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus));
4798
4799 /* valid set should never be empty */
4800 MPASS(!CPU_EMPTY(&ctx->ifc_cpus));
4801
4802 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4803 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4804 n = n % CPU_COUNT(&ctx->ifc_cpus);
4805 while (n > 0) {
4806 do {
4807 cpuid++;
4808 if (cpuid > last_valid)
4809 cpuid = first_valid;
4810 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus));
4811 n--;
4812 }
4813
4814 return (cpuid);
4815 }
4816
4817 /*
4818 * CPU mapping behaviors
4819 * ---------------------
4820 * 'separate txrx' refers to the separate_txrx sysctl
4821 * 'use logical' refers to the use_logical_cores sysctl
4822 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded
4823 *
4824 * separate use INTR
4825 * txrx logical CPUS result
4826 * ---------- --------- ------ ------------------------------------------------
4827 * - - X RX and TX queues mapped to consecutive physical
4828 * cores with RX/TX pairs on same core and excess
4829 * of either following
4830 * - X X RX and TX queues mapped to consecutive cores
4831 * of any type with RX/TX pairs on same core and
4832 * excess of either following
4833 * X - X RX and TX queues mapped to consecutive physical
4834 * cores; all RX then all TX
4835 * X X X RX queues mapped to consecutive physical cores
4836 * first, then TX queues mapped to L2 neighbor of
4837 * the corresponding RX queue if one exists,
4838 * otherwise to consecutive physical cores
4839 * - n/a - RX and TX queues mapped to consecutive cores of
4840 * any type with RX/TX pairs on same core and excess
4841 * of either following
4842 * X n/a - RX and TX queues mapped to consecutive cores of
4843 * any type; all RX then all TX
4844 */
4845 static unsigned int
get_cpuid_for_queue(if_ctx_t ctx,unsigned int base_cpuid,unsigned int qid,bool is_tx)4846 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid,
4847 bool is_tx)
4848 {
4849 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4850 unsigned int core_index;
4851
4852 if (ctx->ifc_sysctl_separate_txrx) {
4853 /*
4854 * When using separate CPUs for TX and RX, the assignment
4855 * will always be of a consecutive CPU out of the set of
4856 * context CPUs, except for the specific case where the
4857 * context CPUs are phsyical cores, the use of logical cores
4858 * has been enabled, the assignment is for TX, the TX qid
4859 * corresponds to an RX qid, and the CPU assigned to the
4860 * corresponding RX queue has an L2 neighbor.
4861 */
4862 if (ctx->ifc_sysctl_use_logical_cores &&
4863 ctx->ifc_cpus_are_physical_cores &&
4864 is_tx && qid < scctx->isc_nrxqsets) {
4865 int l2_neighbor;
4866 unsigned int rx_cpuid;
4867
4868 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid);
4869 l2_neighbor = sched_find_l2_neighbor(rx_cpuid);
4870 if (l2_neighbor != -1) {
4871 return (l2_neighbor);
4872 }
4873 /*
4874 * ... else fall through to the normal
4875 * consecutive-after-RX assignment scheme.
4876 *
4877 * Note that we are assuming that all RX queue CPUs
4878 * have an L2 neighbor, or all do not. If a mixed
4879 * scenario is possible, we will have to keep track
4880 * separately of how many queues prior to this one
4881 * were not able to be assigned to an L2 neighbor.
4882 */
4883 }
4884 if (is_tx)
4885 core_index = scctx->isc_nrxqsets + qid;
4886 else
4887 core_index = qid;
4888 } else {
4889 core_index = qid;
4890 }
4891
4892 return (cpuid_advance(ctx, base_cpuid, core_index));
4893 }
4894
4895 static uint16_t
get_ctx_core_offset(if_ctx_t ctx)4896 get_ctx_core_offset(if_ctx_t ctx)
4897 {
4898 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
4899 struct cpu_offset *op;
4900 cpuset_t assigned_cpus;
4901 unsigned int cores_consumed;
4902 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset;
4903 unsigned int first_valid;
4904 unsigned int last_valid;
4905 unsigned int i;
4906
4907 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1;
4908 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1;
4909
4910 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) {
4911 /*
4912 * Align the user-chosen base CPU ID to the next valid CPU
4913 * for this device. If the chosen base CPU ID is smaller
4914 * than the first valid CPU or larger than the last valid
4915 * CPU, we assume the user does not know what the valid
4916 * range is for this device and is thinking in terms of a
4917 * zero-based reference frame, and so we shift the given
4918 * value into the valid range (and wrap accordingly) so the
4919 * intent is translated to the proper frame of reference.
4920 * If the base CPU ID is within the valid first/last, but
4921 * does not correspond to a valid CPU, it is advanced to the
4922 * next valid CPU (wrapping if necessary).
4923 */
4924 if (base_cpuid < first_valid || base_cpuid > last_valid) {
4925 /* shift from zero-based to first_valid-based */
4926 base_cpuid += first_valid;
4927 /* wrap to range [first_valid, last_valid] */
4928 base_cpuid = (base_cpuid - first_valid) %
4929 (last_valid - first_valid + 1);
4930 }
4931 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) {
4932 /*
4933 * base_cpuid is in [first_valid, last_valid], but
4934 * not a member of the valid set. In this case,
4935 * there will always be a member of the valid set
4936 * with a CPU ID that is greater than base_cpuid,
4937 * and we simply advance to it.
4938 */
4939 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus))
4940 base_cpuid++;
4941 }
4942 return (base_cpuid);
4943 }
4944
4945 /*
4946 * Determine how many cores will be consumed by performing the CPU
4947 * assignments and counting how many of the assigned CPUs correspond
4948 * to CPUs in the set of context CPUs. This is done using the CPU
4949 * ID first_valid as the base CPU ID, as the base CPU must be within
4950 * the set of context CPUs.
4951 *
4952 * Note not all assigned CPUs will be in the set of context CPUs
4953 * when separate CPUs are being allocated to TX and RX queues,
4954 * assignment to logical cores has been enabled, the set of context
4955 * CPUs contains only physical CPUs, and TX queues are mapped to L2
4956 * neighbors of CPUs that RX queues have been mapped to - in this
4957 * case we do only want to count how many CPUs in the set of context
4958 * CPUs have been consumed, as that determines the next CPU in that
4959 * set to start allocating at for the next device for which
4960 * core_offset is not set.
4961 */
4962 CPU_ZERO(&assigned_cpus);
4963 for (i = 0; i < scctx->isc_ntxqsets; i++)
4964 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true),
4965 &assigned_cpus);
4966 for (i = 0; i < scctx->isc_nrxqsets; i++)
4967 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false),
4968 &assigned_cpus);
4969 CPU_AND(&assigned_cpus, &assigned_cpus, &ctx->ifc_cpus);
4970 cores_consumed = CPU_COUNT(&assigned_cpus);
4971
4972 mtx_lock(&cpu_offset_mtx);
4973 SLIST_FOREACH(op, &cpu_offsets, entries) {
4974 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
4975 base_cpuid = op->next_cpuid;
4976 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid,
4977 cores_consumed);
4978 MPASS(op->refcount < UINT_MAX);
4979 op->refcount++;
4980 break;
4981 }
4982 }
4983 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) {
4984 base_cpuid = first_valid;
4985 op = malloc(sizeof(struct cpu_offset), M_IFLIB,
4986 M_NOWAIT | M_ZERO);
4987 if (op == NULL) {
4988 device_printf(ctx->ifc_dev,
4989 "allocation for cpu offset failed.\n");
4990 } else {
4991 op->next_cpuid = cpuid_advance(ctx, base_cpuid,
4992 cores_consumed);
4993 op->refcount = 1;
4994 CPU_COPY(&ctx->ifc_cpus, &op->set);
4995 SLIST_INSERT_HEAD(&cpu_offsets, op, entries);
4996 }
4997 }
4998 mtx_unlock(&cpu_offset_mtx);
4999
5000 return (base_cpuid);
5001 }
5002
5003 static void
unref_ctx_core_offset(if_ctx_t ctx)5004 unref_ctx_core_offset(if_ctx_t ctx)
5005 {
5006 struct cpu_offset *op, *top;
5007
5008 mtx_lock(&cpu_offset_mtx);
5009 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) {
5010 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) {
5011 MPASS(op->refcount > 0);
5012 op->refcount--;
5013 if (op->refcount == 0) {
5014 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries);
5015 free(op, M_IFLIB);
5016 }
5017 break;
5018 }
5019 }
5020 mtx_unlock(&cpu_offset_mtx);
5021 }
5022
5023 int
iflib_device_register(device_t dev,void * sc,if_shared_ctx_t sctx,if_ctx_t * ctxp)5024 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp)
5025 {
5026 if_ctx_t ctx;
5027 if_t ifp;
5028 if_softc_ctx_t scctx;
5029 kobjop_desc_t kobj_desc;
5030 kobj_method_t *kobj_method;
5031 int err, msix, rid;
5032 int num_txd, num_rxd;
5033 char namebuf[TASKQUEUE_NAMELEN];
5034
5035 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK | M_ZERO);
5036
5037 if (sc == NULL) {
5038 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK | M_ZERO);
5039 device_set_softc(dev, ctx);
5040 ctx->ifc_flags |= IFC_SC_ALLOCATED;
5041 }
5042
5043 ctx->ifc_sctx = sctx;
5044 ctx->ifc_dev = dev;
5045 ctx->ifc_softc = sc;
5046
5047 iflib_register(ctx);
5048 iflib_add_device_sysctl_pre(ctx);
5049
5050 scctx = &ctx->ifc_softc_ctx;
5051 ifp = ctx->ifc_ifp;
5052 if (ctx->ifc_sysctl_simple_tx) {
5053 #ifndef ALTQ
5054 if_settransmitfn(ifp, iflib_simple_transmit);
5055 device_printf(dev, "using simple if_transmit\n");
5056 #else
5057 device_printf(dev, "ALTQ prevents using simple if_transmit\n");
5058 #endif
5059 }
5060 iflib_reset_qvalues(ctx);
5061 IFNET_WLOCK();
5062 CTX_LOCK(ctx);
5063 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) {
5064 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err);
5065 goto fail_unlock;
5066 }
5067 _iflib_pre_assert(scctx);
5068 ctx->ifc_txrx = *scctx->isc_txrx;
5069
5070 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR));
5071
5072 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA)
5073 ctx->ifc_mediap = scctx->isc_media;
5074
5075 #ifdef INVARIANTS
5076 if (scctx->isc_capabilities & IFCAP_TXCSUM)
5077 MPASS(scctx->isc_tx_csum_flags);
5078 #endif
5079
5080 if_setcapabilities(ifp,
5081 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG);
5082 if_setcapenable(ifp,
5083 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG);
5084
5085 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets))
5086 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max;
5087 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets))
5088 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max;
5089
5090 num_txd = iflib_num_tx_descs(ctx);
5091 num_rxd = iflib_num_rx_descs(ctx);
5092
5093 /* XXX change for per-queue sizes */
5094 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n",
5095 num_txd, num_rxd);
5096
5097 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION)
5098 scctx->isc_tx_nsegments = max(1, num_txd /
5099 MAX_SINGLE_PACKET_FRACTION);
5100 if (scctx->isc_tx_tso_segments_max > num_txd /
5101 MAX_SINGLE_PACKET_FRACTION)
5102 scctx->isc_tx_tso_segments_max = max(1,
5103 num_txd / MAX_SINGLE_PACKET_FRACTION);
5104
5105 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */
5106 if (if_getcapabilities(ifp) & IFCAP_TSO) {
5107 /*
5108 * The stack can't handle a TSO size larger than IP_MAXPACKET,
5109 * but some MACs do.
5110 */
5111 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max,
5112 IP_MAXPACKET));
5113 /*
5114 * Take maximum number of m_pullup(9)'s in iflib_parse_header()
5115 * into account. In the worst case, each of these calls will
5116 * add another mbuf and, thus, the requirement for another DMA
5117 * segment. So for best performance, it doesn't make sense to
5118 * advertize a maximum of TSO segments that typically will
5119 * require defragmentation in iflib_encap().
5120 */
5121 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3);
5122 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max);
5123 }
5124 if (scctx->isc_rss_table_size == 0)
5125 scctx->isc_rss_table_size = 64;
5126 scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1;
5127
5128 /* Create and start admin taskqueue */
5129 snprintf(namebuf, TASKQUEUE_NAMELEN, "if_%s_tq", device_get_nameunit(dev));
5130 ctx->ifc_tq = taskqueue_create_fast(namebuf, M_NOWAIT,
5131 taskqueue_thread_enqueue, &ctx->ifc_tq);
5132 if (ctx->ifc_tq == NULL) {
5133 device_printf(dev, "Unable to create admin taskqueue\n");
5134 return (ENOMEM);
5135 }
5136
5137 err = taskqueue_start_threads(&ctx->ifc_tq, 1, PI_NET, "%s", namebuf);
5138 if (err) {
5139 device_printf(dev,
5140 "Unable to start admin taskqueue threads error: %d\n",
5141 err);
5142 taskqueue_free(ctx->ifc_tq);
5143 return (err);
5144 }
5145
5146 TASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx);
5147
5148 /* Set up cpu set. If it fails, use the set of all CPUs. */
5149 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) {
5150 device_printf(dev, "Unable to fetch CPU list\n");
5151 CPU_COPY(&all_cpus, &ctx->ifc_cpus);
5152 ctx->ifc_cpus_are_physical_cores = false;
5153 } else
5154 ctx->ifc_cpus_are_physical_cores = true;
5155 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0);
5156
5157 /*
5158 * Now set up MSI or MSI-X, should return us the number of supported
5159 * vectors (will be 1 for a legacy interrupt and MSI).
5160 */
5161 if (sctx->isc_flags & IFLIB_SKIP_MSIX) {
5162 msix = scctx->isc_vectors;
5163 } else if (scctx->isc_msix_bar != 0)
5164 /*
5165 * The simple fact that isc_msix_bar is not 0 does not mean we
5166 * we have a good value there that is known to work.
5167 */
5168 msix = iflib_msix_init(ctx);
5169 else {
5170 scctx->isc_vectors = 1;
5171 scctx->isc_ntxqsets = 1;
5172 scctx->isc_nrxqsets = 1;
5173 scctx->isc_intr = IFLIB_INTR_LEGACY;
5174 msix = 0;
5175 }
5176 /* Get memory for the station queues */
5177 if ((err = iflib_queues_alloc(ctx))) {
5178 device_printf(dev, "Unable to allocate queue memory\n");
5179 goto fail_intr_free;
5180 }
5181
5182 if ((err = iflib_qset_structures_setup(ctx)))
5183 goto fail_queues;
5184
5185 /*
5186 * Now that we know how many queues there are, get the core offset.
5187 */
5188 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx);
5189
5190 if (msix > 1) {
5191 /*
5192 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable
5193 * aren't the default NULL implementation.
5194 */
5195 kobj_desc = &ifdi_rx_queue_intr_enable_desc;
5196 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5197 kobj_desc);
5198 if (kobj_method == &kobj_desc->deflt) {
5199 device_printf(dev,
5200 "MSI-X requires ifdi_rx_queue_intr_enable method");
5201 err = EOPNOTSUPP;
5202 goto fail_queues;
5203 }
5204 kobj_desc = &ifdi_tx_queue_intr_enable_desc;
5205 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL,
5206 kobj_desc);
5207 if (kobj_method == &kobj_desc->deflt) {
5208 device_printf(dev,
5209 "MSI-X requires ifdi_tx_queue_intr_enable method");
5210 err = EOPNOTSUPP;
5211 goto fail_queues;
5212 }
5213
5214 /*
5215 * Assign the MSI-X vectors.
5216 * Note that the default NULL ifdi_msix_intr_assign method will
5217 * fail here, too.
5218 */
5219 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix);
5220 if (err != 0) {
5221 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n",
5222 err);
5223 goto fail_queues;
5224 }
5225 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) {
5226 rid = 0;
5227 if (scctx->isc_intr == IFLIB_INTR_MSI) {
5228 MPASS(msix == 1);
5229 rid = 1;
5230 }
5231 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) {
5232 device_printf(dev, "iflib_legacy_setup failed %d\n", err);
5233 goto fail_queues;
5234 }
5235 } else {
5236 device_printf(dev,
5237 "Cannot use iflib with only 1 MSI-X interrupt!\n");
5238 err = ENODEV;
5239 goto fail_queues;
5240 }
5241
5242 /*
5243 * It prevents a double-locking panic with iflib_media_status when
5244 * the driver loads.
5245 */
5246 CTX_UNLOCK(ctx);
5247 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet);
5248 CTX_LOCK(ctx);
5249
5250 if ((err = IFDI_ATTACH_POST(ctx)) != 0) {
5251 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err);
5252 goto fail_detach;
5253 }
5254
5255 /*
5256 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported.
5257 * This must appear after the call to ether_ifattach() because
5258 * ether_ifattach() sets if_hdrlen to the default value.
5259 */
5260 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU)
5261 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
5262
5263 if ((err = iflib_netmap_attach(ctx))) {
5264 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err);
5265 goto fail_detach;
5266 }
5267 *ctxp = ctx;
5268
5269 DEBUGNET_SET(ctx->ifc_ifp, iflib);
5270
5271 iflib_add_device_sysctl_post(ctx);
5272 iflib_add_pfil(ctx);
5273 ctx->ifc_flags |= IFC_INIT_DONE;
5274 CTX_UNLOCK(ctx);
5275 IFNET_WUNLOCK();
5276
5277 return (0);
5278
5279 fail_detach:
5280 ether_ifdetach(ctx->ifc_ifp);
5281 fail_queues:
5282 taskqueue_free(ctx->ifc_tq);
5283 iflib_tqg_detach(ctx);
5284 iflib_tx_structures_free(ctx);
5285 iflib_rx_structures_free(ctx);
5286 IFDI_DETACH(ctx);
5287 IFDI_QUEUES_FREE(ctx);
5288 fail_intr_free:
5289 iflib_free_intr_mem(ctx);
5290 fail_unlock:
5291 CTX_UNLOCK(ctx);
5292 IFNET_WUNLOCK();
5293 iflib_deregister(ctx);
5294 device_set_softc(ctx->ifc_dev, NULL);
5295 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5296 free(ctx->ifc_softc, M_IFLIB);
5297 free(ctx, M_IFLIB);
5298 return (err);
5299 }
5300
5301 int
iflib_device_attach(device_t dev)5302 iflib_device_attach(device_t dev)
5303 {
5304 if_ctx_t ctx;
5305 if_shared_ctx_t sctx;
5306
5307 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC)
5308 return (ENOTSUP);
5309
5310 pci_enable_busmaster(dev);
5311
5312 return (iflib_device_register(dev, NULL, sctx, &ctx));
5313 }
5314
5315 int
iflib_device_deregister(if_ctx_t ctx)5316 iflib_device_deregister(if_ctx_t ctx)
5317 {
5318 if_t ifp = ctx->ifc_ifp;
5319 device_t dev = ctx->ifc_dev;
5320
5321 /* Make sure VLANS are not using driver */
5322 if (if_vlantrunkinuse(ifp)) {
5323 device_printf(dev, "Vlan in use, detach first\n");
5324 return (EBUSY);
5325 }
5326 #ifdef PCI_IOV
5327 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) {
5328 device_printf(dev, "SR-IOV in use; detach first.\n");
5329 return (EBUSY);
5330 }
5331 #endif
5332
5333 STATE_LOCK(ctx);
5334 ctx->ifc_flags |= IFC_IN_DETACH;
5335 STATE_UNLOCK(ctx);
5336
5337 /* Unregister VLAN handlers before calling iflib_stop() */
5338 iflib_unregister_vlan_handlers(ctx);
5339
5340 iflib_netmap_detach(ifp);
5341 ether_ifdetach(ifp);
5342
5343 CTX_LOCK(ctx);
5344 iflib_stop(ctx);
5345 CTX_UNLOCK(ctx);
5346
5347 iflib_rem_pfil(ctx);
5348 if (ctx->ifc_led_dev != NULL)
5349 led_destroy(ctx->ifc_led_dev);
5350
5351 iflib_tqg_detach(ctx);
5352 iflib_tx_structures_free(ctx);
5353 iflib_rx_structures_free(ctx);
5354
5355 CTX_LOCK(ctx);
5356 IFDI_DETACH(ctx);
5357 IFDI_QUEUES_FREE(ctx);
5358 CTX_UNLOCK(ctx);
5359
5360 taskqueue_free(ctx->ifc_tq);
5361 ctx->ifc_tq = NULL;
5362
5363 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5364 iflib_free_intr_mem(ctx);
5365
5366 bus_generic_detach(dev);
5367
5368 iflib_deregister(ctx);
5369
5370 device_set_softc(ctx->ifc_dev, NULL);
5371 if (ctx->ifc_flags & IFC_SC_ALLOCATED)
5372 free(ctx->ifc_softc, M_IFLIB);
5373 unref_ctx_core_offset(ctx);
5374 free(ctx, M_IFLIB);
5375 return (0);
5376 }
5377
5378 static void
iflib_tqg_detach(if_ctx_t ctx)5379 iflib_tqg_detach(if_ctx_t ctx)
5380 {
5381 iflib_txq_t txq;
5382 iflib_rxq_t rxq;
5383 int i;
5384 struct taskqgroup *tqg;
5385
5386 /* XXX drain any dependent tasks */
5387 tqg = qgroup_if_io_tqg;
5388 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) {
5389 callout_drain(&txq->ift_timer);
5390 #ifdef DEV_NETMAP
5391 callout_drain(&txq->ift_netmap_timer);
5392 #endif /* DEV_NETMAP */
5393 if (txq->ift_task.gt_uniq != NULL)
5394 taskqgroup_detach(tqg, &txq->ift_task);
5395 }
5396 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) {
5397 if (rxq->ifr_task.gt_uniq != NULL)
5398 taskqgroup_detach(tqg, &rxq->ifr_task);
5399 }
5400 }
5401
5402 static void
iflib_free_intr_mem(if_ctx_t ctx)5403 iflib_free_intr_mem(if_ctx_t ctx)
5404 {
5405
5406 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) {
5407 iflib_irq_free(ctx, &ctx->ifc_legacy_irq);
5408 }
5409 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) {
5410 pci_release_msi(ctx->ifc_dev);
5411 }
5412 if (ctx->ifc_msix_mem != NULL) {
5413 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY,
5414 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem);
5415 ctx->ifc_msix_mem = NULL;
5416 }
5417 }
5418
5419 int
iflib_device_detach(device_t dev)5420 iflib_device_detach(device_t dev)
5421 {
5422 if_ctx_t ctx = device_get_softc(dev);
5423
5424 return (iflib_device_deregister(ctx));
5425 }
5426
5427 int
iflib_device_suspend(device_t dev)5428 iflib_device_suspend(device_t dev)
5429 {
5430 if_ctx_t ctx = device_get_softc(dev);
5431
5432 CTX_LOCK(ctx);
5433 IFDI_SUSPEND(ctx);
5434 CTX_UNLOCK(ctx);
5435
5436 return (bus_generic_suspend(dev));
5437 }
5438 int
iflib_device_shutdown(device_t dev)5439 iflib_device_shutdown(device_t dev)
5440 {
5441 if_ctx_t ctx = device_get_softc(dev);
5442
5443 CTX_LOCK(ctx);
5444 IFDI_SHUTDOWN(ctx);
5445 CTX_UNLOCK(ctx);
5446
5447 return (bus_generic_suspend(dev));
5448 }
5449
5450 int
iflib_device_resume(device_t dev)5451 iflib_device_resume(device_t dev)
5452 {
5453 if_ctx_t ctx = device_get_softc(dev);
5454 iflib_txq_t txq = ctx->ifc_txqs;
5455
5456 CTX_LOCK(ctx);
5457 IFDI_RESUME(ctx);
5458 iflib_if_init_locked(ctx);
5459 CTX_UNLOCK(ctx);
5460 for (int i = 0; i < NTXQSETS(ctx); i++, txq++)
5461 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET);
5462
5463 return (bus_generic_resume(dev));
5464 }
5465
5466 int
iflib_device_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * params)5467 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
5468 {
5469 int error;
5470 if_ctx_t ctx = device_get_softc(dev);
5471
5472 CTX_LOCK(ctx);
5473 error = IFDI_IOV_INIT(ctx, num_vfs, params);
5474 CTX_UNLOCK(ctx);
5475
5476 return (error);
5477 }
5478
5479 void
iflib_device_iov_uninit(device_t dev)5480 iflib_device_iov_uninit(device_t dev)
5481 {
5482 if_ctx_t ctx = device_get_softc(dev);
5483
5484 CTX_LOCK(ctx);
5485 IFDI_IOV_UNINIT(ctx);
5486 CTX_UNLOCK(ctx);
5487 }
5488
5489 int
iflib_device_iov_add_vf(device_t dev,uint16_t vfnum,const nvlist_t * params)5490 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
5491 {
5492 int error;
5493 if_ctx_t ctx = device_get_softc(dev);
5494
5495 CTX_LOCK(ctx);
5496 error = IFDI_IOV_VF_ADD(ctx, vfnum, params);
5497 CTX_UNLOCK(ctx);
5498
5499 return (error);
5500 }
5501
5502 /*********************************************************************
5503 *
5504 * MODULE FUNCTION DEFINITIONS
5505 *
5506 **********************************************************************/
5507
5508 /*
5509 * - Start a fast taskqueue thread for each core
5510 * - Start a taskqueue for control operations
5511 */
5512 static int
iflib_module_init(void)5513 iflib_module_init(void)
5514 {
5515 iflib_timer_default = hz / 2;
5516 return (0);
5517 }
5518
5519 static int
iflib_module_event_handler(module_t mod,int what,void * arg)5520 iflib_module_event_handler(module_t mod, int what, void *arg)
5521 {
5522 int err;
5523
5524 switch (what) {
5525 case MOD_LOAD:
5526 if ((err = iflib_module_init()) != 0)
5527 return (err);
5528 break;
5529 case MOD_UNLOAD:
5530 return (EBUSY);
5531 default:
5532 return (EOPNOTSUPP);
5533 }
5534
5535 return (0);
5536 }
5537
5538 /*********************************************************************
5539 *
5540 * PUBLIC FUNCTION DEFINITIONS
5541 * ordered as in iflib.h
5542 *
5543 **********************************************************************/
5544
5545 static void
_iflib_assert(if_shared_ctx_t sctx)5546 _iflib_assert(if_shared_ctx_t sctx)
5547 {
5548 int i;
5549
5550 MPASS(sctx->isc_tx_maxsize);
5551 MPASS(sctx->isc_tx_maxsegsize);
5552
5553 MPASS(sctx->isc_rx_maxsize);
5554 MPASS(sctx->isc_rx_nsegments);
5555 MPASS(sctx->isc_rx_maxsegsize);
5556
5557 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8);
5558 for (i = 0; i < sctx->isc_nrxqs; i++) {
5559 MPASS(sctx->isc_nrxd_min[i]);
5560 MPASS(powerof2(sctx->isc_nrxd_min[i]));
5561 MPASS(sctx->isc_nrxd_max[i]);
5562 MPASS(powerof2(sctx->isc_nrxd_max[i]));
5563 MPASS(sctx->isc_nrxd_default[i]);
5564 MPASS(powerof2(sctx->isc_nrxd_default[i]));
5565 }
5566
5567 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8);
5568 for (i = 0; i < sctx->isc_ntxqs; i++) {
5569 MPASS(sctx->isc_ntxd_min[i]);
5570 MPASS(powerof2(sctx->isc_ntxd_min[i]));
5571 MPASS(sctx->isc_ntxd_max[i]);
5572 MPASS(powerof2(sctx->isc_ntxd_max[i]));
5573 MPASS(sctx->isc_ntxd_default[i]);
5574 MPASS(powerof2(sctx->isc_ntxd_default[i]));
5575 }
5576 }
5577
5578 static void
_iflib_pre_assert(if_softc_ctx_t scctx)5579 _iflib_pre_assert(if_softc_ctx_t scctx)
5580 {
5581
5582 MPASS(scctx->isc_txrx->ift_txd_encap);
5583 MPASS(scctx->isc_txrx->ift_txd_flush);
5584 MPASS(scctx->isc_txrx->ift_txd_credits_update);
5585 MPASS(scctx->isc_txrx->ift_rxd_available);
5586 MPASS(scctx->isc_txrx->ift_rxd_pkt_get);
5587 MPASS(scctx->isc_txrx->ift_rxd_refill);
5588 MPASS(scctx->isc_txrx->ift_rxd_flush);
5589 }
5590
5591 static void
iflib_register(if_ctx_t ctx)5592 iflib_register(if_ctx_t ctx)
5593 {
5594 if_shared_ctx_t sctx = ctx->ifc_sctx;
5595 driver_t *driver = sctx->isc_driver;
5596 device_t dev = ctx->ifc_dev;
5597 if_t ifp;
5598
5599 _iflib_assert(sctx);
5600
5601 CTX_LOCK_INIT(ctx);
5602 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev));
5603 ifp = ctx->ifc_ifp = if_alloc_dev(IFT_ETHER, dev);
5604
5605 /*
5606 * Initialize our context's device specific methods
5607 */
5608 kobj_init((kobj_t) ctx, (kobj_class_t) driver);
5609 kobj_class_compile((kobj_class_t) driver);
5610
5611 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
5612 if_setsoftc(ifp, ctx);
5613 if_setdev(ifp, dev);
5614 if_setinitfn(ifp, iflib_if_init);
5615 if_setioctlfn(ifp, iflib_if_ioctl);
5616 #ifdef ALTQ
5617 if_setstartfn(ifp, iflib_altq_if_start);
5618 if_settransmitfn(ifp, iflib_altq_if_transmit);
5619 if_setsendqready(ifp);
5620 #else
5621 if_settransmitfn(ifp, iflib_if_transmit);
5622 #endif
5623 if_setqflushfn(ifp, iflib_if_qflush);
5624 if_setgetcounterfn(ifp, iflib_if_get_counter);
5625 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
5626 ctx->ifc_vlan_attach_event =
5627 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx,
5628 EVENTHANDLER_PRI_FIRST);
5629 ctx->ifc_vlan_detach_event =
5630 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx,
5631 EVENTHANDLER_PRI_FIRST);
5632
5633 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) {
5634 ctx->ifc_mediap = &ctx->ifc_media;
5635 ifmedia_init(ctx->ifc_mediap, IFM_IMASK,
5636 iflib_media_change, iflib_media_status);
5637 }
5638 }
5639
5640 static void
iflib_unregister_vlan_handlers(if_ctx_t ctx)5641 iflib_unregister_vlan_handlers(if_ctx_t ctx)
5642 {
5643 /* Unregister VLAN events */
5644 if (ctx->ifc_vlan_attach_event != NULL) {
5645 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event);
5646 ctx->ifc_vlan_attach_event = NULL;
5647 }
5648 if (ctx->ifc_vlan_detach_event != NULL) {
5649 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event);
5650 ctx->ifc_vlan_detach_event = NULL;
5651 }
5652
5653 }
5654
5655 static void
iflib_deregister(if_ctx_t ctx)5656 iflib_deregister(if_ctx_t ctx)
5657 {
5658 if_t ifp = ctx->ifc_ifp;
5659
5660 /* Remove all media */
5661 ifmedia_removeall(&ctx->ifc_media);
5662
5663 /* Ensure that VLAN event handlers are unregistered */
5664 iflib_unregister_vlan_handlers(ctx);
5665
5666 /* Release kobject reference */
5667 kobj_delete((kobj_t) ctx, NULL);
5668
5669 /* Free the ifnet structure */
5670 if_free(ifp);
5671
5672 STATE_LOCK_DESTROY(ctx);
5673
5674 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/
5675 CTX_LOCK_DESTROY(ctx);
5676 }
5677
5678 static int
iflib_queues_alloc(if_ctx_t ctx)5679 iflib_queues_alloc(if_ctx_t ctx)
5680 {
5681 if_shared_ctx_t sctx = ctx->ifc_sctx;
5682 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
5683 device_t dev = ctx->ifc_dev;
5684 int nrxqsets = scctx->isc_nrxqsets;
5685 int ntxqsets = scctx->isc_ntxqsets;
5686 iflib_txq_t txq;
5687 iflib_rxq_t rxq;
5688 iflib_fl_t fl = NULL;
5689 int i, j, cpu, err, txconf, rxconf;
5690 iflib_dma_info_t ifdip;
5691 uint32_t *rxqsizes = scctx->isc_rxqsizes;
5692 uint32_t *txqsizes = scctx->isc_txqsizes;
5693 uint8_t nrxqs = sctx->isc_nrxqs;
5694 uint8_t ntxqs = sctx->isc_ntxqs;
5695 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1;
5696 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0);
5697 caddr_t *vaddrs;
5698 uint64_t *paddrs;
5699
5700 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1"));
5701 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1"));
5702 KASSERT(nrxqs >= fl_offset + nfree_lists,
5703 ("there must be at least a rxq for each free list"));
5704
5705 /* Allocate the TX ring struct memory */
5706 if (!(ctx->ifc_txqs =
5707 (iflib_txq_t) malloc(sizeof(struct iflib_txq) *
5708 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5709 device_printf(dev, "Unable to allocate TX ring memory\n");
5710 err = ENOMEM;
5711 goto fail;
5712 }
5713
5714 /* Now allocate the RX */
5715 if (!(ctx->ifc_rxqs =
5716 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) *
5717 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) {
5718 device_printf(dev, "Unable to allocate RX ring memory\n");
5719 err = ENOMEM;
5720 goto rx_fail;
5721 }
5722
5723 txq = ctx->ifc_txqs;
5724 rxq = ctx->ifc_rxqs;
5725
5726 /*
5727 * XXX handle allocation failure
5728 */
5729 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) {
5730 /* Set up some basics */
5731
5732 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs,
5733 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5734 device_printf(dev,
5735 "Unable to allocate TX DMA info memory\n");
5736 err = ENOMEM;
5737 goto err_tx_desc;
5738 }
5739 txq->ift_ifdi = ifdip;
5740 for (j = 0; j < ntxqs; j++, ifdip++) {
5741 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) {
5742 device_printf(dev,
5743 "Unable to allocate TX descriptors\n");
5744 err = ENOMEM;
5745 goto err_tx_desc;
5746 }
5747 txq->ift_txd_size[j] = scctx->isc_txd_size[j];
5748 bzero((void *)ifdip->idi_vaddr, txqsizes[j]);
5749 }
5750 txq->ift_ctx = ctx;
5751 txq->ift_id = i;
5752 if (sctx->isc_flags & IFLIB_HAS_TXCQ) {
5753 txq->ift_br_offset = 1;
5754 } else {
5755 txq->ift_br_offset = 0;
5756 }
5757
5758 if (iflib_txsd_alloc(txq)) {
5759 device_printf(dev, "Critical Failure setting up TX buffers\n");
5760 err = ENOMEM;
5761 goto err_tx_desc;
5762 }
5763
5764 /* Initialize the TX lock */
5765 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout",
5766 device_get_nameunit(dev), txq->ift_id);
5767 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF);
5768 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0);
5769 txq->ift_timer.c_cpu = cpu;
5770 #ifdef DEV_NETMAP
5771 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0);
5772 txq->ift_netmap_timer.c_cpu = cpu;
5773 #endif /* DEV_NETMAP */
5774
5775 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain,
5776 iflib_txq_can_drain, M_IFLIB, M_WAITOK);
5777 if (err) {
5778 /* XXX free any allocated rings */
5779 device_printf(dev, "Unable to allocate buf_ring\n");
5780 goto err_tx_desc;
5781 }
5782 txq->ift_reclaim_thresh = ctx->ifc_sysctl_tx_reclaim_thresh;
5783 }
5784
5785 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) {
5786 /* Set up some basics */
5787 callout_init(&rxq->ifr_watchdog, 1);
5788
5789 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs,
5790 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) {
5791 device_printf(dev,
5792 "Unable to allocate RX DMA info memory\n");
5793 err = ENOMEM;
5794 goto err_tx_desc;
5795 }
5796
5797 rxq->ifr_ifdi = ifdip;
5798 /* XXX this needs to be changed if #rx queues != #tx queues */
5799 rxq->ifr_ntxqirq = 1;
5800 rxq->ifr_txqid[0] = i;
5801 for (j = 0; j < nrxqs; j++, ifdip++) {
5802 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) {
5803 device_printf(dev,
5804 "Unable to allocate RX descriptors\n");
5805 err = ENOMEM;
5806 goto err_tx_desc;
5807 }
5808 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]);
5809 }
5810 rxq->ifr_ctx = ctx;
5811 rxq->ifr_id = i;
5812 rxq->ifr_fl_offset = fl_offset;
5813 rxq->ifr_nfl = nfree_lists;
5814 if (!(fl =
5815 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) {
5816 device_printf(dev, "Unable to allocate free list memory\n");
5817 err = ENOMEM;
5818 goto err_tx_desc;
5819 }
5820 rxq->ifr_fl = fl;
5821 for (j = 0; j < nfree_lists; j++) {
5822 fl[j].ifl_rxq = rxq;
5823 fl[j].ifl_id = j;
5824 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset];
5825 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j];
5826 }
5827 /* Allocate receive buffers for the ring */
5828 if (iflib_rxsd_alloc(rxq)) {
5829 device_printf(dev,
5830 "Critical Failure setting up receive buffers\n");
5831 err = ENOMEM;
5832 goto err_rx_desc;
5833 }
5834
5835 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++)
5836 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB,
5837 M_WAITOK);
5838 }
5839
5840 /* TXQs */
5841 vaddrs = malloc(sizeof(caddr_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK);
5842 paddrs = malloc(sizeof(uint64_t) * ntxqsets * ntxqs, M_IFLIB, M_WAITOK);
5843 for (i = 0; i < ntxqsets; i++) {
5844 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi;
5845
5846 for (j = 0; j < ntxqs; j++, di++) {
5847 vaddrs[i * ntxqs + j] = di->idi_vaddr;
5848 paddrs[i * ntxqs + j] = di->idi_paddr;
5849 }
5850 }
5851 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) {
5852 device_printf(ctx->ifc_dev,
5853 "Unable to allocate device TX queue\n");
5854 iflib_tx_structures_free(ctx);
5855 free(vaddrs, M_IFLIB);
5856 free(paddrs, M_IFLIB);
5857 goto err_rx_desc;
5858 }
5859 free(vaddrs, M_IFLIB);
5860 free(paddrs, M_IFLIB);
5861
5862 /* RXQs */
5863 vaddrs = malloc(sizeof(caddr_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK);
5864 paddrs = malloc(sizeof(uint64_t) * nrxqsets * nrxqs, M_IFLIB, M_WAITOK);
5865 for (i = 0; i < nrxqsets; i++) {
5866 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi;
5867
5868 for (j = 0; j < nrxqs; j++, di++) {
5869 vaddrs[i * nrxqs + j] = di->idi_vaddr;
5870 paddrs[i * nrxqs + j] = di->idi_paddr;
5871 }
5872 }
5873 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) {
5874 device_printf(ctx->ifc_dev,
5875 "Unable to allocate device RX queue\n");
5876 iflib_tx_structures_free(ctx);
5877 free(vaddrs, M_IFLIB);
5878 free(paddrs, M_IFLIB);
5879 goto err_rx_desc;
5880 }
5881 free(vaddrs, M_IFLIB);
5882 free(paddrs, M_IFLIB);
5883
5884 return (0);
5885
5886 /* XXX handle allocation failure changes */
5887 err_rx_desc:
5888 err_tx_desc:
5889 rx_fail:
5890 if (ctx->ifc_rxqs != NULL)
5891 free(ctx->ifc_rxqs, M_IFLIB);
5892 ctx->ifc_rxqs = NULL;
5893 if (ctx->ifc_txqs != NULL)
5894 free(ctx->ifc_txqs, M_IFLIB);
5895 ctx->ifc_txqs = NULL;
5896 fail:
5897 return (err);
5898 }
5899
5900 static int
iflib_tx_structures_setup(if_ctx_t ctx)5901 iflib_tx_structures_setup(if_ctx_t ctx)
5902 {
5903 iflib_txq_t txq = ctx->ifc_txqs;
5904 int i;
5905
5906 for (i = 0; i < NTXQSETS(ctx); i++, txq++)
5907 iflib_txq_setup(txq);
5908
5909 return (0);
5910 }
5911
5912 static void
iflib_tx_structures_free(if_ctx_t ctx)5913 iflib_tx_structures_free(if_ctx_t ctx)
5914 {
5915 iflib_txq_t txq = ctx->ifc_txqs;
5916 if_shared_ctx_t sctx = ctx->ifc_sctx;
5917 int i, j;
5918
5919 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
5920 for (j = 0; j < sctx->isc_ntxqs; j++)
5921 iflib_dma_free(&txq->ift_ifdi[j]);
5922 iflib_txq_destroy(txq);
5923 }
5924 free(ctx->ifc_txqs, M_IFLIB);
5925 ctx->ifc_txqs = NULL;
5926 }
5927
5928 /*********************************************************************
5929 *
5930 * Initialize all receive rings.
5931 *
5932 **********************************************************************/
5933 static int
iflib_rx_structures_setup(if_ctx_t ctx)5934 iflib_rx_structures_setup(if_ctx_t ctx)
5935 {
5936 iflib_rxq_t rxq = ctx->ifc_rxqs;
5937 int q;
5938 #if defined(INET6) || defined(INET)
5939 int err, i;
5940 #endif
5941
5942 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) {
5943 #if defined(INET6) || defined(INET)
5944 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp,
5945 TCP_LRO_ENTRIES, min(1024,
5946 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]));
5947 if (err != 0) {
5948 device_printf(ctx->ifc_dev,
5949 "LRO Initialization failed!\n");
5950 goto fail;
5951 }
5952 #endif
5953 IFDI_RXQ_SETUP(ctx, rxq->ifr_id);
5954 }
5955 return (0);
5956 #if defined(INET6) || defined(INET)
5957 fail:
5958 /*
5959 * Free LRO resources allocated so far, we will only handle
5960 * the rings that completed, the failing case will have
5961 * cleaned up for itself. 'q' failed, so its the terminus.
5962 */
5963 rxq = ctx->ifc_rxqs;
5964 for (i = 0; i < q; ++i, rxq++) {
5965 tcp_lro_free(&rxq->ifr_lc);
5966 }
5967 return (err);
5968 #endif
5969 }
5970
5971 /*********************************************************************
5972 *
5973 * Free all receive rings.
5974 *
5975 **********************************************************************/
5976 static void
iflib_rx_structures_free(if_ctx_t ctx)5977 iflib_rx_structures_free(if_ctx_t ctx)
5978 {
5979 iflib_rxq_t rxq = ctx->ifc_rxqs;
5980 if_shared_ctx_t sctx = ctx->ifc_sctx;
5981 int i, j;
5982
5983 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) {
5984 for (j = 0; j < sctx->isc_nrxqs; j++)
5985 iflib_dma_free(&rxq->ifr_ifdi[j]);
5986 iflib_rx_sds_free(rxq);
5987 #if defined(INET6) || defined(INET)
5988 tcp_lro_free(&rxq->ifr_lc);
5989 #endif
5990 }
5991 free(ctx->ifc_rxqs, M_IFLIB);
5992 ctx->ifc_rxqs = NULL;
5993 }
5994
5995 static int
iflib_qset_structures_setup(if_ctx_t ctx)5996 iflib_qset_structures_setup(if_ctx_t ctx)
5997 {
5998 int err;
5999
6000 /*
6001 * It is expected that the caller takes care of freeing queues if this
6002 * fails.
6003 */
6004 if ((err = iflib_tx_structures_setup(ctx)) != 0) {
6005 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err);
6006 return (err);
6007 }
6008
6009 if ((err = iflib_rx_structures_setup(ctx)) != 0)
6010 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err);
6011
6012 return (err);
6013 }
6014
6015 int
iflib_irq_alloc(if_ctx_t ctx,if_irq_t irq,int rid,driver_filter_t filter,void * filter_arg,driver_intr_t handler,void * arg,const char * name)6016 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid,
6017 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name)
6018 {
6019
6020 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name));
6021 }
6022
6023 /* Just to avoid copy/paste */
6024 static inline int
iflib_irq_set_affinity(if_ctx_t ctx,if_irq_t irq,iflib_intr_type_t type,int qid,struct grouptask * gtask,struct taskqgroup * tqg,void * uniq,const char * name)6025 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6026 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq,
6027 const char *name)
6028 {
6029 device_t dev;
6030 unsigned int base_cpuid, cpuid;
6031 int err;
6032
6033 dev = ctx->ifc_dev;
6034 base_cpuid = ctx->ifc_sysctl_core_offset;
6035 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX);
6036 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev,
6037 irq ? irq->ii_res : NULL, name);
6038 if (err) {
6039 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err);
6040 return (err);
6041 }
6042 #ifdef notyet
6043 if (cpuid > ctx->ifc_cpuid_highest)
6044 ctx->ifc_cpuid_highest = cpuid;
6045 #endif
6046 return (0);
6047 }
6048
6049 /*
6050 * Allocate a hardware interrupt for subctx using the parent (ctx)'s hardware
6051 * resources.
6052 *
6053 * Similar to iflib_irq_alloc_generic(), but for interrupt type IFLIB_INTR_RXTX
6054 * only.
6055 *
6056 * XXX: Could be removed if subctx's dev has its intr resource allocation
6057 * methods replaced with custom ones?
6058 */
6059 int
iflib_irq_alloc_generic_subctx(if_ctx_t ctx,if_ctx_t subctx,if_irq_t irq,int rid,iflib_intr_type_t type,driver_filter_t * filter,void * filter_arg,int qid,const char * name)6060 iflib_irq_alloc_generic_subctx(if_ctx_t ctx, if_ctx_t subctx, if_irq_t irq,
6061 int rid, iflib_intr_type_t type,
6062 driver_filter_t *filter, void *filter_arg,
6063 int qid, const char *name)
6064 {
6065 device_t dev, subdev;
6066 struct grouptask *gtask;
6067 struct taskqgroup *tqg;
6068 iflib_filter_info_t info;
6069 gtask_fn_t *fn;
6070 int tqrid, err;
6071 driver_filter_t *intr_fast;
6072 void *q;
6073
6074 MPASS(ctx != NULL);
6075 MPASS(subctx != NULL);
6076
6077 tqrid = rid;
6078 dev = ctx->ifc_dev;
6079 subdev = subctx->ifc_dev;
6080
6081 switch (type) {
6082 case IFLIB_INTR_RXTX:
6083 q = &subctx->ifc_rxqs[qid];
6084 info = &subctx->ifc_rxqs[qid].ifr_filter_info;
6085 gtask = &subctx->ifc_rxqs[qid].ifr_task;
6086 tqg = qgroup_if_io_tqg;
6087 fn = _task_fn_rx;
6088 intr_fast = iflib_fast_intr_rxtx;
6089 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6090 break;
6091 default:
6092 device_printf(dev, "%s: unknown net intr type for subctx %s (%d)\n",
6093 __func__, device_get_nameunit(subdev), type);
6094 return (EINVAL);
6095 }
6096
6097 info->ifi_filter = filter;
6098 info->ifi_filter_arg = filter_arg;
6099 info->ifi_task = gtask;
6100 info->ifi_ctx = q;
6101
6102 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6103
6104 /* Allocate interrupts from hardware using parent context */
6105 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6106 if (err != 0) {
6107 device_printf(dev, "_iflib_irq_alloc failed for subctx %s: %d\n",
6108 device_get_nameunit(subdev), err);
6109 return (err);
6110 }
6111
6112 if (tqrid != -1) {
6113 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6114 name);
6115 if (err)
6116 return (err);
6117 } else {
6118 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6119 }
6120
6121 return (0);
6122 }
6123
6124 int
iflib_irq_alloc_generic(if_ctx_t ctx,if_irq_t irq,int rid,iflib_intr_type_t type,driver_filter_t * filter,void * filter_arg,int qid,const char * name)6125 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid,
6126 iflib_intr_type_t type, driver_filter_t *filter,
6127 void *filter_arg, int qid, const char *name)
6128 {
6129 device_t dev;
6130 struct grouptask *gtask;
6131 struct taskqgroup *tqg;
6132 iflib_filter_info_t info;
6133 gtask_fn_t *fn;
6134 int tqrid, err;
6135 driver_filter_t *intr_fast;
6136 void *q;
6137
6138 info = &ctx->ifc_filter_info;
6139 tqrid = rid;
6140
6141 switch (type) {
6142 /* XXX merge tx/rx for netmap? */
6143 case IFLIB_INTR_TX:
6144 q = &ctx->ifc_txqs[qid];
6145 info = &ctx->ifc_txqs[qid].ift_filter_info;
6146 gtask = &ctx->ifc_txqs[qid].ift_task;
6147 tqg = qgroup_if_io_tqg;
6148 fn = _task_fn_tx;
6149 intr_fast = iflib_fast_intr;
6150 GROUPTASK_INIT(gtask, 0, fn, q);
6151 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ;
6152 break;
6153 case IFLIB_INTR_RX:
6154 q = &ctx->ifc_rxqs[qid];
6155 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6156 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6157 tqg = qgroup_if_io_tqg;
6158 fn = _task_fn_rx;
6159 intr_fast = iflib_fast_intr;
6160 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6161 break;
6162 case IFLIB_INTR_RXTX:
6163 q = &ctx->ifc_rxqs[qid];
6164 info = &ctx->ifc_rxqs[qid].ifr_filter_info;
6165 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6166 tqg = qgroup_if_io_tqg;
6167 fn = _task_fn_rx;
6168 intr_fast = iflib_fast_intr_rxtx;
6169 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6170 break;
6171 case IFLIB_INTR_ADMIN:
6172 q = ctx;
6173 tqrid = -1;
6174 info = &ctx->ifc_filter_info;
6175 gtask = NULL;
6176 intr_fast = iflib_fast_intr_ctx;
6177 break;
6178 default:
6179 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n",
6180 __func__);
6181 return (EINVAL);
6182 }
6183
6184 info->ifi_filter = filter;
6185 info->ifi_filter_arg = filter_arg;
6186 info->ifi_task = gtask;
6187 info->ifi_ctx = q;
6188
6189 dev = ctx->ifc_dev;
6190 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name);
6191 if (err != 0) {
6192 device_printf(dev, "_iflib_irq_alloc failed %d\n", err);
6193 return (err);
6194 }
6195 if (type == IFLIB_INTR_ADMIN)
6196 return (0);
6197
6198 if (tqrid != -1) {
6199 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q,
6200 name);
6201 if (err)
6202 return (err);
6203 } else {
6204 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name);
6205 }
6206
6207 return (0);
6208 }
6209
6210 void
iflib_softirq_alloc_generic(if_ctx_t ctx,if_irq_t irq,iflib_intr_type_t type,void * arg,int qid,const char * name)6211 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type,
6212 void *arg, int qid, const char *name)
6213 {
6214 device_t dev;
6215 struct grouptask *gtask;
6216 struct taskqgroup *tqg;
6217 gtask_fn_t *fn;
6218 void *q;
6219 int err;
6220
6221 switch (type) {
6222 case IFLIB_INTR_TX:
6223 q = &ctx->ifc_txqs[qid];
6224 gtask = &ctx->ifc_txqs[qid].ift_task;
6225 tqg = qgroup_if_io_tqg;
6226 fn = _task_fn_tx;
6227 GROUPTASK_INIT(gtask, 0, fn, q);
6228 break;
6229 case IFLIB_INTR_RX:
6230 q = &ctx->ifc_rxqs[qid];
6231 gtask = &ctx->ifc_rxqs[qid].ifr_task;
6232 tqg = qgroup_if_io_tqg;
6233 fn = _task_fn_rx;
6234 NET_GROUPTASK_INIT(gtask, 0, fn, q);
6235 break;
6236 case IFLIB_INTR_IOV:
6237 TASK_INIT(&ctx->ifc_vflr_task, 0, _task_fn_iov, ctx);
6238 return;
6239 default:
6240 panic("unknown net intr type");
6241 }
6242 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name);
6243 if (err) {
6244 dev = ctx->ifc_dev;
6245 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL,
6246 name);
6247 }
6248 }
6249
6250 void
iflib_irq_free(if_ctx_t ctx,if_irq_t irq)6251 iflib_irq_free(if_ctx_t ctx, if_irq_t irq)
6252 {
6253
6254 if (irq->ii_tag)
6255 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag);
6256
6257 if (irq->ii_res)
6258 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ,
6259 rman_get_rid(irq->ii_res), irq->ii_res);
6260 }
6261
6262 static int
iflib_legacy_setup(if_ctx_t ctx,driver_filter_t filter,void * filter_arg,int * rid,const char * name)6263 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name)
6264 {
6265 iflib_txq_t txq = ctx->ifc_txqs;
6266 iflib_rxq_t rxq = ctx->ifc_rxqs;
6267 if_irq_t irq = &ctx->ifc_legacy_irq;
6268 iflib_filter_info_t info;
6269 device_t dev;
6270 struct grouptask *gtask;
6271 struct resource *res;
6272 int err, tqrid;
6273 bool rx_only;
6274
6275 info = &rxq->ifr_filter_info;
6276 gtask = &rxq->ifr_task;
6277 tqrid = *rid;
6278 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0;
6279
6280 ctx->ifc_flags |= IFC_LEGACY;
6281 info->ifi_filter = filter;
6282 info->ifi_filter_arg = filter_arg;
6283 info->ifi_task = gtask;
6284 info->ifi_ctx = rxq;
6285
6286 dev = ctx->ifc_dev;
6287 /* We allocate a single interrupt resource */
6288 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr :
6289 iflib_fast_intr_rxtx, NULL, info, name);
6290 if (err != 0)
6291 return (err);
6292 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, rxq);
6293 res = irq->ii_res;
6294 taskqgroup_attach(qgroup_if_io_tqg, gtask, rxq, dev, res, name);
6295
6296 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq);
6297 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res,
6298 "tx");
6299 return (0);
6300 }
6301
6302 void
iflib_led_create(if_ctx_t ctx)6303 iflib_led_create(if_ctx_t ctx)
6304 {
6305
6306 ctx->ifc_led_dev = led_create(iflib_led_func, ctx,
6307 device_get_nameunit(ctx->ifc_dev));
6308 }
6309
6310 void
iflib_tx_intr_deferred(if_ctx_t ctx,int txqid)6311 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid)
6312 {
6313
6314 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task);
6315 }
6316
6317 void
iflib_rx_intr_deferred(if_ctx_t ctx,int rxqid)6318 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid)
6319 {
6320
6321 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task);
6322 }
6323
6324 void
iflib_admin_intr_deferred(if_ctx_t ctx)6325 iflib_admin_intr_deferred(if_ctx_t ctx)
6326 {
6327
6328 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_admin_task);
6329 }
6330
6331 void
iflib_iov_intr_deferred(if_ctx_t ctx)6332 iflib_iov_intr_deferred(if_ctx_t ctx)
6333 {
6334
6335 taskqueue_enqueue(ctx->ifc_tq, &ctx->ifc_vflr_task);
6336 }
6337
6338 void
iflib_io_tqg_attach(struct grouptask * gt,void * uniq,int cpu,const char * name)6339 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name)
6340 {
6341
6342 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL,
6343 name);
6344 }
6345
6346 void
iflib_config_task_init(if_ctx_t ctx,struct task * config_task,task_fn_t * fn)6347 iflib_config_task_init(if_ctx_t ctx, struct task *config_task, task_fn_t *fn)
6348 {
6349 TASK_INIT(config_task, 0, fn, ctx);
6350 }
6351
6352 void
iflib_config_task_enqueue(if_ctx_t ctx,struct task * config_task)6353 iflib_config_task_enqueue(if_ctx_t ctx, struct task *config_task)
6354 {
6355 taskqueue_enqueue(ctx->ifc_tq, config_task);
6356 }
6357
6358 void
iflib_link_state_change(if_ctx_t ctx,int link_state,uint64_t baudrate)6359 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate)
6360 {
6361 if_t ifp = ctx->ifc_ifp;
6362 iflib_txq_t txq = ctx->ifc_txqs;
6363
6364 if_setbaudrate(ifp, baudrate);
6365 if (baudrate >= IF_Gbps(10)) {
6366 STATE_LOCK(ctx);
6367 ctx->ifc_flags |= IFC_PREFETCH;
6368 STATE_UNLOCK(ctx);
6369 }
6370 /* If link down, disable watchdog */
6371 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) {
6372 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++)
6373 txq->ift_qstatus = IFLIB_QUEUE_IDLE;
6374 }
6375 ctx->ifc_link_state = link_state;
6376 if_link_state_change(ifp, link_state);
6377 }
6378
6379 static int
iflib_tx_credits_update(if_ctx_t ctx,iflib_txq_t txq)6380 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq)
6381 {
6382 int credits;
6383 #ifdef INVARIANTS
6384 int credits_pre = txq->ift_cidx_processed;
6385 #endif
6386
6387 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map,
6388 BUS_DMASYNC_POSTREAD);
6389 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0)
6390 return (0);
6391
6392 txq->ift_processed += credits;
6393 txq->ift_cidx_processed += credits;
6394
6395 MPASS(credits_pre + credits == txq->ift_cidx_processed);
6396 if (txq->ift_cidx_processed >= txq->ift_size)
6397 txq->ift_cidx_processed -= txq->ift_size;
6398 return (credits);
6399 }
6400
6401 static int
iflib_rxd_avail(if_ctx_t ctx,iflib_rxq_t rxq,qidx_t cidx,qidx_t budget)6402 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget)
6403 {
6404 iflib_fl_t fl;
6405 u_int i;
6406
6407 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++)
6408 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map,
6409 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6410 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx,
6411 budget));
6412 }
6413
6414 void
iflib_add_int_delay_sysctl(if_ctx_t ctx,const char * name,const char * description,if_int_delay_info_t info,int offset,int value)6415 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name,
6416 const char *description, if_int_delay_info_t info,
6417 int offset, int value)
6418 {
6419 info->iidi_ctx = ctx;
6420 info->iidi_offset = offset;
6421 info->iidi_value = value;
6422 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev),
6423 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)),
6424 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
6425 info, 0, iflib_sysctl_int_delay, "I", description);
6426 }
6427
6428 struct sx *
iflib_ctx_lock_get(if_ctx_t ctx)6429 iflib_ctx_lock_get(if_ctx_t ctx)
6430 {
6431
6432 return (&ctx->ifc_ctx_sx);
6433 }
6434
6435 static int
iflib_msix_init(if_ctx_t ctx)6436 iflib_msix_init(if_ctx_t ctx)
6437 {
6438 device_t dev = ctx->ifc_dev;
6439 if_shared_ctx_t sctx = ctx->ifc_sctx;
6440 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6441 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues;
6442 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors;
6443
6444 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs;
6445 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs;
6446
6447 if (bootverbose)
6448 device_printf(dev, "msix_init qsets capped at %d\n",
6449 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets));
6450
6451 /* Override by tuneable */
6452 if (scctx->isc_disable_msix)
6453 goto msi;
6454
6455 /* First try MSI-X */
6456 if ((msgs = pci_msix_count(dev)) == 0) {
6457 if (bootverbose)
6458 device_printf(dev, "MSI-X not supported or disabled\n");
6459 goto msi;
6460 }
6461
6462 bar = ctx->ifc_softc_ctx.isc_msix_bar;
6463 /*
6464 * bar == -1 => "trust me I know what I'm doing"
6465 * Some drivers are for hardware that is so shoddily
6466 * documented that no one knows which bars are which
6467 * so the developer has to map all bars. This hack
6468 * allows shoddy garbage to use MSI-X in this framework.
6469 */
6470 if (bar != -1) {
6471 ctx->ifc_msix_mem = bus_alloc_resource_any(dev,
6472 SYS_RES_MEMORY, &bar, RF_ACTIVE);
6473 if (ctx->ifc_msix_mem == NULL) {
6474 device_printf(dev, "Unable to map MSI-X table\n");
6475 goto msi;
6476 }
6477 }
6478
6479 admincnt = sctx->isc_admin_intrcnt;
6480 #if IFLIB_DEBUG
6481 /* use only 1 qset in debug mode */
6482 queuemsgs = min(msgs - admincnt, 1);
6483 #else
6484 queuemsgs = msgs - admincnt;
6485 #endif
6486 #ifdef RSS
6487 queues = imin(queuemsgs, rss_getnumbuckets());
6488 #else
6489 queues = queuemsgs;
6490 #endif
6491 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues);
6492 if (bootverbose)
6493 device_printf(dev,
6494 "intr CPUs: %d queue msgs: %d admincnt: %d\n",
6495 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt);
6496 #ifdef RSS
6497 /* If we're doing RSS, clamp at the number of RSS buckets */
6498 if (queues > rss_getnumbuckets())
6499 queues = rss_getnumbuckets();
6500 #endif
6501 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt)
6502 rx_queues = iflib_num_rx_queues;
6503 else
6504 rx_queues = queues;
6505
6506 if (rx_queues > scctx->isc_nrxqsets)
6507 rx_queues = scctx->isc_nrxqsets;
6508
6509 /*
6510 * We want this to be all logical CPUs by default
6511 */
6512 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues)
6513 tx_queues = iflib_num_tx_queues;
6514 else
6515 tx_queues = mp_ncpus;
6516
6517 if (tx_queues > scctx->isc_ntxqsets)
6518 tx_queues = scctx->isc_ntxqsets;
6519
6520 if (ctx->ifc_sysctl_qs_eq_override == 0) {
6521 #ifdef INVARIANTS
6522 if (tx_queues != rx_queues)
6523 device_printf(dev,
6524 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n",
6525 min(rx_queues, tx_queues), min(rx_queues, tx_queues));
6526 #endif
6527 tx_queues = min(rx_queues, tx_queues);
6528 rx_queues = min(rx_queues, tx_queues);
6529 }
6530
6531 vectors = rx_queues + admincnt;
6532 if (msgs < vectors) {
6533 device_printf(dev,
6534 "insufficient number of MSI-X vectors "
6535 "(supported %d, need %d)\n", msgs, vectors);
6536 goto msi;
6537 }
6538
6539 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues,
6540 tx_queues);
6541 msgs = vectors;
6542 if ((err = pci_alloc_msix(dev, &vectors)) == 0) {
6543 if (vectors != msgs) {
6544 device_printf(dev,
6545 "Unable to allocate sufficient MSI-X vectors "
6546 "(got %d, need %d)\n", vectors, msgs);
6547 pci_release_msi(dev);
6548 if (bar != -1) {
6549 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6550 ctx->ifc_msix_mem);
6551 ctx->ifc_msix_mem = NULL;
6552 }
6553 goto msi;
6554 }
6555 device_printf(dev, "Using MSI-X interrupts with %d vectors\n",
6556 vectors);
6557 scctx->isc_vectors = vectors;
6558 scctx->isc_nrxqsets = rx_queues;
6559 scctx->isc_ntxqsets = tx_queues;
6560 scctx->isc_intr = IFLIB_INTR_MSIX;
6561
6562 return (vectors);
6563 } else {
6564 device_printf(dev,
6565 "failed to allocate %d MSI-X vectors, err: %d\n", vectors,
6566 err);
6567 if (bar != -1) {
6568 bus_release_resource(dev, SYS_RES_MEMORY, bar,
6569 ctx->ifc_msix_mem);
6570 ctx->ifc_msix_mem = NULL;
6571 }
6572 }
6573
6574 msi:
6575 vectors = pci_msi_count(dev);
6576 scctx->isc_nrxqsets = 1;
6577 scctx->isc_ntxqsets = 1;
6578 scctx->isc_vectors = vectors;
6579 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) {
6580 device_printf(dev, "Using an MSI interrupt\n");
6581 scctx->isc_intr = IFLIB_INTR_MSI;
6582 } else {
6583 scctx->isc_vectors = 1;
6584 device_printf(dev, "Using a Legacy interrupt\n");
6585 scctx->isc_intr = IFLIB_INTR_LEGACY;
6586 }
6587
6588 return (vectors);
6589 }
6590
6591 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" };
6592
6593 static int
mp_ring_state_handler(SYSCTL_HANDLER_ARGS)6594 mp_ring_state_handler(SYSCTL_HANDLER_ARGS)
6595 {
6596 int rc;
6597 uint16_t *state = ((uint16_t *)oidp->oid_arg1);
6598 struct sbuf *sb;
6599 const char *ring_state = "UNKNOWN";
6600
6601 /* XXX needed ? */
6602 rc = sysctl_wire_old_buffer(req, 0);
6603 MPASS(rc == 0);
6604 if (rc != 0)
6605 return (rc);
6606 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req);
6607 MPASS(sb != NULL);
6608 if (sb == NULL)
6609 return (ENOMEM);
6610 if (state[3] <= 3)
6611 ring_state = ring_states[state[3]];
6612
6613 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s",
6614 state[0], state[1], state[2], ring_state);
6615 rc = sbuf_finish(sb);
6616 sbuf_delete(sb);
6617 return (rc);
6618 }
6619
6620 enum iflib_ndesc_handler {
6621 IFLIB_NTXD_HANDLER,
6622 IFLIB_NRXD_HANDLER,
6623 };
6624
6625 static int
mp_ndesc_handler(SYSCTL_HANDLER_ARGS)6626 mp_ndesc_handler(SYSCTL_HANDLER_ARGS)
6627 {
6628 if_ctx_t ctx = (void *)arg1;
6629 enum iflib_ndesc_handler type = arg2;
6630 char buf[256] = {0};
6631 qidx_t *ndesc;
6632 char *p, *next;
6633 int nqs, rc, i;
6634
6635 nqs = 8;
6636 switch (type) {
6637 case IFLIB_NTXD_HANDLER:
6638 ndesc = ctx->ifc_sysctl_ntxds;
6639 if (ctx->ifc_sctx)
6640 nqs = ctx->ifc_sctx->isc_ntxqs;
6641 break;
6642 case IFLIB_NRXD_HANDLER:
6643 ndesc = ctx->ifc_sysctl_nrxds;
6644 if (ctx->ifc_sctx)
6645 nqs = ctx->ifc_sctx->isc_nrxqs;
6646 break;
6647 default:
6648 printf("%s: unhandled type\n", __func__);
6649 return (EINVAL);
6650 }
6651 if (nqs == 0)
6652 nqs = 8;
6653
6654 for (i = 0; i < 8; i++) {
6655 if (i >= nqs)
6656 break;
6657 if (i)
6658 strcat(buf, ",");
6659 sprintf(strchr(buf, 0), "%d", ndesc[i]);
6660 }
6661
6662 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req);
6663 if (rc || req->newptr == NULL)
6664 return (rc);
6665
6666 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p;
6667 i++, p = strsep(&next, " ,")) {
6668 ndesc[i] = strtoul(p, NULL, 10);
6669 }
6670
6671 return (rc);
6672 }
6673
6674 static int
iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS)6675 iflib_handle_tx_reclaim_thresh(SYSCTL_HANDLER_ARGS)
6676 {
6677 if_ctx_t ctx = (void *)arg1;
6678 iflib_txq_t txq;
6679 int i, err;
6680 int thresh;
6681
6682 thresh = ctx->ifc_sysctl_tx_reclaim_thresh;
6683 err = sysctl_handle_int(oidp, &thresh, arg2, req);
6684 if (err != 0) {
6685 return err;
6686 }
6687
6688 if (thresh == ctx->ifc_sysctl_tx_reclaim_thresh)
6689 return 0;
6690
6691 if (thresh > ctx->ifc_softc_ctx.isc_ntxd[0] / 2) {
6692 device_printf(ctx->ifc_dev, "TX Reclaim thresh must be <= %d\n",
6693 ctx->ifc_softc_ctx.isc_ntxd[0] / 2);
6694 return (EINVAL);
6695 }
6696
6697 ctx->ifc_sysctl_tx_reclaim_thresh = thresh;
6698 if (ctx->ifc_txqs == NULL)
6699 return (err);
6700
6701 txq = &ctx->ifc_txqs[0];
6702 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6703 txq->ift_reclaim_thresh = thresh;
6704 }
6705 return (err);
6706 }
6707
6708 static int
iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS)6709 iflib_handle_tx_reclaim_ticks(SYSCTL_HANDLER_ARGS)
6710 {
6711 if_ctx_t ctx = (void *)arg1;
6712 iflib_txq_t txq;
6713 int i, err;
6714 int ticks;
6715
6716 ticks = ctx->ifc_sysctl_tx_reclaim_ticks;
6717 err = sysctl_handle_int(oidp, &ticks, arg2, req);
6718 if (err != 0) {
6719 return err;
6720 }
6721
6722 if (ticks == ctx->ifc_sysctl_tx_reclaim_ticks)
6723 return 0;
6724
6725 if (ticks > hz) {
6726 device_printf(ctx->ifc_dev,
6727 "TX Reclaim ticks must be <= hz (%d)\n", hz);
6728 return (EINVAL);
6729 }
6730
6731 ctx->ifc_sysctl_tx_reclaim_ticks = ticks;
6732 if (ctx->ifc_txqs == NULL)
6733 return (err);
6734
6735 txq = &ctx->ifc_txqs[0];
6736 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6737 txq->ift_reclaim_ticks = ticks;
6738 }
6739 return (err);
6740 }
6741
6742 static int
iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS)6743 iflib_handle_tx_defer_mfree(SYSCTL_HANDLER_ARGS)
6744 {
6745 if_ctx_t ctx = (void *)arg1;
6746 iflib_txq_t txq;
6747 int i, err;
6748 int defer;
6749
6750 defer = ctx->ifc_sysctl_tx_defer_mfree;
6751 err = sysctl_handle_int(oidp, &defer, arg2, req);
6752 if (err != 0) {
6753 return err;
6754 }
6755
6756 if (defer == ctx->ifc_sysctl_tx_defer_mfree)
6757 return 0;
6758
6759 ctx->ifc_sysctl_tx_defer_mfree = defer;
6760 if (ctx->ifc_txqs == NULL)
6761 return (err);
6762
6763 txq = &ctx->ifc_txqs[0];
6764 for (i = 0; i < NTXQSETS(ctx); i++, txq++) {
6765 txq->ift_defer_mfree = defer;
6766 }
6767 return (err);
6768 }
6769
6770 #define NAME_BUFLEN 32
6771 static void
iflib_add_device_sysctl_pre(if_ctx_t ctx)6772 iflib_add_device_sysctl_pre(if_ctx_t ctx)
6773 {
6774 device_t dev = iflib_get_dev(ctx);
6775 struct sysctl_oid_list *child, *oid_list;
6776 struct sysctl_ctx_list *ctx_list;
6777 struct sysctl_oid *node;
6778
6779 ctx_list = device_get_sysctl_ctx(dev);
6780 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
6781 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child,
6782 OID_AUTO, "iflib", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
6783 "IFLIB fields");
6784 oid_list = SYSCTL_CHILDREN(node);
6785
6786 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version",
6787 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, "driver version");
6788
6789 SYSCTL_ADD_BOOL(ctx_list, oid_list, OID_AUTO, "simple_tx",
6790 CTLFLAG_RDTUN, &ctx->ifc_sysctl_simple_tx, 0,
6791 "use simple tx ring");
6792 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs",
6793 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0,
6794 "# of txqs to use, 0 => use default #");
6795 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs",
6796 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0,
6797 "# of rxqs to use, 0 => use default #");
6798 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable",
6799 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0,
6800 "permit #txq != #rxq");
6801 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix",
6802 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0,
6803 "disable MSI-X (default 0)");
6804 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget",
6805 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, "set the RX budget");
6806 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate",
6807 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0,
6808 "cause TX to abdicate instead of running to completion");
6809 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED;
6810 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset",
6811 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0,
6812 "offset to start using cores at");
6813 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx",
6814 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0,
6815 "use separate cores for TX and RX");
6816 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores",
6817 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0,
6818 "try to make use of logical cores for TX and RX");
6819 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "use_extra_msix_vectors",
6820 CTLFLAG_RDTUN, &ctx->ifc_sysctl_extra_msix_vectors, 0,
6821 "attempt to reserve the given number of extra MSI-X vectors during driver load for the creation of additional interfaces later");
6822 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "allocated_msix_vectors",
6823 CTLFLAG_RDTUN, &ctx->ifc_softc_ctx.isc_vectors, 0,
6824 "total # of MSI-X vectors allocated by driver");
6825
6826 /* XXX change for per-queue sizes */
6827 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds",
6828 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6829 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A",
6830 "list of # of TX descriptors to use, 0 = use default #");
6831 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds",
6832 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx,
6833 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A",
6834 "list of # of RX descriptors to use, 0 = use default #");
6835 }
6836
6837 static void
iflib_add_device_sysctl_post(if_ctx_t ctx)6838 iflib_add_device_sysctl_post(if_ctx_t ctx)
6839 {
6840 if_shared_ctx_t sctx = ctx->ifc_sctx;
6841 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx;
6842 device_t dev = iflib_get_dev(ctx);
6843 struct sysctl_oid_list *child;
6844 struct sysctl_ctx_list *ctx_list;
6845 iflib_fl_t fl;
6846 iflib_txq_t txq;
6847 iflib_rxq_t rxq;
6848 int i, j;
6849 char namebuf[NAME_BUFLEN];
6850 char *qfmt;
6851 struct sysctl_oid *queue_node, *fl_node, *node;
6852 struct sysctl_oid_list *queue_list, *fl_list;
6853 ctx_list = device_get_sysctl_ctx(dev);
6854
6855 node = ctx->ifc_sysctl_node;
6856 child = SYSCTL_CHILDREN(node);
6857
6858 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_thresh",
6859 CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
6860 0, iflib_handle_tx_reclaim_thresh, "I",
6861 "Number of TX descs outstanding before reclaim is called");
6862
6863 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_reclaim_ticks",
6864 CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
6865 0, iflib_handle_tx_reclaim_ticks, "I",
6866 "Number of ticks before a TX reclaim is forced");
6867
6868 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "tx_defer_mfree",
6869 CTLTYPE_INT | CTLFLAG_RWTUN, ctx,
6870 0, iflib_handle_tx_defer_mfree, "I",
6871 "Free completed transmits outside of TX ring lock");
6872
6873 if (scctx->isc_ntxqsets > 100)
6874 qfmt = "txq%03d";
6875 else if (scctx->isc_ntxqsets > 10)
6876 qfmt = "txq%02d";
6877 else
6878 qfmt = "txq%d";
6879 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) {
6880 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6881 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6882 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6883 queue_list = SYSCTL_CHILDREN(queue_node);
6884 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
6885 CTLFLAG_RD, &txq->ift_task.gt_cpu, 0,
6886 "cpu this queue is bound to");
6887 #if MEMORY_LOGGING
6888 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued",
6889 CTLFLAG_RD, &txq->ift_dequeued, "total mbufs freed");
6890 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued",
6891 CTLFLAG_RD, &txq->ift_enqueued, "total mbufs enqueued");
6892 #endif
6893 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag",
6894 CTLFLAG_RD, &txq->ift_mbuf_defrag,
6895 "# of times m_defrag was called");
6896 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "m_pullups",
6897 CTLFLAG_RD, &txq->ift_pullups,
6898 "# of times m_pullup was called");
6899 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6900 "mbuf_defrag_failed", CTLFLAG_RD,
6901 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed");
6902 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6903 "no_desc_avail", CTLFLAG_RD, &txq->ift_no_desc_avail,
6904 "# of times no descriptors were available");
6905 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6906 "tx_map_failed", CTLFLAG_RD, &txq->ift_map_failed,
6907 "# of times DMA map failed");
6908 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6909 "txd_encap_efbig", CTLFLAG_RD, &txq->ift_txd_encap_efbig,
6910 "# of times txd_encap returned EFBIG");
6911 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6912 "no_tx_dma_setup", CTLFLAG_RD, &txq->ift_no_tx_dma_setup,
6913 "# of times map failed for other than EFBIG");
6914 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx",
6915 CTLFLAG_RD, &txq->ift_pidx, 1, "Producer Index");
6916 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx",
6917 CTLFLAG_RD, &txq->ift_cidx, 1, "Consumer Index");
6918 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO,
6919 "txq_cidx_processed", CTLFLAG_RD, &txq->ift_cidx_processed,
6920 1, "Consumer Index seen by credit update");
6921 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use",
6922 CTLFLAG_RD, &txq->ift_in_use, 1, "descriptors in use");
6923 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO,
6924 "txq_processed", CTLFLAG_RD, &txq->ift_processed,
6925 "descriptors procesed for clean");
6926 SYSCTL_ADD_UQUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned",
6927 CTLFLAG_RD, &txq->ift_cleaned, "total cleaned");
6928 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state",
6929 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
6930 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0,
6931 mp_ring_state_handler, "A", "soft ring state");
6932 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6933 "r_enqueues", CTLFLAG_RD, &txq->ift_br->enqueues,
6934 "# of enqueues to the mp_ring for this queue");
6935 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6936 "r_drops", CTLFLAG_RD, &txq->ift_br->drops,
6937 "# of drops in the mp_ring for this queue");
6938 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6939 "r_starts", CTLFLAG_RD, &txq->ift_br->starts,
6940 "# of normal consumer starts in mp_ring for this queue");
6941 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6942 "r_stalls", CTLFLAG_RD, &txq->ift_br->stalls,
6943 "# of consumer stalls in the mp_ring for this queue");
6944 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6945 "r_restarts", CTLFLAG_RD, &txq->ift_br->restarts,
6946 "# of consumer restarts in the mp_ring for this queue");
6947 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO,
6948 "r_abdications", CTLFLAG_RD, &txq->ift_br->abdications,
6949 "# of consumer abdications in the mp_ring for this queue");
6950 }
6951
6952 if (scctx->isc_nrxqsets > 100)
6953 qfmt = "rxq%03d";
6954 else if (scctx->isc_nrxqsets > 10)
6955 qfmt = "rxq%02d";
6956 else
6957 qfmt = "rxq%d";
6958 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) {
6959 snprintf(namebuf, NAME_BUFLEN, qfmt, i);
6960 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf,
6961 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
6962 queue_list = SYSCTL_CHILDREN(queue_node);
6963 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu",
6964 CTLFLAG_RD, &rxq->ifr_task.gt_cpu, 0,
6965 "cpu this queue is bound to");
6966 if (sctx->isc_flags & IFLIB_HAS_RXCQ) {
6967 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO,
6968 "rxq_cq_cidx", CTLFLAG_RD, &rxq->ifr_cq_cidx, 1,
6969 "Consumer Index");
6970 }
6971
6972 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) {
6973 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j);
6974 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list,
6975 OID_AUTO, namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE,
6976 NULL, "freelist Name");
6977 fl_list = SYSCTL_CHILDREN(fl_node);
6978 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx",
6979 CTLFLAG_RD, &fl->ifl_pidx, 1, "Producer Index");
6980 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx",
6981 CTLFLAG_RD, &fl->ifl_cidx, 1, "Consumer Index");
6982 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits",
6983 CTLFLAG_RD, &fl->ifl_credits, 1,
6984 "credits available");
6985 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size",
6986 CTLFLAG_RD, &fl->ifl_buf_size, 1, "buffer size");
6987 #if MEMORY_LOGGING
6988 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6989 "fl_m_enqueued", CTLFLAG_RD, &fl->ifl_m_enqueued,
6990 "mbufs allocated");
6991 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6992 "fl_m_dequeued", CTLFLAG_RD, &fl->ifl_m_dequeued,
6993 "mbufs freed");
6994 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6995 "fl_cl_enqueued", CTLFLAG_RD, &fl->ifl_cl_enqueued,
6996 "clusters allocated");
6997 SYSCTL_ADD_UQUAD(ctx_list, fl_list, OID_AUTO,
6998 "fl_cl_dequeued", CTLFLAG_RD, &fl->ifl_cl_dequeued,
6999 "clusters freed");
7000 #endif
7001 }
7002 }
7003
7004 }
7005
7006 void
iflib_request_reset(if_ctx_t ctx)7007 iflib_request_reset(if_ctx_t ctx)
7008 {
7009
7010 STATE_LOCK(ctx);
7011 ctx->ifc_flags |= IFC_DO_RESET;
7012 STATE_UNLOCK(ctx);
7013 }
7014
7015 #ifndef __NO_STRICT_ALIGNMENT
7016 static struct mbuf *
iflib_fixup_rx(struct mbuf * m)7017 iflib_fixup_rx(struct mbuf *m)
7018 {
7019 struct mbuf *n;
7020
7021 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
7022 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
7023 m->m_data += ETHER_HDR_LEN;
7024 n = m;
7025 } else {
7026 MGETHDR(n, M_NOWAIT, MT_DATA);
7027 if (n == NULL) {
7028 m_freem(m);
7029 return (NULL);
7030 }
7031 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
7032 m->m_data += ETHER_HDR_LEN;
7033 m->m_len -= ETHER_HDR_LEN;
7034 n->m_len = ETHER_HDR_LEN;
7035 M_MOVE_PKTHDR(n, m);
7036 n->m_next = m;
7037 }
7038 return (n);
7039 }
7040 #endif
7041
7042 #ifdef DEBUGNET
7043 static void
iflib_debugnet_init(if_t ifp,int * nrxr,int * ncl,int * clsize)7044 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
7045 {
7046 if_ctx_t ctx;
7047
7048 ctx = if_getsoftc(ifp);
7049 CTX_LOCK(ctx);
7050 *nrxr = NRXQSETS(ctx);
7051 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size;
7052 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size;
7053 CTX_UNLOCK(ctx);
7054 }
7055
7056 static void
iflib_debugnet_event(if_t ifp,enum debugnet_ev event)7057 iflib_debugnet_event(if_t ifp, enum debugnet_ev event)
7058 {
7059 if_ctx_t ctx;
7060 if_softc_ctx_t scctx;
7061 iflib_fl_t fl;
7062 iflib_rxq_t rxq;
7063 int i, j;
7064
7065 ctx = if_getsoftc(ifp);
7066 scctx = &ctx->ifc_softc_ctx;
7067
7068 switch (event) {
7069 case DEBUGNET_START:
7070 for (i = 0; i < scctx->isc_nrxqsets; i++) {
7071 rxq = &ctx->ifc_rxqs[i];
7072 for (j = 0; j < rxq->ifr_nfl; j++) {
7073 fl = rxq->ifr_fl;
7074 fl->ifl_zone = m_getzone(fl->ifl_buf_size);
7075 }
7076 }
7077 iflib_no_tx_batch = 1;
7078 break;
7079 default:
7080 break;
7081 }
7082 }
7083
7084 static int
iflib_debugnet_transmit(if_t ifp,struct mbuf * m)7085 iflib_debugnet_transmit(if_t ifp, struct mbuf *m)
7086 {
7087 if_ctx_t ctx;
7088 iflib_txq_t txq;
7089 int error;
7090
7091 ctx = if_getsoftc(ifp);
7092 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7093 IFF_DRV_RUNNING)
7094 return (EBUSY);
7095
7096 txq = &ctx->ifc_txqs[0];
7097 error = iflib_encap(txq, &m);
7098 if (error == 0)
7099 (void)iflib_txd_db_check(txq, true);
7100 return (error);
7101 }
7102
7103 static int
iflib_debugnet_poll(if_t ifp,int count)7104 iflib_debugnet_poll(if_t ifp, int count)
7105 {
7106 struct epoch_tracker et;
7107 if_ctx_t ctx;
7108 if_softc_ctx_t scctx;
7109 iflib_txq_t txq;
7110 int i;
7111
7112 ctx = if_getsoftc(ifp);
7113 scctx = &ctx->ifc_softc_ctx;
7114
7115 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
7116 IFF_DRV_RUNNING)
7117 return (EBUSY);
7118
7119 txq = &ctx->ifc_txqs[0];
7120 (void)iflib_completed_tx_reclaim(txq, NULL);
7121
7122 NET_EPOCH_ENTER(et);
7123 for (i = 0; i < scctx->isc_nrxqsets; i++)
7124 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */);
7125 NET_EPOCH_EXIT(et);
7126 return (0);
7127 }
7128 #endif /* DEBUGNET */
7129
7130 #ifndef ALTQ
7131 static inline iflib_txq_t
iflib_simple_select_queue(if_ctx_t ctx,struct mbuf * m)7132 iflib_simple_select_queue(if_ctx_t ctx, struct mbuf *m)
7133 {
7134 int qidx;
7135
7136 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m))
7137 qidx = QIDX(ctx, m);
7138 else
7139 qidx = NTXQSETS(ctx) + FIRST_QSET(ctx) - 1;
7140 return (&ctx->ifc_txqs[qidx]);
7141 }
7142
7143 static int
iflib_simple_transmit(if_t ifp,struct mbuf * m)7144 iflib_simple_transmit(if_t ifp, struct mbuf *m)
7145 {
7146 if_ctx_t ctx;
7147 iflib_txq_t txq;
7148 struct mbuf **m_defer;
7149 int error, i, reclaimable;
7150 int bytes_sent = 0, pkt_sent = 0, mcast_sent = 0;
7151
7152
7153 ctx = if_getsoftc(ifp);
7154 if (__predict_false((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0
7155 || !LINK_ACTIVE(ctx))) {
7156 DBG_COUNTER_INC(tx_frees);
7157 m_freem(m);
7158 return (ENETDOWN);
7159 }
7160
7161 txq = iflib_simple_select_queue(ctx, m);
7162 mtx_lock(&txq->ift_mtx);
7163 error = iflib_encap(txq, &m);
7164 if (error == 0) {
7165 pkt_sent++;
7166 bytes_sent += m->m_pkthdr.len;
7167 mcast_sent += !!(m->m_flags & M_MCAST);
7168 (void)iflib_txd_db_check(txq, true);
7169 } else {
7170 if (error == ENOBUFS)
7171 if_inc_counter(ifp, IFCOUNTER_OQDROPS, 1);
7172 else
7173 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
7174 }
7175 m_defer = NULL;
7176 reclaimable = iflib_txq_can_reclaim(txq);
7177 if (reclaimable != 0) {
7178 /*
7179 * Try to set m_defer to the deferred mbuf reclaim array. If
7180 * we can, the frees will happen outside the tx lock. If we
7181 * can't, it means another thread is still proccessing frees.
7182 */
7183 if (txq->ift_defer_mfree &&
7184 atomic_cmpset_acq_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer,
7185 (uintptr_t )txq->ift_sds.ifsd_m_deferb, 0)) {
7186 m_defer = txq->ift_sds.ifsd_m_deferb;
7187 }
7188 _iflib_completed_tx_reclaim(txq, m_defer, reclaimable);
7189 }
7190 mtx_unlock(&txq->ift_mtx);
7191
7192 /*
7193 * Process mbuf frees outside the tx lock
7194 */
7195 if (m_defer != NULL) {
7196 for (i = 0; m_defer[i] != NULL; i++) {
7197 m_freem(m_defer[i]);
7198 m_defer[i] = NULL;
7199 }
7200 atomic_store_rel_ptr((uintptr_t *)&txq->ift_sds.ifsd_m_defer,
7201 (uintptr_t)m_defer);
7202 }
7203 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent);
7204 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent);
7205 if (mcast_sent)
7206 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent);
7207
7208 return (error);
7209 }
7210 #endif
7211