1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_helper.h> 7 #include <drm/drm_blend.h> 8 #include <drm/drm_damage_helper.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_drv.h" 12 #include "i915_reg.h" 13 #include "intel_atomic_plane.h" 14 #include "intel_de.h" 15 #include "intel_display_irq.h" 16 #include "intel_display_types.h" 17 #include "intel_dpt.h" 18 #include "intel_fb.h" 19 #include "intel_fbc.h" 20 #include "intel_frontbuffer.h" 21 #include "intel_psr.h" 22 #include "intel_psr_regs.h" 23 #include "skl_scaler.h" 24 #include "skl_universal_plane.h" 25 #include "skl_universal_plane_regs.h" 26 #include "skl_watermark.h" 27 #include "pxp/intel_pxp.h" 28 29 static const u32 skl_plane_formats[] = { 30 DRM_FORMAT_C8, 31 DRM_FORMAT_RGB565, 32 DRM_FORMAT_XRGB8888, 33 DRM_FORMAT_XBGR8888, 34 DRM_FORMAT_ARGB8888, 35 DRM_FORMAT_ABGR8888, 36 DRM_FORMAT_XRGB2101010, 37 DRM_FORMAT_XBGR2101010, 38 DRM_FORMAT_XRGB16161616F, 39 DRM_FORMAT_XBGR16161616F, 40 DRM_FORMAT_YUYV, 41 DRM_FORMAT_YVYU, 42 DRM_FORMAT_UYVY, 43 DRM_FORMAT_VYUY, 44 DRM_FORMAT_XYUV8888, 45 }; 46 47 static const u32 skl_planar_formats[] = { 48 DRM_FORMAT_C8, 49 DRM_FORMAT_RGB565, 50 DRM_FORMAT_XRGB8888, 51 DRM_FORMAT_XBGR8888, 52 DRM_FORMAT_ARGB8888, 53 DRM_FORMAT_ABGR8888, 54 DRM_FORMAT_XRGB2101010, 55 DRM_FORMAT_XBGR2101010, 56 DRM_FORMAT_XRGB16161616F, 57 DRM_FORMAT_XBGR16161616F, 58 DRM_FORMAT_YUYV, 59 DRM_FORMAT_YVYU, 60 DRM_FORMAT_UYVY, 61 DRM_FORMAT_VYUY, 62 DRM_FORMAT_NV12, 63 DRM_FORMAT_XYUV8888, 64 }; 65 66 static const u32 glk_planar_formats[] = { 67 DRM_FORMAT_C8, 68 DRM_FORMAT_RGB565, 69 DRM_FORMAT_XRGB8888, 70 DRM_FORMAT_XBGR8888, 71 DRM_FORMAT_ARGB8888, 72 DRM_FORMAT_ABGR8888, 73 DRM_FORMAT_XRGB2101010, 74 DRM_FORMAT_XBGR2101010, 75 DRM_FORMAT_XRGB16161616F, 76 DRM_FORMAT_XBGR16161616F, 77 DRM_FORMAT_YUYV, 78 DRM_FORMAT_YVYU, 79 DRM_FORMAT_UYVY, 80 DRM_FORMAT_VYUY, 81 DRM_FORMAT_NV12, 82 DRM_FORMAT_XYUV8888, 83 DRM_FORMAT_P010, 84 DRM_FORMAT_P012, 85 DRM_FORMAT_P016, 86 }; 87 88 static const u32 icl_sdr_y_plane_formats[] = { 89 DRM_FORMAT_C8, 90 DRM_FORMAT_RGB565, 91 DRM_FORMAT_XRGB8888, 92 DRM_FORMAT_XBGR8888, 93 DRM_FORMAT_ARGB8888, 94 DRM_FORMAT_ABGR8888, 95 DRM_FORMAT_XRGB2101010, 96 DRM_FORMAT_XBGR2101010, 97 DRM_FORMAT_ARGB2101010, 98 DRM_FORMAT_ABGR2101010, 99 DRM_FORMAT_YUYV, 100 DRM_FORMAT_YVYU, 101 DRM_FORMAT_UYVY, 102 DRM_FORMAT_VYUY, 103 DRM_FORMAT_Y210, 104 DRM_FORMAT_Y212, 105 DRM_FORMAT_Y216, 106 DRM_FORMAT_XYUV8888, 107 DRM_FORMAT_XVYU2101010, 108 DRM_FORMAT_XVYU12_16161616, 109 DRM_FORMAT_XVYU16161616, 110 }; 111 112 static const u32 icl_sdr_uv_plane_formats[] = { 113 DRM_FORMAT_C8, 114 DRM_FORMAT_RGB565, 115 DRM_FORMAT_XRGB8888, 116 DRM_FORMAT_XBGR8888, 117 DRM_FORMAT_ARGB8888, 118 DRM_FORMAT_ABGR8888, 119 DRM_FORMAT_XRGB2101010, 120 DRM_FORMAT_XBGR2101010, 121 DRM_FORMAT_ARGB2101010, 122 DRM_FORMAT_ABGR2101010, 123 DRM_FORMAT_YUYV, 124 DRM_FORMAT_YVYU, 125 DRM_FORMAT_UYVY, 126 DRM_FORMAT_VYUY, 127 DRM_FORMAT_NV12, 128 DRM_FORMAT_P010, 129 DRM_FORMAT_P012, 130 DRM_FORMAT_P016, 131 DRM_FORMAT_Y210, 132 DRM_FORMAT_Y212, 133 DRM_FORMAT_Y216, 134 DRM_FORMAT_XYUV8888, 135 DRM_FORMAT_XVYU2101010, 136 DRM_FORMAT_XVYU12_16161616, 137 DRM_FORMAT_XVYU16161616, 138 }; 139 140 static const u32 icl_hdr_plane_formats[] = { 141 DRM_FORMAT_C8, 142 DRM_FORMAT_RGB565, 143 DRM_FORMAT_XRGB8888, 144 DRM_FORMAT_XBGR8888, 145 DRM_FORMAT_ARGB8888, 146 DRM_FORMAT_ABGR8888, 147 DRM_FORMAT_XRGB2101010, 148 DRM_FORMAT_XBGR2101010, 149 DRM_FORMAT_ARGB2101010, 150 DRM_FORMAT_ABGR2101010, 151 DRM_FORMAT_XRGB16161616F, 152 DRM_FORMAT_XBGR16161616F, 153 DRM_FORMAT_ARGB16161616F, 154 DRM_FORMAT_ABGR16161616F, 155 DRM_FORMAT_YUYV, 156 DRM_FORMAT_YVYU, 157 DRM_FORMAT_UYVY, 158 DRM_FORMAT_VYUY, 159 DRM_FORMAT_NV12, 160 DRM_FORMAT_P010, 161 DRM_FORMAT_P012, 162 DRM_FORMAT_P016, 163 DRM_FORMAT_Y210, 164 DRM_FORMAT_Y212, 165 DRM_FORMAT_Y216, 166 DRM_FORMAT_XYUV8888, 167 DRM_FORMAT_XVYU2101010, 168 DRM_FORMAT_XVYU12_16161616, 169 DRM_FORMAT_XVYU16161616, 170 }; 171 172 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) 173 { 174 switch (format) { 175 case PLANE_CTL_FORMAT_RGB_565: 176 return DRM_FORMAT_RGB565; 177 case PLANE_CTL_FORMAT_NV12: 178 return DRM_FORMAT_NV12; 179 case PLANE_CTL_FORMAT_XYUV: 180 return DRM_FORMAT_XYUV8888; 181 case PLANE_CTL_FORMAT_P010: 182 return DRM_FORMAT_P010; 183 case PLANE_CTL_FORMAT_P012: 184 return DRM_FORMAT_P012; 185 case PLANE_CTL_FORMAT_P016: 186 return DRM_FORMAT_P016; 187 case PLANE_CTL_FORMAT_Y210: 188 return DRM_FORMAT_Y210; 189 case PLANE_CTL_FORMAT_Y212: 190 return DRM_FORMAT_Y212; 191 case PLANE_CTL_FORMAT_Y216: 192 return DRM_FORMAT_Y216; 193 case PLANE_CTL_FORMAT_Y410: 194 return DRM_FORMAT_XVYU2101010; 195 case PLANE_CTL_FORMAT_Y412: 196 return DRM_FORMAT_XVYU12_16161616; 197 case PLANE_CTL_FORMAT_Y416: 198 return DRM_FORMAT_XVYU16161616; 199 default: 200 case PLANE_CTL_FORMAT_XRGB_8888: 201 if (rgb_order) { 202 if (alpha) 203 return DRM_FORMAT_ABGR8888; 204 else 205 return DRM_FORMAT_XBGR8888; 206 } else { 207 if (alpha) 208 return DRM_FORMAT_ARGB8888; 209 else 210 return DRM_FORMAT_XRGB8888; 211 } 212 case PLANE_CTL_FORMAT_XRGB_2101010: 213 if (rgb_order) { 214 if (alpha) 215 return DRM_FORMAT_ABGR2101010; 216 else 217 return DRM_FORMAT_XBGR2101010; 218 } else { 219 if (alpha) 220 return DRM_FORMAT_ARGB2101010; 221 else 222 return DRM_FORMAT_XRGB2101010; 223 } 224 case PLANE_CTL_FORMAT_XRGB_16161616F: 225 if (rgb_order) { 226 if (alpha) 227 return DRM_FORMAT_ABGR16161616F; 228 else 229 return DRM_FORMAT_XBGR16161616F; 230 } else { 231 if (alpha) 232 return DRM_FORMAT_ARGB16161616F; 233 else 234 return DRM_FORMAT_XRGB16161616F; 235 } 236 } 237 } 238 239 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 240 { 241 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 242 return BIT(PLANE_4) | BIT(PLANE_5); 243 else 244 return BIT(PLANE_6) | BIT(PLANE_7); 245 } 246 247 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, 248 enum plane_id plane_id) 249 { 250 return DISPLAY_VER(dev_priv) >= 11 && 251 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); 252 } 253 254 u8 icl_hdr_plane_mask(void) 255 { 256 return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3); 257 } 258 259 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 260 { 261 return DISPLAY_VER(dev_priv) >= 11 && 262 icl_hdr_plane_mask() & BIT(plane_id); 263 } 264 265 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 266 const struct intel_plane_state *plane_state) 267 { 268 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 269 270 /* two pixels per clock */ 271 return DIV_ROUND_UP(pixel_rate, 2); 272 } 273 274 static void 275 glk_plane_ratio(const struct intel_plane_state *plane_state, 276 unsigned int *num, unsigned int *den) 277 { 278 const struct drm_framebuffer *fb = plane_state->hw.fb; 279 280 if (fb->format->cpp[0] == 8) { 281 *num = 10; 282 *den = 8; 283 } else { 284 *num = 1; 285 *den = 1; 286 } 287 } 288 289 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 290 const struct intel_plane_state *plane_state) 291 { 292 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 293 unsigned int num, den; 294 295 glk_plane_ratio(plane_state, &num, &den); 296 297 /* two pixels per clock */ 298 return DIV_ROUND_UP(pixel_rate * num, 2 * den); 299 } 300 301 static void 302 skl_plane_ratio(const struct intel_plane_state *plane_state, 303 unsigned int *num, unsigned int *den) 304 { 305 const struct drm_framebuffer *fb = plane_state->hw.fb; 306 307 if (fb->format->cpp[0] == 8) { 308 *num = 9; 309 *den = 8; 310 } else { 311 *num = 1; 312 *den = 1; 313 } 314 } 315 316 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 317 const struct intel_plane_state *plane_state) 318 { 319 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); 320 unsigned int num, den; 321 322 skl_plane_ratio(plane_state, &num, &den); 323 324 return DIV_ROUND_UP(pixel_rate * num, den); 325 } 326 327 static int skl_plane_max_width(const struct drm_framebuffer *fb, 328 int color_plane, 329 unsigned int rotation) 330 { 331 int cpp = fb->format->cpp[color_plane]; 332 333 switch (fb->modifier) { 334 case DRM_FORMAT_MOD_LINEAR: 335 case I915_FORMAT_MOD_X_TILED: 336 /* 337 * Validated limit is 4k, but has 5k should 338 * work apart from the following features: 339 * - Ytile (already limited to 4k) 340 * - FP16 (already limited to 4k) 341 * - render compression (already limited to 4k) 342 * - KVMR sprite and cursor (don't care) 343 * - horizontal panning (TODO verify this) 344 * - pipe and plane scaling (TODO verify this) 345 */ 346 if (cpp == 8) 347 return 4096; 348 else 349 return 5120; 350 case I915_FORMAT_MOD_Y_TILED_CCS: 351 case I915_FORMAT_MOD_Yf_TILED_CCS: 352 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 353 /* FIXME AUX plane? */ 354 case I915_FORMAT_MOD_Y_TILED: 355 case I915_FORMAT_MOD_Yf_TILED: 356 if (cpp == 8) 357 return 2048; 358 else 359 return 4096; 360 default: 361 MISSING_CASE(fb->modifier); 362 return 2048; 363 } 364 } 365 366 static int glk_plane_max_width(const struct drm_framebuffer *fb, 367 int color_plane, 368 unsigned int rotation) 369 { 370 int cpp = fb->format->cpp[color_plane]; 371 372 switch (fb->modifier) { 373 case DRM_FORMAT_MOD_LINEAR: 374 case I915_FORMAT_MOD_X_TILED: 375 if (cpp == 8) 376 return 4096; 377 else 378 return 5120; 379 case I915_FORMAT_MOD_Y_TILED_CCS: 380 case I915_FORMAT_MOD_Yf_TILED_CCS: 381 /* FIXME AUX plane? */ 382 case I915_FORMAT_MOD_Y_TILED: 383 case I915_FORMAT_MOD_Yf_TILED: 384 if (cpp == 8) 385 return 2048; 386 else 387 return 5120; 388 default: 389 MISSING_CASE(fb->modifier); 390 return 2048; 391 } 392 } 393 394 static int icl_plane_min_width(const struct drm_framebuffer *fb, 395 int color_plane, 396 unsigned int rotation) 397 { 398 /* Wa_14011264657, Wa_14011050563: gen11+ */ 399 switch (fb->format->format) { 400 case DRM_FORMAT_C8: 401 return 18; 402 case DRM_FORMAT_RGB565: 403 return 10; 404 case DRM_FORMAT_XRGB8888: 405 case DRM_FORMAT_XBGR8888: 406 case DRM_FORMAT_ARGB8888: 407 case DRM_FORMAT_ABGR8888: 408 case DRM_FORMAT_XRGB2101010: 409 case DRM_FORMAT_XBGR2101010: 410 case DRM_FORMAT_ARGB2101010: 411 case DRM_FORMAT_ABGR2101010: 412 case DRM_FORMAT_XVYU2101010: 413 case DRM_FORMAT_Y212: 414 case DRM_FORMAT_Y216: 415 return 6; 416 case DRM_FORMAT_NV12: 417 return 20; 418 case DRM_FORMAT_P010: 419 case DRM_FORMAT_P012: 420 case DRM_FORMAT_P016: 421 return 12; 422 case DRM_FORMAT_XRGB16161616F: 423 case DRM_FORMAT_XBGR16161616F: 424 case DRM_FORMAT_ARGB16161616F: 425 case DRM_FORMAT_ABGR16161616F: 426 case DRM_FORMAT_XVYU12_16161616: 427 case DRM_FORMAT_XVYU16161616: 428 return 4; 429 default: 430 return 1; 431 } 432 } 433 434 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb, 435 int color_plane, 436 unsigned int rotation) 437 { 438 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 439 return 4096; 440 else 441 return 5120; 442 } 443 444 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb, 445 int color_plane, 446 unsigned int rotation) 447 { 448 return 5120; 449 } 450 451 static int skl_plane_max_height(const struct drm_framebuffer *fb, 452 int color_plane, 453 unsigned int rotation) 454 { 455 return 4096; 456 } 457 458 static int icl_plane_max_height(const struct drm_framebuffer *fb, 459 int color_plane, 460 unsigned int rotation) 461 { 462 return 4320; 463 } 464 465 static unsigned int 466 plane_max_stride(struct intel_plane *plane, 467 u32 pixel_format, u64 modifier, 468 unsigned int rotation, 469 unsigned int max_pixels, 470 unsigned int max_bytes) 471 { 472 const struct drm_format_info *info = drm_format_info(pixel_format); 473 int cpp = info->cpp[0]; 474 475 if (drm_rotation_90_or_270(rotation)) 476 return min(max_pixels, max_bytes / cpp); 477 else 478 return min(max_pixels * cpp, max_bytes); 479 } 480 481 static unsigned int 482 adl_plane_max_stride(struct intel_plane *plane, 483 u32 pixel_format, u64 modifier, 484 unsigned int rotation) 485 { 486 unsigned int max_pixels = 65536; /* PLANE_OFFSET limit */ 487 unsigned int max_bytes = 128 * 1024; 488 489 return plane_max_stride(plane, pixel_format, 490 modifier, rotation, 491 max_pixels, max_bytes); 492 } 493 494 static unsigned int 495 skl_plane_max_stride(struct intel_plane *plane, 496 u32 pixel_format, u64 modifier, 497 unsigned int rotation) 498 { 499 unsigned int max_pixels = 8192; /* PLANE_OFFSET limit */ 500 unsigned int max_bytes = 32 * 1024; 501 502 return plane_max_stride(plane, pixel_format, 503 modifier, rotation, 504 max_pixels, max_bytes); 505 } 506 507 static u32 tgl_plane_min_alignment(struct intel_plane *plane, 508 const struct drm_framebuffer *fb, 509 int color_plane) 510 { 511 struct drm_i915_private *i915 = to_i915(plane->base.dev); 512 /* PLANE_SURF GGTT -> DPT alignment */ 513 int mult = intel_fb_uses_dpt(fb) ? 512 : 1; 514 515 /* AUX_DIST needs only 4K alignment */ 516 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 517 return mult * 4 * 1024; 518 519 switch (fb->modifier) { 520 case DRM_FORMAT_MOD_LINEAR: 521 case I915_FORMAT_MOD_X_TILED: 522 case I915_FORMAT_MOD_Y_TILED: 523 case I915_FORMAT_MOD_4_TILED: 524 /* 525 * FIXME ADL sees GGTT/DMAR faults with async 526 * flips unless we align to 16k at least. 527 * Figure out what's going on here... 528 */ 529 if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) 530 return mult * 16 * 1024; 531 return mult * 4 * 1024; 532 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 533 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 534 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 535 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 536 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 537 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 538 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 539 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 540 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 541 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 542 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 543 /* 544 * Align to at least 4x1 main surface 545 * tiles (16K) to match 64B of AUX. 546 */ 547 return max(mult * 4 * 1024, 16 * 1024); 548 default: 549 MISSING_CASE(fb->modifier); 550 return 0; 551 } 552 } 553 554 static u32 skl_plane_min_alignment(struct intel_plane *plane, 555 const struct drm_framebuffer *fb, 556 int color_plane) 557 { 558 /* 559 * AUX_DIST needs only 4K alignment, 560 * as does ICL UV PLANE_SURF. 561 */ 562 if (color_plane != 0) 563 return 4 * 1024; 564 565 switch (fb->modifier) { 566 case DRM_FORMAT_MOD_LINEAR: 567 case I915_FORMAT_MOD_X_TILED: 568 return 256 * 1024; 569 case I915_FORMAT_MOD_Y_TILED_CCS: 570 case I915_FORMAT_MOD_Yf_TILED_CCS: 571 case I915_FORMAT_MOD_Y_TILED: 572 case I915_FORMAT_MOD_Yf_TILED: 573 return 1 * 1024 * 1024; 574 default: 575 MISSING_CASE(fb->modifier); 576 return 0; 577 } 578 } 579 580 /* Preoffset values for YUV to RGB Conversion */ 581 #define PREOFF_YUV_TO_RGB_HI 0x1800 582 #define PREOFF_YUV_TO_RGB_ME 0x0000 583 #define PREOFF_YUV_TO_RGB_LO 0x1800 584 585 #define ROFF(x) (((x) & 0xffff) << 16) 586 #define GOFF(x) (((x) & 0xffff) << 0) 587 #define BOFF(x) (((x) & 0xffff) << 16) 588 589 /* 590 * Programs the input color space conversion stage for ICL HDR planes. 591 * Note that it is assumed that this stage always happens after YUV 592 * range correction. Thus, the input to this stage is assumed to be 593 * in full-range YCbCr. 594 */ 595 static void 596 icl_program_input_csc(struct intel_plane *plane, 597 const struct intel_crtc_state *crtc_state, 598 const struct intel_plane_state *plane_state) 599 { 600 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 601 enum pipe pipe = plane->pipe; 602 enum plane_id plane_id = plane->id; 603 604 static const u16 input_csc_matrix[][9] = { 605 /* 606 * BT.601 full range YCbCr -> full range RGB 607 * The matrix required is : 608 * [1.000, 0.000, 1.371, 609 * 1.000, -0.336, -0.698, 610 * 1.000, 1.732, 0.0000] 611 */ 612 [DRM_COLOR_YCBCR_BT601] = { 613 0x7AF8, 0x7800, 0x0, 614 0x8B28, 0x7800, 0x9AC0, 615 0x0, 0x7800, 0x7DD8, 616 }, 617 /* 618 * BT.709 full range YCbCr -> full range RGB 619 * The matrix required is : 620 * [1.000, 0.000, 1.574, 621 * 1.000, -0.187, -0.468, 622 * 1.000, 1.855, 0.0000] 623 */ 624 [DRM_COLOR_YCBCR_BT709] = { 625 0x7C98, 0x7800, 0x0, 626 0x9EF8, 0x7800, 0xAC00, 627 0x0, 0x7800, 0x7ED8, 628 }, 629 /* 630 * BT.2020 full range YCbCr -> full range RGB 631 * The matrix required is : 632 * [1.000, 0.000, 1.474, 633 * 1.000, -0.1645, -0.5713, 634 * 1.000, 1.8814, 0.0000] 635 */ 636 [DRM_COLOR_YCBCR_BT2020] = { 637 0x7BC8, 0x7800, 0x0, 638 0x8928, 0x7800, 0xAA88, 639 0x0, 0x7800, 0x7F10, 640 }, 641 }; 642 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; 643 644 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), 645 ROFF(csc[0]) | GOFF(csc[1])); 646 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), 647 BOFF(csc[2])); 648 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), 649 ROFF(csc[3]) | GOFF(csc[4])); 650 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), 651 BOFF(csc[5])); 652 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), 653 ROFF(csc[6]) | GOFF(csc[7])); 654 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), 655 BOFF(csc[8])); 656 657 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 658 PREOFF_YUV_TO_RGB_HI); 659 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 660 PREOFF_YUV_TO_RGB_ME); 661 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 662 PREOFF_YUV_TO_RGB_LO); 663 intel_de_write_fw(dev_priv, 664 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 665 intel_de_write_fw(dev_priv, 666 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 667 intel_de_write_fw(dev_priv, 668 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 669 } 670 671 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, 672 int color_plane, unsigned int rotation) 673 { 674 /* 675 * The stride is either expressed as a multiple of 64 bytes chunks for 676 * linear buffers or in number of tiles for tiled buffers. 677 */ 678 if (is_surface_linear(fb, color_plane)) 679 return 64; 680 else if (drm_rotation_90_or_270(rotation)) 681 return intel_tile_height(fb, color_plane); 682 else 683 return intel_tile_width_bytes(fb, color_plane); 684 } 685 686 static u32 skl_plane_stride(const struct intel_plane_state *plane_state, 687 int color_plane) 688 { 689 const struct drm_framebuffer *fb = plane_state->hw.fb; 690 unsigned int rotation = plane_state->hw.rotation; 691 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride; 692 693 if (color_plane >= fb->format->num_planes) 694 return 0; 695 696 return stride / skl_plane_stride_mult(fb, color_plane, rotation); 697 } 698 699 static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) 700 { 701 if (!entry->end) 702 return 0; 703 704 return PLANE_BUF_END(entry->end - 1) | 705 PLANE_BUF_START(entry->start); 706 } 707 708 static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) 709 { 710 u32 val = 0; 711 712 if (level->enable) 713 val |= PLANE_WM_EN; 714 if (level->ignore_lines) 715 val |= PLANE_WM_IGNORE_LINES; 716 val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); 717 val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); 718 719 return val; 720 } 721 722 static void skl_write_plane_wm(struct intel_plane *plane, 723 const struct intel_crtc_state *crtc_state) 724 { 725 struct drm_i915_private *i915 = to_i915(plane->base.dev); 726 enum plane_id plane_id = plane->id; 727 enum pipe pipe = plane->pipe; 728 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; 729 const struct skl_ddb_entry *ddb = 730 &crtc_state->wm.skl.plane_ddb[plane_id]; 731 const struct skl_ddb_entry *ddb_y = 732 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 733 int level; 734 735 for (level = 0; level < i915->display.wm.num_levels; level++) 736 intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level), 737 skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); 738 739 intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id), 740 skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); 741 742 if (HAS_HW_SAGV_WM(i915)) { 743 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 744 745 intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id), 746 skl_plane_wm_reg_val(&wm->sagv.wm0)); 747 intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id), 748 skl_plane_wm_reg_val(&wm->sagv.trans_wm)); 749 } 750 751 intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id), 752 skl_plane_ddb_reg_val(ddb)); 753 754 if (DISPLAY_VER(i915) < 11) 755 intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id), 756 skl_plane_ddb_reg_val(ddb_y)); 757 } 758 759 static void 760 skl_plane_disable_arm(struct intel_plane *plane, 761 const struct intel_crtc_state *crtc_state) 762 { 763 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 764 enum plane_id plane_id = plane->id; 765 enum pipe pipe = plane->pipe; 766 767 skl_write_plane_wm(plane, crtc_state); 768 769 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 770 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 771 } 772 773 static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane, 774 const struct intel_crtc_state *crtc_state) 775 { 776 struct drm_i915_private *i915 = to_i915(plane->base.dev); 777 enum pipe pipe = plane->pipe; 778 779 if (!crtc_state->enable_psr2_sel_fetch) 780 return; 781 782 intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); 783 } 784 785 static void 786 icl_plane_disable_arm(struct intel_plane *plane, 787 const struct intel_crtc_state *crtc_state) 788 { 789 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 790 enum plane_id plane_id = plane->id; 791 enum pipe pipe = plane->pipe; 792 793 if (icl_is_hdr_plane(dev_priv, plane_id)) 794 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); 795 796 skl_write_plane_wm(plane, crtc_state); 797 798 icl_plane_disable_sel_fetch_arm(plane, crtc_state); 799 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); 800 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); 801 } 802 803 static bool 804 skl_plane_get_hw_state(struct intel_plane *plane, 805 enum pipe *pipe) 806 { 807 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 808 enum intel_display_power_domain power_domain; 809 enum plane_id plane_id = plane->id; 810 intel_wakeref_t wakeref; 811 bool ret; 812 813 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 814 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 815 if (!wakeref) 816 return false; 817 818 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 819 820 *pipe = plane->pipe; 821 822 intel_display_power_put(dev_priv, power_domain, wakeref); 823 824 return ret; 825 } 826 827 static u32 skl_plane_ctl_format(u32 pixel_format) 828 { 829 switch (pixel_format) { 830 case DRM_FORMAT_C8: 831 return PLANE_CTL_FORMAT_INDEXED; 832 case DRM_FORMAT_RGB565: 833 return PLANE_CTL_FORMAT_RGB_565; 834 case DRM_FORMAT_XBGR8888: 835 case DRM_FORMAT_ABGR8888: 836 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; 837 case DRM_FORMAT_XRGB8888: 838 case DRM_FORMAT_ARGB8888: 839 return PLANE_CTL_FORMAT_XRGB_8888; 840 case DRM_FORMAT_XBGR2101010: 841 case DRM_FORMAT_ABGR2101010: 842 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX; 843 case DRM_FORMAT_XRGB2101010: 844 case DRM_FORMAT_ARGB2101010: 845 return PLANE_CTL_FORMAT_XRGB_2101010; 846 case DRM_FORMAT_XBGR16161616F: 847 case DRM_FORMAT_ABGR16161616F: 848 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX; 849 case DRM_FORMAT_XRGB16161616F: 850 case DRM_FORMAT_ARGB16161616F: 851 return PLANE_CTL_FORMAT_XRGB_16161616F; 852 case DRM_FORMAT_XYUV8888: 853 return PLANE_CTL_FORMAT_XYUV; 854 case DRM_FORMAT_YUYV: 855 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV; 856 case DRM_FORMAT_YVYU: 857 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU; 858 case DRM_FORMAT_UYVY: 859 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY; 860 case DRM_FORMAT_VYUY: 861 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY; 862 case DRM_FORMAT_NV12: 863 return PLANE_CTL_FORMAT_NV12; 864 case DRM_FORMAT_P010: 865 return PLANE_CTL_FORMAT_P010; 866 case DRM_FORMAT_P012: 867 return PLANE_CTL_FORMAT_P012; 868 case DRM_FORMAT_P016: 869 return PLANE_CTL_FORMAT_P016; 870 case DRM_FORMAT_Y210: 871 return PLANE_CTL_FORMAT_Y210; 872 case DRM_FORMAT_Y212: 873 return PLANE_CTL_FORMAT_Y212; 874 case DRM_FORMAT_Y216: 875 return PLANE_CTL_FORMAT_Y216; 876 case DRM_FORMAT_XVYU2101010: 877 return PLANE_CTL_FORMAT_Y410; 878 case DRM_FORMAT_XVYU12_16161616: 879 return PLANE_CTL_FORMAT_Y412; 880 case DRM_FORMAT_XVYU16161616: 881 return PLANE_CTL_FORMAT_Y416; 882 default: 883 MISSING_CASE(pixel_format); 884 } 885 886 return 0; 887 } 888 889 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) 890 { 891 if (!plane_state->hw.fb->format->has_alpha) 892 return PLANE_CTL_ALPHA_DISABLE; 893 894 switch (plane_state->hw.pixel_blend_mode) { 895 case DRM_MODE_BLEND_PIXEL_NONE: 896 return PLANE_CTL_ALPHA_DISABLE; 897 case DRM_MODE_BLEND_PREMULTI: 898 return PLANE_CTL_ALPHA_SW_PREMULTIPLY; 899 case DRM_MODE_BLEND_COVERAGE: 900 return PLANE_CTL_ALPHA_HW_PREMULTIPLY; 901 default: 902 MISSING_CASE(plane_state->hw.pixel_blend_mode); 903 return PLANE_CTL_ALPHA_DISABLE; 904 } 905 } 906 907 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) 908 { 909 if (!plane_state->hw.fb->format->has_alpha) 910 return PLANE_COLOR_ALPHA_DISABLE; 911 912 switch (plane_state->hw.pixel_blend_mode) { 913 case DRM_MODE_BLEND_PIXEL_NONE: 914 return PLANE_COLOR_ALPHA_DISABLE; 915 case DRM_MODE_BLEND_PREMULTI: 916 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY; 917 case DRM_MODE_BLEND_COVERAGE: 918 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY; 919 default: 920 MISSING_CASE(plane_state->hw.pixel_blend_mode); 921 return PLANE_COLOR_ALPHA_DISABLE; 922 } 923 } 924 925 static u32 skl_plane_ctl_tiling(u64 fb_modifier) 926 { 927 switch (fb_modifier) { 928 case DRM_FORMAT_MOD_LINEAR: 929 break; 930 case I915_FORMAT_MOD_X_TILED: 931 return PLANE_CTL_TILED_X; 932 case I915_FORMAT_MOD_Y_TILED: 933 return PLANE_CTL_TILED_Y; 934 case I915_FORMAT_MOD_4_TILED: 935 return PLANE_CTL_TILED_4; 936 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 937 return PLANE_CTL_TILED_4 | 938 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 939 PLANE_CTL_CLEAR_COLOR_DISABLE; 940 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 941 return PLANE_CTL_TILED_4 | 942 PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE | 943 PLANE_CTL_CLEAR_COLOR_DISABLE; 944 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 945 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 946 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 947 return PLANE_CTL_TILED_4 | 948 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 949 PLANE_CTL_CLEAR_COLOR_DISABLE; 950 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 951 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 952 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 953 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 954 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 955 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 956 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 957 case I915_FORMAT_MOD_Y_TILED_CCS: 958 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 959 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 960 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 961 return PLANE_CTL_TILED_Y | 962 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 963 PLANE_CTL_CLEAR_COLOR_DISABLE; 964 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 965 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 966 case I915_FORMAT_MOD_Yf_TILED: 967 return PLANE_CTL_TILED_YF; 968 case I915_FORMAT_MOD_Yf_TILED_CCS: 969 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 970 default: 971 MISSING_CASE(fb_modifier); 972 } 973 974 return 0; 975 } 976 977 static u32 skl_plane_ctl_rotate(unsigned int rotate) 978 { 979 switch (rotate) { 980 case DRM_MODE_ROTATE_0: 981 break; 982 /* 983 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 984 * while i915 HW rotation is clockwise, thats why this swapping. 985 */ 986 case DRM_MODE_ROTATE_90: 987 return PLANE_CTL_ROTATE_270; 988 case DRM_MODE_ROTATE_180: 989 return PLANE_CTL_ROTATE_180; 990 case DRM_MODE_ROTATE_270: 991 return PLANE_CTL_ROTATE_90; 992 default: 993 MISSING_CASE(rotate); 994 } 995 996 return 0; 997 } 998 999 static u32 icl_plane_ctl_flip(unsigned int reflect) 1000 { 1001 switch (reflect) { 1002 case 0: 1003 break; 1004 case DRM_MODE_REFLECT_X: 1005 return PLANE_CTL_FLIP_HORIZONTAL; 1006 case DRM_MODE_REFLECT_Y: 1007 default: 1008 MISSING_CASE(reflect); 1009 } 1010 1011 return 0; 1012 } 1013 1014 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) 1015 { 1016 const struct drm_framebuffer *fb = plane_state->hw.fb; 1017 1018 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 1019 switch (fb->format->cpp[0]) { 1020 case 2: 1021 return PLANE_CTL_ARB_SLOTS(1); 1022 default: 1023 return PLANE_CTL_ARB_SLOTS(0); 1024 } 1025 } else { 1026 switch (fb->format->cpp[0]) { 1027 case 8: 1028 return PLANE_CTL_ARB_SLOTS(3); 1029 case 4: 1030 return PLANE_CTL_ARB_SLOTS(1); 1031 default: 1032 return PLANE_CTL_ARB_SLOTS(0); 1033 } 1034 } 1035 } 1036 1037 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 1038 { 1039 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1040 u32 plane_ctl = 0; 1041 1042 if (DISPLAY_VER(dev_priv) >= 10) 1043 return plane_ctl; 1044 1045 if (crtc_state->gamma_enable) 1046 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE; 1047 1048 if (crtc_state->csc_enable) 1049 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; 1050 1051 return plane_ctl; 1052 } 1053 1054 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, 1055 const struct intel_plane_state *plane_state) 1056 { 1057 struct drm_i915_private *dev_priv = 1058 to_i915(plane_state->uapi.plane->dev); 1059 const struct drm_framebuffer *fb = plane_state->hw.fb; 1060 unsigned int rotation = plane_state->hw.rotation; 1061 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1062 u32 plane_ctl; 1063 1064 plane_ctl = PLANE_CTL_ENABLE; 1065 1066 if (DISPLAY_VER(dev_priv) < 10) { 1067 plane_ctl |= skl_plane_ctl_alpha(plane_state); 1068 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 1069 1070 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1071 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709; 1072 1073 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1074 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE; 1075 } 1076 1077 plane_ctl |= skl_plane_ctl_format(fb->format->format); 1078 plane_ctl |= skl_plane_ctl_tiling(fb->modifier); 1079 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); 1080 1081 if (DISPLAY_VER(dev_priv) >= 11) 1082 plane_ctl |= icl_plane_ctl_flip(rotation & 1083 DRM_MODE_REFLECT_MASK); 1084 1085 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1086 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 1087 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1088 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 1089 1090 /* Wa_22012358565:adl-p */ 1091 if (DISPLAY_VER(dev_priv) == 13) 1092 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); 1093 1094 return plane_ctl; 1095 } 1096 1097 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) 1098 { 1099 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1100 u32 plane_color_ctl = 0; 1101 1102 if (DISPLAY_VER(dev_priv) >= 11) 1103 return plane_color_ctl; 1104 1105 if (crtc_state->gamma_enable) 1106 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; 1107 1108 if (crtc_state->csc_enable) 1109 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; 1110 1111 return plane_color_ctl; 1112 } 1113 1114 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, 1115 const struct intel_plane_state *plane_state) 1116 { 1117 struct drm_i915_private *dev_priv = 1118 to_i915(plane_state->uapi.plane->dev); 1119 const struct drm_framebuffer *fb = plane_state->hw.fb; 1120 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1121 u32 plane_color_ctl = 0; 1122 1123 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; 1124 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); 1125 1126 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { 1127 switch (plane_state->hw.color_encoding) { 1128 case DRM_COLOR_YCBCR_BT709: 1129 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; 1130 break; 1131 case DRM_COLOR_YCBCR_BT2020: 1132 plane_color_ctl |= 1133 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; 1134 break; 1135 default: 1136 plane_color_ctl |= 1137 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; 1138 } 1139 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1140 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 1141 } else if (fb->format->is_yuv) { 1142 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE; 1143 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1144 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; 1145 } 1146 1147 if (plane_state->force_black) 1148 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; 1149 1150 return plane_color_ctl; 1151 } 1152 1153 static u32 skl_surf_address(const struct intel_plane_state *plane_state, 1154 int color_plane) 1155 { 1156 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1157 const struct drm_framebuffer *fb = plane_state->hw.fb; 1158 u32 offset = plane_state->view.color_plane[color_plane].offset; 1159 1160 if (intel_fb_uses_dpt(fb)) { 1161 /* 1162 * The DPT object contains only one vma, so the VMA's offset 1163 * within the DPT is always 0. 1164 */ 1165 drm_WARN_ON(&i915->drm, plane_state->dpt_vma && 1166 intel_dpt_offset(plane_state->dpt_vma)); 1167 drm_WARN_ON(&i915->drm, offset & 0x1fffff); 1168 return offset >> 9; 1169 } else { 1170 drm_WARN_ON(&i915->drm, offset & 0xfff); 1171 return offset; 1172 } 1173 } 1174 1175 static u32 skl_plane_surf(const struct intel_plane_state *plane_state, 1176 int color_plane) 1177 { 1178 u32 plane_surf; 1179 1180 plane_surf = intel_plane_ggtt_offset(plane_state) + 1181 skl_surf_address(plane_state, color_plane); 1182 1183 if (plane_state->decrypt) 1184 plane_surf |= PLANE_SURF_DECRYPT; 1185 1186 return plane_surf; 1187 } 1188 1189 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, 1190 int color_plane) 1191 { 1192 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1193 const struct drm_framebuffer *fb = plane_state->hw.fb; 1194 int aux_plane = skl_main_to_aux_plane(fb, color_plane); 1195 u32 aux_dist; 1196 1197 if (!aux_plane) 1198 return 0; 1199 1200 aux_dist = skl_surf_address(plane_state, aux_plane) - 1201 skl_surf_address(plane_state, color_plane); 1202 1203 if (DISPLAY_VER(i915) < 12) 1204 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); 1205 1206 return aux_dist; 1207 } 1208 1209 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state) 1210 { 1211 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1212 1213 return key->min_value; 1214 } 1215 1216 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state) 1217 { 1218 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1219 u8 alpha = plane_state->hw.alpha >> 8; 1220 1221 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 1222 } 1223 1224 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state) 1225 { 1226 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1227 u8 alpha = plane_state->hw.alpha >> 8; 1228 u32 keymsk; 1229 1230 keymsk = key->channel_mask & 0x7ffffff; 1231 if (alpha < 0xff) 1232 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 1233 1234 return keymsk; 1235 } 1236 1237 static void icl_plane_csc_load_black(struct intel_plane *plane) 1238 { 1239 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1240 enum plane_id plane_id = plane->id; 1241 enum pipe pipe = plane->pipe; 1242 1243 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0); 1244 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0); 1245 1246 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0); 1247 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0); 1248 1249 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0); 1250 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0); 1251 1252 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0); 1253 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0); 1254 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0); 1255 1256 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0); 1257 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0); 1258 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0); 1259 } 1260 1261 static int icl_plane_color_plane(const struct intel_plane_state *plane_state) 1262 { 1263 /* Program the UV plane on planar master */ 1264 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 1265 return 1; 1266 else 1267 return 0; 1268 } 1269 1270 static void 1271 skl_plane_update_noarm(struct intel_plane *plane, 1272 const struct intel_crtc_state *crtc_state, 1273 const struct intel_plane_state *plane_state) 1274 { 1275 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1276 enum plane_id plane_id = plane->id; 1277 enum pipe pipe = plane->pipe; 1278 u32 stride = skl_plane_stride(plane_state, 0); 1279 int crtc_x = plane_state->uapi.dst.x1; 1280 int crtc_y = plane_state->uapi.dst.y1; 1281 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1282 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1283 1284 /* The scaler will handle the output position */ 1285 if (plane_state->scaler_id >= 0) { 1286 crtc_x = 0; 1287 crtc_y = 0; 1288 } 1289 1290 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1291 PLANE_STRIDE_(stride)); 1292 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1293 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1294 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1295 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1296 1297 skl_write_plane_wm(plane, crtc_state); 1298 } 1299 1300 static void 1301 skl_plane_update_arm(struct intel_plane *plane, 1302 const struct intel_crtc_state *crtc_state, 1303 const struct intel_plane_state *plane_state) 1304 { 1305 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1306 enum plane_id plane_id = plane->id; 1307 enum pipe pipe = plane->pipe; 1308 u32 x = plane_state->view.color_plane[0].x; 1309 u32 y = plane_state->view.color_plane[0].y; 1310 u32 plane_ctl, plane_color_ctl = 0; 1311 1312 plane_ctl = plane_state->ctl | 1313 skl_plane_ctl_crtc(crtc_state); 1314 1315 /* see intel_plane_atomic_calc_changes() */ 1316 if (plane->need_async_flip_toggle_wa && 1317 crtc_state->async_flip_planes & BIT(plane->id)) 1318 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1319 1320 if (DISPLAY_VER(dev_priv) >= 10) 1321 plane_color_ctl = plane_state->color_ctl | 1322 glk_plane_color_ctl_crtc(crtc_state); 1323 1324 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1325 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1326 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1327 1328 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1329 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1330 1331 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1332 skl_plane_aux_dist(plane_state, 0)); 1333 1334 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), 1335 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | 1336 PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); 1337 1338 if (DISPLAY_VER(dev_priv) >= 10) 1339 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1340 1341 /* 1342 * Enable the scaler before the plane so that we don't 1343 * get a catastrophic underrun even if the two operations 1344 * end up happening in two different frames. 1345 * 1346 * TODO: split into noarm+arm pair 1347 */ 1348 if (plane_state->scaler_id >= 0) 1349 skl_program_plane_scaler(plane, crtc_state, plane_state); 1350 1351 /* 1352 * The control register self-arms if the plane was previously 1353 * disabled. Try to make the plane enable atomic by writing 1354 * the control register just before the surface register. 1355 */ 1356 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1357 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1358 skl_plane_surf(plane_state, 0)); 1359 } 1360 1361 static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, 1362 const struct intel_crtc_state *crtc_state, 1363 const struct intel_plane_state *plane_state, 1364 int color_plane) 1365 { 1366 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1367 enum pipe pipe = plane->pipe; 1368 const struct drm_rect *clip; 1369 u32 val; 1370 int x, y; 1371 1372 if (!crtc_state->enable_psr2_sel_fetch) 1373 return; 1374 1375 clip = &plane_state->psr2_sel_fetch_area; 1376 1377 if (crtc_state->enable_psr2_su_region_et) 1378 y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1); 1379 else 1380 y = (clip->y1 + plane_state->uapi.dst.y1); 1381 val = y << 16; 1382 val |= plane_state->uapi.dst.x1; 1383 intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); 1384 1385 x = plane_state->view.color_plane[color_plane].x; 1386 1387 /* 1388 * From Bspec: UV surface Start Y Position = half of Y plane Y 1389 * start position. 1390 */ 1391 if (!color_plane) 1392 y = plane_state->view.color_plane[color_plane].y + clip->y1; 1393 else 1394 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; 1395 1396 val = y << 16 | x; 1397 1398 intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), 1399 val); 1400 1401 /* Sizes are 0 based */ 1402 val = (drm_rect_height(clip) - 1) << 16; 1403 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; 1404 intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); 1405 } 1406 1407 static void 1408 icl_plane_update_noarm(struct intel_plane *plane, 1409 const struct intel_crtc_state *crtc_state, 1410 const struct intel_plane_state *plane_state) 1411 { 1412 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1413 enum plane_id plane_id = plane->id; 1414 enum pipe pipe = plane->pipe; 1415 int color_plane = icl_plane_color_plane(plane_state); 1416 u32 stride = skl_plane_stride(plane_state, color_plane); 1417 const struct drm_framebuffer *fb = plane_state->hw.fb; 1418 int crtc_x = plane_state->uapi.dst.x1; 1419 int crtc_y = plane_state->uapi.dst.y1; 1420 int x = plane_state->view.color_plane[color_plane].x; 1421 int y = plane_state->view.color_plane[color_plane].y; 1422 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1423 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1424 u32 plane_color_ctl; 1425 1426 plane_color_ctl = plane_state->color_ctl | 1427 glk_plane_color_ctl_crtc(crtc_state); 1428 1429 /* The scaler will handle the output position */ 1430 if (plane_state->scaler_id >= 0) { 1431 crtc_x = 0; 1432 crtc_y = 0; 1433 } 1434 1435 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), 1436 PLANE_STRIDE_(stride)); 1437 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), 1438 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x)); 1439 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), 1440 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1)); 1441 1442 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); 1443 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state)); 1444 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state)); 1445 1446 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), 1447 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x)); 1448 1449 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) { 1450 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0), 1451 lower_32_bits(plane_state->ccval)); 1452 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1), 1453 upper_32_bits(plane_state->ccval)); 1454 } 1455 1456 /* FLAT CCS doesn't need to program AUX_DIST */ 1457 if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20) 1458 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), 1459 skl_plane_aux_dist(plane_state, color_plane)); 1460 1461 if (icl_is_hdr_plane(dev_priv, plane_id)) 1462 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 1463 plane_state->cus_ctl); 1464 1465 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 1466 1467 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 1468 icl_program_input_csc(plane, crtc_state, plane_state); 1469 1470 skl_write_plane_wm(plane, crtc_state); 1471 1472 /* 1473 * FIXME: pxp session invalidation can hit any time even at time of commit 1474 * or after the commit, display content will be garbage. 1475 */ 1476 if (plane_state->force_black) 1477 icl_plane_csc_load_black(plane); 1478 1479 icl_plane_update_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane); 1480 } 1481 1482 static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane, 1483 const struct intel_crtc_state *crtc_state, 1484 const struct intel_plane_state *plane_state) 1485 { 1486 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1487 enum pipe pipe = plane->pipe; 1488 1489 if (!crtc_state->enable_psr2_sel_fetch) 1490 return; 1491 1492 if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) 1493 intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 1494 SEL_FETCH_PLANE_CTL_ENABLE); 1495 else 1496 icl_plane_disable_sel_fetch_arm(plane, crtc_state); 1497 } 1498 1499 static void 1500 icl_plane_update_arm(struct intel_plane *plane, 1501 const struct intel_crtc_state *crtc_state, 1502 const struct intel_plane_state *plane_state) 1503 { 1504 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1505 enum plane_id plane_id = plane->id; 1506 enum pipe pipe = plane->pipe; 1507 int color_plane = icl_plane_color_plane(plane_state); 1508 u32 plane_ctl; 1509 1510 plane_ctl = plane_state->ctl | 1511 skl_plane_ctl_crtc(crtc_state); 1512 1513 /* 1514 * Enable the scaler before the plane so that we don't 1515 * get a catastrophic underrun even if the two operations 1516 * end up happening in two different frames. 1517 * 1518 * TODO: split into noarm+arm pair 1519 */ 1520 if (plane_state->scaler_id >= 0) 1521 skl_program_plane_scaler(plane, crtc_state, plane_state); 1522 1523 icl_plane_update_sel_fetch_arm(plane, crtc_state, plane_state); 1524 1525 /* 1526 * The control register self-arms if the plane was previously 1527 * disabled. Try to make the plane enable atomic by writing 1528 * the control register just before the surface register. 1529 */ 1530 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1531 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1532 skl_plane_surf(plane_state, color_plane)); 1533 } 1534 1535 static void 1536 skl_plane_async_flip(struct intel_plane *plane, 1537 const struct intel_crtc_state *crtc_state, 1538 const struct intel_plane_state *plane_state, 1539 bool async_flip) 1540 { 1541 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1542 enum plane_id plane_id = plane->id; 1543 enum pipe pipe = plane->pipe; 1544 u32 plane_ctl = plane_state->ctl; 1545 1546 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 1547 1548 if (async_flip) 1549 plane_ctl |= PLANE_CTL_ASYNC_FLIP; 1550 1551 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); 1552 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 1553 skl_plane_surf(plane_state, 0)); 1554 } 1555 1556 static bool intel_format_is_p01x(u32 format) 1557 { 1558 switch (format) { 1559 case DRM_FORMAT_P010: 1560 case DRM_FORMAT_P012: 1561 case DRM_FORMAT_P016: 1562 return true; 1563 default: 1564 return false; 1565 } 1566 } 1567 1568 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 1569 const struct intel_plane_state *plane_state) 1570 { 1571 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1572 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1573 const struct drm_framebuffer *fb = plane_state->hw.fb; 1574 unsigned int rotation = plane_state->hw.rotation; 1575 1576 if (!fb) 1577 return 0; 1578 1579 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 1580 intel_fb_is_ccs_modifier(fb->modifier)) { 1581 drm_dbg_kms(&dev_priv->drm, 1582 "RC support only with 0/180 degree rotation (%x)\n", 1583 rotation); 1584 return -EINVAL; 1585 } 1586 1587 if (rotation & DRM_MODE_REFLECT_X && 1588 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1589 drm_dbg_kms(&dev_priv->drm, 1590 "horizontal flip is not supported with linear surface formats\n"); 1591 return -EINVAL; 1592 } 1593 1594 if (drm_rotation_90_or_270(rotation)) { 1595 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { 1596 drm_dbg_kms(&dev_priv->drm, 1597 "Y/Yf tiling required for 90/270!\n"); 1598 return -EINVAL; 1599 } 1600 1601 /* 1602 * 90/270 is not allowed with RGB64 16:16:16:16 and 1603 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 1604 */ 1605 switch (fb->format->format) { 1606 case DRM_FORMAT_RGB565: 1607 if (DISPLAY_VER(dev_priv) >= 11) 1608 break; 1609 fallthrough; 1610 case DRM_FORMAT_C8: 1611 case DRM_FORMAT_XRGB16161616F: 1612 case DRM_FORMAT_XBGR16161616F: 1613 case DRM_FORMAT_ARGB16161616F: 1614 case DRM_FORMAT_ABGR16161616F: 1615 case DRM_FORMAT_Y210: 1616 case DRM_FORMAT_Y212: 1617 case DRM_FORMAT_Y216: 1618 case DRM_FORMAT_XVYU12_16161616: 1619 case DRM_FORMAT_XVYU16161616: 1620 drm_dbg_kms(&dev_priv->drm, 1621 "Unsupported pixel format %p4cc for 90/270!\n", 1622 &fb->format->format); 1623 return -EINVAL; 1624 default: 1625 break; 1626 } 1627 } 1628 1629 /* Y-tiling is not supported in IF-ID Interlace mode */ 1630 if (crtc_state->hw.enable && 1631 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 1632 fb->modifier != DRM_FORMAT_MOD_LINEAR && 1633 fb->modifier != I915_FORMAT_MOD_X_TILED) { 1634 drm_dbg_kms(&dev_priv->drm, 1635 "Y/Yf tiling not supported in IF-ID mode\n"); 1636 return -EINVAL; 1637 } 1638 1639 /* Wa_1606054188:tgl,adl-s */ 1640 if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && 1641 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && 1642 intel_format_is_p01x(fb->format->format)) { 1643 drm_dbg_kms(&dev_priv->drm, 1644 "Source color keying not supported with P01x formats\n"); 1645 return -EINVAL; 1646 } 1647 1648 return 0; 1649 } 1650 1651 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 1652 const struct intel_plane_state *plane_state) 1653 { 1654 struct drm_i915_private *dev_priv = 1655 to_i915(plane_state->uapi.plane->dev); 1656 int crtc_x = plane_state->uapi.dst.x1; 1657 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 1658 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); 1659 1660 /* 1661 * Display WA #1175: glk 1662 * Planes other than the cursor may cause FIFO underflow and display 1663 * corruption if starting less than 4 pixels from the right edge of 1664 * the screen. 1665 * Besides the above WA fix the similar problem, where planes other 1666 * than the cursor ending less than 4 pixels from the left edge of the 1667 * screen may cause FIFO underflow and display corruption. 1668 */ 1669 if (DISPLAY_VER(dev_priv) == 10 && 1670 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 1671 drm_dbg_kms(&dev_priv->drm, 1672 "requested plane X %s position %d invalid (valid range %d-%d)\n", 1673 crtc_x + crtc_w < 4 ? "end" : "start", 1674 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 1675 4, pipe_src_w - 4); 1676 return -ERANGE; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 1683 { 1684 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1685 const struct drm_framebuffer *fb = plane_state->hw.fb; 1686 unsigned int rotation = plane_state->hw.rotation; 1687 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1688 1689 /* Display WA #1106 */ 1690 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 1691 src_w & 3 && 1692 (rotation == DRM_MODE_ROTATE_270 || 1693 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 1694 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); 1695 return -EINVAL; 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 1702 const struct drm_framebuffer *fb) 1703 { 1704 /* 1705 * We don't yet know the final source width nor 1706 * whether we can use the HQ scaler mode. Assume 1707 * the best case. 1708 * FIXME need to properly check this later. 1709 */ 1710 if (DISPLAY_VER(dev_priv) >= 10 || 1711 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 1712 return 0x30000 - 1; 1713 else 1714 return 0x20000 - 1; 1715 } 1716 1717 static int intel_plane_min_width(struct intel_plane *plane, 1718 const struct drm_framebuffer *fb, 1719 int color_plane, 1720 unsigned int rotation) 1721 { 1722 if (plane->min_width) 1723 return plane->min_width(fb, color_plane, rotation); 1724 else 1725 return 1; 1726 } 1727 1728 static int intel_plane_max_width(struct intel_plane *plane, 1729 const struct drm_framebuffer *fb, 1730 int color_plane, 1731 unsigned int rotation) 1732 { 1733 if (plane->max_width) 1734 return plane->max_width(fb, color_plane, rotation); 1735 else 1736 return INT_MAX; 1737 } 1738 1739 static int intel_plane_max_height(struct intel_plane *plane, 1740 const struct drm_framebuffer *fb, 1741 int color_plane, 1742 unsigned int rotation) 1743 { 1744 if (plane->max_height) 1745 return plane->max_height(fb, color_plane, rotation); 1746 else 1747 return INT_MAX; 1748 } 1749 1750 static bool 1751 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, 1752 int main_x, int main_y, u32 main_offset, 1753 int ccs_plane) 1754 { 1755 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1756 const struct drm_framebuffer *fb = plane_state->hw.fb; 1757 int aux_x = plane_state->view.color_plane[ccs_plane].x; 1758 int aux_y = plane_state->view.color_plane[ccs_plane].y; 1759 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1760 unsigned int alignment = plane->min_alignment(plane, fb, ccs_plane); 1761 int hsub; 1762 int vsub; 1763 1764 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1765 while (aux_offset >= main_offset && aux_y <= main_y) { 1766 int x, y; 1767 1768 if (aux_x == main_x && aux_y == main_y) 1769 break; 1770 1771 if (aux_offset == 0) 1772 break; 1773 1774 x = aux_x / hsub; 1775 y = aux_y / vsub; 1776 aux_offset = intel_plane_adjust_aligned_offset(&x, &y, 1777 plane_state, 1778 ccs_plane, 1779 aux_offset, 1780 aux_offset - alignment); 1781 aux_x = x * hsub + aux_x % hsub; 1782 aux_y = y * vsub + aux_y % vsub; 1783 } 1784 1785 if (aux_x != main_x || aux_y != main_y) 1786 return false; 1787 1788 plane_state->view.color_plane[ccs_plane].offset = aux_offset; 1789 plane_state->view.color_plane[ccs_plane].x = aux_x; 1790 plane_state->view.color_plane[ccs_plane].y = aux_y; 1791 1792 return true; 1793 } 1794 1795 1796 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, 1797 int *x, int *y, u32 *offset) 1798 { 1799 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1800 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1801 const struct drm_framebuffer *fb = plane_state->hw.fb; 1802 int aux_plane = skl_main_to_aux_plane(fb, 0); 1803 u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; 1804 unsigned int alignment = plane->min_alignment(plane, fb, 0); 1805 int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1806 1807 intel_add_fb_offsets(x, y, plane_state, 0); 1808 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); 1809 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) 1810 return -EINVAL; 1811 1812 /* 1813 * AUX surface offset is specified as the distance from the 1814 * main surface offset, and it must be non-negative. Make 1815 * sure that is what we will get. 1816 */ 1817 if (aux_plane && *offset > aux_offset) 1818 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1819 *offset, 1820 aux_offset & ~(alignment - 1)); 1821 1822 /* 1823 * When using an X-tiled surface, the plane blows up 1824 * if the x offset + width exceed the stride. 1825 * 1826 * TODO: linear and Y-tiled seem fine, Yf untested, 1827 */ 1828 if (fb->modifier == I915_FORMAT_MOD_X_TILED) { 1829 int cpp = fb->format->cpp[0]; 1830 1831 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 1832 if (*offset == 0) { 1833 drm_dbg_kms(&dev_priv->drm, 1834 "Unable to find suitable display surface offset due to X-tiling\n"); 1835 return -EINVAL; 1836 } 1837 1838 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0, 1839 *offset, 1840 *offset - alignment); 1841 } 1842 } 1843 1844 return 0; 1845 } 1846 1847 static int skl_check_main_surface(struct intel_plane_state *plane_state) 1848 { 1849 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1850 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1851 const struct drm_framebuffer *fb = plane_state->hw.fb; 1852 unsigned int rotation = plane_state->hw.rotation; 1853 int x = plane_state->uapi.src.x1 >> 16; 1854 int y = plane_state->uapi.src.y1 >> 16; 1855 int w = drm_rect_width(&plane_state->uapi.src) >> 16; 1856 int h = drm_rect_height(&plane_state->uapi.src) >> 16; 1857 int min_width = intel_plane_min_width(plane, fb, 0, rotation); 1858 int max_width = intel_plane_max_width(plane, fb, 0, rotation); 1859 int max_height = intel_plane_max_height(plane, fb, 0, rotation); 1860 unsigned int alignment = plane->min_alignment(plane, fb, 0); 1861 int aux_plane = skl_main_to_aux_plane(fb, 0); 1862 u32 offset; 1863 int ret; 1864 1865 if (w > max_width || w < min_width || h > max_height || h < 1) { 1866 drm_dbg_kms(&dev_priv->drm, 1867 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", 1868 w, h, min_width, max_width, max_height); 1869 return -EINVAL; 1870 } 1871 1872 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset); 1873 if (ret) 1874 return ret; 1875 1876 /* 1877 * CCS AUX surface doesn't have its own x/y offsets, we must make sure 1878 * they match with the main surface x/y offsets. On DG2 1879 * there's no aux plane on fb so skip this checking. 1880 */ 1881 if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) { 1882 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1883 offset, aux_plane)) { 1884 if (offset == 0) 1885 break; 1886 1887 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 1888 offset, offset - alignment); 1889 } 1890 1891 if (x != plane_state->view.color_plane[aux_plane].x || 1892 y != plane_state->view.color_plane[aux_plane].y) { 1893 drm_dbg_kms(&dev_priv->drm, 1894 "Unable to find suitable display surface offset due to CCS\n"); 1895 return -EINVAL; 1896 } 1897 } 1898 1899 if (DISPLAY_VER(dev_priv) >= 13) 1900 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); 1901 else 1902 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); 1903 1904 plane_state->view.color_plane[0].offset = offset; 1905 plane_state->view.color_plane[0].x = x; 1906 plane_state->view.color_plane[0].y = y; 1907 1908 /* 1909 * Put the final coordinates back so that the src 1910 * coordinate checks will see the right values. 1911 */ 1912 drm_rect_translate_to(&plane_state->uapi.src, 1913 x << 16, y << 16); 1914 1915 return 0; 1916 } 1917 1918 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) 1919 { 1920 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1921 struct drm_i915_private *i915 = to_i915(plane->base.dev); 1922 const struct drm_framebuffer *fb = plane_state->hw.fb; 1923 unsigned int rotation = plane_state->hw.rotation; 1924 int uv_plane = 1; 1925 int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ? 1926 skl_main_to_aux_plane(fb, uv_plane) : 0; 1927 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation); 1928 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation); 1929 int x = plane_state->uapi.src.x1 >> 17; 1930 int y = plane_state->uapi.src.y1 >> 17; 1931 int w = drm_rect_width(&plane_state->uapi.src) >> 17; 1932 int h = drm_rect_height(&plane_state->uapi.src) >> 17; 1933 u32 offset; 1934 1935 /* FIXME not quite sure how/if these apply to the chroma plane */ 1936 if (w > max_width || h > max_height) { 1937 drm_dbg_kms(&i915->drm, 1938 "CbCr source size %dx%d too big (limit %dx%d)\n", 1939 w, h, max_width, max_height); 1940 return -EINVAL; 1941 } 1942 1943 intel_add_fb_offsets(&x, &y, plane_state, uv_plane); 1944 offset = intel_plane_compute_aligned_offset(&x, &y, 1945 plane_state, uv_plane); 1946 1947 if (ccs_plane) { 1948 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; 1949 unsigned int alignment = plane->min_alignment(plane, fb, uv_plane); 1950 1951 if (offset > aux_offset) 1952 offset = intel_plane_adjust_aligned_offset(&x, &y, 1953 plane_state, 1954 uv_plane, 1955 offset, 1956 aux_offset & ~(alignment - 1)); 1957 1958 while (!skl_check_main_ccs_coordinates(plane_state, x, y, 1959 offset, ccs_plane)) { 1960 if (offset == 0) 1961 break; 1962 1963 offset = intel_plane_adjust_aligned_offset(&x, &y, 1964 plane_state, 1965 uv_plane, 1966 offset, offset - alignment); 1967 } 1968 1969 if (x != plane_state->view.color_plane[ccs_plane].x || 1970 y != plane_state->view.color_plane[ccs_plane].y) { 1971 drm_dbg_kms(&i915->drm, 1972 "Unable to find suitable display surface offset due to CCS\n"); 1973 return -EINVAL; 1974 } 1975 } 1976 1977 if (DISPLAY_VER(i915) >= 13) 1978 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); 1979 else 1980 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); 1981 1982 plane_state->view.color_plane[uv_plane].offset = offset; 1983 plane_state->view.color_plane[uv_plane].x = x; 1984 plane_state->view.color_plane[uv_plane].y = y; 1985 1986 return 0; 1987 } 1988 1989 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) 1990 { 1991 const struct drm_framebuffer *fb = plane_state->hw.fb; 1992 int src_x = plane_state->uapi.src.x1 >> 16; 1993 int src_y = plane_state->uapi.src.y1 >> 16; 1994 u32 offset; 1995 int ccs_plane; 1996 1997 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { 1998 int main_hsub, main_vsub; 1999 int hsub, vsub; 2000 int x, y; 2001 2002 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 2003 continue; 2004 2005 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, 2006 skl_ccs_to_main_plane(fb, ccs_plane)); 2007 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 2008 2009 hsub *= main_hsub; 2010 vsub *= main_vsub; 2011 x = src_x / hsub; 2012 y = src_y / vsub; 2013 2014 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); 2015 2016 offset = intel_plane_compute_aligned_offset(&x, &y, 2017 plane_state, 2018 ccs_plane); 2019 2020 plane_state->view.color_plane[ccs_plane].offset = offset; 2021 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub; 2022 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub; 2023 } 2024 2025 return 0; 2026 } 2027 2028 static int skl_check_plane_surface(struct intel_plane_state *plane_state) 2029 { 2030 const struct drm_framebuffer *fb = plane_state->hw.fb; 2031 int ret; 2032 2033 ret = intel_plane_compute_gtt(plane_state); 2034 if (ret) 2035 return ret; 2036 2037 if (!plane_state->uapi.visible) 2038 return 0; 2039 2040 /* 2041 * Handle the AUX surface first since the main surface setup depends on 2042 * it. 2043 */ 2044 if (intel_fb_is_ccs_modifier(fb->modifier)) { 2045 ret = skl_check_ccs_aux_surface(plane_state); 2046 if (ret) 2047 return ret; 2048 } 2049 2050 if (intel_format_info_is_yuv_semiplanar(fb->format, 2051 fb->modifier)) { 2052 ret = skl_check_nv12_aux_surface(plane_state); 2053 if (ret) 2054 return ret; 2055 } 2056 2057 ret = skl_check_main_surface(plane_state); 2058 if (ret) 2059 return ret; 2060 2061 return 0; 2062 } 2063 2064 static bool skl_fb_scalable(const struct drm_framebuffer *fb) 2065 { 2066 if (!fb) 2067 return false; 2068 2069 switch (fb->format->format) { 2070 case DRM_FORMAT_C8: 2071 return false; 2072 case DRM_FORMAT_XRGB16161616F: 2073 case DRM_FORMAT_ARGB16161616F: 2074 case DRM_FORMAT_XBGR16161616F: 2075 case DRM_FORMAT_ABGR16161616F: 2076 return DISPLAY_VER(to_i915(fb->dev)) >= 11; 2077 default: 2078 return true; 2079 } 2080 } 2081 2082 static void check_protection(struct intel_plane_state *plane_state) 2083 { 2084 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2085 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2086 const struct drm_framebuffer *fb = plane_state->hw.fb; 2087 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2088 2089 if (DISPLAY_VER(i915) < 11) 2090 return; 2091 2092 plane_state->decrypt = intel_pxp_key_check(i915->pxp, obj, false) == 0; 2093 plane_state->force_black = i915_gem_object_is_protected(obj) && 2094 !plane_state->decrypt; 2095 } 2096 2097 static int skl_plane_check(struct intel_crtc_state *crtc_state, 2098 struct intel_plane_state *plane_state) 2099 { 2100 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2101 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2102 const struct drm_framebuffer *fb = plane_state->hw.fb; 2103 int min_scale = DRM_PLANE_NO_SCALING; 2104 int max_scale = DRM_PLANE_NO_SCALING; 2105 int ret; 2106 2107 ret = skl_plane_check_fb(crtc_state, plane_state); 2108 if (ret) 2109 return ret; 2110 2111 /* use scaler when colorkey is not required */ 2112 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { 2113 min_scale = 1; 2114 max_scale = skl_plane_max_scale(dev_priv, fb); 2115 } 2116 2117 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 2118 min_scale, max_scale, true); 2119 if (ret) 2120 return ret; 2121 2122 ret = skl_check_plane_surface(plane_state); 2123 if (ret) 2124 return ret; 2125 2126 if (!plane_state->uapi.visible) 2127 return 0; 2128 2129 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 2130 if (ret) 2131 return ret; 2132 2133 ret = intel_plane_check_src_coordinates(plane_state); 2134 if (ret) 2135 return ret; 2136 2137 ret = skl_plane_check_nv12_rotation(plane_state); 2138 if (ret) 2139 return ret; 2140 2141 check_protection(plane_state); 2142 2143 /* HW only has 8 bits pixel precision, disable plane if invisible */ 2144 if (!(plane_state->hw.alpha >> 8)) 2145 plane_state->uapi.visible = false; 2146 2147 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 2148 2149 if (DISPLAY_VER(dev_priv) >= 10) 2150 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 2151 plane_state); 2152 2153 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2154 icl_is_hdr_plane(dev_priv, plane->id)) 2155 /* Enable and use MPEG-2 chroma siting */ 2156 plane_state->cus_ctl = PLANE_CUS_ENABLE | 2157 PLANE_CUS_HPHASE_0 | 2158 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 2159 else 2160 plane_state->cus_ctl = 0; 2161 2162 return 0; 2163 } 2164 2165 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) 2166 { 2167 return pipe - PIPE_A + INTEL_FBC_A; 2168 } 2169 2170 static bool skl_plane_has_fbc(struct drm_i915_private *i915, 2171 enum intel_fbc_id fbc_id, enum plane_id plane_id) 2172 { 2173 if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) 2174 return false; 2175 2176 if (DISPLAY_VER(i915) >= 20) 2177 return icl_is_hdr_plane(i915, plane_id); 2178 else 2179 return plane_id == PLANE_1; 2180 } 2181 2182 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, 2183 enum pipe pipe, enum plane_id plane_id) 2184 { 2185 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); 2186 2187 if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) 2188 return dev_priv->display.fbc[fbc_id]; 2189 else 2190 return NULL; 2191 } 2192 2193 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 2194 enum pipe pipe, enum plane_id plane_id) 2195 { 2196 /* Display WA #0870: skl, bxt */ 2197 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 2198 return false; 2199 2200 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) 2201 return false; 2202 2203 if (plane_id != PLANE_1 && plane_id != PLANE_2) 2204 return false; 2205 2206 return true; 2207 } 2208 2209 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 2210 enum pipe pipe, enum plane_id plane_id, 2211 int *num_formats) 2212 { 2213 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2214 *num_formats = ARRAY_SIZE(skl_planar_formats); 2215 return skl_planar_formats; 2216 } else { 2217 *num_formats = ARRAY_SIZE(skl_plane_formats); 2218 return skl_plane_formats; 2219 } 2220 } 2221 2222 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 2223 enum pipe pipe, enum plane_id plane_id, 2224 int *num_formats) 2225 { 2226 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2227 *num_formats = ARRAY_SIZE(glk_planar_formats); 2228 return glk_planar_formats; 2229 } else { 2230 *num_formats = ARRAY_SIZE(skl_plane_formats); 2231 return skl_plane_formats; 2232 } 2233 } 2234 2235 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 2236 enum pipe pipe, enum plane_id plane_id, 2237 int *num_formats) 2238 { 2239 if (icl_is_hdr_plane(dev_priv, plane_id)) { 2240 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 2241 return icl_hdr_plane_formats; 2242 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { 2243 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 2244 return icl_sdr_y_plane_formats; 2245 } else { 2246 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 2247 return icl_sdr_uv_plane_formats; 2248 } 2249 } 2250 2251 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2252 u32 format, u64 modifier) 2253 { 2254 struct intel_plane *plane = to_intel_plane(_plane); 2255 2256 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2257 return false; 2258 2259 switch (format) { 2260 case DRM_FORMAT_XRGB8888: 2261 case DRM_FORMAT_XBGR8888: 2262 case DRM_FORMAT_ARGB8888: 2263 case DRM_FORMAT_ABGR8888: 2264 if (intel_fb_is_ccs_modifier(modifier)) 2265 return true; 2266 fallthrough; 2267 case DRM_FORMAT_RGB565: 2268 case DRM_FORMAT_XRGB2101010: 2269 case DRM_FORMAT_XBGR2101010: 2270 case DRM_FORMAT_ARGB2101010: 2271 case DRM_FORMAT_ABGR2101010: 2272 case DRM_FORMAT_YUYV: 2273 case DRM_FORMAT_YVYU: 2274 case DRM_FORMAT_UYVY: 2275 case DRM_FORMAT_VYUY: 2276 case DRM_FORMAT_NV12: 2277 case DRM_FORMAT_XYUV8888: 2278 case DRM_FORMAT_P010: 2279 case DRM_FORMAT_P012: 2280 case DRM_FORMAT_P016: 2281 case DRM_FORMAT_XVYU2101010: 2282 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2283 return true; 2284 fallthrough; 2285 case DRM_FORMAT_C8: 2286 case DRM_FORMAT_XBGR16161616F: 2287 case DRM_FORMAT_ABGR16161616F: 2288 case DRM_FORMAT_XRGB16161616F: 2289 case DRM_FORMAT_ARGB16161616F: 2290 case DRM_FORMAT_Y210: 2291 case DRM_FORMAT_Y212: 2292 case DRM_FORMAT_Y216: 2293 case DRM_FORMAT_XVYU12_16161616: 2294 case DRM_FORMAT_XVYU16161616: 2295 if (modifier == DRM_FORMAT_MOD_LINEAR || 2296 modifier == I915_FORMAT_MOD_X_TILED || 2297 modifier == I915_FORMAT_MOD_Y_TILED) 2298 return true; 2299 fallthrough; 2300 default: 2301 return false; 2302 } 2303 } 2304 2305 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 2306 u32 format, u64 modifier) 2307 { 2308 struct intel_plane *plane = to_intel_plane(_plane); 2309 2310 if (!intel_fb_plane_supports_modifier(plane, modifier)) 2311 return false; 2312 2313 switch (format) { 2314 case DRM_FORMAT_XRGB8888: 2315 case DRM_FORMAT_XBGR8888: 2316 case DRM_FORMAT_ARGB8888: 2317 case DRM_FORMAT_ABGR8888: 2318 if (intel_fb_is_ccs_modifier(modifier)) 2319 return true; 2320 fallthrough; 2321 case DRM_FORMAT_YUYV: 2322 case DRM_FORMAT_YVYU: 2323 case DRM_FORMAT_UYVY: 2324 case DRM_FORMAT_VYUY: 2325 case DRM_FORMAT_NV12: 2326 case DRM_FORMAT_XYUV8888: 2327 case DRM_FORMAT_P010: 2328 case DRM_FORMAT_P012: 2329 case DRM_FORMAT_P016: 2330 if (intel_fb_is_mc_ccs_modifier(modifier)) 2331 return true; 2332 fallthrough; 2333 case DRM_FORMAT_RGB565: 2334 case DRM_FORMAT_XRGB2101010: 2335 case DRM_FORMAT_XBGR2101010: 2336 case DRM_FORMAT_ARGB2101010: 2337 case DRM_FORMAT_ABGR2101010: 2338 case DRM_FORMAT_XVYU2101010: 2339 case DRM_FORMAT_C8: 2340 case DRM_FORMAT_XBGR16161616F: 2341 case DRM_FORMAT_ABGR16161616F: 2342 case DRM_FORMAT_XRGB16161616F: 2343 case DRM_FORMAT_ARGB16161616F: 2344 case DRM_FORMAT_Y210: 2345 case DRM_FORMAT_Y212: 2346 case DRM_FORMAT_Y216: 2347 case DRM_FORMAT_XVYU12_16161616: 2348 case DRM_FORMAT_XVYU16161616: 2349 if (!intel_fb_is_ccs_modifier(modifier)) 2350 return true; 2351 fallthrough; 2352 default: 2353 return false; 2354 } 2355 } 2356 2357 static const struct drm_plane_funcs skl_plane_funcs = { 2358 .update_plane = drm_atomic_helper_update_plane, 2359 .disable_plane = drm_atomic_helper_disable_plane, 2360 .destroy = intel_plane_destroy, 2361 .atomic_duplicate_state = intel_plane_duplicate_state, 2362 .atomic_destroy_state = intel_plane_destroy_state, 2363 .format_mod_supported = skl_plane_format_mod_supported, 2364 }; 2365 2366 static const struct drm_plane_funcs gen12_plane_funcs = { 2367 .update_plane = drm_atomic_helper_update_plane, 2368 .disable_plane = drm_atomic_helper_disable_plane, 2369 .destroy = intel_plane_destroy, 2370 .atomic_duplicate_state = intel_plane_duplicate_state, 2371 .atomic_destroy_state = intel_plane_destroy_state, 2372 .format_mod_supported = gen12_plane_format_mod_supported, 2373 }; 2374 2375 static void 2376 skl_plane_enable_flip_done(struct intel_plane *plane) 2377 { 2378 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2379 enum pipe pipe = plane->pipe; 2380 2381 spin_lock_irq(&i915->irq_lock); 2382 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2383 spin_unlock_irq(&i915->irq_lock); 2384 } 2385 2386 static void 2387 skl_plane_disable_flip_done(struct intel_plane *plane) 2388 { 2389 struct drm_i915_private *i915 = to_i915(plane->base.dev); 2390 enum pipe pipe = plane->pipe; 2391 2392 spin_lock_irq(&i915->irq_lock); 2393 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id)); 2394 spin_unlock_irq(&i915->irq_lock); 2395 } 2396 2397 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, 2398 enum pipe pipe, enum plane_id plane_id) 2399 { 2400 /* Wa_22011186057 */ 2401 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2402 return false; 2403 2404 if (DISPLAY_VER(i915) >= 11) 2405 return true; 2406 2407 if (IS_GEMINILAKE(i915)) 2408 return pipe != PIPE_C; 2409 2410 return pipe != PIPE_C && 2411 (plane_id == PLANE_1 || plane_id == PLANE_2); 2412 } 2413 2414 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, 2415 enum plane_id plane_id) 2416 { 2417 if (DISPLAY_VER(i915) < 12) 2418 return false; 2419 2420 /* Wa_14010477008 */ 2421 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || 2422 (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) 2423 return false; 2424 2425 /* Wa_22011186057 */ 2426 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) 2427 return false; 2428 2429 return plane_id < PLANE_6; 2430 } 2431 2432 static u8 skl_get_plane_caps(struct drm_i915_private *i915, 2433 enum pipe pipe, enum plane_id plane_id) 2434 { 2435 u8 caps = INTEL_PLANE_CAP_TILING_X; 2436 2437 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) 2438 caps |= INTEL_PLANE_CAP_TILING_Y; 2439 if (DISPLAY_VER(i915) < 12) 2440 caps |= INTEL_PLANE_CAP_TILING_Yf; 2441 if (HAS_4TILE(i915)) 2442 caps |= INTEL_PLANE_CAP_TILING_4; 2443 2444 if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915)) 2445 return caps; 2446 2447 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { 2448 caps |= INTEL_PLANE_CAP_CCS_RC; 2449 if (DISPLAY_VER(i915) >= 12) 2450 caps |= INTEL_PLANE_CAP_CCS_RC_CC; 2451 } 2452 2453 if (gen12_plane_has_mc_ccs(i915, plane_id)) 2454 caps |= INTEL_PLANE_CAP_CCS_MC; 2455 2456 if (DISPLAY_VER(i915) >= 14 && IS_DGFX(i915)) 2457 caps |= INTEL_PLANE_CAP_NEED64K_PHYS; 2458 2459 return caps; 2460 } 2461 2462 struct intel_plane * 2463 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2464 enum pipe pipe, enum plane_id plane_id) 2465 { 2466 const struct drm_plane_funcs *plane_funcs; 2467 struct intel_plane *plane; 2468 enum drm_plane_type plane_type; 2469 unsigned int supported_rotations; 2470 unsigned int supported_csc; 2471 const u64 *modifiers; 2472 const u32 *formats; 2473 int num_formats; 2474 int ret; 2475 2476 plane = intel_plane_alloc(); 2477 if (IS_ERR(plane)) 2478 return plane; 2479 2480 plane->pipe = pipe; 2481 plane->id = plane_id; 2482 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 2483 2484 intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); 2485 2486 if (DISPLAY_VER(dev_priv) >= 11) { 2487 plane->min_width = icl_plane_min_width; 2488 if (icl_is_hdr_plane(dev_priv, plane_id)) 2489 plane->max_width = icl_hdr_plane_max_width; 2490 else 2491 plane->max_width = icl_sdr_plane_max_width; 2492 plane->max_height = icl_plane_max_height; 2493 plane->min_cdclk = icl_plane_min_cdclk; 2494 } else if (DISPLAY_VER(dev_priv) >= 10) { 2495 plane->max_width = glk_plane_max_width; 2496 plane->max_height = skl_plane_max_height; 2497 plane->min_cdclk = glk_plane_min_cdclk; 2498 } else { 2499 plane->max_width = skl_plane_max_width; 2500 plane->max_height = skl_plane_max_height; 2501 plane->min_cdclk = skl_plane_min_cdclk; 2502 } 2503 2504 if (DISPLAY_VER(dev_priv) >= 13) 2505 plane->max_stride = adl_plane_max_stride; 2506 else 2507 plane->max_stride = skl_plane_max_stride; 2508 2509 if (DISPLAY_VER(dev_priv) >= 12) 2510 plane->min_alignment = tgl_plane_min_alignment; 2511 else 2512 plane->min_alignment = skl_plane_min_alignment; 2513 2514 if (DISPLAY_VER(dev_priv) >= 11) { 2515 plane->update_noarm = icl_plane_update_noarm; 2516 plane->update_arm = icl_plane_update_arm; 2517 plane->disable_arm = icl_plane_disable_arm; 2518 } else { 2519 plane->update_noarm = skl_plane_update_noarm; 2520 plane->update_arm = skl_plane_update_arm; 2521 plane->disable_arm = skl_plane_disable_arm; 2522 } 2523 plane->get_hw_state = skl_plane_get_hw_state; 2524 plane->check_plane = skl_plane_check; 2525 2526 if (plane_id == PLANE_1) { 2527 plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); 2528 plane->async_flip = skl_plane_async_flip; 2529 plane->enable_flip_done = skl_plane_enable_flip_done; 2530 plane->disable_flip_done = skl_plane_disable_flip_done; 2531 } 2532 2533 if (DISPLAY_VER(dev_priv) >= 11) 2534 formats = icl_get_plane_formats(dev_priv, pipe, 2535 plane_id, &num_formats); 2536 else if (DISPLAY_VER(dev_priv) >= 10) 2537 formats = glk_get_plane_formats(dev_priv, pipe, 2538 plane_id, &num_formats); 2539 else 2540 formats = skl_get_plane_formats(dev_priv, pipe, 2541 plane_id, &num_formats); 2542 2543 if (DISPLAY_VER(dev_priv) >= 12) 2544 plane_funcs = &gen12_plane_funcs; 2545 else 2546 plane_funcs = &skl_plane_funcs; 2547 2548 if (plane_id == PLANE_1) 2549 plane_type = DRM_PLANE_TYPE_PRIMARY; 2550 else 2551 plane_type = DRM_PLANE_TYPE_OVERLAY; 2552 2553 modifiers = intel_fb_plane_get_modifiers(dev_priv, 2554 skl_get_plane_caps(dev_priv, pipe, plane_id)); 2555 2556 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 2557 0, plane_funcs, 2558 formats, num_formats, modifiers, 2559 plane_type, 2560 "plane %d%c", plane_id + 1, 2561 pipe_name(pipe)); 2562 2563 kfree(modifiers); 2564 2565 if (ret) 2566 goto fail; 2567 2568 if (DISPLAY_VER(dev_priv) >= 13) 2569 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 2570 else 2571 supported_rotations = 2572 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 2573 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 2574 2575 if (DISPLAY_VER(dev_priv) >= 11) 2576 supported_rotations |= DRM_MODE_REFLECT_X; 2577 2578 drm_plane_create_rotation_property(&plane->base, 2579 DRM_MODE_ROTATE_0, 2580 supported_rotations); 2581 2582 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); 2583 2584 if (DISPLAY_VER(dev_priv) >= 10) 2585 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); 2586 2587 drm_plane_create_color_properties(&plane->base, 2588 supported_csc, 2589 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 2590 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 2591 DRM_COLOR_YCBCR_BT709, 2592 DRM_COLOR_YCBCR_LIMITED_RANGE); 2593 2594 drm_plane_create_alpha_property(&plane->base); 2595 drm_plane_create_blend_mode_property(&plane->base, 2596 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 2597 BIT(DRM_MODE_BLEND_PREMULTI) | 2598 BIT(DRM_MODE_BLEND_COVERAGE)); 2599 2600 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 2601 2602 if (DISPLAY_VER(dev_priv) >= 12) 2603 drm_plane_enable_fb_damage_clips(&plane->base); 2604 2605 if (DISPLAY_VER(dev_priv) >= 11) 2606 drm_plane_create_scaling_filter_property(&plane->base, 2607 BIT(DRM_SCALING_FILTER_DEFAULT) | 2608 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); 2609 2610 intel_plane_helper_add(plane); 2611 2612 return plane; 2613 2614 fail: 2615 intel_plane_free(plane); 2616 2617 return ERR_PTR(ret); 2618 } 2619 2620 void 2621 skl_get_initial_plane_config(struct intel_crtc *crtc, 2622 struct intel_initial_plane_config *plane_config) 2623 { 2624 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 2625 struct drm_device *dev = crtc->base.dev; 2626 struct drm_i915_private *dev_priv = to_i915(dev); 2627 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2628 enum plane_id plane_id = plane->id; 2629 enum pipe pipe; 2630 u32 val, base, offset, stride_mult, tiling, alpha; 2631 int fourcc, pixel_format; 2632 unsigned int aligned_height; 2633 struct drm_framebuffer *fb; 2634 struct intel_framebuffer *intel_fb; 2635 static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4); 2636 2637 if (!plane->get_hw_state(plane, &pipe)) 2638 return; 2639 2640 drm_WARN_ON(dev, pipe != crtc->pipe); 2641 2642 if (crtc_state->joiner_pipes) { 2643 drm_dbg_kms(&dev_priv->drm, 2644 "Unsupported joiner configuration for initial FB\n"); 2645 return; 2646 } 2647 2648 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 2649 if (!intel_fb) { 2650 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 2651 return; 2652 } 2653 2654 fb = &intel_fb->base; 2655 2656 fb->dev = dev; 2657 2658 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); 2659 2660 if (DISPLAY_VER(dev_priv) >= 11) 2661 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; 2662 else 2663 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; 2664 2665 if (DISPLAY_VER(dev_priv) >= 10) { 2666 u32 color_ctl; 2667 2668 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); 2669 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); 2670 } else { 2671 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); 2672 } 2673 2674 fourcc = skl_format_to_fourcc(pixel_format, 2675 val & PLANE_CTL_ORDER_RGBX, alpha); 2676 fb->format = drm_format_info(fourcc); 2677 2678 tiling = val & PLANE_CTL_TILED_MASK; 2679 switch (tiling) { 2680 case PLANE_CTL_TILED_LINEAR: 2681 fb->modifier = DRM_FORMAT_MOD_LINEAR; 2682 break; 2683 case PLANE_CTL_TILED_X: 2684 plane_config->tiling = I915_TILING_X; 2685 fb->modifier = I915_FORMAT_MOD_X_TILED; 2686 break; 2687 case PLANE_CTL_TILED_Y: 2688 plane_config->tiling = I915_TILING_Y; 2689 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2690 if (DISPLAY_VER(dev_priv) >= 14) 2691 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS; 2692 else if (DISPLAY_VER(dev_priv) >= 12) 2693 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; 2694 else 2695 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; 2696 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2697 if (DISPLAY_VER(dev_priv) >= 14) 2698 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS; 2699 else 2700 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; 2701 else 2702 fb->modifier = I915_FORMAT_MOD_Y_TILED; 2703 break; 2704 case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ 2705 if (HAS_4TILE(dev_priv)) { 2706 u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 2707 PLANE_CTL_CLEAR_COLOR_DISABLE; 2708 2709 if ((val & rc_mask) == rc_mask) 2710 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS; 2711 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) 2712 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; 2713 else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2714 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; 2715 else 2716 fb->modifier = I915_FORMAT_MOD_4_TILED; 2717 } else { 2718 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) 2719 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; 2720 else 2721 fb->modifier = I915_FORMAT_MOD_Yf_TILED; 2722 } 2723 break; 2724 default: 2725 MISSING_CASE(tiling); 2726 goto error; 2727 } 2728 2729 if (!dev_priv->display.params.enable_dpt && 2730 intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { 2731 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); 2732 goto error; 2733 } 2734 2735 /* 2736 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr 2737 * while i915 HW rotation is clockwise, thats why this swapping. 2738 */ 2739 switch (val & PLANE_CTL_ROTATE_MASK) { 2740 case PLANE_CTL_ROTATE_0: 2741 plane_config->rotation = DRM_MODE_ROTATE_0; 2742 break; 2743 case PLANE_CTL_ROTATE_90: 2744 plane_config->rotation = DRM_MODE_ROTATE_270; 2745 break; 2746 case PLANE_CTL_ROTATE_180: 2747 plane_config->rotation = DRM_MODE_ROTATE_180; 2748 break; 2749 case PLANE_CTL_ROTATE_270: 2750 plane_config->rotation = DRM_MODE_ROTATE_90; 2751 break; 2752 } 2753 2754 if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) 2755 plane_config->rotation |= DRM_MODE_REFLECT_X; 2756 2757 /* 90/270 degree rotation would require extra work */ 2758 if (drm_rotation_90_or_270(plane_config->rotation)) 2759 goto error; 2760 2761 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; 2762 plane_config->base = base; 2763 2764 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); 2765 drm_WARN_ON(&dev_priv->drm, offset != 0); 2766 2767 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); 2768 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; 2769 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; 2770 2771 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); 2772 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); 2773 2774 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; 2775 2776 aligned_height = intel_fb_align_height(fb, 0, fb->height); 2777 2778 plane_config->size = fb->pitches[0] * aligned_height; 2779 2780 drm_dbg_kms(&dev_priv->drm, 2781 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 2782 crtc->base.name, plane->base.name, fb->width, fb->height, 2783 fb->format->cpp[0] * 8, base, fb->pitches[0], 2784 plane_config->size); 2785 2786 plane_config->fb = intel_fb; 2787 return; 2788 2789 error: 2790 kfree(intel_fb); 2791 } 2792 2793 bool skl_fixup_initial_plane_config(struct intel_crtc *crtc, 2794 const struct intel_initial_plane_config *plane_config) 2795 { 2796 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2797 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2798 const struct intel_plane_state *plane_state = 2799 to_intel_plane_state(plane->base.state); 2800 enum plane_id plane_id = plane->id; 2801 enum pipe pipe = crtc->pipe; 2802 u32 base; 2803 2804 if (!plane_state->uapi.visible) 2805 return false; 2806 2807 base = intel_plane_ggtt_offset(plane_state); 2808 2809 /* 2810 * We may have moved the surface to a different 2811 * part of ggtt, make the plane aware of that. 2812 */ 2813 if (plane_config->base == base) 2814 return false; 2815 2816 intel_de_write(i915, PLANE_SURF(pipe, plane_id), base); 2817 2818 return true; 2819 } 2820