1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-2005 Nate Lawson (SDG)
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/bus.h>
31 #include <sys/cpu.h>
32 #include <sys/kernel.h>
33 #include <sys/malloc.h>
34 #include <sys/module.h>
35 #include <sys/pcpu.h>
36 #include <sys/sysctl.h>
37 #include <sys/systm.h>
38
39 #include <dev/pci/pcivar.h>
40 #include <machine/bus.h>
41 #include <machine/resource.h>
42 #include <sys/rman.h>
43
44 #include "cpufreq_if.h"
45
46 /*
47 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency
48 * transition available on the ICH2M, 3M, and 4M. It is different from
49 * the newer Pentium-M SpeedStep feature. It offers only two levels of
50 * frequency/voltage. Often, the BIOS will select one of the levels via
51 * SMM code during the power-on process (i.e., choose a lower level if the
52 * system is off AC power.)
53 */
54
55 struct ichss_softc {
56 device_t dev;
57 int bm_rid; /* Bus-mastering control (PM2REG). */
58 struct resource *bm_reg;
59 int ctrl_rid; /* Control/status register. */
60 struct resource *ctrl_reg;
61 struct cf_setting sets[2]; /* Only two settings. */
62 };
63
64 /* Supported PCI IDs. */
65 #define PCI_VENDOR_INTEL 0x8086
66 #define PCI_DEV_82801BA 0x244c /* ICH2M */
67 #define PCI_DEV_82801CA 0x248c /* ICH3M */
68 #define PCI_DEV_82801DB 0x24cc /* ICH4M */
69 #define PCI_DEV_82815_MC 0x1130 /* Unsupported/buggy part */
70
71 /* PCI config registers for finding PMBASE and enabling SpeedStep. */
72 #define ICHSS_PMBASE_OFFSET 0x40
73 #define ICHSS_PMCFG_OFFSET 0xa0
74
75 /* Values and masks. */
76 #define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */
77 #define ICHSS_IO_REG 0x1 /* Access register via I/O space. */
78 #define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */
79 #define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */
80 #define ICHSS_BM_DISABLE 0x1
81
82 /* Offsets from PMBASE for various registers. */
83 #define ICHSS_BM_OFFSET 0x20
84 #define ICHSS_CTRL_OFFSET 0x50
85
86 #define ICH_GET_REG(reg) \
87 (bus_space_read_1(rman_get_bustag((reg)), \
88 rman_get_bushandle((reg)), 0))
89 #define ICH_SET_REG(reg, val) \
90 (bus_space_write_1(rman_get_bustag((reg)), \
91 rman_get_bushandle((reg)), 0, (val)))
92
93 static void ichss_identify(driver_t *driver, device_t parent);
94 static int ichss_probe(device_t dev);
95 static int ichss_attach(device_t dev);
96 static int ichss_detach(device_t dev);
97 static int ichss_settings(device_t dev, struct cf_setting *sets,
98 int *count);
99 static int ichss_set(device_t dev, const struct cf_setting *set);
100 static int ichss_get(device_t dev, struct cf_setting *set);
101 static int ichss_type(device_t dev, int *type);
102
103 static device_method_t ichss_methods[] = {
104 /* Device interface */
105 DEVMETHOD(device_identify, ichss_identify),
106 DEVMETHOD(device_probe, ichss_probe),
107 DEVMETHOD(device_attach, ichss_attach),
108 DEVMETHOD(device_detach, ichss_detach),
109
110 /* cpufreq interface */
111 DEVMETHOD(cpufreq_drv_set, ichss_set),
112 DEVMETHOD(cpufreq_drv_get, ichss_get),
113 DEVMETHOD(cpufreq_drv_type, ichss_type),
114 DEVMETHOD(cpufreq_drv_settings, ichss_settings),
115 DEVMETHOD_END
116 };
117
118 static driver_t ichss_driver = {
119 "ichss", ichss_methods, sizeof(struct ichss_softc)
120 };
121
122 DRIVER_MODULE(ichss, cpu, ichss_driver, 0, 0);
123
124 static device_t ich_device;
125
126 #if 0
127 #define DPRINT(x...) printf(x)
128 #else
129 #define DPRINT(x...)
130 #endif
131
132 static void
ichss_identify(driver_t * driver,device_t parent)133 ichss_identify(driver_t *driver, device_t parent)
134 {
135 device_t child;
136 uint32_t pmbase;
137
138 if (resource_disabled("ichss", 0))
139 return;
140
141 /*
142 * It appears that ICH SpeedStep only requires a single CPU to
143 * set the value (since the chipset is shared by all CPUs.)
144 * Thus, we only add a child to cpu 0.
145 */
146 if (device_get_unit(parent) != 0)
147 return;
148
149 /* Avoid duplicates. */
150 if (device_find_child(parent, "ichss", -1))
151 return;
152
153 /*
154 * ICH2/3/4-M I/O Controller Hub is at bus 0, slot 1F, function 0.
155 * E.g. see Section 6.1 "PCI Devices and Functions" and table 6.1 of
156 * Intel(r) 82801BA I/O Controller Hub 2 (ICH2) and Intel(r) 82801BAM
157 * I/O Controller Hub 2 Mobile (ICH2-M).
158 */
159 ich_device = pci_find_bsf(0, 0x1f, 0);
160 if (ich_device == NULL ||
161 pci_get_vendor(ich_device) != PCI_VENDOR_INTEL ||
162 (pci_get_device(ich_device) != PCI_DEV_82801BA &&
163 pci_get_device(ich_device) != PCI_DEV_82801CA &&
164 pci_get_device(ich_device) != PCI_DEV_82801DB))
165 return;
166
167 /*
168 * Certain systems with ICH2 and an Intel 82815_MC host bridge
169 * where the host bridge's revision is < 5 lockup if SpeedStep
170 * is used.
171 */
172 if (pci_get_device(ich_device) == PCI_DEV_82801BA) {
173 device_t hostb;
174
175 hostb = pci_find_bsf(0, 0, 0);
176 if (hostb != NULL &&
177 pci_get_vendor(hostb) == PCI_VENDOR_INTEL &&
178 pci_get_device(hostb) == PCI_DEV_82815_MC &&
179 pci_get_revid(hostb) < 5)
180 return;
181 }
182
183 /* Find the PMBASE register from our PCI config header. */
184 pmbase = pci_read_config(ich_device, ICHSS_PMBASE_OFFSET,
185 sizeof(pmbase));
186 if ((pmbase & ICHSS_IO_REG) == 0) {
187 printf("ichss: invalid PMBASE memory type\n");
188 return;
189 }
190 pmbase &= ICHSS_PMBASE_MASK;
191 if (pmbase == 0) {
192 printf("ichss: invalid zero PMBASE address\n");
193 return;
194 }
195 DPRINT("ichss: PMBASE is %#x\n", pmbase);
196
197 child = BUS_ADD_CHILD(parent, 20, "ichss", 0);
198 if (child == NULL) {
199 device_printf(parent, "add SpeedStep child failed\n");
200 return;
201 }
202
203 /* Add the bus master arbitration and control registers. */
204 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET,
205 1);
206 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET,
207 1);
208 }
209
210 static int
ichss_probe(device_t dev)211 ichss_probe(device_t dev)
212 {
213 device_t est_dev, perf_dev;
214 int error, type;
215
216 /*
217 * If the ACPI perf driver has attached and is not just offering
218 * info, let it manage things. Also, if Enhanced SpeedStep is
219 * available, don't attach.
220 */
221 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
222 if (perf_dev && device_is_attached(perf_dev)) {
223 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
224 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
225 return (ENXIO);
226 }
227 est_dev = device_find_child(device_get_parent(dev), "est", -1);
228 if (est_dev && device_is_attached(est_dev))
229 return (ENXIO);
230
231 device_set_desc(dev, "SpeedStep ICH");
232 return (-1000);
233 }
234
235 static int
ichss_attach(device_t dev)236 ichss_attach(device_t dev)
237 {
238 struct ichss_softc *sc;
239 uint16_t ss_en;
240
241 sc = device_get_softc(dev);
242 sc->dev = dev;
243
244 sc->bm_rid = 0;
245 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid,
246 RF_ACTIVE);
247 if (sc->bm_reg == NULL) {
248 device_printf(dev, "failed to alloc BM arb register\n");
249 return (ENXIO);
250 }
251 sc->ctrl_rid = 1;
252 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
253 &sc->ctrl_rid, RF_ACTIVE);
254 if (sc->ctrl_reg == NULL) {
255 device_printf(dev, "failed to alloc control register\n");
256 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid,
257 sc->bm_reg);
258 return (ENXIO);
259 }
260
261 /* Activate SpeedStep control if not already enabled. */
262 ss_en = pci_read_config(ich_device, ICHSS_PMCFG_OFFSET, sizeof(ss_en));
263 if ((ss_en & ICHSS_ENABLE) == 0) {
264 device_printf(dev, "enabling SpeedStep support\n");
265 pci_write_config(ich_device, ICHSS_PMCFG_OFFSET,
266 ss_en | ICHSS_ENABLE, sizeof(ss_en));
267 }
268
269 /* Setup some defaults for our exported settings. */
270 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
271 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
272 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
273 sc->sets[0].lat = 1000;
274 sc->sets[0].dev = dev;
275 sc->sets[1] = sc->sets[0];
276 cpufreq_register(dev);
277
278 return (0);
279 }
280
281 static int
ichss_detach(device_t dev)282 ichss_detach(device_t dev)
283 {
284 /* TODO: teardown BM and CTRL registers. */
285 return (ENXIO);
286 }
287
288 static int
ichss_settings(device_t dev,struct cf_setting * sets,int * count)289 ichss_settings(device_t dev, struct cf_setting *sets, int *count)
290 {
291 struct ichss_softc *sc;
292 struct cf_setting set;
293 int first, i;
294
295 if (sets == NULL || count == NULL)
296 return (EINVAL);
297 if (*count < 2) {
298 *count = 2;
299 return (E2BIG);
300 }
301 sc = device_get_softc(dev);
302
303 /*
304 * Estimate frequencies for both levels, temporarily switching to
305 * the other one if we haven't calibrated it yet.
306 */
307 ichss_get(dev, &set);
308 for (i = 0; i < 2; i++) {
309 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
310 first = (i == 0) ? 1 : 0;
311 ichss_set(dev, &sc->sets[i]);
312 ichss_set(dev, &sc->sets[first]);
313 }
314 }
315
316 bcopy(sc->sets, sets, sizeof(sc->sets));
317 *count = 2;
318
319 return (0);
320 }
321
322 static int
ichss_set(device_t dev,const struct cf_setting * set)323 ichss_set(device_t dev, const struct cf_setting *set)
324 {
325 struct ichss_softc *sc;
326 uint8_t bmval, new_val, old_val, req_val;
327 uint64_t rate;
328 register_t regs;
329
330 /* Look up appropriate bit value based on frequency. */
331 sc = device_get_softc(dev);
332 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
333 req_val = 0;
334 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
335 req_val = ICHSS_CTRL_BIT;
336 else
337 return (EINVAL);
338 DPRINT("ichss: requested setting %d\n", req_val);
339
340 /* Disable interrupts and get the other register contents. */
341 regs = intr_disable();
342 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT;
343
344 /*
345 * Disable bus master arbitration, write the new value to the control
346 * register, and then re-enable bus master arbitration.
347 */
348 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE;
349 ICH_SET_REG(sc->bm_reg, bmval);
350 ICH_SET_REG(sc->ctrl_reg, old_val | req_val);
351 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE);
352
353 /* Get the new value and re-enable interrupts. */
354 new_val = ICH_GET_REG(sc->ctrl_reg);
355 intr_restore(regs);
356
357 /* Check if the desired state was indeed selected. */
358 if (req_val != (new_val & ICHSS_CTRL_BIT)) {
359 device_printf(sc->dev, "transition to %d failed\n", req_val);
360 return (ENXIO);
361 }
362
363 /* Re-initialize our cycle counter if we don't know this new state. */
364 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) {
365 cpu_est_clockrate(0, &rate);
366 sc->sets[req_val].freq = rate / 1000000;
367 DPRINT("ichss: set calibrated new rate of %d\n",
368 sc->sets[req_val].freq);
369 }
370
371 return (0);
372 }
373
374 static int
ichss_get(device_t dev,struct cf_setting * set)375 ichss_get(device_t dev, struct cf_setting *set)
376 {
377 struct ichss_softc *sc;
378 uint64_t rate;
379 uint8_t state;
380
381 sc = device_get_softc(dev);
382 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT;
383
384 /* If we haven't changed settings yet, estimate the current value. */
385 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
386 cpu_est_clockrate(0, &rate);
387 sc->sets[state].freq = rate / 1000000;
388 DPRINT("ichss: get calibrated new rate of %d\n",
389 sc->sets[state].freq);
390 }
391 *set = sc->sets[state];
392
393 return (0);
394 }
395
396 static int
ichss_type(device_t dev,int * type)397 ichss_type(device_t dev, int *type)
398 {
399
400 if (type == NULL)
401 return (EINVAL);
402
403 *type = CPUFREQ_TYPE_ABSOLUTE;
404 return (0);
405 }
406