1 /*-
2 * ichsmb.c
3 *
4 * Author: Archie Cobbs <archie@freebsd.org>
5 * Copyright (c) 2000 Whistle Communications, Inc.
6 * All rights reserved.
7 *
8 * Subject to the following obligations and disclaimer of warranty, use and
9 * redistribution of this software, in source or object code forms, with or
10 * without modifications are expressly permitted by Whistle Communications;
11 * provided, however, that:
12 * 1. Any and all reproductions of the source or object code must include the
13 * copyright notice above and the following disclaimer of warranties; and
14 * 2. No rights are granted, in any manner or form, to use Whistle
15 * Communications, Inc. trademarks, including the mark "WHISTLE
16 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as
17 * such appears in the above copyright notice or in the software.
18 *
19 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
20 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
21 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
22 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
24 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
25 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
26 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
27 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
28 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
29 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
30 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
35 * OF SUCH DAMAGE.
36 */
37
38 #include <sys/cdefs.h>
39 /*
40 * Support for the SMBus controller logical device which is part of the
41 * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips.
42 *
43 * This driver assumes that the generic SMBus code will ensure that
44 * at most one process at a time calls into the SMBus methods below.
45 */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/errno.h>
51 #include <sys/lock.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/syslog.h>
55 #include <sys/bus.h>
56
57 #include <machine/bus.h>
58 #include <sys/rman.h>
59 #include <machine/resource.h>
60
61 #include <dev/smbus/smbconf.h>
62
63 #include <dev/ichsmb/ichsmb_var.h>
64 #include <dev/ichsmb/ichsmb_reg.h>
65
66 /*
67 * Enable debugging by defining ICHSMB_DEBUG to a non-zero value.
68 */
69 #define ICHSMB_DEBUG 0
70 #if ICHSMB_DEBUG != 0
71 #define DBG(fmt, args...) \
72 do { printf("%s: " fmt, __func__ , ## args); } while (0)
73 #else
74 #define DBG(fmt, args...) do { } while (0)
75 #endif
76
77 /*
78 * Our child device driver name
79 */
80 #define DRIVER_SMBUS "smbus"
81
82 /*
83 * Internal functions
84 */
85 static int ichsmb_wait(sc_p sc);
86
87 /********************************************************************
88 BUS-INDEPENDENT BUS METHODS
89 ********************************************************************/
90
91 /*
92 * Handle probe-time duties that are independent of the bus
93 * our device lives on.
94 */
95 int
ichsmb_probe(device_t dev)96 ichsmb_probe(device_t dev)
97 {
98 return (BUS_PROBE_DEFAULT);
99 }
100
101 /*
102 * Handle attach-time duties that are independent of the bus
103 * our device lives on.
104 */
105 int
ichsmb_attach(device_t dev)106 ichsmb_attach(device_t dev)
107 {
108 const sc_p sc = device_get_softc(dev);
109 int error;
110
111 /* Create mutex */
112 mtx_init(&sc->mutex, device_get_nameunit(dev), "ichsmb", MTX_DEF);
113
114 /* Add child: an instance of the "smbus" device */
115 if ((sc->smb = device_add_child(dev, DRIVER_SMBUS,
116 DEVICE_UNIT_ANY)) == NULL) {
117 device_printf(dev, "no \"%s\" child found\n", DRIVER_SMBUS);
118 error = ENXIO;
119 goto fail;
120 }
121
122 /* Clear interrupt conditions */
123 bus_write_1(sc->io_res, ICH_HST_STA, 0xff);
124
125 /* Set up interrupt handler */
126 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
127 NULL, ichsmb_device_intr, sc, &sc->irq_handle);
128 if (error != 0) {
129 device_printf(dev, "can't setup irq\n");
130 goto fail;
131 }
132
133 /* Attach children when interrupts are available */
134 bus_delayed_attach_children(dev);
135 return (0);
136 fail:
137 mtx_destroy(&sc->mutex);
138 return (error);
139 }
140
141 /********************************************************************
142 SMBUS METHODS
143 ********************************************************************/
144
145 int
ichsmb_callback(device_t dev,int index,void * data)146 ichsmb_callback(device_t dev, int index, void *data)
147 {
148 int smb_error = 0;
149
150 DBG("index=%d how=%d\n", index, data ? *(int *)data : -1);
151 switch (index) {
152 case SMB_REQUEST_BUS:
153 break;
154 case SMB_RELEASE_BUS:
155 break;
156 default:
157 smb_error = SMB_EABORT; /* XXX */
158 break;
159 }
160 DBG("smb_error=%d\n", smb_error);
161 return (smb_error);
162 }
163
164 int
ichsmb_quick(device_t dev,u_char slave,int how)165 ichsmb_quick(device_t dev, u_char slave, int how)
166 {
167 const sc_p sc = device_get_softc(dev);
168 int smb_error;
169
170 DBG("slave=0x%02x how=%d\n", slave, how);
171 KASSERT(sc->ich_cmd == -1,
172 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
173 switch (how) {
174 case SMB_QREAD:
175 case SMB_QWRITE:
176 mtx_lock(&sc->mutex);
177 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_QUICK;
178 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
179 slave | (how == SMB_QREAD ?
180 ICH_XMIT_SLVA_READ : ICH_XMIT_SLVA_WRITE));
181 bus_write_1(sc->io_res, ICH_HST_CNT,
182 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
183 smb_error = ichsmb_wait(sc);
184 mtx_unlock(&sc->mutex);
185 break;
186 default:
187 smb_error = SMB_ENOTSUPP;
188 }
189 DBG("smb_error=%d\n", smb_error);
190 return (smb_error);
191 }
192
193 int
ichsmb_sendb(device_t dev,u_char slave,char byte)194 ichsmb_sendb(device_t dev, u_char slave, char byte)
195 {
196 const sc_p sc = device_get_softc(dev);
197 int smb_error;
198
199 DBG("slave=0x%02x byte=0x%02x\n", slave, (u_char)byte);
200 KASSERT(sc->ich_cmd == -1,
201 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
202 mtx_lock(&sc->mutex);
203 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE;
204 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
205 slave | ICH_XMIT_SLVA_WRITE);
206 bus_write_1(sc->io_res, ICH_HST_CMD, byte);
207 bus_write_1(sc->io_res, ICH_HST_CNT,
208 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
209 smb_error = ichsmb_wait(sc);
210 mtx_unlock(&sc->mutex);
211 DBG("smb_error=%d\n", smb_error);
212 return (smb_error);
213 }
214
215 int
ichsmb_recvb(device_t dev,u_char slave,char * byte)216 ichsmb_recvb(device_t dev, u_char slave, char *byte)
217 {
218 const sc_p sc = device_get_softc(dev);
219 int smb_error;
220
221 DBG("slave=0x%02x\n", slave);
222 KASSERT(sc->ich_cmd == -1,
223 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
224 mtx_lock(&sc->mutex);
225 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE;
226 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
227 slave | ICH_XMIT_SLVA_READ);
228 bus_write_1(sc->io_res, ICH_HST_CNT,
229 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
230 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR)
231 *byte = bus_read_1(sc->io_res, ICH_D0);
232 mtx_unlock(&sc->mutex);
233 DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte);
234 return (smb_error);
235 }
236
237 int
ichsmb_writeb(device_t dev,u_char slave,char cmd,char byte)238 ichsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
239 {
240 const sc_p sc = device_get_softc(dev);
241 int smb_error;
242
243 DBG("slave=0x%02x cmd=0x%02x byte=0x%02x\n",
244 slave, (u_char)cmd, (u_char)byte);
245 KASSERT(sc->ich_cmd == -1,
246 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
247 mtx_lock(&sc->mutex);
248 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA;
249 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
250 slave | ICH_XMIT_SLVA_WRITE);
251 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
252 bus_write_1(sc->io_res, ICH_D0, byte);
253 bus_write_1(sc->io_res, ICH_HST_CNT,
254 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
255 smb_error = ichsmb_wait(sc);
256 mtx_unlock(&sc->mutex);
257 DBG("smb_error=%d\n", smb_error);
258 return (smb_error);
259 }
260
261 int
ichsmb_writew(device_t dev,u_char slave,char cmd,short word)262 ichsmb_writew(device_t dev, u_char slave, char cmd, short word)
263 {
264 const sc_p sc = device_get_softc(dev);
265 int smb_error;
266
267 DBG("slave=0x%02x cmd=0x%02x word=0x%04x\n",
268 slave, (u_char)cmd, (u_int16_t)word);
269 KASSERT(sc->ich_cmd == -1,
270 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
271 mtx_lock(&sc->mutex);
272 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
273 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
274 slave | ICH_XMIT_SLVA_WRITE);
275 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
276 bus_write_1(sc->io_res, ICH_D0, word & 0xff);
277 bus_write_1(sc->io_res, ICH_D1, word >> 8);
278 bus_write_1(sc->io_res, ICH_HST_CNT,
279 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
280 smb_error = ichsmb_wait(sc);
281 mtx_unlock(&sc->mutex);
282 DBG("smb_error=%d\n", smb_error);
283 return (smb_error);
284 }
285
286 int
ichsmb_readb(device_t dev,u_char slave,char cmd,char * byte)287 ichsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
288 {
289 const sc_p sc = device_get_softc(dev);
290 int smb_error;
291
292 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
293 KASSERT(sc->ich_cmd == -1,
294 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
295 mtx_lock(&sc->mutex);
296 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA;
297 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
298 slave | ICH_XMIT_SLVA_READ);
299 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
300 bus_write_1(sc->io_res, ICH_HST_CNT,
301 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
302 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR)
303 *byte = bus_read_1(sc->io_res, ICH_D0);
304 mtx_unlock(&sc->mutex);
305 DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte);
306 return (smb_error);
307 }
308
309 int
ichsmb_readw(device_t dev,u_char slave,char cmd,short * word)310 ichsmb_readw(device_t dev, u_char slave, char cmd, short *word)
311 {
312 const sc_p sc = device_get_softc(dev);
313 int smb_error;
314
315 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
316 KASSERT(sc->ich_cmd == -1,
317 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
318 mtx_lock(&sc->mutex);
319 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
320 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
321 slave | ICH_XMIT_SLVA_READ);
322 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
323 bus_write_1(sc->io_res, ICH_HST_CNT,
324 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
325 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
326 *word = (bus_read_1(sc->io_res,
327 ICH_D0) & 0xff)
328 | (bus_read_1(sc->io_res,
329 ICH_D1) << 8);
330 }
331 mtx_unlock(&sc->mutex);
332 DBG("smb_error=%d word=0x%04x\n", smb_error, (u_int16_t)*word);
333 return (smb_error);
334 }
335
336 int
ichsmb_pcall(device_t dev,u_char slave,char cmd,short sdata,short * rdata)337 ichsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
338 {
339 const sc_p sc = device_get_softc(dev);
340 int smb_error;
341
342 DBG("slave=0x%02x cmd=0x%02x sdata=0x%04x\n",
343 slave, (u_char)cmd, (u_int16_t)sdata);
344 KASSERT(sc->ich_cmd == -1,
345 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
346 mtx_lock(&sc->mutex);
347 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_PROC_CALL;
348 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
349 slave | ICH_XMIT_SLVA_WRITE);
350 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
351 bus_write_1(sc->io_res, ICH_D0, sdata & 0xff);
352 bus_write_1(sc->io_res, ICH_D1, sdata >> 8);
353 bus_write_1(sc->io_res, ICH_HST_CNT,
354 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
355 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
356 *rdata = (bus_read_1(sc->io_res,
357 ICH_D0) & 0xff)
358 | (bus_read_1(sc->io_res,
359 ICH_D1) << 8);
360 }
361 mtx_unlock(&sc->mutex);
362 DBG("smb_error=%d rdata=0x%04x\n", smb_error, (u_int16_t)*rdata);
363 return (smb_error);
364 }
365
366 int
ichsmb_bwrite(device_t dev,u_char slave,char cmd,u_char count,char * buf)367 ichsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
368 {
369 const sc_p sc = device_get_softc(dev);
370 int smb_error;
371
372 DBG("slave=0x%02x cmd=0x%02x count=%d\n", slave, (u_char)cmd, count);
373 #if ICHSMB_DEBUG
374 #define DISP(ch) (((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch))
375 {
376 u_char *p;
377
378 for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) {
379 DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x"
380 " %c%c%c%c%c%c%c%c", (p - (u_char *)buf),
381 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
382 DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]),
383 DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7]));
384 }
385 }
386 #undef DISP
387 #endif
388 KASSERT(sc->ich_cmd == -1,
389 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
390 if (count < 1 || count > 32)
391 return (SMB_EINVAL);
392 bcopy(buf, sc->block_data, count);
393 sc->block_count = count;
394 sc->block_index = 1; /* buf[0] is written here */
395 sc->block_write = true;
396
397 mtx_lock(&sc->mutex);
398 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK;
399 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
400 slave | ICH_XMIT_SLVA_WRITE);
401 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
402 bus_write_1(sc->io_res, ICH_D0, count);
403 bus_write_1(sc->io_res, ICH_BLOCK_DB, buf[0]);
404 bus_write_1(sc->io_res, ICH_HST_CNT,
405 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
406 smb_error = ichsmb_wait(sc);
407 mtx_unlock(&sc->mutex);
408 DBG("smb_error=%d\n", smb_error);
409 return (smb_error);
410 }
411
412 int
ichsmb_bread(device_t dev,u_char slave,char cmd,u_char * count,char * buf)413 ichsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
414 {
415 const sc_p sc = device_get_softc(dev);
416 int smb_error;
417
418 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
419 KASSERT(sc->ich_cmd == -1,
420 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
421 bzero(sc->block_data, sizeof(sc->block_data));
422 sc->block_count = 0;
423 sc->block_index = 0;
424 sc->block_write = false;
425
426 mtx_lock(&sc->mutex);
427 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK;
428 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
429 slave | ICH_XMIT_SLVA_READ);
430 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
431 bus_write_1(sc->io_res, ICH_HST_CNT,
432 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
433 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
434 bcopy(sc->block_data, buf, sc->block_count);
435 *count = sc->block_count;
436 }
437 mtx_unlock(&sc->mutex);
438 DBG("smb_error=%d\n", smb_error);
439 #if ICHSMB_DEBUG
440 #define DISP(ch) (((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch))
441 {
442 u_char *p;
443
444 for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) {
445 DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x"
446 " %c%c%c%c%c%c%c%c", (p - (u_char *)buf),
447 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
448 DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]),
449 DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7]));
450 }
451 }
452 #undef DISP
453 #endif
454 return (smb_error);
455 }
456
457 /********************************************************************
458 OTHER FUNCTIONS
459 ********************************************************************/
460
461 /*
462 * This table describes what interrupts we should ever expect to
463 * see after each ICH command, not including the SMBALERT interrupt.
464 */
465 static const u_int8_t ichsmb_state_irqs[] = {
466 /* quick */
467 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
468 /* byte */
469 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
470 /* byte data */
471 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
472 /* word data */
473 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
474 /* process call */
475 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
476 /* block */
477 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR
478 | ICH_HST_STA_BYTE_DONE_STS),
479 /* i2c read (not used) */
480 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR
481 | ICH_HST_STA_BYTE_DONE_STS)
482 };
483
484 /*
485 * Interrupt handler. This handler is bus-independent. Note that our
486 * interrupt may be shared, so we must handle "false" interrupts.
487 */
488 void
ichsmb_device_intr(void * cookie)489 ichsmb_device_intr(void *cookie)
490 {
491 const sc_p sc = cookie;
492 const device_t dev = sc->dev;
493 const int maxloops = 16;
494 u_int8_t status;
495 u_int8_t ok_bits;
496 int cmd_index;
497 int count;
498
499 mtx_lock(&sc->mutex);
500 for (count = 0; count < maxloops; count++) {
501
502 /* Get and reset status bits */
503 status = bus_read_1(sc->io_res, ICH_HST_STA);
504 #if ICHSMB_DEBUG
505 if ((status & ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY))
506 || count > 0) {
507 DBG("%d stat=0x%02x\n", count, status);
508 }
509 #endif
510 status &= ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY |
511 ICH_HST_STA_SMBALERT_STS);
512 if (status == 0)
513 break;
514
515 /* Check for unexpected interrupt */
516 ok_bits = ICH_HST_STA_SMBALERT_STS;
517
518 if (sc->killed) {
519 sc->killed = 0;
520 ok_bits |= ICH_HST_STA_FAILED;
521 bus_write_1(sc->io_res, ICH_HST_CNT,
522 ICH_HST_CNT_INTREN);
523 }
524
525 if (sc->ich_cmd != -1) {
526 cmd_index = sc->ich_cmd >> 2;
527 KASSERT(cmd_index < sizeof(ichsmb_state_irqs),
528 ("%s: ich_cmd=%d", device_get_nameunit(dev),
529 sc->ich_cmd));
530 ok_bits |= ichsmb_state_irqs[cmd_index];
531 }
532 if ((status & ~ok_bits) != 0) {
533 device_printf(dev, "irq 0x%02x during 0x%02x\n", status,
534 sc->ich_cmd);
535 bus_write_1(sc->io_res,
536 ICH_HST_STA, (status & ~ok_bits));
537 continue;
538 }
539
540 /* Check for killed / aborted command */
541 if (status & ICH_HST_STA_FAILED) {
542 sc->smb_error = SMB_EABORT;
543 goto finished;
544 }
545
546 /* Check for bus error */
547 if (status & ICH_HST_STA_BUS_ERR) {
548 sc->smb_error = SMB_ECOLLI; /* XXX SMB_EBUSERR? */
549 goto finished;
550 }
551
552 /* Check for device error */
553 if (status & ICH_HST_STA_DEV_ERR) {
554 sc->smb_error = SMB_ENOACK; /* or SMB_ETIMEOUT? */
555 goto finished;
556 }
557
558 /* Check for byte completion in block transfer */
559 if (status & ICH_HST_STA_BYTE_DONE_STS) {
560 if (sc->block_write) {
561 if (sc->block_index < sc->block_count) {
562
563 /* Write next byte */
564 bus_write_1(sc->io_res,
565 ICH_BLOCK_DB,
566 sc->block_data[sc->block_index++]);
567 }
568 } else {
569
570 /* First interrupt, get the count also */
571 if (sc->block_index == 0) {
572 sc->block_count = bus_read_1(
573 sc->io_res, ICH_D0);
574 if (sc->block_count < 1 ||
575 sc->block_count > 32) {
576 device_printf(dev, "block read "
577 "wrong length: %d\n",
578 sc->block_count);
579 bus_write_1(sc->io_res,
580 ICH_HST_CNT,
581 ICH_HST_CNT_KILL |
582 ICH_HST_CNT_INTREN);
583 sc->block_count = 0;
584 sc->killed = true;
585 }
586 }
587
588 /* Get next byte, if any */
589 if (sc->block_index < sc->block_count) {
590
591 /* Read next byte */
592 sc->block_data[sc->block_index++] =
593 bus_read_1(sc->io_res,
594 ICH_BLOCK_DB);
595
596 /*
597 * Set "LAST_BYTE" bit before reading
598 * the last byte of block data
599 */
600 if (sc->block_index ==
601 sc->block_count - 1) {
602 bus_write_1(sc->io_res,
603 ICH_HST_CNT,
604 ICH_HST_CNT_LAST_BYTE |
605 ICH_HST_CNT_INTREN |
606 sc->ich_cmd);
607 }
608 }
609 }
610 }
611
612 /* Check command completion */
613 if (status & ICH_HST_STA_INTR) {
614 sc->smb_error = SMB_ENOERR;
615 finished:
616 sc->ich_cmd = -1;
617 bus_write_1(sc->io_res,
618 ICH_HST_STA, status);
619 wakeup(sc);
620 break;
621 }
622
623 /* Clear status bits and try again */
624 bus_write_1(sc->io_res, ICH_HST_STA, status);
625 }
626 mtx_unlock(&sc->mutex);
627
628 /* Too many loops? */
629 if (count == maxloops) {
630 device_printf(dev, "interrupt loop, status=0x%02x\n",
631 bus_read_1(sc->io_res, ICH_HST_STA));
632 }
633 }
634
635 /*
636 * Wait for command completion. Assumes mutex is held.
637 * Returns an SMB_* error code.
638 */
639 static int
ichsmb_wait(sc_p sc)640 ichsmb_wait(sc_p sc)
641 {
642 const device_t dev = sc->dev;
643 int error, smb_error;
644
645 KASSERT(sc->ich_cmd != -1,
646 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
647 mtx_assert(&sc->mutex, MA_OWNED);
648 error = msleep(sc, &sc->mutex, PZERO, "ichsmb", hz / 4);
649 DBG("msleep -> %d\n", error);
650 switch (error) {
651 case 0:
652 smb_error = sc->smb_error;
653 break;
654 case EWOULDBLOCK:
655 device_printf(dev, "device timeout, status=0x%02x\n",
656 bus_read_1(sc->io_res, ICH_HST_STA));
657 sc->ich_cmd = -1;
658 smb_error = SMB_ETIMEOUT;
659 break;
660 default:
661 smb_error = SMB_EABORT;
662 break;
663 }
664 return (smb_error);
665 }
666
667 /*
668 * Release resources associated with device.
669 */
670 void
ichsmb_release_resources(sc_p sc)671 ichsmb_release_resources(sc_p sc)
672 {
673 const device_t dev = sc->dev;
674
675 if (sc->irq_handle != NULL) {
676 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
677 sc->irq_handle = NULL;
678 }
679 if (sc->irq_res != NULL) {
680 bus_release_resource(dev,
681 SYS_RES_IRQ, sc->irq_rid, sc->irq_res);
682 sc->irq_res = NULL;
683 }
684 if (sc->io_res != NULL) {
685 bus_release_resource(dev,
686 SYS_RES_IOPORT, sc->io_rid, sc->io_res);
687 sc->io_res = NULL;
688 }
689 }
690
691 int
ichsmb_detach(device_t dev)692 ichsmb_detach(device_t dev)
693 {
694 const sc_p sc = device_get_softc(dev);
695 int error;
696
697 error = bus_generic_detach(dev);
698 if (error)
699 return (error);
700 ichsmb_release_resources(sc);
701 mtx_destroy(&sc->mutex);
702
703 return 0;
704 }
705
706 DRIVER_MODULE(smbus, ichsmb, smbus_driver, 0, 0);
707