1 /*-
2 * ichsmb.c
3 *
4 * Author: Archie Cobbs <archie@freebsd.org>
5 * Copyright (c) 2000 Whistle Communications, Inc.
6 * All rights reserved.
7 *
8 * Subject to the following obligations and disclaimer of warranty, use and
9 * redistribution of this software, in source or object code forms, with or
10 * without modifications are expressly permitted by Whistle Communications;
11 * provided, however, that:
12 * 1. Any and all reproductions of the source or object code must include the
13 * copyright notice above and the following disclaimer of warranties; and
14 * 2. No rights are granted, in any manner or form, to use Whistle
15 * Communications, Inc. trademarks, including the mark "WHISTLE
16 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as
17 * such appears in the above copyright notice or in the software.
18 *
19 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
20 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
21 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
22 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
24 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
25 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
26 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
27 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
28 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
29 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
30 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
35 * OF SUCH DAMAGE.
36 */
37
38 #include <sys/cdefs.h>
39 /*
40 * Support for the SMBus controller logical device which is part of the
41 * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips.
42 *
43 * This driver assumes that the generic SMBus code will ensure that
44 * at most one process at a time calls into the SMBus methods below.
45 */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/errno.h>
51 #include <sys/lock.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/syslog.h>
55 #include <sys/bus.h>
56
57 #include <machine/bus.h>
58 #include <sys/rman.h>
59 #include <machine/resource.h>
60
61 #include <dev/smbus/smbconf.h>
62
63 #include <dev/ichsmb/ichsmb_var.h>
64 #include <dev/ichsmb/ichsmb_reg.h>
65
66 /*
67 * Enable debugging by defining ICHSMB_DEBUG to a non-zero value.
68 */
69 #define ICHSMB_DEBUG 0
70 #if ICHSMB_DEBUG != 0
71 #define DBG(fmt, args...) \
72 do { printf("%s: " fmt, __func__ , ## args); } while (0)
73 #else
74 #define DBG(fmt, args...) do { } while (0)
75 #endif
76
77 /*
78 * Our child device driver name
79 */
80 #define DRIVER_SMBUS "smbus"
81
82 /*
83 * Internal functions
84 */
85 static int ichsmb_wait(sc_p sc);
86
87 /********************************************************************
88 BUS-INDEPENDENT BUS METHODS
89 ********************************************************************/
90
91 /*
92 * Handle probe-time duties that are independent of the bus
93 * our device lives on.
94 */
95 int
ichsmb_probe(device_t dev)96 ichsmb_probe(device_t dev)
97 {
98 return (BUS_PROBE_DEFAULT);
99 }
100
101 /*
102 * Handle attach-time duties that are independent of the bus
103 * our device lives on.
104 */
105 int
ichsmb_attach(device_t dev)106 ichsmb_attach(device_t dev)
107 {
108 const sc_p sc = device_get_softc(dev);
109 int error;
110
111 /* Create mutex */
112 mtx_init(&sc->mutex, device_get_nameunit(dev), "ichsmb", MTX_DEF);
113
114 /* Add child: an instance of the "smbus" device */
115 if ((sc->smb = device_add_child(dev, DRIVER_SMBUS,
116 DEVICE_UNIT_ANY)) == NULL) {
117 device_printf(dev, "no \"%s\" child found\n", DRIVER_SMBUS);
118 error = ENXIO;
119 goto fail;
120 }
121
122 /* Clear interrupt conditions */
123 bus_write_1(sc->io_res, ICH_HST_STA, 0xff);
124
125 /* Set up interrupt handler */
126 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
127 NULL, ichsmb_device_intr, sc, &sc->irq_handle);
128 if (error != 0) {
129 device_printf(dev, "can't setup irq\n");
130 goto fail;
131 }
132
133 /* Attach children when interrupts are available */
134 bus_delayed_attach_children(dev);
135 return (0);
136 fail:
137 mtx_destroy(&sc->mutex);
138 return (error);
139 }
140
141 /********************************************************************
142 SMBUS METHODS
143 ********************************************************************/
144
145 int
ichsmb_callback(device_t dev,int index,void * data)146 ichsmb_callback(device_t dev, int index, void *data)
147 {
148 int smb_error = 0;
149
150 DBG("index=%d how=%d\n", index, data ? *(int *)data : -1);
151 switch (index) {
152 case SMB_REQUEST_BUS:
153 break;
154 case SMB_RELEASE_BUS:
155 break;
156 default:
157 smb_error = SMB_EABORT; /* XXX */
158 break;
159 }
160 DBG("smb_error=%d\n", smb_error);
161 return (smb_error);
162 }
163
164 int
ichsmb_quick(device_t dev,u_char slave,int how)165 ichsmb_quick(device_t dev, u_char slave, int how)
166 {
167 const sc_p sc = device_get_softc(dev);
168 int smb_error;
169
170 DBG("slave=0x%02x how=%d\n", slave, how);
171 KASSERT(sc->ich_cmd == -1,
172 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
173 switch (how) {
174 case SMB_QREAD:
175 case SMB_QWRITE:
176 mtx_lock(&sc->mutex);
177 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_QUICK;
178 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
179 slave | (how == SMB_QREAD ?
180 ICH_XMIT_SLVA_READ : ICH_XMIT_SLVA_WRITE));
181 bus_write_1(sc->io_res, ICH_HST_CNT,
182 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
183 smb_error = ichsmb_wait(sc);
184 mtx_unlock(&sc->mutex);
185 break;
186 default:
187 smb_error = SMB_ENOTSUPP;
188 }
189 DBG("smb_error=%d\n", smb_error);
190 return (smb_error);
191 }
192
193 int
ichsmb_sendb(device_t dev,u_char slave,char byte)194 ichsmb_sendb(device_t dev, u_char slave, char byte)
195 {
196 const sc_p sc = device_get_softc(dev);
197 int smb_error;
198
199 DBG("slave=0x%02x byte=0x%02x\n", slave, (u_char)byte);
200 KASSERT(sc->ich_cmd == -1,
201 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
202 mtx_lock(&sc->mutex);
203 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE;
204 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
205 slave | ICH_XMIT_SLVA_WRITE);
206 bus_write_1(sc->io_res, ICH_HST_CMD, byte);
207 bus_write_1(sc->io_res, ICH_HST_CNT,
208 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
209 smb_error = ichsmb_wait(sc);
210 mtx_unlock(&sc->mutex);
211 DBG("smb_error=%d\n", smb_error);
212 return (smb_error);
213 }
214
215 int
ichsmb_recvb(device_t dev,u_char slave,char * byte)216 ichsmb_recvb(device_t dev, u_char slave, char *byte)
217 {
218 const sc_p sc = device_get_softc(dev);
219 int smb_error;
220
221 DBG("slave=0x%02x\n", slave);
222 KASSERT(sc->ich_cmd == -1,
223 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
224 mtx_lock(&sc->mutex);
225 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE;
226 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
227 slave | ICH_XMIT_SLVA_READ);
228 bus_write_1(sc->io_res, ICH_HST_CNT,
229 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
230 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR)
231 *byte = bus_read_1(sc->io_res, ICH_D0);
232 mtx_unlock(&sc->mutex);
233 DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte);
234 return (smb_error);
235 }
236
237 int
ichsmb_writeb(device_t dev,u_char slave,char cmd,char byte)238 ichsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
239 {
240 const sc_p sc = device_get_softc(dev);
241 int smb_error;
242
243 DBG("slave=0x%02x cmd=0x%02x byte=0x%02x\n",
244 slave, (u_char)cmd, (u_char)byte);
245 KASSERT(sc->ich_cmd == -1,
246 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
247 mtx_lock(&sc->mutex);
248 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA;
249 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
250 slave | ICH_XMIT_SLVA_WRITE);
251 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
252 bus_write_1(sc->io_res, ICH_D0, byte);
253 bus_write_1(sc->io_res, ICH_HST_CNT,
254 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
255 smb_error = ichsmb_wait(sc);
256 mtx_unlock(&sc->mutex);
257 DBG("smb_error=%d\n", smb_error);
258 return (smb_error);
259 }
260
261 int
ichsmb_writew(device_t dev,u_char slave,char cmd,short word)262 ichsmb_writew(device_t dev, u_char slave, char cmd, short word)
263 {
264 const sc_p sc = device_get_softc(dev);
265 int smb_error;
266
267 DBG("slave=0x%02x cmd=0x%02x word=0x%04x\n",
268 slave, (u_char)cmd, (u_int16_t)word);
269 KASSERT(sc->ich_cmd == -1,
270 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
271 mtx_lock(&sc->mutex);
272 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
273 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
274 slave | ICH_XMIT_SLVA_WRITE);
275 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
276 bus_write_1(sc->io_res, ICH_D0, word & 0xff);
277 bus_write_1(sc->io_res, ICH_D1, word >> 8);
278 bus_write_1(sc->io_res, ICH_HST_CNT,
279 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
280 smb_error = ichsmb_wait(sc);
281 mtx_unlock(&sc->mutex);
282 DBG("smb_error=%d\n", smb_error);
283 return (smb_error);
284 }
285
286 int
ichsmb_readb(device_t dev,u_char slave,char cmd,char * byte)287 ichsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
288 {
289 const sc_p sc = device_get_softc(dev);
290 int smb_error;
291
292 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
293 KASSERT(sc->ich_cmd == -1,
294 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
295 mtx_lock(&sc->mutex);
296 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA;
297 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
298 slave | ICH_XMIT_SLVA_READ);
299 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
300 bus_write_1(sc->io_res, ICH_HST_CNT,
301 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
302 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR)
303 *byte = bus_read_1(sc->io_res, ICH_D0);
304 mtx_unlock(&sc->mutex);
305 DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte);
306 return (smb_error);
307 }
308
309 int
ichsmb_readw(device_t dev,u_char slave,char cmd,short * word)310 ichsmb_readw(device_t dev, u_char slave, char cmd, short *word)
311 {
312 const sc_p sc = device_get_softc(dev);
313 int smb_error;
314
315 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
316 KASSERT(sc->ich_cmd == -1,
317 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
318 mtx_lock(&sc->mutex);
319 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
320 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
321 slave | ICH_XMIT_SLVA_READ);
322 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
323 bus_write_1(sc->io_res, ICH_HST_CNT,
324 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
325 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
326 *word = (bus_read_1(sc->io_res,
327 ICH_D0) & 0xff)
328 | (bus_read_1(sc->io_res,
329 ICH_D1) << 8);
330 }
331 mtx_unlock(&sc->mutex);
332 DBG("smb_error=%d word=0x%04x\n", smb_error, (u_int16_t)*word);
333 return (smb_error);
334 }
335
336 int
ichsmb_pcall(device_t dev,u_char slave,char cmd,short sdata,short * rdata)337 ichsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
338 {
339 const sc_p sc = device_get_softc(dev);
340 int smb_error;
341
342 DBG("slave=0x%02x cmd=0x%02x sdata=0x%04x\n",
343 slave, (u_char)cmd, (u_int16_t)sdata);
344 KASSERT(sc->ich_cmd == -1,
345 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
346 mtx_lock(&sc->mutex);
347 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_PROC_CALL;
348 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
349 slave | ICH_XMIT_SLVA_WRITE);
350 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
351 bus_write_1(sc->io_res, ICH_D0, sdata & 0xff);
352 bus_write_1(sc->io_res, ICH_D1, sdata >> 8);
353 bus_write_1(sc->io_res, ICH_HST_CNT,
354 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
355 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
356 *rdata = (bus_read_1(sc->io_res,
357 ICH_D0) & 0xff)
358 | (bus_read_1(sc->io_res,
359 ICH_D1) << 8);
360 }
361 mtx_unlock(&sc->mutex);
362 DBG("smb_error=%d rdata=0x%04x\n", smb_error, (u_int16_t)*rdata);
363 return (smb_error);
364 }
365
366 int
ichsmb_bwrite(device_t dev,u_char slave,char cmd,u_char count,char * buf)367 ichsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
368 {
369 const sc_p sc = device_get_softc(dev);
370 int smb_error;
371
372 DBG("slave=0x%02x cmd=0x%02x count=%d\n", slave, (u_char)cmd, count);
373 #if ICHSMB_DEBUG
374 #define DISP(ch) (((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch))
375 {
376 u_char *p;
377
378 for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) {
379 DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x"
380 " %c%c%c%c%c%c%c%c", (p - (u_char *)buf),
381 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
382 DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]),
383 DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7]));
384 }
385 }
386 #undef DISP
387 #endif
388 KASSERT(sc->ich_cmd == -1,
389 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
390 if (count < 1 || count > 32)
391 return (SMB_EINVAL);
392 bcopy(buf, sc->block_data, count);
393 sc->block_count = count;
394 sc->block_index = 1; /* buf[0] is written here */
395 sc->block_write = true;
396
397 mtx_lock(&sc->mutex);
398 /*
399 * We don't expect the block buffer to be enabled. However, BIOS code
400 * might enable it and doesn't restore it at any time, so we should
401 * ensure it's disabled before sending an SMBus command.
402 */
403 if (sc->features & ICHSMB_FEATURE_BLOCK_BUFFER) {
404 bus_write_1(sc->io_res, ICH_AUX_CNT,
405 bus_read_1(sc->io_res, ICH_AUX_CNT) & ~ICH_AUX_CNT_E32B);
406 }
407 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK;
408 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
409 slave | ICH_XMIT_SLVA_WRITE);
410 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
411 bus_write_1(sc->io_res, ICH_D0, count);
412 bus_write_1(sc->io_res, ICH_BLOCK_DB, buf[0]);
413 bus_write_1(sc->io_res, ICH_HST_CNT,
414 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
415 smb_error = ichsmb_wait(sc);
416 mtx_unlock(&sc->mutex);
417 DBG("smb_error=%d\n", smb_error);
418 return (smb_error);
419 }
420
421 int
ichsmb_bread(device_t dev,u_char slave,char cmd,u_char * count,char * buf)422 ichsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
423 {
424 const sc_p sc = device_get_softc(dev);
425 int smb_error;
426
427 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
428 KASSERT(sc->ich_cmd == -1,
429 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
430 bzero(sc->block_data, sizeof(sc->block_data));
431 sc->block_count = 0;
432 sc->block_index = 0;
433 sc->block_write = false;
434
435 mtx_lock(&sc->mutex);
436 /*
437 * We don't expect the block buffer to be enabled. However, BIOS code
438 * might enable it and doesn't restore it at any time, so we should
439 * ensure it's disabled before sending an SMBus command.
440 */
441 if (sc->features & ICHSMB_FEATURE_BLOCK_BUFFER) {
442 bus_write_1(sc->io_res, ICH_AUX_CNT,
443 bus_read_1(sc->io_res, ICH_AUX_CNT) & ~ICH_AUX_CNT_E32B);
444 }
445 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK;
446 bus_write_1(sc->io_res, ICH_XMIT_SLVA,
447 slave | ICH_XMIT_SLVA_READ);
448 bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
449 bus_write_1(sc->io_res, ICH_HST_CNT,
450 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
451 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
452 bcopy(sc->block_data, buf, sc->block_count);
453 *count = sc->block_count;
454 }
455 mtx_unlock(&sc->mutex);
456 DBG("smb_error=%d\n", smb_error);
457 #if ICHSMB_DEBUG
458 #define DISP(ch) (((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch))
459 {
460 u_char *p;
461
462 for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) {
463 DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x"
464 " %c%c%c%c%c%c%c%c", (p - (u_char *)buf),
465 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
466 DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]),
467 DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7]));
468 }
469 }
470 #undef DISP
471 #endif
472 return (smb_error);
473 }
474
475 /********************************************************************
476 OTHER FUNCTIONS
477 ********************************************************************/
478
479 /*
480 * This table describes what interrupts we should ever expect to
481 * see after each ICH command, not including the SMBALERT interrupt.
482 */
483 static const u_int8_t ichsmb_state_irqs[] = {
484 /* quick */
485 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
486 /* byte */
487 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
488 /* byte data */
489 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
490 /* word data */
491 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
492 /* process call */
493 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
494 /* block */
495 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR
496 | ICH_HST_STA_BYTE_DONE_STS),
497 /* i2c read (not used) */
498 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR
499 | ICH_HST_STA_BYTE_DONE_STS)
500 };
501
502 /*
503 * Interrupt handler. This handler is bus-independent. Note that our
504 * interrupt may be shared, so we must handle "false" interrupts.
505 */
506 void
ichsmb_device_intr(void * cookie)507 ichsmb_device_intr(void *cookie)
508 {
509 const sc_p sc = cookie;
510 const device_t dev = sc->dev;
511 const int maxloops = 16;
512 u_int8_t status;
513 u_int8_t ok_bits;
514 int cmd_index;
515 int count;
516
517 mtx_lock(&sc->mutex);
518 for (count = 0; count < maxloops; count++) {
519
520 /* Get and reset status bits */
521 status = bus_read_1(sc->io_res, ICH_HST_STA);
522 #if ICHSMB_DEBUG
523 if ((status & ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY))
524 || count > 0) {
525 DBG("%d stat=0x%02x\n", count, status);
526 }
527 #endif
528 status &= ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY |
529 ICH_HST_STA_SMBALERT_STS);
530 if (status == 0)
531 break;
532
533 /* Check for unexpected interrupt */
534 ok_bits = ICH_HST_STA_SMBALERT_STS;
535
536 if (sc->killed) {
537 sc->killed = 0;
538 ok_bits |= ICH_HST_STA_FAILED;
539 bus_write_1(sc->io_res, ICH_HST_CNT,
540 ICH_HST_CNT_INTREN);
541 }
542
543 if (sc->ich_cmd != -1) {
544 cmd_index = sc->ich_cmd >> 2;
545 KASSERT(cmd_index < sizeof(ichsmb_state_irqs),
546 ("%s: ich_cmd=%d", device_get_nameunit(dev),
547 sc->ich_cmd));
548 ok_bits |= ichsmb_state_irqs[cmd_index];
549 }
550 if ((status & ~ok_bits) != 0) {
551 device_printf(dev, "irq 0x%02x during 0x%02x\n", status,
552 sc->ich_cmd);
553 bus_write_1(sc->io_res,
554 ICH_HST_STA, (status & ~ok_bits));
555 continue;
556 }
557
558 /* Check for killed / aborted command */
559 if (status & ICH_HST_STA_FAILED) {
560 sc->smb_error = SMB_EABORT;
561 goto finished;
562 }
563
564 /* Check for bus error */
565 if (status & ICH_HST_STA_BUS_ERR) {
566 sc->smb_error = SMB_ECOLLI; /* XXX SMB_EBUSERR? */
567 goto finished;
568 }
569
570 /* Check for device error */
571 if (status & ICH_HST_STA_DEV_ERR) {
572 sc->smb_error = SMB_ENOACK; /* or SMB_ETIMEOUT? */
573 goto finished;
574 }
575
576 /* Check for byte completion in block transfer */
577 if (status & ICH_HST_STA_BYTE_DONE_STS) {
578 if (sc->block_write) {
579 if (sc->block_index < sc->block_count) {
580
581 /* Write next byte */
582 bus_write_1(sc->io_res,
583 ICH_BLOCK_DB,
584 sc->block_data[sc->block_index++]);
585 }
586 } else {
587
588 /* First interrupt, get the count also */
589 if (sc->block_index == 0) {
590 sc->block_count = bus_read_1(
591 sc->io_res, ICH_D0);
592 if (sc->block_count < 1 ||
593 sc->block_count > 32) {
594 device_printf(dev, "block read "
595 "wrong length: %d\n",
596 sc->block_count);
597 bus_write_1(sc->io_res,
598 ICH_HST_CNT,
599 ICH_HST_CNT_KILL |
600 ICH_HST_CNT_INTREN);
601 sc->block_count = 0;
602 sc->killed = true;
603 }
604 }
605
606 /* Get next byte, if any */
607 if (sc->block_index < sc->block_count) {
608
609 /* Read next byte */
610 sc->block_data[sc->block_index++] =
611 bus_read_1(sc->io_res,
612 ICH_BLOCK_DB);
613
614 /*
615 * Set "LAST_BYTE" bit before reading
616 * the last byte of block data
617 */
618 if (sc->block_index ==
619 sc->block_count - 1) {
620 bus_write_1(sc->io_res,
621 ICH_HST_CNT,
622 ICH_HST_CNT_LAST_BYTE |
623 ICH_HST_CNT_INTREN |
624 sc->ich_cmd);
625 }
626 }
627 }
628 }
629
630 /* Check command completion */
631 if (status & ICH_HST_STA_INTR) {
632 sc->smb_error = SMB_ENOERR;
633 finished:
634 sc->ich_cmd = -1;
635 bus_write_1(sc->io_res,
636 ICH_HST_STA, status);
637 wakeup(sc);
638 break;
639 }
640
641 /* Clear status bits and try again */
642 bus_write_1(sc->io_res, ICH_HST_STA, status);
643 }
644 mtx_unlock(&sc->mutex);
645
646 /* Too many loops? */
647 if (count == maxloops) {
648 device_printf(dev, "interrupt loop, status=0x%02x\n",
649 bus_read_1(sc->io_res, ICH_HST_STA));
650 }
651 }
652
653 /*
654 * Wait for command completion. Assumes mutex is held.
655 * Returns an SMB_* error code.
656 */
657 static int
ichsmb_wait(sc_p sc)658 ichsmb_wait(sc_p sc)
659 {
660 const device_t dev = sc->dev;
661 int error, smb_error;
662
663 KASSERT(sc->ich_cmd != -1,
664 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
665 mtx_assert(&sc->mutex, MA_OWNED);
666 error = msleep(sc, &sc->mutex, PZERO, "ichsmb", hz / 4);
667 DBG("msleep -> %d\n", error);
668 switch (error) {
669 case 0:
670 smb_error = sc->smb_error;
671 break;
672 case EWOULDBLOCK:
673 device_printf(dev, "device timeout, status=0x%02x\n",
674 bus_read_1(sc->io_res, ICH_HST_STA));
675 sc->ich_cmd = -1;
676 smb_error = SMB_ETIMEOUT;
677 break;
678 default:
679 smb_error = SMB_EABORT;
680 break;
681 }
682 return (smb_error);
683 }
684
685 /*
686 * Release resources associated with device.
687 */
688 void
ichsmb_release_resources(sc_p sc)689 ichsmb_release_resources(sc_p sc)
690 {
691 const device_t dev = sc->dev;
692
693 if (sc->irq_handle != NULL) {
694 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
695 sc->irq_handle = NULL;
696 }
697 if (sc->irq_res != NULL) {
698 bus_release_resource(dev,
699 SYS_RES_IRQ, sc->irq_rid, sc->irq_res);
700 sc->irq_res = NULL;
701 }
702 if (sc->io_res != NULL) {
703 bus_release_resource(dev,
704 SYS_RES_IOPORT, sc->io_rid, sc->io_res);
705 sc->io_res = NULL;
706 }
707 }
708
709 int
ichsmb_detach(device_t dev)710 ichsmb_detach(device_t dev)
711 {
712 const sc_p sc = device_get_softc(dev);
713 int error;
714
715 error = bus_generic_detach(dev);
716 if (error)
717 return (error);
718 ichsmb_release_resources(sc);
719 mtx_destroy(&sc->mutex);
720
721 return 0;
722 }
723
724 int
ichsmb_shutdown(device_t dev)725 ichsmb_shutdown(device_t dev)
726 {
727 const sc_p sc = device_get_softc(dev);
728
729 /* Disable interrupts */
730 bus_write_1(sc->io_res, ICH_HST_CNT, 0);
731
732 return (0);
733 }
734
735 DRIVER_MODULE(smbus, ichsmb, smbus_driver, 0, 0);
736