1 /* 2 * Copyright © 2014-2018 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #ifndef _V3D_DRM_H_ 25 #define _V3D_DRM_H_ 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 #define DRM_V3D_SUBMIT_CL 0x00 34 #define DRM_V3D_WAIT_BO 0x01 35 #define DRM_V3D_CREATE_BO 0x02 36 #define DRM_V3D_MMAP_BO 0x03 37 #define DRM_V3D_GET_PARAM 0x04 38 #define DRM_V3D_GET_BO_OFFSET 0x05 39 #define DRM_V3D_SUBMIT_TFU 0x06 40 #define DRM_V3D_SUBMIT_CSD 0x07 41 #define DRM_V3D_PERFMON_CREATE 0x08 42 #define DRM_V3D_PERFMON_DESTROY 0x09 43 #define DRM_V3D_PERFMON_GET_VALUES 0x0a 44 #define DRM_V3D_SUBMIT_CPU 0x0b 45 #define DRM_V3D_PERFMON_GET_COUNTER 0x0c 46 #define DRM_V3D_PERFMON_SET_GLOBAL 0x0d 47 48 #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) 49 #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) 50 #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo) 51 #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) 52 #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) 53 #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) 54 #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) 55 #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd) 56 #define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \ 57 struct drm_v3d_perfmon_create) 58 #define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \ 59 struct drm_v3d_perfmon_destroy) 60 #define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \ 61 struct drm_v3d_perfmon_get_values) 62 #define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu) 63 #define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \ 64 struct drm_v3d_perfmon_get_counter) 65 #define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_PERFMON_SET_GLOBAL, \ 66 struct drm_v3d_perfmon_set_global) 67 68 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01 69 #define DRM_V3D_SUBMIT_EXTENSION 0x02 70 71 /* struct drm_v3d_extension - ioctl extensions 72 * 73 * Linked-list of generic extensions where the id identify which struct is 74 * pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify 75 * the extension type. 76 */ 77 struct drm_v3d_extension { 78 __u64 next; 79 __u32 id; 80 #define DRM_V3D_EXT_ID_MULTI_SYNC 0x01 81 #define DRM_V3D_EXT_ID_CPU_INDIRECT_CSD 0x02 82 #define DRM_V3D_EXT_ID_CPU_TIMESTAMP_QUERY 0x03 83 #define DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY 0x04 84 #define DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY 0x05 85 #define DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY 0x06 86 #define DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY 0x07 87 __u32 flags; /* mbz */ 88 }; 89 90 /* struct drm_v3d_sem - wait/signal semaphore 91 * 92 * If binary semaphore, it only takes syncobj handle and ignores flags and 93 * point fields. Point is defined for timeline syncobj feature. 94 */ 95 struct drm_v3d_sem { 96 __u32 handle; /* syncobj */ 97 /* rsv below, for future uses */ 98 __u32 flags; 99 __u64 point; /* for timeline sem support */ 100 __u64 mbz[2]; /* must be zero, rsv */ 101 }; 102 103 /* Enum for each of the V3D queues. */ 104 enum v3d_queue { 105 V3D_BIN, 106 V3D_RENDER, 107 V3D_TFU, 108 V3D_CSD, 109 V3D_CACHE_CLEAN, 110 V3D_CPU, 111 }; 112 113 /** 114 * struct drm_v3d_multi_sync - ioctl extension to add support multiples 115 * syncobjs for commands submission. 116 * 117 * When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to 118 * this extension to define wait and signal dependencies, instead of single 119 * in/out sync entries on submitting commands. The field flags is used to 120 * determine the stage to set wait dependencies. 121 */ 122 struct drm_v3d_multi_sync { 123 struct drm_v3d_extension base; 124 /* Array of wait and signal semaphores */ 125 __u64 in_syncs; 126 __u64 out_syncs; 127 128 /* Number of entries */ 129 __u32 in_sync_count; 130 __u32 out_sync_count; 131 132 /* set the stage (v3d_queue) to sync */ 133 __u32 wait_stage; 134 135 __u32 pad; /* mbz */ 136 }; 137 138 /** 139 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D 140 * engine. 141 * 142 * This asks the kernel to have the GPU execute an optional binner 143 * command list, and a render command list. 144 * 145 * The L1T, slice, L2C, L2T, and GCA caches will be flushed before 146 * each CL executes. The VCD cache should be flushed (if necessary) 147 * by the submitted CLs. The TLB writes are guaranteed to have been 148 * flushed by the time the render done IRQ happens, which is the 149 * trigger for out_sync. Any dirtying of cachelines by the job (only 150 * possible using TMU writes) must be flushed by the caller using the 151 * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag. 152 */ 153 struct drm_v3d_submit_cl { 154 /* Pointer to the binner command list. 155 * 156 * This is the first set of commands executed, which runs the 157 * coordinate shader to determine where primitives land on the screen, 158 * then writes out the state updates and draw calls necessary per tile 159 * to the tile allocation BO. 160 * 161 * This BCL will block on any previous BCL submitted on the 162 * same FD, but not on any RCL or BCLs submitted by other 163 * clients -- that is left up to the submitter to control 164 * using in_sync_bcl if necessary. 165 */ 166 __u32 bcl_start; 167 168 /** End address of the BCL (first byte after the BCL) */ 169 __u32 bcl_end; 170 171 /* Offset of the render command list. 172 * 173 * This is the second set of commands executed, which will either 174 * execute the tiles that have been set up by the BCL, or a fixed set 175 * of tiles (in the case of RCL-only blits). 176 * 177 * This RCL will block on this submit's BCL, and any previous 178 * RCL submitted on the same FD, but not on any RCL or BCLs 179 * submitted by other clients -- that is left up to the 180 * submitter to control using in_sync_rcl if necessary. 181 */ 182 __u32 rcl_start; 183 184 /** End address of the RCL (first byte after the RCL) */ 185 __u32 rcl_end; 186 187 /** An optional sync object to wait on before starting the BCL. */ 188 __u32 in_sync_bcl; 189 /** An optional sync object to wait on before starting the RCL. */ 190 __u32 in_sync_rcl; 191 /** An optional sync object to place the completion fence in. */ 192 __u32 out_sync; 193 194 /* Offset of the tile alloc memory 195 * 196 * This is optional on V3D 3.3 (where the CL can set the value) but 197 * required on V3D 4.1. 198 */ 199 __u32 qma; 200 201 /** Size of the tile alloc memory. */ 202 __u32 qms; 203 204 /** Offset of the tile state data array. */ 205 __u32 qts; 206 207 /* Pointer to a u32 array of the BOs that are referenced by the job. 208 */ 209 __u64 bo_handles; 210 211 /* Number of BO handles passed in (size is that times 4). */ 212 __u32 bo_handle_count; 213 214 /* DRM_V3D_SUBMIT_* properties */ 215 __u32 flags; 216 217 /* ID of the perfmon to attach to this job. 0 means no perfmon. */ 218 __u32 perfmon_id; 219 220 __u32 pad; 221 222 /* Pointer to an array of ioctl extensions*/ 223 __u64 extensions; 224 }; 225 226 /** 227 * struct drm_v3d_wait_bo - ioctl argument for waiting for 228 * completion of the last DRM_V3D_SUBMIT_CL on a BO. 229 * 230 * This is useful for cases where multiple processes might be 231 * rendering to a BO and you want to wait for all rendering to be 232 * completed. 233 */ 234 struct drm_v3d_wait_bo { 235 __u32 handle; 236 __u32 pad; 237 __u64 timeout_ns; 238 }; 239 240 /** 241 * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs. 242 * 243 * There are currently no values for the flags argument, but it may be 244 * used in a future extension. 245 */ 246 struct drm_v3d_create_bo { 247 __u32 size; 248 __u32 flags; 249 /** Returned GEM handle for the BO. */ 250 __u32 handle; 251 /** 252 * Returned offset for the BO in the V3D address space. This offset 253 * is private to the DRM fd and is valid for the lifetime of the GEM 254 * handle. 255 * 256 * This offset value will always be nonzero, since various HW 257 * units treat 0 specially. 258 */ 259 __u32 offset; 260 }; 261 262 /** 263 * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs. 264 * 265 * This doesn't actually perform an mmap. Instead, it returns the 266 * offset you need to use in an mmap on the DRM device node. This 267 * means that tools like valgrind end up knowing about the mapped 268 * memory. 269 * 270 * There are currently no values for the flags argument, but it may be 271 * used in a future extension. 272 */ 273 struct drm_v3d_mmap_bo { 274 /** Handle for the object being mapped. */ 275 __u32 handle; 276 __u32 flags; 277 /** offset into the drm node to use for subsequent mmap call. */ 278 __u64 offset; 279 }; 280 281 enum drm_v3d_param { 282 DRM_V3D_PARAM_V3D_UIFCFG, 283 DRM_V3D_PARAM_V3D_HUB_IDENT1, 284 DRM_V3D_PARAM_V3D_HUB_IDENT2, 285 DRM_V3D_PARAM_V3D_HUB_IDENT3, 286 DRM_V3D_PARAM_V3D_CORE0_IDENT0, 287 DRM_V3D_PARAM_V3D_CORE0_IDENT1, 288 DRM_V3D_PARAM_V3D_CORE0_IDENT2, 289 DRM_V3D_PARAM_SUPPORTS_TFU, 290 DRM_V3D_PARAM_SUPPORTS_CSD, 291 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH, 292 DRM_V3D_PARAM_SUPPORTS_PERFMON, 293 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT, 294 DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE, 295 DRM_V3D_PARAM_MAX_PERF_COUNTERS, 296 DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES, 297 DRM_V3D_PARAM_GLOBAL_RESET_COUNTER, 298 DRM_V3D_PARAM_CONTEXT_RESET_COUNTER, 299 }; 300 301 struct drm_v3d_get_param { 302 __u32 param; 303 __u32 pad; 304 __u64 value; 305 }; 306 307 /** 308 * Returns the offset for the BO in the V3D address space for this DRM fd. 309 * This is the same value returned by drm_v3d_create_bo, if that was called 310 * from this DRM fd. 311 */ 312 struct drm_v3d_get_bo_offset { 313 __u32 handle; 314 __u32 offset; 315 }; 316 317 struct drm_v3d_submit_tfu { 318 __u32 icfg; 319 __u32 iia; 320 __u32 iis; 321 __u32 ica; 322 __u32 iua; 323 __u32 ioa; 324 __u32 ios; 325 __u32 coef[4]; 326 /* First handle is the output BO, following are other inputs. 327 * 0 for unused. 328 */ 329 __u32 bo_handles[4]; 330 /* sync object to block on before running the TFU job. Each TFU 331 * job will execute in the order submitted to its FD. Synchronization 332 * against rendering jobs requires using sync objects. 333 */ 334 __u32 in_sync; 335 /* Sync object to signal when the TFU job is done. */ 336 __u32 out_sync; 337 338 __u32 flags; 339 340 /* Pointer to an array of ioctl extensions*/ 341 __u64 extensions; 342 343 struct { 344 __u32 ioc; 345 __u32 pad; 346 } v71; 347 }; 348 349 /* Submits a compute shader for dispatch. This job will block on any 350 * previous compute shaders submitted on this fd, and any other 351 * synchronization must be performed with in_sync/out_sync. 352 */ 353 struct drm_v3d_submit_csd { 354 __u32 cfg[7]; 355 __u32 coef[4]; 356 357 /* Pointer to a u32 array of the BOs that are referenced by the job. 358 */ 359 __u64 bo_handles; 360 361 /* Number of BO handles passed in (size is that times 4). */ 362 __u32 bo_handle_count; 363 364 /* sync object to block on before running the CSD job. Each 365 * CSD job will execute in the order submitted to its FD. 366 * Synchronization against rendering/TFU jobs or CSD from 367 * other fds requires using sync objects. 368 */ 369 __u32 in_sync; 370 /* Sync object to signal when the CSD job is done. */ 371 __u32 out_sync; 372 373 /* ID of the perfmon to attach to this job. 0 means no perfmon. */ 374 __u32 perfmon_id; 375 376 /* Pointer to an array of ioctl extensions*/ 377 __u64 extensions; 378 379 __u32 flags; 380 381 __u32 pad; 382 }; 383 384 /** 385 * struct drm_v3d_indirect_csd - ioctl extension for the CPU job to create an 386 * indirect CSD 387 * 388 * When an extension of DRM_V3D_EXT_ID_CPU_INDIRECT_CSD id is defined, it 389 * points to this extension to define a indirect CSD submission. It creates a 390 * CPU job linked to a CSD job. The CPU job waits for the indirect CSD 391 * dependencies and, once they are signaled, it updates the CSD job config 392 * before allowing the CSD job execution. 393 */ 394 struct drm_v3d_indirect_csd { 395 struct drm_v3d_extension base; 396 397 /* Indirect CSD */ 398 struct drm_v3d_submit_csd submit; 399 400 /* Handle of the indirect BO, that should be also attached to the 401 * indirect CSD. 402 */ 403 __u32 indirect; 404 405 /* Offset within the BO where the workgroup counts are stored */ 406 __u32 offset; 407 408 /* Workgroups size */ 409 __u32 wg_size; 410 411 /* Indices of the uniforms with the workgroup dispatch counts 412 * in the uniform stream. If the uniform rewrite is not needed, 413 * the offset must be 0xffffffff. 414 */ 415 __u32 wg_uniform_offsets[3]; 416 }; 417 418 /** 419 * struct drm_v3d_timestamp_query - ioctl extension for the CPU job to calculate 420 * a timestamp query 421 * 422 * When an extension DRM_V3D_EXT_ID_TIMESTAMP_QUERY is defined, it points to 423 * this extension to define a timestamp query submission. This CPU job will 424 * calculate the timestamp query and update the query value within the 425 * timestamp BO. Moreover, it will signal the timestamp syncobj to indicate 426 * query availability. 427 */ 428 struct drm_v3d_timestamp_query { 429 struct drm_v3d_extension base; 430 431 /* Array of queries' offsets within the timestamp BO for their value */ 432 __u64 offsets; 433 434 /* Array of timestamp's syncobjs to indicate its availability */ 435 __u64 syncs; 436 437 /* Number of queries */ 438 __u32 count; 439 440 /* mbz */ 441 __u32 pad; 442 }; 443 444 /** 445 * struct drm_v3d_reset_timestamp_query - ioctl extension for the CPU job to 446 * reset timestamp queries 447 * 448 * When an extension DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY is defined, it 449 * points to this extension to define a reset timestamp submission. This CPU 450 * job will reset the timestamp queries based on value offset of the first 451 * query. Moreover, it will reset the timestamp syncobj to reset query 452 * availability. 453 */ 454 struct drm_v3d_reset_timestamp_query { 455 struct drm_v3d_extension base; 456 457 /* Array of timestamp's syncobjs to indicate its availability */ 458 __u64 syncs; 459 460 /* Offset of the first query within the timestamp BO for its value */ 461 __u32 offset; 462 463 /* Number of queries */ 464 __u32 count; 465 }; 466 467 /** 468 * struct drm_v3d_copy_timestamp_query - ioctl extension for the CPU job to copy 469 * query results to a buffer 470 * 471 * When an extension DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY is defined, it 472 * points to this extension to define a copy timestamp query submission. This 473 * CPU job will copy the timestamp queries results to a BO with the offset 474 * and stride defined in the extension. 475 */ 476 struct drm_v3d_copy_timestamp_query { 477 struct drm_v3d_extension base; 478 479 /* Define if should write to buffer using 64 or 32 bits */ 480 __u8 do_64bit; 481 482 /* Define if it can write to buffer even if the query is not available */ 483 __u8 do_partial; 484 485 /* Define if it should write availability bit to buffer */ 486 __u8 availability_bit; 487 488 /* mbz */ 489 __u8 pad; 490 491 /* Offset of the buffer in the BO */ 492 __u32 offset; 493 494 /* Stride of the buffer in the BO */ 495 __u32 stride; 496 497 /* Number of queries */ 498 __u32 count; 499 500 /* Array of queries' offsets within the timestamp BO for their value */ 501 __u64 offsets; 502 503 /* Array of timestamp's syncobjs to indicate its availability */ 504 __u64 syncs; 505 }; 506 507 /** 508 * struct drm_v3d_reset_performance_query - ioctl extension for the CPU job to 509 * reset performance queries 510 * 511 * When an extension DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY is defined, it 512 * points to this extension to define a reset performance submission. This CPU 513 * job will reset the performance queries by resetting the values of the 514 * performance monitors. Moreover, it will reset the syncobj to reset query 515 * availability. 516 */ 517 struct drm_v3d_reset_performance_query { 518 struct drm_v3d_extension base; 519 520 /* Array of performance queries's syncobjs to indicate its availability */ 521 __u64 syncs; 522 523 /* Number of queries */ 524 __u32 count; 525 526 /* Number of performance monitors */ 527 __u32 nperfmons; 528 529 /* Array of u64 user-pointers that point to an array of kperfmon_ids */ 530 __u64 kperfmon_ids; 531 }; 532 533 /** 534 * struct drm_v3d_copy_performance_query - ioctl extension for the CPU job to copy 535 * performance query results to a buffer 536 * 537 * When an extension DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY is defined, it 538 * points to this extension to define a copy performance query submission. This 539 * CPU job will copy the performance queries results to a BO with the offset 540 * and stride defined in the extension. 541 */ 542 struct drm_v3d_copy_performance_query { 543 struct drm_v3d_extension base; 544 545 /* Define if should write to buffer using 64 or 32 bits */ 546 __u8 do_64bit; 547 548 /* Define if it can write to buffer even if the query is not available */ 549 __u8 do_partial; 550 551 /* Define if it should write availability bit to buffer */ 552 __u8 availability_bit; 553 554 /* mbz */ 555 __u8 pad; 556 557 /* Offset of the buffer in the BO */ 558 __u32 offset; 559 560 /* Stride of the buffer in the BO */ 561 __u32 stride; 562 563 /* Number of performance monitors */ 564 __u32 nperfmons; 565 566 /* Number of performance counters related to this query pool */ 567 __u32 ncounters; 568 569 /* Number of queries */ 570 __u32 count; 571 572 /* Array of performance queries's syncobjs to indicate its availability */ 573 __u64 syncs; 574 575 /* Array of u64 user-pointers that point to an array of kperfmon_ids */ 576 __u64 kperfmon_ids; 577 }; 578 579 struct drm_v3d_submit_cpu { 580 /* Pointer to a u32 array of the BOs that are referenced by the job. 581 * 582 * For DRM_V3D_EXT_ID_CPU_INDIRECT_CSD, it must contain only one BO, 583 * that contains the workgroup counts. 584 * 585 * For DRM_V3D_EXT_ID_TIMESTAMP_QUERY, it must contain only one BO, 586 * that will contain the timestamp. 587 * 588 * For DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY, it must contain only 589 * one BO, that contains the timestamp. 590 * 591 * For DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY, it must contain two 592 * BOs. The first is the BO where the timestamp queries will be written 593 * to. The second is the BO that contains the timestamp. 594 * 595 * For DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY, it must contain no 596 * BOs. 597 * 598 * For DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY, it must contain one 599 * BO, where the performance queries will be written. 600 */ 601 __u64 bo_handles; 602 603 /* Number of BO handles passed in (size is that times 4). */ 604 __u32 bo_handle_count; 605 606 __u32 flags; 607 608 /* Pointer to an array of ioctl extensions*/ 609 __u64 extensions; 610 }; 611 612 /* The performance counters index represented by this enum are deprecated and 613 * must no longer be used. These counters are only valid for V3D 4.2. 614 * 615 * In order to check for performance counter information, 616 * use DRM_IOCTL_V3D_PERFMON_GET_COUNTER. 617 * 618 * Don't use V3D_PERFCNT_NUM to retrieve the maximum number of performance 619 * counters. You should use DRM_IOCTL_V3D_GET_PARAM with the following 620 * parameter: DRM_V3D_PARAM_MAX_PERF_COUNTERS. 621 */ 622 enum { 623 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS, 624 V3D_PERFCNT_FEP_VALID_PRIMS, 625 V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS, 626 V3D_PERFCNT_FEP_VALID_QUADS, 627 V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL, 628 V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL, 629 V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS, 630 V3D_PERFCNT_TLB_QUADS_ZERO_COV, 631 V3D_PERFCNT_TLB_QUADS_NONZERO_COV, 632 V3D_PERFCNT_TLB_QUADS_WRITTEN, 633 V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD, 634 V3D_PERFCNT_PTB_PRIM_CLIP, 635 V3D_PERFCNT_PTB_PRIM_REV, 636 V3D_PERFCNT_QPU_IDLE_CYCLES, 637 V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER, 638 V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG, 639 V3D_PERFCNT_QPU_CYCLES_VALID_INSTR, 640 V3D_PERFCNT_QPU_CYCLES_TMU_STALL, 641 V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL, 642 V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL, 643 V3D_PERFCNT_QPU_IC_HIT, 644 V3D_PERFCNT_QPU_IC_MISS, 645 V3D_PERFCNT_QPU_UC_HIT, 646 V3D_PERFCNT_QPU_UC_MISS, 647 V3D_PERFCNT_TMU_TCACHE_ACCESS, 648 V3D_PERFCNT_TMU_TCACHE_MISS, 649 V3D_PERFCNT_VPM_VDW_STALL, 650 V3D_PERFCNT_VPM_VCD_STALL, 651 V3D_PERFCNT_BIN_ACTIVE, 652 V3D_PERFCNT_RDR_ACTIVE, 653 V3D_PERFCNT_L2T_HITS, 654 V3D_PERFCNT_L2T_MISSES, 655 V3D_PERFCNT_CYCLE_COUNT, 656 V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER, 657 V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT, 658 V3D_PERFCNT_PTB_PRIMS_BINNED, 659 V3D_PERFCNT_AXI_WRITES_WATCH_0, 660 V3D_PERFCNT_AXI_READS_WATCH_0, 661 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0, 662 V3D_PERFCNT_AXI_READ_STALLS_WATCH_0, 663 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0, 664 V3D_PERFCNT_AXI_READ_BYTES_WATCH_0, 665 V3D_PERFCNT_AXI_WRITES_WATCH_1, 666 V3D_PERFCNT_AXI_READS_WATCH_1, 667 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1, 668 V3D_PERFCNT_AXI_READ_STALLS_WATCH_1, 669 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1, 670 V3D_PERFCNT_AXI_READ_BYTES_WATCH_1, 671 V3D_PERFCNT_TLB_PARTIAL_QUADS, 672 V3D_PERFCNT_TMU_CONFIG_ACCESSES, 673 V3D_PERFCNT_L2T_NO_ID_STALL, 674 V3D_PERFCNT_L2T_COM_QUE_STALL, 675 V3D_PERFCNT_L2T_TMU_WRITES, 676 V3D_PERFCNT_TMU_ACTIVE_CYCLES, 677 V3D_PERFCNT_TMU_STALLED_CYCLES, 678 V3D_PERFCNT_CLE_ACTIVE, 679 V3D_PERFCNT_L2T_TMU_READS, 680 V3D_PERFCNT_L2T_CLE_READS, 681 V3D_PERFCNT_L2T_VCD_READS, 682 V3D_PERFCNT_L2T_TMUCFG_READS, 683 V3D_PERFCNT_L2T_SLC0_READS, 684 V3D_PERFCNT_L2T_SLC1_READS, 685 V3D_PERFCNT_L2T_SLC2_READS, 686 V3D_PERFCNT_L2T_TMU_W_MISSES, 687 V3D_PERFCNT_L2T_TMU_R_MISSES, 688 V3D_PERFCNT_L2T_CLE_MISSES, 689 V3D_PERFCNT_L2T_VCD_MISSES, 690 V3D_PERFCNT_L2T_TMUCFG_MISSES, 691 V3D_PERFCNT_L2T_SLC0_MISSES, 692 V3D_PERFCNT_L2T_SLC1_MISSES, 693 V3D_PERFCNT_L2T_SLC2_MISSES, 694 V3D_PERFCNT_CORE_MEM_WRITES, 695 V3D_PERFCNT_L2T_MEM_WRITES, 696 V3D_PERFCNT_PTB_MEM_WRITES, 697 V3D_PERFCNT_TLB_MEM_WRITES, 698 V3D_PERFCNT_CORE_MEM_READS, 699 V3D_PERFCNT_L2T_MEM_READS, 700 V3D_PERFCNT_PTB_MEM_READS, 701 V3D_PERFCNT_PSE_MEM_READS, 702 V3D_PERFCNT_TLB_MEM_READS, 703 V3D_PERFCNT_GMP_MEM_READS, 704 V3D_PERFCNT_PTB_W_MEM_WORDS, 705 V3D_PERFCNT_TLB_W_MEM_WORDS, 706 V3D_PERFCNT_PSE_R_MEM_WORDS, 707 V3D_PERFCNT_TLB_R_MEM_WORDS, 708 V3D_PERFCNT_TMU_MRU_HITS, 709 V3D_PERFCNT_COMPUTE_ACTIVE, 710 V3D_PERFCNT_NUM, 711 }; 712 713 #define DRM_V3D_MAX_PERF_COUNTERS 32 714 715 struct drm_v3d_perfmon_create { 716 __u32 id; 717 __u32 ncounters; 718 __u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 719 }; 720 721 struct drm_v3d_perfmon_destroy { 722 __u32 id; 723 }; 724 725 /* 726 * Returns the values of the performance counters tracked by this 727 * perfmon (as an array of ncounters u64 values). 728 * 729 * No implicit synchronization is performed, so the user has to 730 * guarantee that any jobs using this perfmon have already been 731 * completed (probably by blocking on the seqno returned by the 732 * last exec that used the perfmon). 733 */ 734 struct drm_v3d_perfmon_get_values { 735 __u32 id; 736 __u32 pad; 737 __u64 values_ptr; 738 }; 739 740 #define DRM_V3D_PERFCNT_MAX_NAME 64 741 #define DRM_V3D_PERFCNT_MAX_CATEGORY 32 742 #define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256 743 744 /** 745 * struct drm_v3d_perfmon_get_counter - ioctl to get the description of a 746 * performance counter 747 * 748 * As userspace needs to retrieve information about the performance counters 749 * available, this IOCTL allows users to get information about a performance 750 * counter (name, category and description). 751 */ 752 struct drm_v3d_perfmon_get_counter { 753 /* 754 * Counter ID 755 * 756 * Must be smaller than the maximum number of performance counters, which 757 * can be retrieve through DRM_V3D_PARAM_MAX_PERF_COUNTERS. 758 */ 759 __u8 counter; 760 761 /* Name of the counter */ 762 __u8 name[DRM_V3D_PERFCNT_MAX_NAME]; 763 764 /* Category of the counter */ 765 __u8 category[DRM_V3D_PERFCNT_MAX_CATEGORY]; 766 767 /* Description of the counter */ 768 __u8 description[DRM_V3D_PERFCNT_MAX_DESCRIPTION]; 769 770 /* mbz */ 771 __u8 reserved[7]; 772 }; 773 774 #define DRM_V3D_PERFMON_CLEAR_GLOBAL 0x0001 775 776 /** 777 * struct drm_v3d_perfmon_set_global - ioctl to define a global performance 778 * monitor 779 * 780 * The global performance monitor will be used for all jobs. If a global 781 * performance monitor is defined, jobs with a self-defined performance 782 * monitor won't be allowed. 783 */ 784 struct drm_v3d_perfmon_set_global { 785 __u32 flags; 786 __u32 id; 787 }; 788 789 #if defined(__cplusplus) 790 } 791 #endif 792 793 #endif /* _V3D_DRM_H_ */ 794