1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_DB21554_CTRL_H 27 #define _SYS_DB21554_CTRL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* definitions for device state */ 36 #define DB_SECONDARY_NEXUS 0x80000000 /* secondary towards host */ 37 #define DB_PRIMARY_NEXUS 0x40000000 /* primary towards host */ 38 #define DB_ATTACHED 0x00000001 /* driver attached */ 39 #define DB_SUSPENDED 0x00100000 40 #define DB_DEBUG_MODE_ON 0x01000000 41 42 #define DB_PCI_CONF_RNUMBER 0 43 #define DB_PCI_CONF_OFFSET 0 44 #define DB_CSR_MEMBAR_RNUMBER 1 45 #define DB_CSR_MEM_OFFSET 0 46 #define DB_CSR_SIZE 0x1000 /* 4K CSR space */ 47 #define DB_CSR_IOBAR_RNUMBER 2 48 #define DB_CSR_IO_OFFSET 0 49 #define DB_PCI_TIMEOUT 10000 /* 10 ms */ 50 #define DB_PCI_WAIT_MS 0 51 #define DB_CONF_FAILURE -1 52 53 #define DB_PIF_SECONDARY_TO_HOST 0x80 54 #define DB_PIF_PRIMARY_TO_HOST 0x40 55 56 /* 57 * the following definition is used to save the state of all PCI children 58 * under us. 59 */ 60 typedef struct db_cfg_state { 61 dev_info_t *dip; 62 uchar_t cache_line_size; 63 uchar_t latency_timer; 64 uchar_t header_type; 65 uchar_t sec_latency_timer; 66 ushort_t command; 67 ushort_t bridge_control; 68 } db_cfg_state_t; 69 70 /* the main control structure of our device */ 71 typedef struct db_ctrl { 72 dev_info_t *dip; 73 uint32_t dev_state; /* device state */ 74 caddr_t csr_mem; /* pointer to CSR map in memory space */ 75 caddr_t csr_io; /* pointer to CSR map in IO space */ 76 caddr_t conf_io; /* pointer to Conf indirect map */ 77 78 /* our bus range information */ 79 pci_bus_range_t range; 80 81 /* any device tuning parameters here. */ 82 uint16_t p_command; 83 uint16_t s_command; 84 int8_t p_latency_timer; 85 int8_t p_cache_line_size; 86 int8_t s_latency_timer; 87 int8_t s_cache_line_size; 88 int8_t p_pwrite_threshold; 89 int8_t s_pwrite_threshold; 90 int8_t p_dread_threshold; 91 int8_t s_dread_threshold; 92 int8_t delayed_trans_order; 93 int8_t serr_fwd_enable; 94 95 /* for child initialization */ 96 uint8_t latency_timer; 97 uint8_t cache_line_size; 98 99 /* error holders */ 100 uint32_t db_pci_err_count; /* indirect cycle timeout count */ 101 #ifdef DEBUG 102 uint32_t db_pci_max_wait_count; /* indirect cycle wait count */ 103 #endif 104 /* cpr related. */ 105 uint_t config_state_index; 106 db_cfg_state_t *db_config_state_p; 107 108 /* all map handles below */ 109 ddi_acc_handle_t csr_mem_handle; /* CSR memory handle */ 110 ddi_acc_handle_t csr_io_handle; /* CSR IO handle */ 111 ddi_acc_handle_t conf_handle; /* config space handle */ 112 ddi_iblock_cookie_t i_block_cookie; /* interrupt cookie */ 113 kmutex_t db_busown; /* bus config own mutex */ 114 kmutex_t db_mutex; 115 uint_t db_soft_state; 116 #define DB_SOFT_STATE_CLOSED 0x00 117 #define DB_SOFT_STATE_OPEN 0x01 118 #define DB_SOFT_STATE_OPEN_EXCL 0x02 119 int fm_cap; 120 ddi_iblock_cookie_t fm_ibc; 121 }db_ctrl_t; 122 123 typedef struct db_acc_cfg_addr { 124 uchar_t c_busnum; /* bus number */ 125 uchar_t c_devnum; /* device number */ 126 uchar_t c_funcnum; /* function number */ 127 uchar_t c_fill; /* reserve field */ 128 } db_acc_cfg_addr_t; 129 130 typedef struct db_acc_pvt { 131 db_acc_cfg_addr_t dev_addr; /* pci device address */ 132 uint32_t *addr; /* upstream/downstream config addr */ 133 uint32_t *data; /* upstream/downstream config data */ 134 uint8_t *bus_own; /* reg to check if bus owned */ 135 uint8_t *bus_release; /* reg to check if bus released */ 136 uint8_t mask; /* bitmask for upstream/downstream */ 137 ushort_t access_mode; /* access through IO or Config */ 138 db_ctrl_t *dbp; 139 ddi_acc_handle_t handle; /* handle for bus access DDI calls */ 140 } db_acc_pvt_t; 141 142 /* We can use the following modes for generating indirect PCI transcations */ 143 #define DB_IO_MAP_DIRECT 1 /* memory mapped IO */ 144 #define DB_IO_MAP_INDIRECT 2 /* indirect map IO */ 145 #define DB_CONF_MAP_INDIRECT_CONF 4 /* access config via config regs */ 146 #define DB_CONF_MAP_INDIRECT_IO 8 /* access config via IO regs */ 147 #define DB_PCI_CONF_CYCLE_TYPE0 0x100 /* type 0 conf cycle */ 148 #define DB_PCI_CONF_CYCLE_TYPE1 0x200 /* type 1 conf cycle */ 149 150 #ifdef __cplusplus 151 } 152 #endif 153 154 #endif /* _SYS_DB21554_CTRL_H */ 155