1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/aperture.h>
31 #include <linux/acpi.h>
32 #include <linux/device.h>
33 #include <linux/module.h>
34 #include <linux/oom.h>
35 #include <linux/pci.h>
36 #include <linux/pm.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/string_helpers.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_managed.h>
46 #include <drm/drm_probe_helper.h>
47
48 #include "display/i9xx_display_sr.h"
49 #include "display/intel_acpi.h"
50 #include "display/intel_bw.h"
51 #include "display/intel_cdclk.h"
52 #include "display/intel_crtc.h"
53 #include "display/intel_display_driver.h"
54 #include "display/intel_dmc.h"
55 #include "display/intel_dp.h"
56 #include "display/intel_dpt.h"
57 #include "display/intel_encoder.h"
58 #include "display/intel_fbdev.h"
59 #include "display/intel_hotplug.h"
60 #include "display/intel_overlay.h"
61 #include "display/intel_pch_refclk.h"
62 #include "display/intel_pps.h"
63 #include "display/intel_sprite_uapi.h"
64 #include "display/intel_vga.h"
65 #include "display/skl_watermark.h"
66
67 #include "gem/i915_gem_context.h"
68 #include "gem/i915_gem_create.h"
69 #include "gem/i915_gem_dmabuf.h"
70 #include "gem/i915_gem_ioctls.h"
71 #include "gem/i915_gem_mman.h"
72 #include "gem/i915_gem_pm.h"
73 #include "gt/intel_gt.h"
74 #include "gt/intel_gt_pm.h"
75 #include "gt/intel_gt_print.h"
76 #include "gt/intel_rc6.h"
77
78 #include "pxp/intel_pxp.h"
79 #include "pxp/intel_pxp_debugfs.h"
80 #include "pxp/intel_pxp_pm.h"
81
82 #include "soc/intel_dram.h"
83 #include "soc/intel_gmch.h"
84
85 #include "i915_debugfs.h"
86 #include "i915_driver.h"
87 #include "i915_drm_client.h"
88 #include "i915_drv.h"
89 #include "i915_file_private.h"
90 #include "i915_getparam.h"
91 #include "i915_hwmon.h"
92 #include "i915_ioc32.h"
93 #include "i915_ioctl.h"
94 #include "i915_irq.h"
95 #include "i915_memcpy.h"
96 #include "i915_perf.h"
97 #include "i915_query.h"
98 #include "i915_reg.h"
99 #include "i915_switcheroo.h"
100 #include "i915_sysfs.h"
101 #include "i915_utils.h"
102 #include "i915_vgpu.h"
103 #include "intel_clock_gating.h"
104 #include "intel_cpu_info.h"
105 #include "intel_gvt.h"
106 #include "intel_memory_region.h"
107 #include "intel_pci_config.h"
108 #include "intel_pcode.h"
109 #include "intel_region_ttm.h"
110 #include "intel_sbi.h"
111 #include "vlv_sideband.h"
112 #include "vlv_suspend.h"
113
114 static const struct drm_driver i915_drm_driver;
115
i915_workqueues_init(struct drm_i915_private * dev_priv)116 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
117 {
118 /*
119 * The i915 workqueue is primarily used for batched retirement of
120 * requests (and thus managing bo) once the task has been completed
121 * by the GPU. i915_retire_requests() is called directly when we
122 * need high-priority retirement, such as waiting for an explicit
123 * bo.
124 *
125 * It is also used for periodic low-priority events, such as
126 * idle-timers and recording error state.
127 *
128 * All tasks on the workqueue are expected to acquire the dev mutex
129 * so there is no point in running more than one instance of the
130 * workqueue at any time. Use an ordered one.
131 */
132 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
133 if (dev_priv->wq == NULL)
134 goto out_err;
135
136 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
137 if (dev_priv->display.hotplug.dp_wq == NULL)
138 goto out_free_wq;
139
140 /*
141 * The unordered i915 workqueue should be used for all work
142 * scheduling that do not require running in order, which used
143 * to be scheduled on the system_wq before moving to a driver
144 * instance due deprecation of flush_scheduled_work().
145 */
146 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);
147 if (dev_priv->unordered_wq == NULL)
148 goto out_free_dp_wq;
149
150 return 0;
151
152 out_free_dp_wq:
153 destroy_workqueue(dev_priv->display.hotplug.dp_wq);
154 out_free_wq:
155 destroy_workqueue(dev_priv->wq);
156 out_err:
157 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
158
159 return -ENOMEM;
160 }
161
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)162 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
163 {
164 destroy_workqueue(dev_priv->unordered_wq);
165 destroy_workqueue(dev_priv->display.hotplug.dp_wq);
166 destroy_workqueue(dev_priv->wq);
167 }
168
169 /*
170 * We don't keep the workarounds for pre-production hardware, so we expect our
171 * driver to fail on these machines in one way or another. A little warning on
172 * dmesg may help both the user and the bug triagers.
173 *
174 * Our policy for removing pre-production workarounds is to keep the
175 * current gen workarounds as a guide to the bring-up of the next gen
176 * (workarounds have a habit of persisting!). Anything older than that
177 * should be removed along with the complications they introduce.
178 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)179 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
180 {
181 bool pre = false;
182
183 pre |= IS_HASWELL_EARLY_SDV(dev_priv);
184 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
185 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
186 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
187 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
188 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
189 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
190 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
191 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
192 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
193 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
194
195 if (pre) {
196 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
197 "It may not be fully functional.\n");
198 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
199 }
200 }
201
sanitize_gpu(struct drm_i915_private * i915)202 static void sanitize_gpu(struct drm_i915_private *i915)
203 {
204 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
205 struct intel_gt *gt;
206 unsigned int i;
207
208 for_each_gt(gt, i915, i)
209 intel_gt_reset_all_engines(gt);
210 }
211 }
212
213 /**
214 * i915_driver_early_probe - setup state not requiring device access
215 * @dev_priv: device private
216 *
217 * Initialize everything that is a "SW-only" state, that is state not
218 * requiring accessing the device or exposing the driver via kernel internal
219 * or userspace interfaces. Example steps belonging here: lock initialization,
220 * system memory allocation, setting up device specific attributes and
221 * function hooks not requiring accessing the device.
222 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)223 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
224 {
225 struct intel_display *display = &dev_priv->display;
226 int ret = 0;
227
228 if (i915_inject_probe_failure(dev_priv))
229 return -ENODEV;
230
231 intel_device_info_runtime_init_early(dev_priv);
232
233 intel_step_init(dev_priv);
234
235 intel_uncore_mmio_debug_init_early(dev_priv);
236
237 spin_lock_init(&dev_priv->irq_lock);
238 spin_lock_init(&dev_priv->gpu_error.lock);
239
240 intel_sbi_init(dev_priv);
241 vlv_iosf_sb_init(dev_priv);
242 mutex_init(&dev_priv->sb_lock);
243
244 i915_memcpy_init_early(dev_priv);
245 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
246
247 ret = i915_workqueues_init(dev_priv);
248 if (ret < 0)
249 return ret;
250
251 ret = vlv_suspend_init(dev_priv);
252 if (ret < 0)
253 goto err_workqueues;
254
255 ret = intel_region_ttm_device_init(dev_priv);
256 if (ret)
257 goto err_ttm;
258
259 ret = intel_root_gt_init_early(dev_priv);
260 if (ret < 0)
261 goto err_rootgt;
262
263 i915_gem_init_early(dev_priv);
264
265 /* This must be called before any calls to HAS_PCH_* */
266 intel_detect_pch(dev_priv);
267
268 intel_irq_init(dev_priv);
269 intel_display_driver_early_probe(display);
270 intel_clock_gating_hooks_init(dev_priv);
271
272 intel_detect_preproduction_hw(dev_priv);
273
274 return 0;
275
276 err_rootgt:
277 intel_region_ttm_device_fini(dev_priv);
278 err_ttm:
279 vlv_suspend_cleanup(dev_priv);
280 err_workqueues:
281 i915_workqueues_cleanup(dev_priv);
282 return ret;
283 }
284
285 /**
286 * i915_driver_late_release - cleanup the setup done in
287 * i915_driver_early_probe()
288 * @dev_priv: device private
289 */
i915_driver_late_release(struct drm_i915_private * dev_priv)290 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
291 {
292 struct intel_display *display = &dev_priv->display;
293
294 intel_irq_fini(dev_priv);
295 intel_power_domains_cleanup(display);
296 i915_gem_cleanup_early(dev_priv);
297 intel_gt_driver_late_release_all(dev_priv);
298 intel_region_ttm_device_fini(dev_priv);
299 vlv_suspend_cleanup(dev_priv);
300 i915_workqueues_cleanup(dev_priv);
301
302 mutex_destroy(&dev_priv->sb_lock);
303 vlv_iosf_sb_fini(dev_priv);
304 intel_sbi_fini(dev_priv);
305
306 i915_params_free(&dev_priv->params);
307 }
308
309 /**
310 * i915_driver_mmio_probe - setup device MMIO
311 * @dev_priv: device private
312 *
313 * Setup minimal device state necessary for MMIO accesses later in the
314 * initialization sequence. The setup here should avoid any other device-wide
315 * side effects or exposing the driver via kernel internal or user space
316 * interfaces.
317 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)318 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
319 {
320 struct intel_display *display = &dev_priv->display;
321 struct intel_gt *gt;
322 int ret, i;
323
324 if (i915_inject_probe_failure(dev_priv))
325 return -ENODEV;
326
327 ret = intel_gmch_bridge_setup(dev_priv);
328 if (ret < 0)
329 return ret;
330
331 for_each_gt(gt, dev_priv, i) {
332 ret = intel_uncore_init_mmio(gt->uncore);
333 if (ret)
334 return ret;
335
336 ret = drmm_add_action_or_reset(&dev_priv->drm,
337 intel_uncore_fini_mmio,
338 gt->uncore);
339 if (ret)
340 return ret;
341 }
342
343 /* Try to make sure MCHBAR is enabled before poking at it */
344 intel_gmch_bar_setup(dev_priv);
345 intel_device_info_runtime_init(dev_priv);
346 intel_display_device_info_runtime_init(display);
347
348 for_each_gt(gt, dev_priv, i) {
349 ret = intel_gt_init_mmio(gt);
350 if (ret)
351 goto err_uncore;
352 }
353
354 /* As early as possible, scrub existing GPU state before clobbering */
355 sanitize_gpu(dev_priv);
356
357 return 0;
358
359 err_uncore:
360 intel_gmch_bar_teardown(dev_priv);
361
362 return ret;
363 }
364
365 /**
366 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
367 * @dev_priv: device private
368 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)369 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
370 {
371 intel_gmch_bar_teardown(dev_priv);
372 }
373
374 /**
375 * i915_set_dma_info - set all relevant PCI dma info as configured for the
376 * platform
377 * @i915: valid i915 instance
378 *
379 * Set the dma max segment size, device and coherent masks. The dma mask set
380 * needs to occur before i915_ggtt_probe_hw.
381 *
382 * A couple of platforms have special needs. Address them as well.
383 *
384 */
i915_set_dma_info(struct drm_i915_private * i915)385 static int i915_set_dma_info(struct drm_i915_private *i915)
386 {
387 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
388 int ret;
389
390 GEM_BUG_ON(!mask_size);
391
392 /*
393 * We don't have a max segment size, so set it to the max so sg's
394 * debugging layer doesn't complain
395 */
396 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
397
398 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
399 if (ret)
400 goto mask_err;
401
402 /* overlay on gen2 is broken and can't address above 1G */
403 if (GRAPHICS_VER(i915) == 2)
404 mask_size = 30;
405
406 /*
407 * 965GM sometimes incorrectly writes to hardware status page (HWS)
408 * using 32bit addressing, overwriting memory if HWS is located
409 * above 4GB.
410 *
411 * The documentation also mentions an issue with undefined
412 * behaviour if any general state is accessed within a page above 4GB,
413 * which also needs to be handled carefully.
414 */
415 if (IS_I965G(i915) || IS_I965GM(i915))
416 mask_size = 32;
417
418 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
419 if (ret)
420 goto mask_err;
421
422 return 0;
423
424 mask_err:
425 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
426 return ret;
427 }
428
429 /* Wa_14022698537:dg2 */
i915_enable_g8(struct drm_i915_private * i915)430 static void i915_enable_g8(struct drm_i915_private *i915)
431 {
432 if (IS_DG2(i915)) {
433 if (IS_DG2_D(i915) && !intel_match_g8_cpu())
434 return;
435
436 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
437 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0);
438 }
439 }
440
i915_pcode_init(struct drm_i915_private * i915)441 static int i915_pcode_init(struct drm_i915_private *i915)
442 {
443 struct intel_gt *gt;
444 int id, ret;
445
446 for_each_gt(gt, i915, id) {
447 ret = intel_pcode_init(gt->uncore);
448 if (ret) {
449 gt_err(gt, "intel_pcode_init failed %d\n", ret);
450 return ret;
451 }
452 }
453
454 i915_enable_g8(i915);
455 return 0;
456 }
457
458 /**
459 * i915_driver_hw_probe - setup state requiring device access
460 * @dev_priv: device private
461 *
462 * Setup state that requires accessing the device, but doesn't require
463 * exposing the driver via kernel internal or userspace interfaces.
464 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)465 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
466 {
467 struct intel_display *display = &dev_priv->display;
468 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
469 int ret;
470
471 if (i915_inject_probe_failure(dev_priv))
472 return -ENODEV;
473
474 if (HAS_PPGTT(dev_priv)) {
475 if (intel_vgpu_active(dev_priv) &&
476 !intel_vgpu_has_full_ppgtt(dev_priv)) {
477 drm_err(&dev_priv->drm,
478 "incompatible vGPU found, support for isolated ppGTT required\n");
479 return -ENXIO;
480 }
481 }
482
483 if (HAS_EXECLISTS(dev_priv)) {
484 /*
485 * Older GVT emulation depends upon intercepting CSB mmio,
486 * which we no longer use, preferring to use the HWSP cache
487 * instead.
488 */
489 if (intel_vgpu_active(dev_priv) &&
490 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
491 drm_err(&dev_priv->drm,
492 "old vGPU host found, support for HWSP emulation required\n");
493 return -ENXIO;
494 }
495 }
496
497 /* needs to be done before ggtt probe */
498 intel_dram_edram_detect(dev_priv);
499
500 ret = i915_set_dma_info(dev_priv);
501 if (ret)
502 return ret;
503
504 ret = i915_perf_init(dev_priv);
505 if (ret)
506 return ret;
507
508 ret = i915_ggtt_probe_hw(dev_priv);
509 if (ret)
510 goto err_perf;
511
512 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name);
513 if (ret)
514 goto err_ggtt;
515
516 ret = i915_ggtt_init_hw(dev_priv);
517 if (ret)
518 goto err_ggtt;
519
520 /*
521 * Make sure we probe lmem before we probe stolen-lmem. The BAR size
522 * might be different due to bar resizing.
523 */
524 ret = intel_gt_tiles_init(dev_priv);
525 if (ret)
526 goto err_ggtt;
527
528 ret = intel_memory_regions_hw_probe(dev_priv);
529 if (ret)
530 goto err_ggtt;
531
532 ret = i915_ggtt_enable_hw(dev_priv);
533 if (ret) {
534 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
535 goto err_mem_regions;
536 }
537
538 pci_set_master(pdev);
539
540 /* On the 945G/GM, the chipset reports the MSI capability on the
541 * integrated graphics even though the support isn't actually there
542 * according to the published specs. It doesn't appear to function
543 * correctly in testing on 945G.
544 * This may be a side effect of MSI having been made available for PEG
545 * and the registers being closely associated.
546 *
547 * According to chipset errata, on the 965GM, MSI interrupts may
548 * be lost or delayed, and was defeatured. MSI interrupts seem to
549 * get lost on g4x as well, and interrupt delivery seems to stay
550 * properly dead afterwards. So we'll just disable them for all
551 * pre-gen5 chipsets.
552 *
553 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
554 * interrupts even when in MSI mode. This results in spurious
555 * interrupt warnings if the legacy irq no. is shared with another
556 * device. The kernel then disables that interrupt source and so
557 * prevents the other device from working properly.
558 */
559 if (GRAPHICS_VER(dev_priv) >= 5) {
560 if (pci_enable_msi(pdev) < 0)
561 drm_dbg(&dev_priv->drm, "can't enable MSI");
562 }
563
564 ret = intel_gvt_init(dev_priv);
565 if (ret)
566 goto err_msi;
567
568 intel_opregion_setup(display);
569
570 ret = i915_pcode_init(dev_priv);
571 if (ret)
572 goto err_opregion;
573
574 /*
575 * Fill the dram structure to get the system dram info. This will be
576 * used for memory latency calculation.
577 */
578 intel_dram_detect(dev_priv);
579
580 intel_bw_init_hw(dev_priv);
581
582 return 0;
583
584 err_opregion:
585 intel_opregion_cleanup(display);
586 err_msi:
587 if (pdev->msi_enabled)
588 pci_disable_msi(pdev);
589 err_mem_regions:
590 intel_memory_regions_driver_release(dev_priv);
591 err_ggtt:
592 i915_ggtt_driver_release(dev_priv);
593 i915_gem_drain_freed_objects(dev_priv);
594 i915_ggtt_driver_late_release(dev_priv);
595 err_perf:
596 i915_perf_fini(dev_priv);
597 return ret;
598 }
599
600 /**
601 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
602 * @dev_priv: device private
603 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)604 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
605 {
606 struct intel_display *display = &dev_priv->display;
607 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
608
609 i915_perf_fini(dev_priv);
610
611 intel_opregion_cleanup(display);
612
613 if (pdev->msi_enabled)
614 pci_disable_msi(pdev);
615 }
616
617 /**
618 * i915_driver_register - register the driver with the rest of the system
619 * @dev_priv: device private
620 *
621 * Perform any steps necessary to make the driver available via kernel
622 * internal or userspace interfaces.
623 */
i915_driver_register(struct drm_i915_private * dev_priv)624 static void i915_driver_register(struct drm_i915_private *dev_priv)
625 {
626 struct intel_display *display = &dev_priv->display;
627 struct intel_gt *gt;
628 unsigned int i;
629
630 i915_gem_driver_register(dev_priv);
631 i915_pmu_register(dev_priv);
632
633 intel_vgpu_register(dev_priv);
634
635 /* Reveal our presence to userspace */
636 if (drm_dev_register(&dev_priv->drm, 0)) {
637 drm_err(&dev_priv->drm,
638 "Failed to register driver for userspace access!\n");
639 return;
640 }
641
642 i915_debugfs_register(dev_priv);
643 i915_setup_sysfs(dev_priv);
644
645 /* Depends on sysfs having been initialized */
646 i915_perf_register(dev_priv);
647
648 for_each_gt(gt, dev_priv, i)
649 intel_gt_driver_register(gt);
650
651 intel_pxp_debugfs_register(dev_priv->pxp);
652
653 i915_hwmon_register(dev_priv);
654
655 intel_display_driver_register(display);
656
657 intel_power_domains_enable(display);
658 intel_runtime_pm_enable(&dev_priv->runtime_pm);
659
660 intel_register_dsm_handler();
661
662 if (i915_switcheroo_register(dev_priv))
663 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
664 }
665
666 /**
667 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
668 * @dev_priv: device private
669 */
i915_driver_unregister(struct drm_i915_private * dev_priv)670 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
671 {
672 struct intel_display *display = &dev_priv->display;
673 struct intel_gt *gt;
674 unsigned int i;
675
676 i915_switcheroo_unregister(dev_priv);
677
678 intel_unregister_dsm_handler();
679
680 intel_runtime_pm_disable(&dev_priv->runtime_pm);
681 intel_power_domains_disable(display);
682
683 intel_display_driver_unregister(display);
684
685 intel_pxp_fini(dev_priv);
686
687 for_each_gt(gt, dev_priv, i)
688 intel_gt_driver_unregister(gt);
689
690 i915_hwmon_unregister(dev_priv);
691
692 i915_perf_unregister(dev_priv);
693 i915_pmu_unregister(dev_priv);
694
695 i915_teardown_sysfs(dev_priv);
696 drm_dev_unplug(&dev_priv->drm);
697
698 i915_gem_driver_unregister(dev_priv);
699 }
700
701 void
i915_print_iommu_status(struct drm_i915_private * i915,struct drm_printer * p)702 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
703 {
704 drm_printf(p, "iommu: %s\n",
705 str_enabled_disabled(i915_vtd_active(i915)));
706 }
707
i915_welcome_messages(struct drm_i915_private * dev_priv)708 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
709 {
710 if (drm_debug_enabled(DRM_UT_DRIVER)) {
711 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER,
712 "device info:");
713 struct intel_gt *gt;
714 unsigned int i;
715
716 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
717 INTEL_DEVID(dev_priv),
718 INTEL_REVID(dev_priv),
719 intel_platform_name(INTEL_INFO(dev_priv)->platform),
720 intel_subplatform(RUNTIME_INFO(dev_priv),
721 INTEL_INFO(dev_priv)->platform),
722 GRAPHICS_VER(dev_priv));
723
724 intel_device_info_print(INTEL_INFO(dev_priv),
725 RUNTIME_INFO(dev_priv), &p);
726 i915_print_iommu_status(dev_priv, &p);
727 for_each_gt(gt, dev_priv, i)
728 intel_gt_info_print(>->info, &p);
729 }
730
731 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
732 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
733 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
734 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
735 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
736 drm_info(&dev_priv->drm,
737 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
738 }
739
740 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)741 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
742 {
743 const struct intel_device_info *match_info =
744 (struct intel_device_info *)ent->driver_data;
745 struct drm_i915_private *i915;
746
747 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
748 struct drm_i915_private, drm);
749 if (IS_ERR(i915))
750 return i915;
751
752 pci_set_drvdata(pdev, &i915->drm);
753
754 /* Device parameters start as a copy of module parameters. */
755 i915_params_copy(&i915->params, &i915_modparams);
756
757 /* Set up device info and initial runtime info. */
758 intel_device_info_driver_create(i915, pdev->device, match_info);
759
760 intel_display_device_probe(pdev);
761
762 return i915;
763 }
764
765 /**
766 * i915_driver_probe - setup chip and create an initial config
767 * @pdev: PCI device
768 * @ent: matching PCI ID entry
769 *
770 * The driver probe routine has to do several things:
771 * - drive output discovery via intel_display_driver_probe()
772 * - initialize the memory manager
773 * - allocate initial config memory
774 * - setup the DRM framebuffer with the allocated memory
775 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)776 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
777 {
778 struct drm_i915_private *i915;
779 struct intel_display *display;
780 int ret;
781
782 ret = pci_enable_device(pdev);
783 if (ret) {
784 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
785 return ret;
786 }
787
788 i915 = i915_driver_create(pdev, ent);
789 if (IS_ERR(i915)) {
790 pci_disable_device(pdev);
791 return PTR_ERR(i915);
792 }
793
794 display = &i915->display;
795
796 ret = i915_driver_early_probe(i915);
797 if (ret < 0)
798 goto out_pci_disable;
799
800 disable_rpm_wakeref_asserts(&i915->runtime_pm);
801
802 intel_vgpu_detect(i915);
803
804 ret = intel_gt_probe_all(i915);
805 if (ret < 0)
806 goto out_runtime_pm_put;
807
808 ret = i915_driver_mmio_probe(i915);
809 if (ret < 0)
810 goto out_runtime_pm_put;
811
812 ret = i915_driver_hw_probe(i915);
813 if (ret < 0)
814 goto out_cleanup_mmio;
815
816 ret = intel_display_driver_probe_noirq(display);
817 if (ret < 0)
818 goto out_cleanup_hw;
819
820 ret = intel_irq_install(i915);
821 if (ret)
822 goto out_cleanup_modeset;
823
824 ret = intel_display_driver_probe_nogem(display);
825 if (ret)
826 goto out_cleanup_irq;
827
828 ret = i915_gem_init(i915);
829 if (ret)
830 goto out_cleanup_modeset2;
831
832 ret = intel_pxp_init(i915);
833 if (ret && ret != -ENODEV)
834 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);
835
836 ret = intel_display_driver_probe(display);
837 if (ret)
838 goto out_cleanup_gem;
839
840 i915_driver_register(i915);
841
842 enable_rpm_wakeref_asserts(&i915->runtime_pm);
843
844 i915_welcome_messages(i915);
845
846 i915->do_release = true;
847
848 return 0;
849
850 out_cleanup_gem:
851 i915_gem_suspend(i915);
852 i915_gem_driver_remove(i915);
853 i915_gem_driver_release(i915);
854 out_cleanup_modeset2:
855 /* FIXME clean up the error path */
856 intel_display_driver_remove(display);
857 intel_irq_uninstall(i915);
858 intel_display_driver_remove_noirq(display);
859 goto out_cleanup_modeset;
860 out_cleanup_irq:
861 intel_irq_uninstall(i915);
862 out_cleanup_modeset:
863 intel_display_driver_remove_nogem(display);
864 out_cleanup_hw:
865 i915_driver_hw_remove(i915);
866 intel_memory_regions_driver_release(i915);
867 i915_ggtt_driver_release(i915);
868 i915_gem_drain_freed_objects(i915);
869 i915_ggtt_driver_late_release(i915);
870 out_cleanup_mmio:
871 i915_driver_mmio_release(i915);
872 out_runtime_pm_put:
873 enable_rpm_wakeref_asserts(&i915->runtime_pm);
874 i915_driver_late_release(i915);
875 out_pci_disable:
876 pci_disable_device(pdev);
877 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
878 return ret;
879 }
880
i915_driver_remove(struct drm_i915_private * i915)881 void i915_driver_remove(struct drm_i915_private *i915)
882 {
883 struct intel_display *display = &i915->display;
884 intel_wakeref_t wakeref;
885
886 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
887
888 i915_driver_unregister(i915);
889
890 /* Flush any external code that still may be under the RCU lock */
891 synchronize_rcu();
892
893 i915_gem_suspend(i915);
894
895 intel_gvt_driver_remove(i915);
896
897 intel_display_driver_remove(display);
898
899 intel_irq_uninstall(i915);
900
901 intel_display_driver_remove_noirq(display);
902
903 i915_reset_error_state(i915);
904 i915_gem_driver_remove(i915);
905
906 intel_display_driver_remove_nogem(display);
907
908 i915_driver_hw_remove(i915);
909
910 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
911 }
912
i915_driver_release(struct drm_device * dev)913 static void i915_driver_release(struct drm_device *dev)
914 {
915 struct drm_i915_private *dev_priv = to_i915(dev);
916 struct intel_display *display = &dev_priv->display;
917 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
918 intel_wakeref_t wakeref;
919
920 if (!dev_priv->do_release)
921 return;
922
923 wakeref = intel_runtime_pm_get(rpm);
924
925 i915_gem_driver_release(dev_priv);
926
927 intel_memory_regions_driver_release(dev_priv);
928 i915_ggtt_driver_release(dev_priv);
929 i915_gem_drain_freed_objects(dev_priv);
930 i915_ggtt_driver_late_release(dev_priv);
931
932 i915_driver_mmio_release(dev_priv);
933
934 intel_runtime_pm_put(rpm, wakeref);
935
936 intel_runtime_pm_driver_release(rpm);
937
938 i915_driver_late_release(dev_priv);
939
940 intel_display_device_remove(display);
941 }
942
i915_driver_open(struct drm_device * dev,struct drm_file * file)943 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
944 {
945 struct drm_i915_private *i915 = to_i915(dev);
946 int ret;
947
948 ret = i915_gem_open(i915, file);
949 if (ret)
950 return ret;
951
952 return 0;
953 }
954
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)955 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
956 {
957 struct drm_i915_file_private *file_priv = file->driver_priv;
958
959 i915_gem_context_close(file);
960 i915_drm_client_put(file_priv->client);
961
962 kfree_rcu(file_priv, rcu);
963
964 /* Catch up with all the deferred frees from "this" client */
965 i915_gem_flush_free_objects(to_i915(dev));
966 }
967
i915_driver_shutdown(struct drm_i915_private * i915)968 void i915_driver_shutdown(struct drm_i915_private *i915)
969 {
970 struct intel_display *display = &i915->display;
971
972 disable_rpm_wakeref_asserts(&i915->runtime_pm);
973 intel_runtime_pm_disable(&i915->runtime_pm);
974 intel_power_domains_disable(display);
975
976 intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true);
977 if (HAS_DISPLAY(i915)) {
978 drm_kms_helper_poll_disable(&i915->drm);
979 intel_display_driver_disable_user_access(display);
980
981 drm_atomic_helper_shutdown(&i915->drm);
982 }
983
984 intel_dp_mst_suspend(display);
985
986 intel_irq_suspend(i915);
987 intel_hpd_cancel_work(i915);
988
989 if (HAS_DISPLAY(i915))
990 intel_display_driver_suspend_access(display);
991
992 intel_encoder_suspend_all(&i915->display);
993 intel_encoder_shutdown_all(&i915->display);
994
995 intel_dmc_suspend(&i915->display);
996
997 i915_gem_suspend(i915);
998
999 /*
1000 * The only requirement is to reboot with display DC states disabled,
1001 * for now leaving all display power wells in the INIT power domain
1002 * enabled.
1003 *
1004 * TODO:
1005 * - unify the pci_driver::shutdown sequence here with the
1006 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1007 * - unify the driver remove and system/runtime suspend sequences with
1008 * the above unified shutdown/poweroff sequence.
1009 */
1010 intel_power_domains_driver_remove(display);
1011 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1012
1013 intel_runtime_pm_driver_last_release(&i915->runtime_pm);
1014 }
1015
suspend_to_idle(struct drm_i915_private * dev_priv)1016 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1017 {
1018 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1019 if (acpi_target_system_state() < ACPI_STATE_S3)
1020 return true;
1021 #endif
1022 return false;
1023 }
1024
i915_drm_complete(struct drm_device * dev)1025 static void i915_drm_complete(struct drm_device *dev)
1026 {
1027 struct drm_i915_private *i915 = to_i915(dev);
1028
1029 intel_pxp_resume_complete(i915->pxp);
1030 }
1031
i915_drm_prepare(struct drm_device * dev)1032 static int i915_drm_prepare(struct drm_device *dev)
1033 {
1034 struct drm_i915_private *i915 = to_i915(dev);
1035
1036 intel_pxp_suspend_prepare(i915->pxp);
1037
1038 /*
1039 * NB intel_display_driver_suspend() may issue new requests after we've
1040 * ostensibly marked the GPU as ready-to-sleep here. We need to
1041 * split out that work and pull it forward so that after point,
1042 * the GPU is not woken again.
1043 */
1044 return i915_gem_backup_suspend(i915);
1045 }
1046
i915_drm_suspend(struct drm_device * dev)1047 static int i915_drm_suspend(struct drm_device *dev)
1048 {
1049 struct drm_i915_private *dev_priv = to_i915(dev);
1050 struct intel_display *display = &dev_priv->display;
1051 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1052 pci_power_t opregion_target_state;
1053
1054 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1055
1056 /* We do a lot of poking in a lot of registers, make sure they work
1057 * properly. */
1058 intel_power_domains_disable(display);
1059 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1060 if (HAS_DISPLAY(dev_priv)) {
1061 drm_kms_helper_poll_disable(dev);
1062 intel_display_driver_disable_user_access(display);
1063 }
1064
1065 pci_save_state(pdev);
1066
1067 intel_display_driver_suspend(display);
1068
1069 intel_irq_suspend(dev_priv);
1070 intel_hpd_cancel_work(dev_priv);
1071
1072 if (HAS_DISPLAY(dev_priv))
1073 intel_display_driver_suspend_access(display);
1074
1075 intel_encoder_suspend_all(&dev_priv->display);
1076
1077 /* Must be called before GGTT is suspended. */
1078 intel_dpt_suspend(dev_priv);
1079 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1080
1081 i9xx_display_sr_save(display);
1082
1083 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1084 intel_opregion_suspend(display, opregion_target_state);
1085
1086 dev_priv->suspend_count++;
1087
1088 intel_dmc_suspend(display);
1089
1090 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1091
1092 i915_gem_drain_freed_objects(dev_priv);
1093
1094 return 0;
1095 }
1096
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1097 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1098 {
1099 struct drm_i915_private *dev_priv = to_i915(dev);
1100 struct intel_display *display = &dev_priv->display;
1101 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1102 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1103 struct intel_gt *gt;
1104 int ret, i;
1105 bool s2idle = !hibernation && suspend_to_idle(dev_priv);
1106
1107 disable_rpm_wakeref_asserts(rpm);
1108
1109 intel_pxp_suspend(dev_priv->pxp);
1110
1111 i915_gem_suspend_late(dev_priv);
1112
1113 for_each_gt(gt, dev_priv, i)
1114 intel_uncore_suspend(gt->uncore);
1115
1116 intel_display_power_suspend_late(display, s2idle);
1117
1118 ret = vlv_suspend_complete(dev_priv);
1119 if (ret) {
1120 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1121 intel_display_power_resume_early(display);
1122
1123 goto out;
1124 }
1125
1126 pci_disable_device(pdev);
1127 /*
1128 * During hibernation on some platforms the BIOS may try to access
1129 * the device even though it's already in D3 and hang the machine. So
1130 * leave the device in D0 on those platforms and hope the BIOS will
1131 * power down the device properly. The issue was seen on multiple old
1132 * GENs with different BIOS vendors, so having an explicit blacklist
1133 * is inpractical; apply the workaround on everything pre GEN6. The
1134 * platforms where the issue was seen:
1135 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1136 * Fujitsu FSC S7110
1137 * Acer Aspire 1830T
1138 */
1139 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1140 pci_set_power_state(pdev, PCI_D3hot);
1141
1142 out:
1143 enable_rpm_wakeref_asserts(rpm);
1144 if (!dev_priv->uncore.user_forcewake_count)
1145 intel_runtime_pm_driver_release(rpm);
1146
1147 return ret;
1148 }
1149
i915_driver_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1150 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1151 pm_message_t state)
1152 {
1153 int error;
1154
1155 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1156 state.event != PM_EVENT_FREEZE))
1157 return -EINVAL;
1158
1159 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1160 return 0;
1161
1162 error = i915_drm_suspend(&i915->drm);
1163 if (error)
1164 return error;
1165
1166 return i915_drm_suspend_late(&i915->drm, false);
1167 }
1168
i915_drm_resume(struct drm_device * dev)1169 static int i915_drm_resume(struct drm_device *dev)
1170 {
1171 struct drm_i915_private *dev_priv = to_i915(dev);
1172 struct intel_display *display = &dev_priv->display;
1173 struct intel_gt *gt;
1174 int ret, i;
1175
1176 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1177
1178 ret = i915_pcode_init(dev_priv);
1179 if (ret)
1180 return ret;
1181
1182 sanitize_gpu(dev_priv);
1183
1184 ret = i915_ggtt_enable_hw(dev_priv);
1185 if (ret)
1186 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1187
1188 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1189
1190 for_each_gt(gt, dev_priv, i)
1191 if (GRAPHICS_VER(gt->i915) >= 8)
1192 setup_private_pat(gt);
1193
1194 /* Must be called after GGTT is resumed. */
1195 intel_dpt_resume(dev_priv);
1196
1197 intel_dmc_resume(display);
1198
1199 i9xx_display_sr_restore(display);
1200
1201 intel_vga_redisable(display);
1202
1203 intel_gmbus_reset(display);
1204
1205 intel_pps_unlock_regs_wa(display);
1206
1207 intel_init_pch_refclk(dev_priv);
1208
1209 /*
1210 * Interrupts have to be enabled before any batches are run. If not the
1211 * GPU will hang. i915_gem_init_hw() will initiate batches to
1212 * update/restore the context.
1213 *
1214 * drm_mode_config_reset() needs AUX interrupts.
1215 *
1216 * Modeset enabling in intel_display_driver_init_hw() also needs working
1217 * interrupts.
1218 */
1219 intel_irq_resume(dev_priv);
1220
1221 if (HAS_DISPLAY(dev_priv))
1222 drm_mode_config_reset(dev);
1223
1224 i915_gem_resume(dev_priv);
1225
1226 intel_display_driver_init_hw(display);
1227
1228 intel_clock_gating_init(dev_priv);
1229
1230 if (HAS_DISPLAY(dev_priv))
1231 intel_display_driver_resume_access(display);
1232
1233 intel_hpd_init(dev_priv);
1234
1235 intel_display_driver_resume(display);
1236
1237 if (HAS_DISPLAY(dev_priv)) {
1238 intel_display_driver_enable_user_access(display);
1239 drm_kms_helper_poll_enable(dev);
1240 }
1241 intel_hpd_poll_disable(dev_priv);
1242
1243 intel_opregion_resume(display);
1244
1245 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1246
1247 intel_power_domains_enable(display);
1248
1249 intel_gvt_resume(dev_priv);
1250
1251 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1252
1253 return 0;
1254 }
1255
i915_drm_resume_early(struct drm_device * dev)1256 static int i915_drm_resume_early(struct drm_device *dev)
1257 {
1258 struct drm_i915_private *dev_priv = to_i915(dev);
1259 struct intel_display *display = &dev_priv->display;
1260 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1261 struct intel_gt *gt;
1262 int ret, i;
1263
1264 /*
1265 * We have a resume ordering issue with the snd-hda driver also
1266 * requiring our device to be power up. Due to the lack of a
1267 * parent/child relationship we currently solve this with an early
1268 * resume hook.
1269 *
1270 * FIXME: This should be solved with a special hdmi sink device or
1271 * similar so that power domains can be employed.
1272 */
1273
1274 /*
1275 * Note that we need to set the power state explicitly, since we
1276 * powered off the device during freeze and the PCI core won't power
1277 * it back up for us during thaw. Powering off the device during
1278 * freeze is not a hard requirement though, and during the
1279 * suspend/resume phases the PCI core makes sure we get here with the
1280 * device powered on. So in case we change our freeze logic and keep
1281 * the device powered we can also remove the following set power state
1282 * call.
1283 */
1284 ret = pci_set_power_state(pdev, PCI_D0);
1285 if (ret) {
1286 drm_err(&dev_priv->drm,
1287 "failed to set PCI D0 power state (%d)\n", ret);
1288 return ret;
1289 }
1290
1291 /*
1292 * Note that pci_enable_device() first enables any parent bridge
1293 * device and only then sets the power state for this device. The
1294 * bridge enabling is a nop though, since bridge devices are resumed
1295 * first. The order of enabling power and enabling the device is
1296 * imposed by the PCI core as described above, so here we preserve the
1297 * same order for the freeze/thaw phases.
1298 *
1299 * TODO: eventually we should remove pci_disable_device() /
1300 * pci_enable_enable_device() from suspend/resume. Due to how they
1301 * depend on the device enable refcount we can't anyway depend on them
1302 * disabling/enabling the device.
1303 */
1304 if (pci_enable_device(pdev))
1305 return -EIO;
1306
1307 pci_set_master(pdev);
1308
1309 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1310
1311 ret = vlv_resume_prepare(dev_priv, false);
1312 if (ret)
1313 drm_err(&dev_priv->drm,
1314 "Resume prepare failed: %d, continuing anyway\n", ret);
1315
1316 for_each_gt(gt, dev_priv, i)
1317 intel_gt_resume_early(gt);
1318
1319 intel_display_power_resume_early(display);
1320
1321 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1322
1323 return ret;
1324 }
1325
i915_driver_resume_switcheroo(struct drm_i915_private * i915)1326 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1327 {
1328 int ret;
1329
1330 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1331 return 0;
1332
1333 ret = i915_drm_resume_early(&i915->drm);
1334 if (ret)
1335 return ret;
1336
1337 return i915_drm_resume(&i915->drm);
1338 }
1339
i915_pm_prepare(struct device * kdev)1340 static int i915_pm_prepare(struct device *kdev)
1341 {
1342 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1343
1344 if (!i915) {
1345 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1346 return -ENODEV;
1347 }
1348
1349 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1350 return 0;
1351
1352 return i915_drm_prepare(&i915->drm);
1353 }
1354
i915_pm_suspend(struct device * kdev)1355 static int i915_pm_suspend(struct device *kdev)
1356 {
1357 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1358
1359 if (!i915) {
1360 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1361 return -ENODEV;
1362 }
1363
1364 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1365 return 0;
1366
1367 return i915_drm_suspend(&i915->drm);
1368 }
1369
i915_pm_suspend_late(struct device * kdev)1370 static int i915_pm_suspend_late(struct device *kdev)
1371 {
1372 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1373
1374 /*
1375 * We have a suspend ordering issue with the snd-hda driver also
1376 * requiring our device to be power up. Due to the lack of a
1377 * parent/child relationship we currently solve this with an late
1378 * suspend hook.
1379 *
1380 * FIXME: This should be solved with a special hdmi sink device or
1381 * similar so that power domains can be employed.
1382 */
1383 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1384 return 0;
1385
1386 return i915_drm_suspend_late(&i915->drm, false);
1387 }
1388
i915_pm_poweroff_late(struct device * kdev)1389 static int i915_pm_poweroff_late(struct device *kdev)
1390 {
1391 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1392
1393 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1394 return 0;
1395
1396 return i915_drm_suspend_late(&i915->drm, true);
1397 }
1398
i915_pm_resume_early(struct device * kdev)1399 static int i915_pm_resume_early(struct device *kdev)
1400 {
1401 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1402
1403 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1404 return 0;
1405
1406 return i915_drm_resume_early(&i915->drm);
1407 }
1408
i915_pm_resume(struct device * kdev)1409 static int i915_pm_resume(struct device *kdev)
1410 {
1411 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1412
1413 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1414 return 0;
1415
1416 return i915_drm_resume(&i915->drm);
1417 }
1418
i915_pm_complete(struct device * kdev)1419 static void i915_pm_complete(struct device *kdev)
1420 {
1421 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1422
1423 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1424 return;
1425
1426 i915_drm_complete(&i915->drm);
1427 }
1428
1429 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)1430 static int i915_pm_freeze(struct device *kdev)
1431 {
1432 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1433 int ret;
1434
1435 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1436 ret = i915_drm_suspend(&i915->drm);
1437 if (ret)
1438 return ret;
1439 }
1440
1441 ret = i915_gem_freeze(i915);
1442 if (ret)
1443 return ret;
1444
1445 return 0;
1446 }
1447
i915_pm_freeze_late(struct device * kdev)1448 static int i915_pm_freeze_late(struct device *kdev)
1449 {
1450 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1451 int ret;
1452
1453 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1454 ret = i915_drm_suspend_late(&i915->drm, true);
1455 if (ret)
1456 return ret;
1457 }
1458
1459 ret = i915_gem_freeze_late(i915);
1460 if (ret)
1461 return ret;
1462
1463 return 0;
1464 }
1465
1466 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)1467 static int i915_pm_thaw_early(struct device *kdev)
1468 {
1469 return i915_pm_resume_early(kdev);
1470 }
1471
i915_pm_thaw(struct device * kdev)1472 static int i915_pm_thaw(struct device *kdev)
1473 {
1474 return i915_pm_resume(kdev);
1475 }
1476
1477 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)1478 static int i915_pm_restore_early(struct device *kdev)
1479 {
1480 return i915_pm_resume_early(kdev);
1481 }
1482
i915_pm_restore(struct device * kdev)1483 static int i915_pm_restore(struct device *kdev)
1484 {
1485 return i915_pm_resume(kdev);
1486 }
1487
intel_runtime_suspend(struct device * kdev)1488 static int intel_runtime_suspend(struct device *kdev)
1489 {
1490 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1491 struct intel_display *display = &dev_priv->display;
1492 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1493 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1494 struct pci_dev *root_pdev;
1495 struct intel_gt *gt;
1496 int ret, i;
1497
1498 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1499 return -ENODEV;
1500
1501 drm_dbg(&dev_priv->drm, "Suspending device\n");
1502
1503 disable_rpm_wakeref_asserts(rpm);
1504
1505 /*
1506 * We are safe here against re-faults, since the fault handler takes
1507 * an RPM reference.
1508 */
1509 i915_gem_runtime_suspend(dev_priv);
1510
1511 intel_pxp_runtime_suspend(dev_priv->pxp);
1512
1513 for_each_gt(gt, dev_priv, i)
1514 intel_gt_runtime_suspend(gt);
1515
1516 intel_irq_suspend(dev_priv);
1517
1518 for_each_gt(gt, dev_priv, i)
1519 intel_uncore_suspend(gt->uncore);
1520
1521 intel_display_power_suspend(display);
1522
1523 ret = vlv_suspend_complete(dev_priv);
1524 if (ret) {
1525 drm_err(&dev_priv->drm,
1526 "Runtime suspend failed, disabling it (%d)\n", ret);
1527 intel_uncore_runtime_resume(&dev_priv->uncore);
1528
1529 intel_irq_resume(dev_priv);
1530
1531 for_each_gt(gt, dev_priv, i)
1532 intel_gt_runtime_resume(gt);
1533
1534 enable_rpm_wakeref_asserts(rpm);
1535
1536 return ret;
1537 }
1538
1539 enable_rpm_wakeref_asserts(rpm);
1540 intel_runtime_pm_driver_release(rpm);
1541
1542 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1543 drm_err(&dev_priv->drm,
1544 "Unclaimed access detected prior to suspending\n");
1545
1546 /*
1547 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1548 * This should be totally removed when we handle the pci states properly
1549 * on runtime PM.
1550 */
1551 root_pdev = pcie_find_root_port(pdev);
1552 if (root_pdev)
1553 pci_d3cold_disable(root_pdev);
1554
1555 /*
1556 * FIXME: We really should find a document that references the arguments
1557 * used below!
1558 */
1559 if (IS_BROADWELL(dev_priv)) {
1560 /*
1561 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1562 * being detected, and the call we do at intel_runtime_resume()
1563 * won't be able to restore them. Since PCI_D3hot matches the
1564 * actual specification and appears to be working, use it.
1565 */
1566 intel_opregion_notify_adapter(display, PCI_D3hot);
1567 } else {
1568 /*
1569 * current versions of firmware which depend on this opregion
1570 * notification have repurposed the D1 definition to mean
1571 * "runtime suspended" vs. what you would normally expect (D3)
1572 * to distinguish it from notifications that might be sent via
1573 * the suspend path.
1574 */
1575 intel_opregion_notify_adapter(display, PCI_D1);
1576 }
1577
1578 assert_forcewakes_inactive(&dev_priv->uncore);
1579
1580 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1581 intel_hpd_poll_enable(dev_priv);
1582
1583 drm_dbg(&dev_priv->drm, "Device suspended\n");
1584 return 0;
1585 }
1586
intel_runtime_resume(struct device * kdev)1587 static int intel_runtime_resume(struct device *kdev)
1588 {
1589 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1590 struct intel_display *display = &dev_priv->display;
1591 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1592 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1593 struct pci_dev *root_pdev;
1594 struct intel_gt *gt;
1595 int ret, i;
1596
1597 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1598 return -ENODEV;
1599
1600 drm_dbg(&dev_priv->drm, "Resuming device\n");
1601
1602 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1603 disable_rpm_wakeref_asserts(rpm);
1604
1605 intel_opregion_notify_adapter(display, PCI_D0);
1606
1607 root_pdev = pcie_find_root_port(pdev);
1608 if (root_pdev)
1609 pci_d3cold_enable(root_pdev);
1610
1611 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1612 drm_dbg(&dev_priv->drm,
1613 "Unclaimed access during suspend, bios?\n");
1614
1615 intel_display_power_resume(display);
1616
1617 ret = vlv_resume_prepare(dev_priv, true);
1618
1619 for_each_gt(gt, dev_priv, i)
1620 intel_uncore_runtime_resume(gt->uncore);
1621
1622 intel_irq_resume(dev_priv);
1623
1624 /*
1625 * No point of rolling back things in case of an error, as the best
1626 * we can do is to hope that things will still work (and disable RPM).
1627 */
1628 for_each_gt(gt, dev_priv, i)
1629 intel_gt_runtime_resume(gt);
1630
1631 intel_pxp_runtime_resume(dev_priv->pxp);
1632
1633 /*
1634 * On VLV/CHV display interrupts are part of the display
1635 * power well, so hpd is reinitialized from there. For
1636 * everyone else do it here.
1637 */
1638 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1639 intel_hpd_init(dev_priv);
1640 intel_hpd_poll_disable(dev_priv);
1641 }
1642
1643 skl_watermark_ipc_update(dev_priv);
1644
1645 enable_rpm_wakeref_asserts(rpm);
1646
1647 if (ret)
1648 drm_err(&dev_priv->drm,
1649 "Runtime resume failed, disabling it (%d)\n", ret);
1650 else
1651 drm_dbg(&dev_priv->drm, "Device resumed\n");
1652
1653 return ret;
1654 }
1655
1656 const struct dev_pm_ops i915_pm_ops = {
1657 /*
1658 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1659 * PMSG_RESUME]
1660 */
1661 .prepare = i915_pm_prepare,
1662 .suspend = i915_pm_suspend,
1663 .suspend_late = i915_pm_suspend_late,
1664 .resume_early = i915_pm_resume_early,
1665 .resume = i915_pm_resume,
1666 .complete = i915_pm_complete,
1667
1668 /*
1669 * S4 event handlers
1670 * @freeze, @freeze_late : called (1) before creating the
1671 * hibernation image [PMSG_FREEZE] and
1672 * (2) after rebooting, before restoring
1673 * the image [PMSG_QUIESCE]
1674 * @thaw, @thaw_early : called (1) after creating the hibernation
1675 * image, before writing it [PMSG_THAW]
1676 * and (2) after failing to create or
1677 * restore the image [PMSG_RECOVER]
1678 * @poweroff, @poweroff_late: called after writing the hibernation
1679 * image, before rebooting [PMSG_HIBERNATE]
1680 * @restore, @restore_early : called after rebooting and restoring the
1681 * hibernation image [PMSG_RESTORE]
1682 */
1683 .freeze = i915_pm_freeze,
1684 .freeze_late = i915_pm_freeze_late,
1685 .thaw_early = i915_pm_thaw_early,
1686 .thaw = i915_pm_thaw,
1687 .poweroff = i915_pm_suspend,
1688 .poweroff_late = i915_pm_poweroff_late,
1689 .restore_early = i915_pm_restore_early,
1690 .restore = i915_pm_restore,
1691
1692 /* S0ix (via runtime suspend) event handlers */
1693 .runtime_suspend = intel_runtime_suspend,
1694 .runtime_resume = intel_runtime_resume,
1695 };
1696
1697 static const struct file_operations i915_driver_fops = {
1698 .owner = THIS_MODULE,
1699 .open = drm_open,
1700 .release = drm_release_noglobal,
1701 .unlocked_ioctl = drm_ioctl,
1702 .mmap = i915_gem_mmap,
1703 .poll = drm_poll,
1704 .read = drm_read,
1705 .compat_ioctl = i915_ioc32_compat_ioctl,
1706 .llseek = noop_llseek,
1707 #ifdef CONFIG_PROC_FS
1708 .show_fdinfo = drm_show_fdinfo,
1709 #endif
1710 .fop_flags = FOP_UNSIGNED_OFFSET,
1711 };
1712
1713 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1714 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1715 struct drm_file *file)
1716 {
1717 return -ENODEV;
1718 }
1719
1720 static const struct drm_ioctl_desc i915_ioctls[] = {
1721 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1722 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1723 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1724 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1725 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1726 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1727 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1728 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1730 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1731 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1732 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1733 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1734 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1735 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1736 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1737 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1738 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1739 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1740 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1741 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1742 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1743 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1744 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1745 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1746 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1747 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1748 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1749 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1750 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1751 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1752 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1753 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1754 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1755 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1756 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1757 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1758 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1759 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1760 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0),
1761 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1762 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1763 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1764 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1765 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1766 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1767 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1768 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1769 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1770 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1771 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1772 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1773 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1774 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1775 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1776 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1777 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1778 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1779 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1780 };
1781
1782 /*
1783 * Interface history:
1784 *
1785 * 1.1: Original.
1786 * 1.2: Add Power Management
1787 * 1.3: Add vblank support
1788 * 1.4: Fix cmdbuffer path, add heap destroy
1789 * 1.5: Add vblank pipe configuration
1790 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1791 * - Support vertical blank on secondary display pipe
1792 */
1793 #define DRIVER_MAJOR 1
1794 #define DRIVER_MINOR 6
1795 #define DRIVER_PATCHLEVEL 0
1796
1797 static const struct drm_driver i915_drm_driver = {
1798 /* Don't use MTRRs here; the Xserver or userspace app should
1799 * deal with them for Intel hardware.
1800 */
1801 .driver_features =
1802 DRIVER_GEM |
1803 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1804 DRIVER_SYNCOBJ_TIMELINE,
1805 .release = i915_driver_release,
1806 .open = i915_driver_open,
1807 .postclose = i915_driver_postclose,
1808 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo),
1809
1810 .gem_prime_import = i915_gem_prime_import,
1811
1812 .dumb_create = i915_gem_dumb_create,
1813 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1814
1815 .ioctls = i915_ioctls,
1816 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1817 .fops = &i915_driver_fops,
1818 .name = DRIVER_NAME,
1819 .desc = DRIVER_DESC,
1820 .major = DRIVER_MAJOR,
1821 .minor = DRIVER_MINOR,
1822 .patchlevel = DRIVER_PATCHLEVEL,
1823 };
1824