xref: /linux/drivers/gpu/drm/i915/i915_reg_defs.h (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __I915_REG_DEFS__
7 #define __I915_REG_DEFS__
8 
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 
12 /**
13  * REG_BIT() - Prepare a u32 bit value
14  * @__n: 0-based bit number
15  *
16  * Local wrapper for BIT() to force u32, with compile time checks.
17  *
18  * @return: Value with bit @__n set.
19  */
20 #define REG_BIT(__n)							\
21 	((u32)(BIT(__n) +						\
22 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&		\
23 				 ((__n) < 0 || (__n) > 31))))
24 
25 /**
26  * REG_BIT8() - Prepare a u8 bit value
27  * @__n: 0-based bit number
28  *
29  * Local wrapper for BIT() to force u8, with compile time checks.
30  *
31  * @return: Value with bit @__n set.
32  */
33 #define REG_BIT8(__n)                                                   \
34 	((u8)(BIT(__n) +                                                \
35 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&         \
36 				 ((__n) < 0 || (__n) > 7))))
37 
38 /**
39  * REG_GENMASK() - Prepare a continuous u32 bitmask
40  * @__high: 0-based high bit
41  * @__low: 0-based low bit
42  *
43  * Local wrapper for GENMASK() to force u32, with compile time checks.
44  *
45  * @return: Continuous bitmask from @__high to @__low, inclusive.
46  */
47 #define REG_GENMASK(__high, __low)					\
48 	((u32)(GENMASK(__high, __low) +					\
49 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&	\
50 				 __is_constexpr(__low) &&		\
51 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
52 
53 /**
54  * REG_GENMASK64() - Prepare a continuous u64 bitmask
55  * @__high: 0-based high bit
56  * @__low: 0-based low bit
57  *
58  * Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
59  *
60  * @return: Continuous bitmask from @__high to @__low, inclusive.
61  */
62 #define REG_GENMASK64(__high, __low)					\
63 	((u64)(GENMASK_ULL(__high, __low) +				\
64 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
65 				 __is_constexpr(__low) &&		\
66 				 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
67 
68 /**
69  * REG_GENMASK8() - Prepare a continuous u8 bitmask
70  * @__high: 0-based high bit
71  * @__low: 0-based low bit
72  *
73  * Local wrapper for GENMASK() to force u8, with compile time checks.
74  *
75  * @return: Continuous bitmask from @__high to @__low, inclusive.
76  */
77 #define REG_GENMASK8(__high, __low)                                     \
78 	((u8)(GENMASK(__high, __low) +                                  \
79 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
80 				 __is_constexpr(__low) &&               \
81 				 ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
82 
83 /*
84  * Local integer constant expression version of is_power_of_2().
85  */
86 #define IS_POWER_OF_2(__x)		((__x) && (((__x) & ((__x) - 1)) == 0))
87 
88 /**
89  * REG_FIELD_PREP() - Prepare a u32 bitfield value
90  * @__mask: shifted mask defining the field's length and position
91  * @__val: value to put in the field
92  *
93  * Local copy of FIELD_PREP() to generate an integer constant expression, force
94  * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
95  *
96  * @return: @__val masked and shifted into the field defined by @__mask.
97  */
98 #define REG_FIELD_PREP(__mask, __val)						\
99 	((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +	\
100 	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +		\
101 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +		\
102 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
103 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
104 
105 /**
106  * REG_FIELD_PREP8() - Prepare a u8 bitfield value
107  * @__mask: shifted mask defining the field's length and position
108  * @__val: value to put in the field
109  *
110  * Local copy of FIELD_PREP() to generate an integer constant expression, force
111  * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
112  *
113  * @return: @__val masked and shifted into the field defined by @__mask.
114  */
115 #define REG_FIELD_PREP8(__mask, __val)                                          \
116 	((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +      \
117 	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
118 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) +          \
119 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
120 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
121 
122 /**
123  * REG_FIELD_GET() - Extract a u32 bitfield value
124  * @__mask: shifted mask defining the field's length and position
125  * @__val: value to extract the bitfield value from
126  *
127  * Local wrapper for FIELD_GET() to force u32 and for consistency with
128  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
129  *
130  * @return: Masked and shifted value of the field defined by @__mask in @__val.
131  */
132 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
133 
134 /**
135  * REG_FIELD_GET64() - Extract a u64 bitfield value
136  * @__mask: shifted mask defining the field's length and position
137  * @__val: value to extract the bitfield value from
138  *
139  * Local wrapper for FIELD_GET() to force u64 and for consistency with
140  * REG_GENMASK64().
141  *
142  * @return: Masked and shifted value of the field defined by @__mask in @__val.
143  */
144 #define REG_FIELD_GET64(__mask, __val)	((u64)FIELD_GET(__mask, __val))
145 
146 /**
147  * REG_BIT16() - Prepare a u16 bit value
148  * @__n: 0-based bit number
149  *
150  * Local wrapper for BIT() to force u16, with compile time
151  * checks.
152  *
153  * @return: Value with bit @__n set.
154  */
155 #define REG_BIT16(__n)                                                   \
156 	((u16)(BIT(__n) +                                                \
157 	       BUILD_BUG_ON_ZERO(__is_constexpr(__n) &&         \
158 				 ((__n) < 0 || (__n) > 15))))
159 
160 /**
161  * REG_GENMASK16() - Prepare a continuous u8 bitmask
162  * @__high: 0-based high bit
163  * @__low: 0-based low bit
164  *
165  * Local wrapper for GENMASK() to force u16, with compile time
166  * checks.
167  *
168  * @return: Continuous bitmask from @__high to @__low, inclusive.
169  */
170 #define REG_GENMASK16(__high, __low)                                     \
171 	((u16)(GENMASK(__high, __low) +                                  \
172 	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&      \
173 				 __is_constexpr(__low) &&               \
174 				 ((__low) < 0 || (__high) > 15 || (__low) > (__high)))))
175 
176 /**
177  * REG_FIELD_PREP16() - Prepare a u16 bitfield value
178  * @__mask: shifted mask defining the field's length and position
179  * @__val: value to put in the field
180  *
181  * Local copy of FIELD_PREP16() to generate an integer constant
182  * expression, force u8 and for consistency with
183  * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16().
184  *
185  * @return: @__val masked and shifted into the field defined by @__mask.
186  */
187 #define REG_FIELD_PREP16(__mask, __val)                                          \
188 	((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +      \
189 	       BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) +             \
190 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) +          \
191 	       BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
192 	       BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
193 
194 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
195 #define _MASKED_FIELD(mask, value) ({					   \
196 	if (__builtin_constant_p(mask))					   \
197 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
198 	if (__builtin_constant_p(value))				   \
199 		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
200 	if (__builtin_constant_p(mask) && __builtin_constant_p(value))	   \
201 		BUILD_BUG_ON_MSG((value) & ~(mask),			   \
202 				 "Incorrect value for mask");		   \
203 	__MASKED_FIELD(mask, value); })
204 #define _MASKED_BIT_ENABLE(a)	({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
205 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
206 
207 /*
208  * Given the first two numbers __a and __b of arbitrarily many evenly spaced
209  * numbers, pick the 0-based __index'th value.
210  *
211  * Always prefer this over _PICK() if the numbers are evenly spaced.
212  */
213 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
214 
215 /*
216  * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets.
217  * @__c_index corresponds to the index in which the second range starts to be
218  * used. Using math interval notation, the first range is used for indexes [ 0,
219  * @__c_index), while the second range is used for [ @__c_index, ... ). Example:
220  *
221  * #define _FOO_A			0xf000
222  * #define _FOO_B			0xf004
223  * #define _FOO_C			0xf008
224  * #define _SUPER_FOO_A			0xa000
225  * #define _SUPER_FOO_B			0xa100
226  * #define FOO(x)			_MMIO(_PICK_EVEN_2RANGES(x, 3,		\
227  *					      _FOO_A, _FOO_B,			\
228  *					      _SUPER_FOO_A, _SUPER_FOO_B))
229  *
230  * This expands to:
231  *	0: 0xf000,
232  *	1: 0xf004,
233  *	2: 0xf008,
234  *	3: 0xa000,
235  *	4: 0xa100,
236  *	5: 0xa200,
237  *	...
238  */
239 #define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d)		\
240 	(BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +			\
241 	 ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) :		\
242 				   _PICK_EVEN((__index) - (__c_index), __c, __d)))
243 
244 /*
245  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
246  *
247  * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
248  */
249 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
250 
251 /**
252  * REG_FIELD_GET8() - Extract a u8 bitfield value
253  * @__mask: shifted mask defining the field's length and position
254  * @__val: value to extract the bitfield value from
255  *
256  * Local wrapper for FIELD_GET() to force u8 and for consistency with
257  * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
258  *
259  * @return: Masked and shifted value of the field defined by @__mask in @__val.
260  */
261 #define REG_FIELD_GET8(__mask, __val)   ((u8)FIELD_GET(__mask, __val))
262 
263 typedef struct {
264 	u32 reg;
265 } i915_reg_t;
266 
267 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
268 
269 typedef struct {
270 	u32 reg;
271 } i915_mcr_reg_t;
272 
273 #define MCR_REG(offset)	((const i915_mcr_reg_t){ .reg = (offset) })
274 
275 #define INVALID_MMIO_REG _MMIO(0)
276 
277 /*
278  * These macros can be used on either i915_reg_t or i915_mcr_reg_t since they're
279  * simply operations on the register's offset and don't care about the MCR vs
280  * non-MCR nature of the register.
281  */
282 #define i915_mmio_reg_offset(r) \
283 	_Generic((r), i915_reg_t: (r).reg, i915_mcr_reg_t: (r).reg)
284 #define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
285 #define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG))
286 
287 #endif /* __I915_REG_DEFS__ */
288