xref: /titanic_41/usr/src/uts/common/io/i40e/core/i40e_common.c (revision 463c7d0ed8a793a3a71f19cc0c4d17e142d945a5)
1 /******************************************************************************
2 
3   Copyright (c) 2013-2015, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #include "i40e_type.h"
36 #include "i40e_adminq.h"
37 #include "i40e_prototype.h"
38 #include "i40e_virtchnl.h"
39 
40 
41 /**
42  * i40e_set_mac_type - Sets MAC type
43  * @hw: pointer to the HW structure
44  *
45  * This function sets the mac type of the adapter based on the
46  * vendor ID and device ID stored in the hw structure.
47  **/
i40e_set_mac_type(struct i40e_hw * hw)48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 {
50 	enum i40e_status_code status = I40E_SUCCESS;
51 
52 	DEBUGFUNC("i40e_set_mac_type\n");
53 
54 	if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
55 		switch (hw->device_id) {
56 		case I40E_DEV_ID_SFP_XL710:
57 		case I40E_DEV_ID_QEMU:
58 		case I40E_DEV_ID_KX_B:
59 		case I40E_DEV_ID_KX_C:
60 		case I40E_DEV_ID_QSFP_A:
61 		case I40E_DEV_ID_QSFP_B:
62 		case I40E_DEV_ID_QSFP_C:
63 		case I40E_DEV_ID_10G_BASE_T:
64 		case I40E_DEV_ID_10G_BASE_T4:
65 		case I40E_DEV_ID_20G_KR2:
66 		case I40E_DEV_ID_20G_KR2_A:
67 		case I40E_DEV_ID_25G_B:
68 		case I40E_DEV_ID_25G_SFP28:
69 			hw->mac.type = I40E_MAC_XL710;
70 			break;
71 		case I40E_DEV_ID_X722_A0:
72 		case I40E_DEV_ID_KX_X722:
73 		case I40E_DEV_ID_QSFP_X722:
74 		case I40E_DEV_ID_SFP_X722:
75 		case I40E_DEV_ID_1G_BASE_T_X722:
76 		case I40E_DEV_ID_10G_BASE_T_X722:
77 		case I40E_DEV_ID_SFP_I_X722:
78 			hw->mac.type = I40E_MAC_X722;
79 			break;
80 		default:
81 			hw->mac.type = I40E_MAC_GENERIC;
82 			break;
83 		}
84 	} else {
85 		status = I40E_ERR_DEVICE_NOT_SUPPORTED;
86 	}
87 
88 	DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
89 		  hw->mac.type, status);
90 	return status;
91 }
92 
93 /**
94  * i40e_aq_str - convert AQ err code to a string
95  * @hw: pointer to the HW structure
96  * @aq_err: the AQ error code to convert
97  **/
i40e_aq_str(struct i40e_hw * hw,enum i40e_admin_queue_err aq_err)98 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
99 {
100 	switch (aq_err) {
101 	case I40E_AQ_RC_OK:
102 		return "OK";
103 	case I40E_AQ_RC_EPERM:
104 		return "I40E_AQ_RC_EPERM";
105 	case I40E_AQ_RC_ENOENT:
106 		return "I40E_AQ_RC_ENOENT";
107 	case I40E_AQ_RC_ESRCH:
108 		return "I40E_AQ_RC_ESRCH";
109 	case I40E_AQ_RC_EINTR:
110 		return "I40E_AQ_RC_EINTR";
111 	case I40E_AQ_RC_EIO:
112 		return "I40E_AQ_RC_EIO";
113 	case I40E_AQ_RC_ENXIO:
114 		return "I40E_AQ_RC_ENXIO";
115 	case I40E_AQ_RC_E2BIG:
116 		return "I40E_AQ_RC_E2BIG";
117 	case I40E_AQ_RC_EAGAIN:
118 		return "I40E_AQ_RC_EAGAIN";
119 	case I40E_AQ_RC_ENOMEM:
120 		return "I40E_AQ_RC_ENOMEM";
121 	case I40E_AQ_RC_EACCES:
122 		return "I40E_AQ_RC_EACCES";
123 	case I40E_AQ_RC_EFAULT:
124 		return "I40E_AQ_RC_EFAULT";
125 	case I40E_AQ_RC_EBUSY:
126 		return "I40E_AQ_RC_EBUSY";
127 	case I40E_AQ_RC_EEXIST:
128 		return "I40E_AQ_RC_EEXIST";
129 	case I40E_AQ_RC_EINVAL:
130 		return "I40E_AQ_RC_EINVAL";
131 	case I40E_AQ_RC_ENOTTY:
132 		return "I40E_AQ_RC_ENOTTY";
133 	case I40E_AQ_RC_ENOSPC:
134 		return "I40E_AQ_RC_ENOSPC";
135 	case I40E_AQ_RC_ENOSYS:
136 		return "I40E_AQ_RC_ENOSYS";
137 	case I40E_AQ_RC_ERANGE:
138 		return "I40E_AQ_RC_ERANGE";
139 	case I40E_AQ_RC_EFLUSHED:
140 		return "I40E_AQ_RC_EFLUSHED";
141 	case I40E_AQ_RC_BAD_ADDR:
142 		return "I40E_AQ_RC_BAD_ADDR";
143 	case I40E_AQ_RC_EMODE:
144 		return "I40E_AQ_RC_EMODE";
145 	case I40E_AQ_RC_EFBIG:
146 		return "I40E_AQ_RC_EFBIG";
147 	}
148 
149 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
150 	return hw->err_str;
151 }
152 
153 /**
154  * i40e_stat_str - convert status err code to a string
155  * @hw: pointer to the HW structure
156  * @stat_err: the status error code to convert
157  **/
i40e_stat_str(struct i40e_hw * hw,enum i40e_status_code stat_err)158 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
159 {
160 	switch (stat_err) {
161 	case I40E_SUCCESS:
162 		return "OK";
163 	case I40E_ERR_NVM:
164 		return "I40E_ERR_NVM";
165 	case I40E_ERR_NVM_CHECKSUM:
166 		return "I40E_ERR_NVM_CHECKSUM";
167 	case I40E_ERR_PHY:
168 		return "I40E_ERR_PHY";
169 	case I40E_ERR_CONFIG:
170 		return "I40E_ERR_CONFIG";
171 	case I40E_ERR_PARAM:
172 		return "I40E_ERR_PARAM";
173 	case I40E_ERR_MAC_TYPE:
174 		return "I40E_ERR_MAC_TYPE";
175 	case I40E_ERR_UNKNOWN_PHY:
176 		return "I40E_ERR_UNKNOWN_PHY";
177 	case I40E_ERR_LINK_SETUP:
178 		return "I40E_ERR_LINK_SETUP";
179 	case I40E_ERR_ADAPTER_STOPPED:
180 		return "I40E_ERR_ADAPTER_STOPPED";
181 	case I40E_ERR_INVALID_MAC_ADDR:
182 		return "I40E_ERR_INVALID_MAC_ADDR";
183 	case I40E_ERR_DEVICE_NOT_SUPPORTED:
184 		return "I40E_ERR_DEVICE_NOT_SUPPORTED";
185 	case I40E_ERR_MASTER_REQUESTS_PENDING:
186 		return "I40E_ERR_MASTER_REQUESTS_PENDING";
187 	case I40E_ERR_INVALID_LINK_SETTINGS:
188 		return "I40E_ERR_INVALID_LINK_SETTINGS";
189 	case I40E_ERR_AUTONEG_NOT_COMPLETE:
190 		return "I40E_ERR_AUTONEG_NOT_COMPLETE";
191 	case I40E_ERR_RESET_FAILED:
192 		return "I40E_ERR_RESET_FAILED";
193 	case I40E_ERR_SWFW_SYNC:
194 		return "I40E_ERR_SWFW_SYNC";
195 	case I40E_ERR_NO_AVAILABLE_VSI:
196 		return "I40E_ERR_NO_AVAILABLE_VSI";
197 	case I40E_ERR_NO_MEMORY:
198 		return "I40E_ERR_NO_MEMORY";
199 	case I40E_ERR_BAD_PTR:
200 		return "I40E_ERR_BAD_PTR";
201 	case I40E_ERR_RING_FULL:
202 		return "I40E_ERR_RING_FULL";
203 	case I40E_ERR_INVALID_PD_ID:
204 		return "I40E_ERR_INVALID_PD_ID";
205 	case I40E_ERR_INVALID_QP_ID:
206 		return "I40E_ERR_INVALID_QP_ID";
207 	case I40E_ERR_INVALID_CQ_ID:
208 		return "I40E_ERR_INVALID_CQ_ID";
209 	case I40E_ERR_INVALID_CEQ_ID:
210 		return "I40E_ERR_INVALID_CEQ_ID";
211 	case I40E_ERR_INVALID_AEQ_ID:
212 		return "I40E_ERR_INVALID_AEQ_ID";
213 	case I40E_ERR_INVALID_SIZE:
214 		return "I40E_ERR_INVALID_SIZE";
215 	case I40E_ERR_INVALID_ARP_INDEX:
216 		return "I40E_ERR_INVALID_ARP_INDEX";
217 	case I40E_ERR_INVALID_FPM_FUNC_ID:
218 		return "I40E_ERR_INVALID_FPM_FUNC_ID";
219 	case I40E_ERR_QP_INVALID_MSG_SIZE:
220 		return "I40E_ERR_QP_INVALID_MSG_SIZE";
221 	case I40E_ERR_QP_TOOMANY_WRS_POSTED:
222 		return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
223 	case I40E_ERR_INVALID_FRAG_COUNT:
224 		return "I40E_ERR_INVALID_FRAG_COUNT";
225 	case I40E_ERR_QUEUE_EMPTY:
226 		return "I40E_ERR_QUEUE_EMPTY";
227 	case I40E_ERR_INVALID_ALIGNMENT:
228 		return "I40E_ERR_INVALID_ALIGNMENT";
229 	case I40E_ERR_FLUSHED_QUEUE:
230 		return "I40E_ERR_FLUSHED_QUEUE";
231 	case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
232 		return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
233 	case I40E_ERR_INVALID_IMM_DATA_SIZE:
234 		return "I40E_ERR_INVALID_IMM_DATA_SIZE";
235 	case I40E_ERR_TIMEOUT:
236 		return "I40E_ERR_TIMEOUT";
237 	case I40E_ERR_OPCODE_MISMATCH:
238 		return "I40E_ERR_OPCODE_MISMATCH";
239 	case I40E_ERR_CQP_COMPL_ERROR:
240 		return "I40E_ERR_CQP_COMPL_ERROR";
241 	case I40E_ERR_INVALID_VF_ID:
242 		return "I40E_ERR_INVALID_VF_ID";
243 	case I40E_ERR_INVALID_HMCFN_ID:
244 		return "I40E_ERR_INVALID_HMCFN_ID";
245 	case I40E_ERR_BACKING_PAGE_ERROR:
246 		return "I40E_ERR_BACKING_PAGE_ERROR";
247 	case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
248 		return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
249 	case I40E_ERR_INVALID_PBLE_INDEX:
250 		return "I40E_ERR_INVALID_PBLE_INDEX";
251 	case I40E_ERR_INVALID_SD_INDEX:
252 		return "I40E_ERR_INVALID_SD_INDEX";
253 	case I40E_ERR_INVALID_PAGE_DESC_INDEX:
254 		return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
255 	case I40E_ERR_INVALID_SD_TYPE:
256 		return "I40E_ERR_INVALID_SD_TYPE";
257 	case I40E_ERR_MEMCPY_FAILED:
258 		return "I40E_ERR_MEMCPY_FAILED";
259 	case I40E_ERR_INVALID_HMC_OBJ_INDEX:
260 		return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
261 	case I40E_ERR_INVALID_HMC_OBJ_COUNT:
262 		return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
263 	case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
264 		return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
265 	case I40E_ERR_SRQ_ENABLED:
266 		return "I40E_ERR_SRQ_ENABLED";
267 	case I40E_ERR_ADMIN_QUEUE_ERROR:
268 		return "I40E_ERR_ADMIN_QUEUE_ERROR";
269 	case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
270 		return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
271 	case I40E_ERR_BUF_TOO_SHORT:
272 		return "I40E_ERR_BUF_TOO_SHORT";
273 	case I40E_ERR_ADMIN_QUEUE_FULL:
274 		return "I40E_ERR_ADMIN_QUEUE_FULL";
275 	case I40E_ERR_ADMIN_QUEUE_NO_WORK:
276 		return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
277 	case I40E_ERR_BAD_IWARP_CQE:
278 		return "I40E_ERR_BAD_IWARP_CQE";
279 	case I40E_ERR_NVM_BLANK_MODE:
280 		return "I40E_ERR_NVM_BLANK_MODE";
281 	case I40E_ERR_NOT_IMPLEMENTED:
282 		return "I40E_ERR_NOT_IMPLEMENTED";
283 	case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
284 		return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
285 	case I40E_ERR_DIAG_TEST_FAILED:
286 		return "I40E_ERR_DIAG_TEST_FAILED";
287 	case I40E_ERR_NOT_READY:
288 		return "I40E_ERR_NOT_READY";
289 	case I40E_NOT_SUPPORTED:
290 		return "I40E_NOT_SUPPORTED";
291 	case I40E_ERR_FIRMWARE_API_VERSION:
292 		return "I40E_ERR_FIRMWARE_API_VERSION";
293 	}
294 
295 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
296 	return hw->err_str;
297 }
298 
299 /**
300  * i40e_debug_aq
301  * @hw: debug mask related to admin queue
302  * @mask: debug mask
303  * @desc: pointer to admin queue descriptor
304  * @buffer: pointer to command buffer
305  * @buf_len: max length of buffer
306  *
307  * Dumps debug log about adminq command with descriptor contents.
308  **/
i40e_debug_aq(struct i40e_hw * hw,enum i40e_debug_mask mask,void * desc,void * buffer,u16 buf_len)309 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
310 		   void *buffer, u16 buf_len)
311 {
312 	struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
313 	u16 len = LE16_TO_CPU(aq_desc->datalen);
314 	u8 *buf = (u8 *)buffer;
315 	u16 i = 0;
316 
317 	if ((!(mask & hw->debug_mask)) || (desc == NULL))
318 		return;
319 
320 	i40e_debug(hw, mask,
321 		   "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
322 		   LE16_TO_CPU(aq_desc->opcode),
323 		   LE16_TO_CPU(aq_desc->flags),
324 		   LE16_TO_CPU(aq_desc->datalen),
325 		   LE16_TO_CPU(aq_desc->retval));
326 	i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
327 		   LE32_TO_CPU(aq_desc->cookie_high),
328 		   LE32_TO_CPU(aq_desc->cookie_low));
329 	i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
330 		   LE32_TO_CPU(aq_desc->params.internal.param0),
331 		   LE32_TO_CPU(aq_desc->params.internal.param1));
332 	i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
333 		   LE32_TO_CPU(aq_desc->params.external.addr_high),
334 		   LE32_TO_CPU(aq_desc->params.external.addr_low));
335 
336 	if ((buffer != NULL) && (aq_desc->datalen != 0)) {
337 		i40e_debug(hw, mask, "AQ CMD Buffer:\n");
338 		if (buf_len < len)
339 			len = buf_len;
340 		/* write the full 16-byte chunks */
341 		for (i = 0; i < (len - 16); i += 16)
342 			i40e_debug(hw, mask,
343 				   "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
344 				   i, buf[i], buf[i+1], buf[i+2], buf[i+3],
345 				   buf[i+4], buf[i+5], buf[i+6], buf[i+7],
346 				   buf[i+8], buf[i+9], buf[i+10], buf[i+11],
347 				   buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
348 		/* the most we could have left is 16 bytes, pad with zeros */
349 		if (i < len) {
350 			char d_buf[16];
351 			int j, i_sav;
352 
353 			i_sav = i;
354 			memset(d_buf, 0, sizeof(d_buf));
355 			for (j = 0; i < len; j++, i++)
356 				d_buf[j] = buf[i];
357 			i40e_debug(hw, mask,
358 				   "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
359 				   i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
360 				   d_buf[4], d_buf[5], d_buf[6], d_buf[7],
361 				   d_buf[8], d_buf[9], d_buf[10], d_buf[11],
362 				   d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
363 		}
364 	}
365 }
366 
367 /**
368  * i40e_check_asq_alive
369  * @hw: pointer to the hw struct
370  *
371  * Returns TRUE if Queue is enabled else FALSE.
372  **/
i40e_check_asq_alive(struct i40e_hw * hw)373 bool i40e_check_asq_alive(struct i40e_hw *hw)
374 {
375 	if (hw->aq.asq.len)
376 		return !!(rd32(hw, hw->aq.asq.len) &
377 			I40E_PF_ATQLEN_ATQENABLE_MASK);
378 	return FALSE;
379 }
380 
381 /**
382  * i40e_aq_queue_shutdown
383  * @hw: pointer to the hw struct
384  * @unloading: is the driver unloading itself
385  *
386  * Tell the Firmware that we're shutting down the AdminQ and whether
387  * or not the driver is unloading as well.
388  **/
i40e_aq_queue_shutdown(struct i40e_hw * hw,bool unloading)389 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
390 					     bool unloading)
391 {
392 	struct i40e_aq_desc desc;
393 	struct i40e_aqc_queue_shutdown *cmd =
394 		(struct i40e_aqc_queue_shutdown *)&desc.params.raw;
395 	enum i40e_status_code status;
396 
397 	i40e_fill_default_direct_cmd_desc(&desc,
398 					  i40e_aqc_opc_queue_shutdown);
399 
400 	if (unloading)
401 		cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
402 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
403 
404 	return status;
405 }
406 
407 /**
408  * i40e_aq_get_set_rss_lut
409  * @hw: pointer to the hardware structure
410  * @vsi_id: vsi fw index
411  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
412  * @lut: pointer to the lut buffer provided by the caller
413  * @lut_size: size of the lut buffer
414  * @set: set TRUE to set the table, FALSE to get the table
415  *
416  * Internal function to get or set RSS look up table
417  **/
i40e_aq_get_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size,bool set)418 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
419 						     u16 vsi_id, bool pf_lut,
420 						     u8 *lut, u16 lut_size,
421 						     bool set)
422 {
423 	enum i40e_status_code status;
424 	struct i40e_aq_desc desc;
425 	struct i40e_aqc_get_set_rss_lut *cmd_resp =
426 		   (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
427 
428 	if (set)
429 		i40e_fill_default_direct_cmd_desc(&desc,
430 						  i40e_aqc_opc_set_rss_lut);
431 	else
432 		i40e_fill_default_direct_cmd_desc(&desc,
433 						  i40e_aqc_opc_get_rss_lut);
434 
435 	/* Indirect command */
436 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
437 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
438 
439 	cmd_resp->vsi_id =
440 			CPU_TO_LE16((u16)((vsi_id <<
441 					  I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
442 					  I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
443 	cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
444 
445 	if (pf_lut)
446 		cmd_resp->flags |= CPU_TO_LE16((u16)
447 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
448 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
449 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
450 	else
451 		cmd_resp->flags |= CPU_TO_LE16((u16)
452 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
453 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
454 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
455 
456 	status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
457 
458 	return status;
459 }
460 
461 /**
462  * i40e_aq_get_rss_lut
463  * @hw: pointer to the hardware structure
464  * @vsi_id: vsi fw index
465  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
466  * @lut: pointer to the lut buffer provided by the caller
467  * @lut_size: size of the lut buffer
468  *
469  * get the RSS lookup table, PF or VSI type
470  **/
i40e_aq_get_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)471 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
472 					  bool pf_lut, u8 *lut, u16 lut_size)
473 {
474 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
475 				       FALSE);
476 }
477 
478 /**
479  * i40e_aq_set_rss_lut
480  * @hw: pointer to the hardware structure
481  * @vsi_id: vsi fw index
482  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
483  * @lut: pointer to the lut buffer provided by the caller
484  * @lut_size: size of the lut buffer
485  *
486  * set the RSS lookup table, PF or VSI type
487  **/
i40e_aq_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)488 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
489 					  bool pf_lut, u8 *lut, u16 lut_size)
490 {
491 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
492 }
493 
494 /**
495  * i40e_aq_get_set_rss_key
496  * @hw: pointer to the hw struct
497  * @vsi_id: vsi fw index
498  * @key: pointer to key info struct
499  * @set: set TRUE to set the key, FALSE to get the key
500  *
501  * get the RSS key per VSI
502  **/
i40e_aq_get_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key,bool set)503 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
504 				      u16 vsi_id,
505 				      struct i40e_aqc_get_set_rss_key_data *key,
506 				      bool set)
507 {
508 	enum i40e_status_code status;
509 	struct i40e_aq_desc desc;
510 	struct i40e_aqc_get_set_rss_key *cmd_resp =
511 			(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
512 	u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
513 
514 	if (set)
515 		i40e_fill_default_direct_cmd_desc(&desc,
516 						  i40e_aqc_opc_set_rss_key);
517 	else
518 		i40e_fill_default_direct_cmd_desc(&desc,
519 						  i40e_aqc_opc_get_rss_key);
520 
521 	/* Indirect command */
522 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
523 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
524 
525 	cmd_resp->vsi_id =
526 			CPU_TO_LE16((u16)((vsi_id <<
527 					  I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
528 					  I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
529 	cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
530 
531 	status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
532 
533 	return status;
534 }
535 
536 /**
537  * i40e_aq_get_rss_key
538  * @hw: pointer to the hw struct
539  * @vsi_id: vsi fw index
540  * @key: pointer to key info struct
541  *
542  **/
i40e_aq_get_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)543 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
544 				      u16 vsi_id,
545 				      struct i40e_aqc_get_set_rss_key_data *key)
546 {
547 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
548 }
549 
550 /**
551  * i40e_aq_set_rss_key
552  * @hw: pointer to the hw struct
553  * @vsi_id: vsi fw index
554  * @key: pointer to key info struct
555  *
556  * set the RSS key per VSI
557  **/
i40e_aq_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)558 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
559 				      u16 vsi_id,
560 				      struct i40e_aqc_get_set_rss_key_data *key)
561 {
562 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
563 }
564 
565 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
566  * hardware to a bit-field that can be used by SW to more easily determine the
567  * packet type.
568  *
569  * Macros are used to shorten the table lines and make this table human
570  * readable.
571  *
572  * We store the PTYPE in the top byte of the bit field - this is just so that
573  * we can check that the table doesn't have a row missing, as the index into
574  * the table should be the PTYPE.
575  *
576  * Typical work flow:
577  *
578  * IF NOT i40e_ptype_lookup[ptype].known
579  * THEN
580  *      Packet is unknown
581  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
582  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
583  * ELSE
584  *      Use the enum i40e_rx_l2_ptype to decode the packet type
585  * ENDIF
586  */
587 
588 /* macro to make the table lines short */
589 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
590 	{	PTYPE, \
591 		1, \
592 		I40E_RX_PTYPE_OUTER_##OUTER_IP, \
593 		I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
594 		I40E_RX_PTYPE_##OUTER_FRAG, \
595 		I40E_RX_PTYPE_TUNNEL_##T, \
596 		I40E_RX_PTYPE_TUNNEL_END_##TE, \
597 		I40E_RX_PTYPE_##TEF, \
598 		I40E_RX_PTYPE_INNER_PROT_##I, \
599 		I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
600 
601 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
602 		{ PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
603 
604 /* shorter macros makes the table fit but are terse */
605 #define I40E_RX_PTYPE_NOF		I40E_RX_PTYPE_NOT_FRAG
606 #define I40E_RX_PTYPE_FRG		I40E_RX_PTYPE_FRAG
607 #define I40E_RX_PTYPE_INNER_PROT_TS	I40E_RX_PTYPE_INNER_PROT_TIMESYNC
608 
609 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
610 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
611 	/* L2 Packet types */
612 	I40E_PTT_UNUSED_ENTRY(0),
613 	I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
614 	I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
615 	I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
616 	I40E_PTT_UNUSED_ENTRY(4),
617 	I40E_PTT_UNUSED_ENTRY(5),
618 	I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
619 	I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
620 	I40E_PTT_UNUSED_ENTRY(8),
621 	I40E_PTT_UNUSED_ENTRY(9),
622 	I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
623 	I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
624 	I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
625 	I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
626 	I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
627 	I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
628 	I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
629 	I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
630 	I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
631 	I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
632 	I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
633 	I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
634 
635 	/* Non Tunneled IPv4 */
636 	I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
637 	I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
638 	I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
639 	I40E_PTT_UNUSED_ENTRY(25),
640 	I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
641 	I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
642 	I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
643 
644 	/* IPv4 --> IPv4 */
645 	I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
646 	I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
647 	I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
648 	I40E_PTT_UNUSED_ENTRY(32),
649 	I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
650 	I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
651 	I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
652 
653 	/* IPv4 --> IPv6 */
654 	I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
655 	I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
656 	I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
657 	I40E_PTT_UNUSED_ENTRY(39),
658 	I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
659 	I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
660 	I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
661 
662 	/* IPv4 --> GRE/NAT */
663 	I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
664 
665 	/* IPv4 --> GRE/NAT --> IPv4 */
666 	I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
667 	I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
668 	I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
669 	I40E_PTT_UNUSED_ENTRY(47),
670 	I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
671 	I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
672 	I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
673 
674 	/* IPv4 --> GRE/NAT --> IPv6 */
675 	I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
676 	I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
677 	I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
678 	I40E_PTT_UNUSED_ENTRY(54),
679 	I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
680 	I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
681 	I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
682 
683 	/* IPv4 --> GRE/NAT --> MAC */
684 	I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
685 
686 	/* IPv4 --> GRE/NAT --> MAC --> IPv4 */
687 	I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
688 	I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
689 	I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
690 	I40E_PTT_UNUSED_ENTRY(62),
691 	I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
692 	I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
693 	I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
694 
695 	/* IPv4 --> GRE/NAT -> MAC --> IPv6 */
696 	I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
697 	I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
698 	I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
699 	I40E_PTT_UNUSED_ENTRY(69),
700 	I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
701 	I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
702 	I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
703 
704 	/* IPv4 --> GRE/NAT --> MAC/VLAN */
705 	I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
706 
707 	/* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
708 	I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
709 	I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
710 	I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
711 	I40E_PTT_UNUSED_ENTRY(77),
712 	I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
713 	I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
714 	I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
715 
716 	/* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
717 	I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
718 	I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
719 	I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
720 	I40E_PTT_UNUSED_ENTRY(84),
721 	I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
722 	I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
723 	I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
724 
725 	/* Non Tunneled IPv6 */
726 	I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
727 	I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
728 	I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
729 	I40E_PTT_UNUSED_ENTRY(91),
730 	I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
731 	I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
732 	I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
733 
734 	/* IPv6 --> IPv4 */
735 	I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
736 	I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
737 	I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
738 	I40E_PTT_UNUSED_ENTRY(98),
739 	I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
740 	I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
741 	I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
742 
743 	/* IPv6 --> IPv6 */
744 	I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
745 	I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
746 	I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
747 	I40E_PTT_UNUSED_ENTRY(105),
748 	I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
749 	I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
750 	I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
751 
752 	/* IPv6 --> GRE/NAT */
753 	I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
754 
755 	/* IPv6 --> GRE/NAT -> IPv4 */
756 	I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
757 	I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
758 	I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
759 	I40E_PTT_UNUSED_ENTRY(113),
760 	I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
761 	I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
762 	I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
763 
764 	/* IPv6 --> GRE/NAT -> IPv6 */
765 	I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
766 	I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
767 	I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
768 	I40E_PTT_UNUSED_ENTRY(120),
769 	I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
770 	I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
771 	I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
772 
773 	/* IPv6 --> GRE/NAT -> MAC */
774 	I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
775 
776 	/* IPv6 --> GRE/NAT -> MAC -> IPv4 */
777 	I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
778 	I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
779 	I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
780 	I40E_PTT_UNUSED_ENTRY(128),
781 	I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
782 	I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
783 	I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
784 
785 	/* IPv6 --> GRE/NAT -> MAC -> IPv6 */
786 	I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
787 	I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
788 	I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
789 	I40E_PTT_UNUSED_ENTRY(135),
790 	I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
791 	I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
792 	I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
793 
794 	/* IPv6 --> GRE/NAT -> MAC/VLAN */
795 	I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
796 
797 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
798 	I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
799 	I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
800 	I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
801 	I40E_PTT_UNUSED_ENTRY(143),
802 	I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
803 	I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
804 	I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
805 
806 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
807 	I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
808 	I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
809 	I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
810 	I40E_PTT_UNUSED_ENTRY(150),
811 	I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
812 	I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
813 	I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
814 
815 	/* unused entries */
816 	I40E_PTT_UNUSED_ENTRY(154),
817 	I40E_PTT_UNUSED_ENTRY(155),
818 	I40E_PTT_UNUSED_ENTRY(156),
819 	I40E_PTT_UNUSED_ENTRY(157),
820 	I40E_PTT_UNUSED_ENTRY(158),
821 	I40E_PTT_UNUSED_ENTRY(159),
822 
823 	I40E_PTT_UNUSED_ENTRY(160),
824 	I40E_PTT_UNUSED_ENTRY(161),
825 	I40E_PTT_UNUSED_ENTRY(162),
826 	I40E_PTT_UNUSED_ENTRY(163),
827 	I40E_PTT_UNUSED_ENTRY(164),
828 	I40E_PTT_UNUSED_ENTRY(165),
829 	I40E_PTT_UNUSED_ENTRY(166),
830 	I40E_PTT_UNUSED_ENTRY(167),
831 	I40E_PTT_UNUSED_ENTRY(168),
832 	I40E_PTT_UNUSED_ENTRY(169),
833 
834 	I40E_PTT_UNUSED_ENTRY(170),
835 	I40E_PTT_UNUSED_ENTRY(171),
836 	I40E_PTT_UNUSED_ENTRY(172),
837 	I40E_PTT_UNUSED_ENTRY(173),
838 	I40E_PTT_UNUSED_ENTRY(174),
839 	I40E_PTT_UNUSED_ENTRY(175),
840 	I40E_PTT_UNUSED_ENTRY(176),
841 	I40E_PTT_UNUSED_ENTRY(177),
842 	I40E_PTT_UNUSED_ENTRY(178),
843 	I40E_PTT_UNUSED_ENTRY(179),
844 
845 	I40E_PTT_UNUSED_ENTRY(180),
846 	I40E_PTT_UNUSED_ENTRY(181),
847 	I40E_PTT_UNUSED_ENTRY(182),
848 	I40E_PTT_UNUSED_ENTRY(183),
849 	I40E_PTT_UNUSED_ENTRY(184),
850 	I40E_PTT_UNUSED_ENTRY(185),
851 	I40E_PTT_UNUSED_ENTRY(186),
852 	I40E_PTT_UNUSED_ENTRY(187),
853 	I40E_PTT_UNUSED_ENTRY(188),
854 	I40E_PTT_UNUSED_ENTRY(189),
855 
856 	I40E_PTT_UNUSED_ENTRY(190),
857 	I40E_PTT_UNUSED_ENTRY(191),
858 	I40E_PTT_UNUSED_ENTRY(192),
859 	I40E_PTT_UNUSED_ENTRY(193),
860 	I40E_PTT_UNUSED_ENTRY(194),
861 	I40E_PTT_UNUSED_ENTRY(195),
862 	I40E_PTT_UNUSED_ENTRY(196),
863 	I40E_PTT_UNUSED_ENTRY(197),
864 	I40E_PTT_UNUSED_ENTRY(198),
865 	I40E_PTT_UNUSED_ENTRY(199),
866 
867 	I40E_PTT_UNUSED_ENTRY(200),
868 	I40E_PTT_UNUSED_ENTRY(201),
869 	I40E_PTT_UNUSED_ENTRY(202),
870 	I40E_PTT_UNUSED_ENTRY(203),
871 	I40E_PTT_UNUSED_ENTRY(204),
872 	I40E_PTT_UNUSED_ENTRY(205),
873 	I40E_PTT_UNUSED_ENTRY(206),
874 	I40E_PTT_UNUSED_ENTRY(207),
875 	I40E_PTT_UNUSED_ENTRY(208),
876 	I40E_PTT_UNUSED_ENTRY(209),
877 
878 	I40E_PTT_UNUSED_ENTRY(210),
879 	I40E_PTT_UNUSED_ENTRY(211),
880 	I40E_PTT_UNUSED_ENTRY(212),
881 	I40E_PTT_UNUSED_ENTRY(213),
882 	I40E_PTT_UNUSED_ENTRY(214),
883 	I40E_PTT_UNUSED_ENTRY(215),
884 	I40E_PTT_UNUSED_ENTRY(216),
885 	I40E_PTT_UNUSED_ENTRY(217),
886 	I40E_PTT_UNUSED_ENTRY(218),
887 	I40E_PTT_UNUSED_ENTRY(219),
888 
889 	I40E_PTT_UNUSED_ENTRY(220),
890 	I40E_PTT_UNUSED_ENTRY(221),
891 	I40E_PTT_UNUSED_ENTRY(222),
892 	I40E_PTT_UNUSED_ENTRY(223),
893 	I40E_PTT_UNUSED_ENTRY(224),
894 	I40E_PTT_UNUSED_ENTRY(225),
895 	I40E_PTT_UNUSED_ENTRY(226),
896 	I40E_PTT_UNUSED_ENTRY(227),
897 	I40E_PTT_UNUSED_ENTRY(228),
898 	I40E_PTT_UNUSED_ENTRY(229),
899 
900 	I40E_PTT_UNUSED_ENTRY(230),
901 	I40E_PTT_UNUSED_ENTRY(231),
902 	I40E_PTT_UNUSED_ENTRY(232),
903 	I40E_PTT_UNUSED_ENTRY(233),
904 	I40E_PTT_UNUSED_ENTRY(234),
905 	I40E_PTT_UNUSED_ENTRY(235),
906 	I40E_PTT_UNUSED_ENTRY(236),
907 	I40E_PTT_UNUSED_ENTRY(237),
908 	I40E_PTT_UNUSED_ENTRY(238),
909 	I40E_PTT_UNUSED_ENTRY(239),
910 
911 	I40E_PTT_UNUSED_ENTRY(240),
912 	I40E_PTT_UNUSED_ENTRY(241),
913 	I40E_PTT_UNUSED_ENTRY(242),
914 	I40E_PTT_UNUSED_ENTRY(243),
915 	I40E_PTT_UNUSED_ENTRY(244),
916 	I40E_PTT_UNUSED_ENTRY(245),
917 	I40E_PTT_UNUSED_ENTRY(246),
918 	I40E_PTT_UNUSED_ENTRY(247),
919 	I40E_PTT_UNUSED_ENTRY(248),
920 	I40E_PTT_UNUSED_ENTRY(249),
921 
922 	I40E_PTT_UNUSED_ENTRY(250),
923 	I40E_PTT_UNUSED_ENTRY(251),
924 	I40E_PTT_UNUSED_ENTRY(252),
925 	I40E_PTT_UNUSED_ENTRY(253),
926 	I40E_PTT_UNUSED_ENTRY(254),
927 	I40E_PTT_UNUSED_ENTRY(255)
928 };
929 
930 
931 /**
932  * i40e_validate_mac_addr - Validate unicast MAC address
933  * @mac_addr: pointer to MAC address
934  *
935  * Tests a MAC address to ensure it is a valid Individual Address
936  **/
i40e_validate_mac_addr(u8 * mac_addr)937 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
938 {
939 	enum i40e_status_code status = I40E_SUCCESS;
940 
941 	DEBUGFUNC("i40e_validate_mac_addr");
942 
943 	/* Broadcast addresses ARE multicast addresses
944 	 * Make sure it is not a multicast address
945 	 * Reject the zero address
946 	 */
947 	if (I40E_IS_MULTICAST(mac_addr) ||
948 	    (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
949 	      mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
950 		status = I40E_ERR_INVALID_MAC_ADDR;
951 
952 	return status;
953 }
954 
955 /**
956  * i40e_init_shared_code - Initialize the shared code
957  * @hw: pointer to hardware structure
958  *
959  * This assigns the MAC type and PHY code and inits the NVM.
960  * Does not touch the hardware. This function must be called prior to any
961  * other function in the shared code. The i40e_hw structure should be
962  * memset to 0 prior to calling this function.  The following fields in
963  * hw structure should be filled in prior to calling this function:
964  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
965  * subsystem_vendor_id, and revision_id
966  **/
i40e_init_shared_code(struct i40e_hw * hw)967 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
968 {
969 	enum i40e_status_code status = I40E_SUCCESS;
970 	u32 port, ari, func_rid;
971 
972 	DEBUGFUNC("i40e_init_shared_code");
973 
974 	i40e_set_mac_type(hw);
975 
976 	switch (hw->mac.type) {
977 	case I40E_MAC_XL710:
978 	case I40E_MAC_X722:
979 		break;
980 	default:
981 		return I40E_ERR_DEVICE_NOT_SUPPORTED;
982 	}
983 
984 	hw->phy.get_link_info = TRUE;
985 
986 	/* Determine port number and PF number*/
987 	port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
988 					   >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
989 	hw->port = (u8)port;
990 	ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
991 						 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
992 	func_rid = rd32(hw, I40E_PF_FUNC_RID);
993 	if (ari)
994 		hw->pf_id = (u8)(func_rid & 0xff);
995 	else
996 		hw->pf_id = (u8)(func_rid & 0x7);
997 
998 	if (hw->mac.type == I40E_MAC_X722)
999 		hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1000 
1001 	status = i40e_init_nvm(hw);
1002 	return status;
1003 }
1004 
1005 /**
1006  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1007  * @hw: pointer to the hw struct
1008  * @flags: a return indicator of what addresses were added to the addr store
1009  * @addrs: the requestor's mac addr store
1010  * @cmd_details: pointer to command details structure or NULL
1011  **/
i40e_aq_mac_address_read(struct i40e_hw * hw,u16 * flags,struct i40e_aqc_mac_address_read_data * addrs,struct i40e_asq_cmd_details * cmd_details)1012 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1013 				   u16 *flags,
1014 				   struct i40e_aqc_mac_address_read_data *addrs,
1015 				   struct i40e_asq_cmd_details *cmd_details)
1016 {
1017 	struct i40e_aq_desc desc;
1018 	struct i40e_aqc_mac_address_read *cmd_data =
1019 		(struct i40e_aqc_mac_address_read *)&desc.params.raw;
1020 	enum i40e_status_code status;
1021 
1022 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1023 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1024 
1025 	status = i40e_asq_send_command(hw, &desc, addrs,
1026 				       sizeof(*addrs), cmd_details);
1027 	*flags = LE16_TO_CPU(cmd_data->command_flags);
1028 
1029 	return status;
1030 }
1031 
1032 /**
1033  * i40e_aq_mac_address_write - Change the MAC addresses
1034  * @hw: pointer to the hw struct
1035  * @flags: indicates which MAC to be written
1036  * @mac_addr: address to write
1037  * @cmd_details: pointer to command details structure or NULL
1038  **/
i40e_aq_mac_address_write(struct i40e_hw * hw,u16 flags,u8 * mac_addr,struct i40e_asq_cmd_details * cmd_details)1039 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1040 				    u16 flags, u8 *mac_addr,
1041 				    struct i40e_asq_cmd_details *cmd_details)
1042 {
1043 	struct i40e_aq_desc desc;
1044 	struct i40e_aqc_mac_address_write *cmd_data =
1045 		(struct i40e_aqc_mac_address_write *)&desc.params.raw;
1046 	enum i40e_status_code status;
1047 
1048 	i40e_fill_default_direct_cmd_desc(&desc,
1049 					  i40e_aqc_opc_mac_address_write);
1050 	cmd_data->command_flags = CPU_TO_LE16(flags);
1051 	cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1052 	cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1053 					((u32)mac_addr[3] << 16) |
1054 					((u32)mac_addr[4] << 8) |
1055 					mac_addr[5]);
1056 
1057 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1058 
1059 	return status;
1060 }
1061 
1062 /**
1063  * i40e_get_mac_addr - get MAC address
1064  * @hw: pointer to the HW structure
1065  * @mac_addr: pointer to MAC address
1066  *
1067  * Reads the adapter's MAC address from register
1068  **/
i40e_get_mac_addr(struct i40e_hw * hw,u8 * mac_addr)1069 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1070 {
1071 	struct i40e_aqc_mac_address_read_data addrs;
1072 	enum i40e_status_code status;
1073 	u16 flags = 0;
1074 
1075 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1076 
1077 	if (flags & I40E_AQC_LAN_ADDR_VALID)
1078 		i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1079 			I40E_NONDMA_TO_NONDMA);
1080 
1081 	return status;
1082 }
1083 
1084 /**
1085  * i40e_get_port_mac_addr - get Port MAC address
1086  * @hw: pointer to the HW structure
1087  * @mac_addr: pointer to Port MAC address
1088  *
1089  * Reads the adapter's Port MAC address
1090  **/
i40e_get_port_mac_addr(struct i40e_hw * hw,u8 * mac_addr)1091 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1092 {
1093 	struct i40e_aqc_mac_address_read_data addrs;
1094 	enum i40e_status_code status;
1095 	u16 flags = 0;
1096 
1097 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1098 	if (status)
1099 		return status;
1100 
1101 	if (flags & I40E_AQC_PORT_ADDR_VALID)
1102 		i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1103 			I40E_NONDMA_TO_NONDMA);
1104 	else
1105 		status = I40E_ERR_INVALID_MAC_ADDR;
1106 
1107 	return status;
1108 }
1109 
1110 /**
1111  * i40e_pre_tx_queue_cfg - pre tx queue configure
1112  * @hw: pointer to the HW structure
1113  * @queue: target pf queue index
1114  * @enable: state change request
1115  *
1116  * Handles hw requirement to indicate intention to enable
1117  * or disable target queue.
1118  **/
i40e_pre_tx_queue_cfg(struct i40e_hw * hw,u32 queue,bool enable)1119 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1120 {
1121 	u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1122 	u32 reg_block = 0;
1123 	u32 reg_val;
1124 
1125 	if (abs_queue_idx >= 128) {
1126 		reg_block = abs_queue_idx / 128;
1127 		abs_queue_idx %= 128;
1128 	}
1129 
1130 	reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1131 	reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1132 	reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1133 
1134 	if (enable)
1135 		reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1136 	else
1137 		reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1138 
1139 	wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1140 }
1141 
1142 /**
1143  *  i40e_read_pba_string - Reads part number string from EEPROM
1144  *  @hw: pointer to hardware structure
1145  *  @pba_num: stores the part number string from the EEPROM
1146  *  @pba_num_size: part number string buffer length
1147  *
1148  *  Reads the part number string from the EEPROM.
1149  **/
i40e_read_pba_string(struct i40e_hw * hw,u8 * pba_num,u32 pba_num_size)1150 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1151 					    u32 pba_num_size)
1152 {
1153 	enum i40e_status_code status = I40E_SUCCESS;
1154 	u16 pba_word = 0;
1155 	u16 pba_size = 0;
1156 	u16 pba_ptr = 0;
1157 	u16 i = 0;
1158 
1159 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1160 	if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1161 		DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1162 		return status;
1163 	}
1164 
1165 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1166 	if (status != I40E_SUCCESS) {
1167 		DEBUGOUT("Failed to read PBA Block pointer.\n");
1168 		return status;
1169 	}
1170 
1171 	status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1172 	if (status != I40E_SUCCESS) {
1173 		DEBUGOUT("Failed to read PBA Block size.\n");
1174 		return status;
1175 	}
1176 
1177 	/* Subtract one to get PBA word count (PBA Size word is included in
1178 	 * total size)
1179 	 */
1180 	pba_size--;
1181 	if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1182 		DEBUGOUT("Buffer to small for PBA data.\n");
1183 		return I40E_ERR_PARAM;
1184 	}
1185 
1186 	for (i = 0; i < pba_size; i++) {
1187 		status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1188 		if (status != I40E_SUCCESS) {
1189 			DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1190 			return status;
1191 		}
1192 
1193 		pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1194 		pba_num[(i * 2) + 1] = pba_word & 0xFF;
1195 	}
1196 	pba_num[(pba_size * 2)] = '\0';
1197 
1198 	return status;
1199 }
1200 
1201 /**
1202  * i40e_get_media_type - Gets media type
1203  * @hw: pointer to the hardware structure
1204  **/
i40e_get_media_type(struct i40e_hw * hw)1205 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1206 {
1207 	enum i40e_media_type media;
1208 
1209 	switch (hw->phy.link_info.phy_type) {
1210 	case I40E_PHY_TYPE_10GBASE_SR:
1211 	case I40E_PHY_TYPE_10GBASE_LR:
1212 	case I40E_PHY_TYPE_1000BASE_SX:
1213 	case I40E_PHY_TYPE_1000BASE_LX:
1214 	case I40E_PHY_TYPE_40GBASE_SR4:
1215 	case I40E_PHY_TYPE_40GBASE_LR4:
1216 	case I40E_PHY_TYPE_25GBASE_LR:
1217 	case I40E_PHY_TYPE_25GBASE_SR:
1218 		media = I40E_MEDIA_TYPE_FIBER;
1219 		break;
1220 	case I40E_PHY_TYPE_100BASE_TX:
1221 	case I40E_PHY_TYPE_1000BASE_T:
1222 	case I40E_PHY_TYPE_10GBASE_T:
1223 		media = I40E_MEDIA_TYPE_BASET;
1224 		break;
1225 	case I40E_PHY_TYPE_10GBASE_CR1_CU:
1226 	case I40E_PHY_TYPE_40GBASE_CR4_CU:
1227 	case I40E_PHY_TYPE_10GBASE_CR1:
1228 	case I40E_PHY_TYPE_40GBASE_CR4:
1229 	case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1230 	case I40E_PHY_TYPE_40GBASE_AOC:
1231 	case I40E_PHY_TYPE_10GBASE_AOC:
1232 	case I40E_PHY_TYPE_25GBASE_CR:
1233 		media = I40E_MEDIA_TYPE_DA;
1234 		break;
1235 	case I40E_PHY_TYPE_1000BASE_KX:
1236 	case I40E_PHY_TYPE_10GBASE_KX4:
1237 	case I40E_PHY_TYPE_10GBASE_KR:
1238 	case I40E_PHY_TYPE_40GBASE_KR4:
1239 	case I40E_PHY_TYPE_20GBASE_KR2:
1240 	case I40E_PHY_TYPE_25GBASE_KR:
1241 		media = I40E_MEDIA_TYPE_BACKPLANE;
1242 		break;
1243 	case I40E_PHY_TYPE_SGMII:
1244 	case I40E_PHY_TYPE_XAUI:
1245 	case I40E_PHY_TYPE_XFI:
1246 	case I40E_PHY_TYPE_XLAUI:
1247 	case I40E_PHY_TYPE_XLPPI:
1248 	default:
1249 		media = I40E_MEDIA_TYPE_UNKNOWN;
1250 		break;
1251 	}
1252 
1253 	return media;
1254 }
1255 
1256 #define I40E_PF_RESET_WAIT_COUNT	200
1257 /**
1258  * i40e_pf_reset - Reset the PF
1259  * @hw: pointer to the hardware structure
1260  *
1261  * Assuming someone else has triggered a global reset,
1262  * assure the global reset is complete and then reset the PF
1263  **/
i40e_pf_reset(struct i40e_hw * hw)1264 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1265 {
1266 	u32 cnt = 0;
1267 	u32 cnt1 = 0;
1268 	u32 reg = 0;
1269 	u32 grst_del;
1270 
1271 	/* Poll for Global Reset steady state in case of recent GRST.
1272 	 * The grst delay value is in 100ms units, and we'll wait a
1273 	 * couple counts longer to be sure we don't just miss the end.
1274 	 */
1275 	grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1276 			I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1277 			I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1278 
1279 	grst_del = grst_del * 20;
1280 
1281 	for (cnt = 0; cnt < grst_del; cnt++) {
1282 		reg = rd32(hw, I40E_GLGEN_RSTAT);
1283 		if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1284 			break;
1285 		i40e_msec_delay(100);
1286 	}
1287 	if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1288 		DEBUGOUT("Global reset polling failed to complete.\n");
1289 		return I40E_ERR_RESET_FAILED;
1290 	}
1291 
1292 	/* Now Wait for the FW to be ready */
1293 	for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1294 		reg = rd32(hw, I40E_GLNVM_ULD);
1295 		reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1296 			I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1297 		if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1298 			    I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1299 			DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1300 			break;
1301 		}
1302 		i40e_msec_delay(10);
1303 	}
1304 	if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1305 		     I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1306 		DEBUGOUT("wait for FW Reset complete timedout\n");
1307 		DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1308 		return I40E_ERR_RESET_FAILED;
1309 	}
1310 
1311 	/* If there was a Global Reset in progress when we got here,
1312 	 * we don't need to do the PF Reset
1313 	 */
1314 	if (!cnt) {
1315 		reg = rd32(hw, I40E_PFGEN_CTRL);
1316 		wr32(hw, I40E_PFGEN_CTRL,
1317 		     (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1318 		for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1319 			reg = rd32(hw, I40E_PFGEN_CTRL);
1320 			if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1321 				break;
1322 			i40e_msec_delay(1);
1323 		}
1324 		if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1325 			DEBUGOUT("PF reset polling failed to complete.\n");
1326 			return I40E_ERR_RESET_FAILED;
1327 		}
1328 	}
1329 
1330 	i40e_clear_pxe_mode(hw);
1331 
1332 
1333 	return I40E_SUCCESS;
1334 }
1335 
1336 /**
1337  * i40e_clear_hw - clear out any left over hw state
1338  * @hw: pointer to the hw struct
1339  *
1340  * Clear queues and interrupts, typically called at init time,
1341  * but after the capabilities have been found so we know how many
1342  * queues and msix vectors have been allocated.
1343  **/
i40e_clear_hw(struct i40e_hw * hw)1344 void i40e_clear_hw(struct i40e_hw *hw)
1345 {
1346 	u32 num_queues, base_queue;
1347 	u32 num_pf_int;
1348 	u32 num_vf_int;
1349 	u32 num_vfs;
1350 	u32 i, j;
1351 	u32 val;
1352 	u32 eol = 0x7ff;
1353 
1354 	/* get number of interrupts, queues, and vfs */
1355 	val = rd32(hw, I40E_GLPCI_CNF2);
1356 	num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1357 			I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1358 	num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1359 			I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1360 
1361 	val = rd32(hw, I40E_PFLAN_QALLOC);
1362 	base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1363 			I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1364 	j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1365 			I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1366 	if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1367 		num_queues = (j - base_queue) + 1;
1368 	else
1369 		num_queues = 0;
1370 
1371 	val = rd32(hw, I40E_PF_VT_PFALLOC);
1372 	i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1373 			I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1374 	j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1375 			I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1376 	if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1377 		num_vfs = (j - i) + 1;
1378 	else
1379 		num_vfs = 0;
1380 
1381 	/* stop all the interrupts */
1382 	wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1383 	val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1384 	for (i = 0; i < num_pf_int - 2; i++)
1385 		wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1386 
1387 	/* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1388 	val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1389 	wr32(hw, I40E_PFINT_LNKLST0, val);
1390 	for (i = 0; i < num_pf_int - 2; i++)
1391 		wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1392 	val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1393 	for (i = 0; i < num_vfs; i++)
1394 		wr32(hw, I40E_VPINT_LNKLST0(i), val);
1395 	for (i = 0; i < num_vf_int - 2; i++)
1396 		wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1397 
1398 	/* warn the HW of the coming Tx disables */
1399 	for (i = 0; i < num_queues; i++) {
1400 		u32 abs_queue_idx = base_queue + i;
1401 		u32 reg_block = 0;
1402 
1403 		if (abs_queue_idx >= 128) {
1404 			reg_block = abs_queue_idx / 128;
1405 			abs_queue_idx %= 128;
1406 		}
1407 
1408 		val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1409 		val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1410 		val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1411 		val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1412 
1413 		wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1414 	}
1415 	i40e_usec_delay(400);
1416 
1417 	/* stop all the queues */
1418 	for (i = 0; i < num_queues; i++) {
1419 		wr32(hw, I40E_QINT_TQCTL(i), 0);
1420 		wr32(hw, I40E_QTX_ENA(i), 0);
1421 		wr32(hw, I40E_QINT_RQCTL(i), 0);
1422 		wr32(hw, I40E_QRX_ENA(i), 0);
1423 	}
1424 
1425 	/* short wait for all queue disables to settle */
1426 	i40e_usec_delay(50);
1427 }
1428 
1429 /**
1430  * i40e_clear_pxe_mode - clear pxe operations mode
1431  * @hw: pointer to the hw struct
1432  *
1433  * Make sure all PXE mode settings are cleared, including things
1434  * like descriptor fetch/write-back mode.
1435  **/
i40e_clear_pxe_mode(struct i40e_hw * hw)1436 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1437 {
1438 	if (i40e_check_asq_alive(hw))
1439 		i40e_aq_clear_pxe_mode(hw, NULL);
1440 }
1441 
1442 /**
1443  * i40e_led_is_mine - helper to find matching led
1444  * @hw: pointer to the hw struct
1445  * @idx: index into GPIO registers
1446  *
1447  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1448  */
i40e_led_is_mine(struct i40e_hw * hw,int idx)1449 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1450 {
1451 	u32 gpio_val = 0;
1452 	u32 port;
1453 
1454 	if (!hw->func_caps.led[idx])
1455 		return 0;
1456 
1457 	gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1458 	port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1459 		I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1460 
1461 	/* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1462 	 * if it is not our port then ignore
1463 	 */
1464 	if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1465 	    (port != hw->port))
1466 		return 0;
1467 
1468 	return gpio_val;
1469 }
1470 
1471 #define I40E_COMBINED_ACTIVITY 0xA
1472 #define I40E_FILTER_ACTIVITY 0xE
1473 #define I40E_LINK_ACTIVITY 0xC
1474 #define I40E_MAC_ACTIVITY 0xD
1475 #define I40E_LED0 22
1476 
1477 /**
1478  * i40e_led_get - return current on/off mode
1479  * @hw: pointer to the hw struct
1480  *
1481  * The value returned is the 'mode' field as defined in the
1482  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1483  * values are variations of possible behaviors relating to
1484  * blink, link, and wire.
1485  **/
i40e_led_get(struct i40e_hw * hw)1486 u32 i40e_led_get(struct i40e_hw *hw)
1487 {
1488 	u32 current_mode = 0;
1489 	u32 mode = 0;
1490 	int i;
1491 
1492 	/* as per the documentation GPIO 22-29 are the LED
1493 	 * GPIO pins named LED0..LED7
1494 	 */
1495 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1496 		u32 gpio_val = i40e_led_is_mine(hw, i);
1497 
1498 		if (!gpio_val)
1499 			continue;
1500 
1501 		/* ignore gpio LED src mode entries related to the activity
1502 		 *  LEDs
1503 		 */
1504 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1505 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1506 		switch (current_mode) {
1507 		case I40E_COMBINED_ACTIVITY:
1508 		case I40E_FILTER_ACTIVITY:
1509 		case I40E_MAC_ACTIVITY:
1510 			continue;
1511 		default:
1512 			break;
1513 		}
1514 
1515 		mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1516 			I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1517 		break;
1518 	}
1519 
1520 	return mode;
1521 }
1522 
1523 /**
1524  * i40e_led_set - set new on/off mode
1525  * @hw: pointer to the hw struct
1526  * @mode: 0=off, 0xf=on (else see manual for mode details)
1527  * @blink: TRUE if the LED should blink when on, FALSE if steady
1528  *
1529  * if this function is used to turn on the blink it should
1530  * be used to disable the blink when restoring the original state.
1531  **/
i40e_led_set(struct i40e_hw * hw,u32 mode,bool blink)1532 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1533 {
1534 	u32 current_mode = 0;
1535 	int i;
1536 
1537 	if (mode & 0xfffffff0)
1538 		DEBUGOUT1("invalid mode passed in %X\n", mode);
1539 
1540 	/* as per the documentation GPIO 22-29 are the LED
1541 	 * GPIO pins named LED0..LED7
1542 	 */
1543 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1544 		u32 gpio_val = i40e_led_is_mine(hw, i);
1545 
1546 		if (!gpio_val)
1547 			continue;
1548 
1549 		/* ignore gpio LED src mode entries related to the activity
1550 		 * LEDs
1551 		 */
1552 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1553 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1554 		switch (current_mode) {
1555 		case I40E_COMBINED_ACTIVITY:
1556 		case I40E_FILTER_ACTIVITY:
1557 		case I40E_MAC_ACTIVITY:
1558 			continue;
1559 		default:
1560 			break;
1561 		}
1562 
1563 		gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1564 		/* this & is a bit of paranoia, but serves as a range check */
1565 		gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1566 			     I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1567 
1568 		if (mode == I40E_LINK_ACTIVITY)
1569 			blink = FALSE;
1570 
1571 		if (blink)
1572 			gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1573 		else
1574 			gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1575 
1576 		wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1577 		break;
1578 	}
1579 }
1580 
1581 /* Admin command wrappers */
1582 
1583 /**
1584  * i40e_aq_get_phy_capabilities
1585  * @hw: pointer to the hw struct
1586  * @abilities: structure for PHY capabilities to be filled
1587  * @qualified_modules: report Qualified Modules
1588  * @report_init: report init capabilities (active are default)
1589  * @cmd_details: pointer to command details structure or NULL
1590  *
1591  * Returns the various PHY abilities supported on the Port.
1592  **/
i40e_aq_get_phy_capabilities(struct i40e_hw * hw,bool qualified_modules,bool report_init,struct i40e_aq_get_phy_abilities_resp * abilities,struct i40e_asq_cmd_details * cmd_details)1593 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1594 			bool qualified_modules, bool report_init,
1595 			struct i40e_aq_get_phy_abilities_resp *abilities,
1596 			struct i40e_asq_cmd_details *cmd_details)
1597 {
1598 	struct i40e_aq_desc desc;
1599 	enum i40e_status_code status;
1600 	u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1601 
1602 	if (!abilities)
1603 		return I40E_ERR_PARAM;
1604 
1605 	i40e_fill_default_direct_cmd_desc(&desc,
1606 					  i40e_aqc_opc_get_phy_abilities);
1607 
1608 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1609 	if (abilities_size > I40E_AQ_LARGE_BUF)
1610 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1611 
1612 	if (qualified_modules)
1613 		desc.params.external.param0 |=
1614 			CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1615 
1616 	if (report_init)
1617 		desc.params.external.param0 |=
1618 			CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1619 
1620 	status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1621 				    cmd_details);
1622 
1623 	if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1624 		status = I40E_ERR_UNKNOWN_PHY;
1625 
1626 	if (report_init) {
1627 		hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1628 		hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1629 	}
1630 
1631 	return status;
1632 }
1633 
1634 /**
1635  * i40e_aq_set_phy_config
1636  * @hw: pointer to the hw struct
1637  * @config: structure with PHY configuration to be set
1638  * @cmd_details: pointer to command details structure or NULL
1639  *
1640  * Set the various PHY configuration parameters
1641  * supported on the Port.One or more of the Set PHY config parameters may be
1642  * ignored in an MFP mode as the PF may not have the privilege to set some
1643  * of the PHY Config parameters. This status will be indicated by the
1644  * command response.
1645  **/
i40e_aq_set_phy_config(struct i40e_hw * hw,struct i40e_aq_set_phy_config * config,struct i40e_asq_cmd_details * cmd_details)1646 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1647 				struct i40e_aq_set_phy_config *config,
1648 				struct i40e_asq_cmd_details *cmd_details)
1649 {
1650 	struct i40e_aq_desc desc;
1651 	struct i40e_aq_set_phy_config *cmd =
1652 		(struct i40e_aq_set_phy_config *)&desc.params.raw;
1653 	enum i40e_status_code status;
1654 
1655 	if (!config)
1656 		return I40E_ERR_PARAM;
1657 
1658 	i40e_fill_default_direct_cmd_desc(&desc,
1659 					  i40e_aqc_opc_set_phy_config);
1660 
1661 	*cmd = *config;
1662 
1663 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1664 
1665 	return status;
1666 }
1667 
1668 /**
1669  * i40e_set_fc
1670  * @hw: pointer to the hw struct
1671  *
1672  * Set the requested flow control mode using set_phy_config.
1673  **/
i40e_set_fc(struct i40e_hw * hw,u8 * aq_failures,bool atomic_restart)1674 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1675 				  bool atomic_restart)
1676 {
1677 	enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1678 	struct i40e_aq_get_phy_abilities_resp abilities;
1679 	struct i40e_aq_set_phy_config config;
1680 	enum i40e_status_code status;
1681 	u8 pause_mask = 0x0;
1682 
1683 	*aq_failures = 0x0;
1684 
1685 	switch (fc_mode) {
1686 	case I40E_FC_FULL:
1687 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1688 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1689 		break;
1690 	case I40E_FC_RX_PAUSE:
1691 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1692 		break;
1693 	case I40E_FC_TX_PAUSE:
1694 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1695 		break;
1696 	default:
1697 		break;
1698 	}
1699 
1700 	/* Get the current phy config */
1701 	status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1702 					      NULL);
1703 	if (status) {
1704 		*aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1705 		return status;
1706 	}
1707 
1708 	memset(&config, 0, sizeof(config));
1709 	/* clear the old pause settings */
1710 	config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1711 			   ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1712 	/* set the new abilities */
1713 	config.abilities |= pause_mask;
1714 	/* If the abilities have changed, then set the new config */
1715 	if (config.abilities != abilities.abilities) {
1716 		/* Auto restart link so settings take effect */
1717 		if (atomic_restart)
1718 			config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1719 		/* Copy over all the old settings */
1720 		config.phy_type = abilities.phy_type;
1721 		config.phy_type_ext = abilities.phy_type_ext;
1722 		config.link_speed = abilities.link_speed;
1723 		config.eee_capability = abilities.eee_capability;
1724 		config.eeer = abilities.eeer_val;
1725 		config.low_power_ctrl = abilities.d3_lpan;
1726 		status = i40e_aq_set_phy_config(hw, &config, NULL);
1727 
1728 		if (status)
1729 			*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1730 	}
1731 	/* Update the link info */
1732 	status = i40e_update_link_info(hw);
1733 	if (status) {
1734 		/* Wait a little bit (on 40G cards it sometimes takes a really
1735 		 * long time for link to come back from the atomic reset)
1736 		 * and try once more
1737 		 */
1738 		i40e_msec_delay(1000);
1739 		status = i40e_update_link_info(hw);
1740 	}
1741 	if (status)
1742 		*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1743 
1744 	return status;
1745 }
1746 
1747 /**
1748  * i40e_aq_set_mac_config
1749  * @hw: pointer to the hw struct
1750  * @max_frame_size: Maximum Frame Size to be supported by the port
1751  * @crc_en: Tell HW to append a CRC to outgoing frames
1752  * @pacing: Pacing configurations
1753  * @cmd_details: pointer to command details structure or NULL
1754  *
1755  * Configure MAC settings for frame size, jumbo frame support and the
1756  * addition of a CRC by the hardware.
1757  **/
i40e_aq_set_mac_config(struct i40e_hw * hw,u16 max_frame_size,bool crc_en,u16 pacing,struct i40e_asq_cmd_details * cmd_details)1758 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1759 				u16 max_frame_size,
1760 				bool crc_en, u16 pacing,
1761 				struct i40e_asq_cmd_details *cmd_details)
1762 {
1763 	struct i40e_aq_desc desc;
1764 	struct i40e_aq_set_mac_config *cmd =
1765 		(struct i40e_aq_set_mac_config *)&desc.params.raw;
1766 	enum i40e_status_code status;
1767 
1768 	if (max_frame_size == 0)
1769 		return I40E_ERR_PARAM;
1770 
1771 	i40e_fill_default_direct_cmd_desc(&desc,
1772 					  i40e_aqc_opc_set_mac_config);
1773 
1774 	cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1775 	cmd->params = ((u8)pacing & 0x0F) << 3;
1776 	if (crc_en)
1777 		cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1778 
1779 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1780 
1781 	return status;
1782 }
1783 
1784 /**
1785  * i40e_aq_clear_pxe_mode
1786  * @hw: pointer to the hw struct
1787  * @cmd_details: pointer to command details structure or NULL
1788  *
1789  * Tell the firmware that the driver is taking over from PXE
1790  **/
i40e_aq_clear_pxe_mode(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)1791 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1792 			struct i40e_asq_cmd_details *cmd_details)
1793 {
1794 	enum i40e_status_code status;
1795 	struct i40e_aq_desc desc;
1796 	struct i40e_aqc_clear_pxe *cmd =
1797 		(struct i40e_aqc_clear_pxe *)&desc.params.raw;
1798 
1799 	i40e_fill_default_direct_cmd_desc(&desc,
1800 					  i40e_aqc_opc_clear_pxe_mode);
1801 
1802 	cmd->rx_cnt = 0x2;
1803 
1804 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1805 
1806 	wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1807 
1808 	return status;
1809 }
1810 
1811 /**
1812  * i40e_aq_set_link_restart_an
1813  * @hw: pointer to the hw struct
1814  * @enable_link: if TRUE: enable link, if FALSE: disable link
1815  * @cmd_details: pointer to command details structure or NULL
1816  *
1817  * Sets up the link and restarts the Auto-Negotiation over the link.
1818  **/
i40e_aq_set_link_restart_an(struct i40e_hw * hw,bool enable_link,struct i40e_asq_cmd_details * cmd_details)1819 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1820 		bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1821 {
1822 	struct i40e_aq_desc desc;
1823 	struct i40e_aqc_set_link_restart_an *cmd =
1824 		(struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1825 	enum i40e_status_code status;
1826 
1827 	i40e_fill_default_direct_cmd_desc(&desc,
1828 					  i40e_aqc_opc_set_link_restart_an);
1829 
1830 	cmd->command = I40E_AQ_PHY_RESTART_AN;
1831 	if (enable_link)
1832 		cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1833 	else
1834 		cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1835 
1836 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1837 
1838 	return status;
1839 }
1840 
1841 /**
1842  * i40e_aq_get_link_info
1843  * @hw: pointer to the hw struct
1844  * @enable_lse: enable/disable LinkStatusEvent reporting
1845  * @link: pointer to link status structure - optional
1846  * @cmd_details: pointer to command details structure or NULL
1847  *
1848  * Returns the link status of the adapter.
1849  **/
i40e_aq_get_link_info(struct i40e_hw * hw,bool enable_lse,struct i40e_link_status * link,struct i40e_asq_cmd_details * cmd_details)1850 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1851 				bool enable_lse, struct i40e_link_status *link,
1852 				struct i40e_asq_cmd_details *cmd_details)
1853 {
1854 	struct i40e_aq_desc desc;
1855 	struct i40e_aqc_get_link_status *resp =
1856 		(struct i40e_aqc_get_link_status *)&desc.params.raw;
1857 	struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1858 	enum i40e_status_code status;
1859 	bool tx_pause, rx_pause;
1860 	u16 command_flags;
1861 
1862 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1863 
1864 	if (enable_lse)
1865 		command_flags = I40E_AQ_LSE_ENABLE;
1866 	else
1867 		command_flags = I40E_AQ_LSE_DISABLE;
1868 	resp->command_flags = CPU_TO_LE16(command_flags);
1869 
1870 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1871 
1872 	if (status != I40E_SUCCESS)
1873 		goto aq_get_link_info_exit;
1874 
1875 	/* save off old link status information */
1876 	i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1877 		    sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1878 
1879 	/* update link status */
1880 	hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1881 	hw->phy.media_type = i40e_get_media_type(hw);
1882 	hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1883 	hw_link_info->link_info = resp->link_info;
1884 	hw_link_info->an_info = resp->an_info;
1885 	hw_link_info->ext_info = resp->ext_info;
1886 	hw_link_info->loopback = resp->loopback;
1887 	hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1888 	hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1889 
1890 	/* update fc info */
1891 	tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1892 	rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1893 	if (tx_pause & rx_pause)
1894 		hw->fc.current_mode = I40E_FC_FULL;
1895 	else if (tx_pause)
1896 		hw->fc.current_mode = I40E_FC_TX_PAUSE;
1897 	else if (rx_pause)
1898 		hw->fc.current_mode = I40E_FC_RX_PAUSE;
1899 	else
1900 		hw->fc.current_mode = I40E_FC_NONE;
1901 
1902 	if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1903 		hw_link_info->crc_enable = TRUE;
1904 	else
1905 		hw_link_info->crc_enable = FALSE;
1906 
1907 	if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1908 		hw_link_info->lse_enable = TRUE;
1909 	else
1910 		hw_link_info->lse_enable = FALSE;
1911 
1912 	if ((hw->mac.type == I40E_MAC_XL710) &&
1913 	    (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1914 	     hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1915 		hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1916 
1917 	/* save link status information */
1918 	if (link)
1919 		i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1920 			    I40E_NONDMA_TO_NONDMA);
1921 
1922 	/* flag cleared so helper functions don't call AQ again */
1923 	hw->phy.get_link_info = FALSE;
1924 
1925 aq_get_link_info_exit:
1926 	return status;
1927 }
1928 
1929 /**
1930  * i40e_aq_set_phy_int_mask
1931  * @hw: pointer to the hw struct
1932  * @mask: interrupt mask to be set
1933  * @cmd_details: pointer to command details structure or NULL
1934  *
1935  * Set link interrupt mask.
1936  **/
i40e_aq_set_phy_int_mask(struct i40e_hw * hw,u16 mask,struct i40e_asq_cmd_details * cmd_details)1937 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1938 				u16 mask,
1939 				struct i40e_asq_cmd_details *cmd_details)
1940 {
1941 	struct i40e_aq_desc desc;
1942 	struct i40e_aqc_set_phy_int_mask *cmd =
1943 		(struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1944 	enum i40e_status_code status;
1945 
1946 	i40e_fill_default_direct_cmd_desc(&desc,
1947 					  i40e_aqc_opc_set_phy_int_mask);
1948 
1949 	cmd->event_mask = CPU_TO_LE16(mask);
1950 
1951 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1952 
1953 	return status;
1954 }
1955 
1956 /**
1957  * i40e_aq_get_local_advt_reg
1958  * @hw: pointer to the hw struct
1959  * @advt_reg: local AN advertisement register value
1960  * @cmd_details: pointer to command details structure or NULL
1961  *
1962  * Get the Local AN advertisement register value.
1963  **/
i40e_aq_get_local_advt_reg(struct i40e_hw * hw,u64 * advt_reg,struct i40e_asq_cmd_details * cmd_details)1964 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
1965 				u64 *advt_reg,
1966 				struct i40e_asq_cmd_details *cmd_details)
1967 {
1968 	struct i40e_aq_desc desc;
1969 	struct i40e_aqc_an_advt_reg *resp =
1970 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
1971 	enum i40e_status_code status;
1972 
1973 	i40e_fill_default_direct_cmd_desc(&desc,
1974 					  i40e_aqc_opc_get_local_advt_reg);
1975 
1976 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1977 
1978 	if (status != I40E_SUCCESS)
1979 		goto aq_get_local_advt_reg_exit;
1980 
1981 	*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
1982 	*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
1983 
1984 aq_get_local_advt_reg_exit:
1985 	return status;
1986 }
1987 
1988 /**
1989  * i40e_aq_set_local_advt_reg
1990  * @hw: pointer to the hw struct
1991  * @advt_reg: local AN advertisement register value
1992  * @cmd_details: pointer to command details structure or NULL
1993  *
1994  * Get the Local AN advertisement register value.
1995  **/
i40e_aq_set_local_advt_reg(struct i40e_hw * hw,u64 advt_reg,struct i40e_asq_cmd_details * cmd_details)1996 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
1997 				u64 advt_reg,
1998 				struct i40e_asq_cmd_details *cmd_details)
1999 {
2000 	struct i40e_aq_desc desc;
2001 	struct i40e_aqc_an_advt_reg *cmd =
2002 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2003 	enum i40e_status_code status;
2004 
2005 	i40e_fill_default_direct_cmd_desc(&desc,
2006 					  i40e_aqc_opc_get_local_advt_reg);
2007 
2008 	cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2009 	cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2010 
2011 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2012 
2013 	return status;
2014 }
2015 
2016 /**
2017  * i40e_aq_get_partner_advt
2018  * @hw: pointer to the hw struct
2019  * @advt_reg: AN partner advertisement register value
2020  * @cmd_details: pointer to command details structure or NULL
2021  *
2022  * Get the link partner AN advertisement register value.
2023  **/
i40e_aq_get_partner_advt(struct i40e_hw * hw,u64 * advt_reg,struct i40e_asq_cmd_details * cmd_details)2024 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2025 				u64 *advt_reg,
2026 				struct i40e_asq_cmd_details *cmd_details)
2027 {
2028 	struct i40e_aq_desc desc;
2029 	struct i40e_aqc_an_advt_reg *resp =
2030 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2031 	enum i40e_status_code status;
2032 
2033 	i40e_fill_default_direct_cmd_desc(&desc,
2034 					  i40e_aqc_opc_get_partner_advt);
2035 
2036 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2037 
2038 	if (status != I40E_SUCCESS)
2039 		goto aq_get_partner_advt_exit;
2040 
2041 	*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2042 	*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2043 
2044 aq_get_partner_advt_exit:
2045 	return status;
2046 }
2047 
2048 /**
2049  * i40e_aq_set_lb_modes
2050  * @hw: pointer to the hw struct
2051  * @lb_modes: loopback mode to be set
2052  * @cmd_details: pointer to command details structure or NULL
2053  *
2054  * Sets loopback modes.
2055  **/
i40e_aq_set_lb_modes(struct i40e_hw * hw,u16 lb_modes,struct i40e_asq_cmd_details * cmd_details)2056 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2057 				u16 lb_modes,
2058 				struct i40e_asq_cmd_details *cmd_details)
2059 {
2060 	struct i40e_aq_desc desc;
2061 	struct i40e_aqc_set_lb_mode *cmd =
2062 		(struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2063 	enum i40e_status_code status;
2064 
2065 	i40e_fill_default_direct_cmd_desc(&desc,
2066 					  i40e_aqc_opc_set_lb_modes);
2067 
2068 	cmd->lb_mode = CPU_TO_LE16(lb_modes);
2069 
2070 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2071 
2072 	return status;
2073 }
2074 
2075 /**
2076  * i40e_aq_set_phy_debug
2077  * @hw: pointer to the hw struct
2078  * @cmd_flags: debug command flags
2079  * @cmd_details: pointer to command details structure or NULL
2080  *
2081  * Reset the external PHY.
2082  **/
i40e_aq_set_phy_debug(struct i40e_hw * hw,u8 cmd_flags,struct i40e_asq_cmd_details * cmd_details)2083 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2084 				struct i40e_asq_cmd_details *cmd_details)
2085 {
2086 	struct i40e_aq_desc desc;
2087 	struct i40e_aqc_set_phy_debug *cmd =
2088 		(struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2089 	enum i40e_status_code status;
2090 
2091 	i40e_fill_default_direct_cmd_desc(&desc,
2092 					  i40e_aqc_opc_set_phy_debug);
2093 
2094 	cmd->command_flags = cmd_flags;
2095 
2096 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2097 
2098 	return status;
2099 }
2100 
2101 /**
2102  * i40e_aq_add_vsi
2103  * @hw: pointer to the hw struct
2104  * @vsi_ctx: pointer to a vsi context struct
2105  * @cmd_details: pointer to command details structure or NULL
2106  *
2107  * Add a VSI context to the hardware.
2108 **/
i40e_aq_add_vsi(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2109 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2110 				struct i40e_vsi_context *vsi_ctx,
2111 				struct i40e_asq_cmd_details *cmd_details)
2112 {
2113 	struct i40e_aq_desc desc;
2114 	struct i40e_aqc_add_get_update_vsi *cmd =
2115 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2116 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2117 		(struct i40e_aqc_add_get_update_vsi_completion *)
2118 		&desc.params.raw;
2119 	enum i40e_status_code status;
2120 
2121 	i40e_fill_default_direct_cmd_desc(&desc,
2122 					  i40e_aqc_opc_add_vsi);
2123 
2124 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2125 	cmd->connection_type = vsi_ctx->connection_type;
2126 	cmd->vf_id = vsi_ctx->vf_num;
2127 	cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2128 
2129 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2130 
2131 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2132 				    sizeof(vsi_ctx->info), cmd_details);
2133 
2134 	if (status != I40E_SUCCESS)
2135 		goto aq_add_vsi_exit;
2136 
2137 	vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2138 	vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2139 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2140 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2141 
2142 aq_add_vsi_exit:
2143 	return status;
2144 }
2145 
2146 /**
2147  * i40e_aq_set_default_vsi
2148  * @hw: pointer to the hw struct
2149  * @seid: vsi number
2150  * @cmd_details: pointer to command details structure or NULL
2151  **/
i40e_aq_set_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)2152 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2153 				u16 seid,
2154 				struct i40e_asq_cmd_details *cmd_details)
2155 {
2156 	struct i40e_aq_desc desc;
2157 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2158 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
2159 		&desc.params.raw;
2160 	enum i40e_status_code status;
2161 
2162 	i40e_fill_default_direct_cmd_desc(&desc,
2163 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2164 
2165 	cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2166 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2167 	cmd->seid = CPU_TO_LE16(seid);
2168 
2169 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2170 
2171 	return status;
2172 }
2173 
2174 /**
2175  * i40e_aq_clear_default_vsi
2176  * @hw: pointer to the hw struct
2177  * @seid: vsi number
2178  * @cmd_details: pointer to command details structure or NULL
2179  **/
i40e_aq_clear_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)2180 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2181 				u16 seid,
2182 				struct i40e_asq_cmd_details *cmd_details)
2183 {
2184 	struct i40e_aq_desc desc;
2185 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2186 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
2187 		&desc.params.raw;
2188 	enum i40e_status_code status;
2189 
2190 	i40e_fill_default_direct_cmd_desc(&desc,
2191 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2192 
2193 	cmd->promiscuous_flags = CPU_TO_LE16(0);
2194 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2195 	cmd->seid = CPU_TO_LE16(seid);
2196 
2197 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2198 
2199 	return status;
2200 }
2201 
2202 /**
2203  * i40e_aq_set_vsi_unicast_promiscuous
2204  * @hw: pointer to the hw struct
2205  * @seid: vsi number
2206  * @set: set unicast promiscuous enable/disable
2207  * @cmd_details: pointer to command details structure or NULL
2208  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2209  **/
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details,bool rx_only_promisc)2210 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2211 				u16 seid, bool set,
2212 				struct i40e_asq_cmd_details *cmd_details,
2213 				bool rx_only_promisc)
2214 {
2215 	struct i40e_aq_desc desc;
2216 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2217 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2218 	enum i40e_status_code status;
2219 	u16 flags = 0;
2220 
2221 	i40e_fill_default_direct_cmd_desc(&desc,
2222 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2223 
2224 	if (set) {
2225 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2226 		if (rx_only_promisc &&
2227 		    (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2228 		     (hw->aq.api_maj_ver > 1)))
2229 			flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2230 	}
2231 
2232 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2233 
2234 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2235 	if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2236 	     (hw->aq.api_maj_ver > 1))
2237 		cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2238 
2239 	cmd->seid = CPU_TO_LE16(seid);
2240 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2241 
2242 	return status;
2243 }
2244 
2245 /**
2246  * i40e_aq_set_vsi_multicast_promiscuous
2247  * @hw: pointer to the hw struct
2248  * @seid: vsi number
2249  * @set: set multicast promiscuous enable/disable
2250  * @cmd_details: pointer to command details structure or NULL
2251  **/
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details)2252 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2253 				u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2254 {
2255 	struct i40e_aq_desc desc;
2256 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2257 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2258 	enum i40e_status_code status;
2259 	u16 flags = 0;
2260 
2261 	i40e_fill_default_direct_cmd_desc(&desc,
2262 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2263 
2264 	if (set)
2265 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2266 
2267 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2268 
2269 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2270 
2271 	cmd->seid = CPU_TO_LE16(seid);
2272 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2273 
2274 	return status;
2275 }
2276 
2277 /**
2278  * i40e_aq_set_vsi_mc_promisc_on_vlan
2279  * @hw: pointer to the hw struct
2280  * @seid: vsi number
2281  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2282  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2283  * @cmd_details: pointer to command details structure or NULL
2284  **/
i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2285 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2286 				u16 seid, bool enable, u16 vid,
2287 				struct i40e_asq_cmd_details *cmd_details)
2288 {
2289 	struct i40e_aq_desc desc;
2290 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2291 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2292 	enum i40e_status_code status;
2293 	u16 flags = 0;
2294 
2295 	i40e_fill_default_direct_cmd_desc(&desc,
2296 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2297 
2298 	if (enable)
2299 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2300 
2301 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2302 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2303 	cmd->seid = CPU_TO_LE16(seid);
2304 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2305 
2306 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2307 
2308 	return status;
2309 }
2310 
2311 /**
2312  * i40e_aq_set_vsi_uc_promisc_on_vlan
2313  * @hw: pointer to the hw struct
2314  * @seid: vsi number
2315  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2316  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2317  * @cmd_details: pointer to command details structure or NULL
2318  **/
i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2319 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2320 				u16 seid, bool enable, u16 vid,
2321 				struct i40e_asq_cmd_details *cmd_details)
2322 {
2323 	struct i40e_aq_desc desc;
2324 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2325 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2326 	enum i40e_status_code status;
2327 	u16 flags = 0;
2328 
2329 	i40e_fill_default_direct_cmd_desc(&desc,
2330 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2331 
2332 	if (enable)
2333 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2334 
2335 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2336 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2337 	cmd->seid = CPU_TO_LE16(seid);
2338 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2339 
2340 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2341 
2342 	return status;
2343 }
2344 
2345 /**
2346  * i40e_aq_set_vsi_bc_promisc_on_vlan
2347  * @hw: pointer to the hw struct
2348  * @seid: vsi number
2349  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2350  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2351  * @cmd_details: pointer to command details structure or NULL
2352  **/
i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2353 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2354 				u16 seid, bool enable, u16 vid,
2355 				struct i40e_asq_cmd_details *cmd_details)
2356 {
2357 	struct i40e_aq_desc desc;
2358 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2359 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2360 	enum i40e_status_code status;
2361 	u16 flags = 0;
2362 
2363 	i40e_fill_default_direct_cmd_desc(&desc,
2364 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2365 
2366 	if (enable)
2367 		flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2368 
2369 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2370 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2371 	cmd->seid = CPU_TO_LE16(seid);
2372 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2373 
2374 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2375 
2376 	return status;
2377 }
2378 
2379 /**
2380  * i40e_aq_set_vsi_broadcast
2381  * @hw: pointer to the hw struct
2382  * @seid: vsi number
2383  * @set_filter: TRUE to set filter, FALSE to clear filter
2384  * @cmd_details: pointer to command details structure or NULL
2385  *
2386  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2387  **/
i40e_aq_set_vsi_broadcast(struct i40e_hw * hw,u16 seid,bool set_filter,struct i40e_asq_cmd_details * cmd_details)2388 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2389 				u16 seid, bool set_filter,
2390 				struct i40e_asq_cmd_details *cmd_details)
2391 {
2392 	struct i40e_aq_desc desc;
2393 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2394 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2395 	enum i40e_status_code status;
2396 
2397 	i40e_fill_default_direct_cmd_desc(&desc,
2398 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2399 
2400 	if (set_filter)
2401 		cmd->promiscuous_flags
2402 			    |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2403 	else
2404 		cmd->promiscuous_flags
2405 			    &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2406 
2407 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2408 	cmd->seid = CPU_TO_LE16(seid);
2409 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2410 
2411 	return status;
2412 }
2413 
2414 /**
2415  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2416  * @hw: pointer to the hw struct
2417  * @seid: vsi number
2418  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2419  * @cmd_details: pointer to command details structure or NULL
2420  **/
i40e_aq_set_vsi_vlan_promisc(struct i40e_hw * hw,u16 seid,bool enable,struct i40e_asq_cmd_details * cmd_details)2421 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2422 				u16 seid, bool enable,
2423 				struct i40e_asq_cmd_details *cmd_details)
2424 {
2425 	struct i40e_aq_desc desc;
2426 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2427 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2428 	enum i40e_status_code status;
2429 	u16 flags = 0;
2430 
2431 	i40e_fill_default_direct_cmd_desc(&desc,
2432 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2433 	if (enable)
2434 		flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2435 
2436 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2437 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2438 	cmd->seid = CPU_TO_LE16(seid);
2439 
2440 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2441 
2442 	return status;
2443 }
2444 
2445 /**
2446  * i40e_get_vsi_params - get VSI configuration info
2447  * @hw: pointer to the hw struct
2448  * @vsi_ctx: pointer to a vsi context struct
2449  * @cmd_details: pointer to command details structure or NULL
2450  **/
i40e_aq_get_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2451 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2452 				struct i40e_vsi_context *vsi_ctx,
2453 				struct i40e_asq_cmd_details *cmd_details)
2454 {
2455 	struct i40e_aq_desc desc;
2456 	struct i40e_aqc_add_get_update_vsi *cmd =
2457 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2458 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2459 		(struct i40e_aqc_add_get_update_vsi_completion *)
2460 		&desc.params.raw;
2461 	enum i40e_status_code status;
2462 
2463 	i40e_fill_default_direct_cmd_desc(&desc,
2464 					  i40e_aqc_opc_get_vsi_parameters);
2465 
2466 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2467 
2468 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2469 
2470 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2471 				    sizeof(vsi_ctx->info), NULL);
2472 
2473 	if (status != I40E_SUCCESS)
2474 		goto aq_get_vsi_params_exit;
2475 
2476 	vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2477 	vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2478 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2479 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2480 
2481 aq_get_vsi_params_exit:
2482 	return status;
2483 }
2484 
2485 /**
2486  * i40e_aq_update_vsi_params
2487  * @hw: pointer to the hw struct
2488  * @vsi_ctx: pointer to a vsi context struct
2489  * @cmd_details: pointer to command details structure or NULL
2490  *
2491  * Update a VSI context.
2492  **/
i40e_aq_update_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2493 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2494 				struct i40e_vsi_context *vsi_ctx,
2495 				struct i40e_asq_cmd_details *cmd_details)
2496 {
2497 	struct i40e_aq_desc desc;
2498 	struct i40e_aqc_add_get_update_vsi *cmd =
2499 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2500 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2501 		(struct i40e_aqc_add_get_update_vsi_completion *)
2502 		&desc.params.raw;
2503 	enum i40e_status_code status;
2504 
2505 	i40e_fill_default_direct_cmd_desc(&desc,
2506 					  i40e_aqc_opc_update_vsi_parameters);
2507 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2508 
2509 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2510 
2511 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2512 				    sizeof(vsi_ctx->info), cmd_details);
2513 
2514 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2515 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2516 
2517 	return status;
2518 }
2519 
2520 /**
2521  * i40e_aq_get_switch_config
2522  * @hw: pointer to the hardware structure
2523  * @buf: pointer to the result buffer
2524  * @buf_size: length of input buffer
2525  * @start_seid: seid to start for the report, 0 == beginning
2526  * @cmd_details: pointer to command details structure or NULL
2527  *
2528  * Fill the buf with switch configuration returned from AdminQ command
2529  **/
i40e_aq_get_switch_config(struct i40e_hw * hw,struct i40e_aqc_get_switch_config_resp * buf,u16 buf_size,u16 * start_seid,struct i40e_asq_cmd_details * cmd_details)2530 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2531 				struct i40e_aqc_get_switch_config_resp *buf,
2532 				u16 buf_size, u16 *start_seid,
2533 				struct i40e_asq_cmd_details *cmd_details)
2534 {
2535 	struct i40e_aq_desc desc;
2536 	struct i40e_aqc_switch_seid *scfg =
2537 		(struct i40e_aqc_switch_seid *)&desc.params.raw;
2538 	enum i40e_status_code status;
2539 
2540 	i40e_fill_default_direct_cmd_desc(&desc,
2541 					  i40e_aqc_opc_get_switch_config);
2542 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2543 	if (buf_size > I40E_AQ_LARGE_BUF)
2544 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2545 	scfg->seid = CPU_TO_LE16(*start_seid);
2546 
2547 	status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2548 	*start_seid = LE16_TO_CPU(scfg->seid);
2549 
2550 	return status;
2551 }
2552 
2553 /**
2554  * i40e_aq_set_switch_config
2555  * @hw: pointer to the hardware structure
2556  * @flags: bit flag values to set
2557  * @valid_flags: which bit flags to set
2558  * @cmd_details: pointer to command details structure or NULL
2559  *
2560  * Set switch configuration bits
2561  **/
i40e_aq_set_switch_config(struct i40e_hw * hw,u16 flags,u16 valid_flags,struct i40e_asq_cmd_details * cmd_details)2562 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2563 				u16 flags, u16 valid_flags,
2564 				struct i40e_asq_cmd_details *cmd_details)
2565 {
2566 	struct i40e_aq_desc desc;
2567 	struct i40e_aqc_set_switch_config *scfg =
2568 		(struct i40e_aqc_set_switch_config *)&desc.params.raw;
2569 	enum i40e_status_code status;
2570 
2571 	i40e_fill_default_direct_cmd_desc(&desc,
2572 					  i40e_aqc_opc_set_switch_config);
2573 	scfg->flags = CPU_TO_LE16(flags);
2574 	scfg->valid_flags = CPU_TO_LE16(valid_flags);
2575 
2576 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2577 
2578 	return status;
2579 }
2580 
2581 /**
2582  * i40e_aq_get_firmware_version
2583  * @hw: pointer to the hw struct
2584  * @fw_major_version: firmware major version
2585  * @fw_minor_version: firmware minor version
2586  * @fw_build: firmware build number
2587  * @api_major_version: major queue version
2588  * @api_minor_version: minor queue version
2589  * @cmd_details: pointer to command details structure or NULL
2590  *
2591  * Get the firmware version from the admin queue commands
2592  **/
i40e_aq_get_firmware_version(struct i40e_hw * hw,u16 * fw_major_version,u16 * fw_minor_version,u32 * fw_build,u16 * api_major_version,u16 * api_minor_version,struct i40e_asq_cmd_details * cmd_details)2593 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2594 				u16 *fw_major_version, u16 *fw_minor_version,
2595 				u32 *fw_build,
2596 				u16 *api_major_version, u16 *api_minor_version,
2597 				struct i40e_asq_cmd_details *cmd_details)
2598 {
2599 	struct i40e_aq_desc desc;
2600 	struct i40e_aqc_get_version *resp =
2601 		(struct i40e_aqc_get_version *)&desc.params.raw;
2602 	enum i40e_status_code status;
2603 
2604 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2605 
2606 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2607 
2608 	if (status == I40E_SUCCESS) {
2609 		if (fw_major_version != NULL)
2610 			*fw_major_version = LE16_TO_CPU(resp->fw_major);
2611 		if (fw_minor_version != NULL)
2612 			*fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2613 		if (fw_build != NULL)
2614 			*fw_build = LE32_TO_CPU(resp->fw_build);
2615 		if (api_major_version != NULL)
2616 			*api_major_version = LE16_TO_CPU(resp->api_major);
2617 		if (api_minor_version != NULL)
2618 			*api_minor_version = LE16_TO_CPU(resp->api_minor);
2619 
2620 		/* A workaround to fix the API version in SW */
2621 		if (api_major_version && api_minor_version &&
2622 		    fw_major_version && fw_minor_version &&
2623 		    ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2624 		    (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2625 		     (*fw_major_version > 4)))
2626 			*api_minor_version = 2;
2627 	}
2628 
2629 	return status;
2630 }
2631 
2632 /**
2633  * i40e_aq_send_driver_version
2634  * @hw: pointer to the hw struct
2635  * @dv: driver's major, minor version
2636  * @cmd_details: pointer to command details structure or NULL
2637  *
2638  * Send the driver version to the firmware
2639  **/
i40e_aq_send_driver_version(struct i40e_hw * hw,struct i40e_driver_version * dv,struct i40e_asq_cmd_details * cmd_details)2640 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2641 				struct i40e_driver_version *dv,
2642 				struct i40e_asq_cmd_details *cmd_details)
2643 {
2644 	struct i40e_aq_desc desc;
2645 	struct i40e_aqc_driver_version *cmd =
2646 		(struct i40e_aqc_driver_version *)&desc.params.raw;
2647 	enum i40e_status_code status;
2648 	u16 len;
2649 
2650 	if (dv == NULL)
2651 		return I40E_ERR_PARAM;
2652 
2653 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2654 
2655 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2656 	cmd->driver_major_ver = dv->major_version;
2657 	cmd->driver_minor_ver = dv->minor_version;
2658 	cmd->driver_build_ver = dv->build_version;
2659 	cmd->driver_subbuild_ver = dv->subbuild_version;
2660 
2661 	len = 0;
2662 	while (len < sizeof(dv->driver_string) &&
2663 	       (dv->driver_string[len] < 0x80) &&
2664 	       dv->driver_string[len])
2665 		len++;
2666 	status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2667 				       len, cmd_details);
2668 
2669 	return status;
2670 }
2671 
2672 /**
2673  * i40e_get_link_status - get status of the HW network link
2674  * @hw: pointer to the hw struct
2675  * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
2676  *
2677  * Variable link_up TRUE if link is up, FALSE if link is down.
2678  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2679  *
2680  * Side effect: LinkStatusEvent reporting becomes enabled
2681  **/
i40e_get_link_status(struct i40e_hw * hw,bool * link_up)2682 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2683 {
2684 	enum i40e_status_code status = I40E_SUCCESS;
2685 
2686 	if (hw->phy.get_link_info) {
2687 		status = i40e_update_link_info(hw);
2688 
2689 		if (status != I40E_SUCCESS)
2690 			i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2691 				   status);
2692 	}
2693 
2694 	*link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2695 
2696 	return status;
2697 }
2698 
2699 /**
2700  * i40e_updatelink_status - update status of the HW network link
2701  * @hw: pointer to the hw struct
2702  **/
i40e_update_link_info(struct i40e_hw * hw)2703 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2704 {
2705 	struct i40e_aq_get_phy_abilities_resp abilities;
2706 	enum i40e_status_code status = I40E_SUCCESS;
2707 
2708 	status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2709 	if (status)
2710 		return status;
2711 
2712 	/* extra checking needed to ensure link info to user is timely */
2713 	if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2714 	    ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2715 	     !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2716 		status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
2717 						      &abilities, NULL);
2718 		if (status)
2719 			return status;
2720 
2721 		i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2722 			sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2723 	}
2724 	return status;
2725 }
2726 
2727 
2728 /**
2729  * i40e_get_link_speed
2730  * @hw: pointer to the hw struct
2731  *
2732  * Returns the link speed of the adapter.
2733  **/
i40e_get_link_speed(struct i40e_hw * hw)2734 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2735 {
2736 	enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2737 	enum i40e_status_code status = I40E_SUCCESS;
2738 
2739 	if (hw->phy.get_link_info) {
2740 		status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2741 
2742 		if (status != I40E_SUCCESS)
2743 			goto i40e_link_speed_exit;
2744 	}
2745 
2746 	speed = hw->phy.link_info.link_speed;
2747 
2748 i40e_link_speed_exit:
2749 	return speed;
2750 }
2751 
2752 /**
2753  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2754  * @hw: pointer to the hw struct
2755  * @uplink_seid: the MAC or other gizmo SEID
2756  * @downlink_seid: the VSI SEID
2757  * @enabled_tc: bitmap of TCs to be enabled
2758  * @default_port: TRUE for default port VSI, FALSE for control port
2759  * @veb_seid: pointer to where to put the resulting VEB SEID
2760  * @enable_stats: TRUE to turn on VEB stats
2761  * @cmd_details: pointer to command details structure or NULL
2762  *
2763  * This asks the FW to add a VEB between the uplink and downlink
2764  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2765  **/
i40e_aq_add_veb(struct i40e_hw * hw,u16 uplink_seid,u16 downlink_seid,u8 enabled_tc,bool default_port,u16 * veb_seid,bool enable_stats,struct i40e_asq_cmd_details * cmd_details)2766 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2767 				u16 downlink_seid, u8 enabled_tc,
2768 				bool default_port, u16 *veb_seid,
2769 				bool enable_stats,
2770 				struct i40e_asq_cmd_details *cmd_details)
2771 {
2772 	struct i40e_aq_desc desc;
2773 	struct i40e_aqc_add_veb *cmd =
2774 		(struct i40e_aqc_add_veb *)&desc.params.raw;
2775 	struct i40e_aqc_add_veb_completion *resp =
2776 		(struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2777 	enum i40e_status_code status;
2778 	u16 veb_flags = 0;
2779 
2780 	/* SEIDs need to either both be set or both be 0 for floating VEB */
2781 	if (!!uplink_seid != !!downlink_seid)
2782 		return I40E_ERR_PARAM;
2783 
2784 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2785 
2786 	cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2787 	cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2788 	cmd->enable_tcs = enabled_tc;
2789 	if (!uplink_seid)
2790 		veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2791 	if (default_port)
2792 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2793 	else
2794 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2795 
2796 	/* reverse logic here: set the bitflag to disable the stats */
2797 	if (!enable_stats)
2798 		veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2799 
2800 	cmd->veb_flags = CPU_TO_LE16(veb_flags);
2801 
2802 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2803 
2804 	if (!status && veb_seid)
2805 		*veb_seid = LE16_TO_CPU(resp->veb_seid);
2806 
2807 	return status;
2808 }
2809 
2810 /**
2811  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2812  * @hw: pointer to the hw struct
2813  * @veb_seid: the SEID of the VEB to query
2814  * @switch_id: the uplink switch id
2815  * @floating: set to TRUE if the VEB is floating
2816  * @statistic_index: index of the stats counter block for this VEB
2817  * @vebs_used: number of VEB's used by function
2818  * @vebs_free: total VEB's not reserved by any function
2819  * @cmd_details: pointer to command details structure or NULL
2820  *
2821  * This retrieves the parameters for a particular VEB, specified by
2822  * uplink_seid, and returns them to the caller.
2823  **/
i40e_aq_get_veb_parameters(struct i40e_hw * hw,u16 veb_seid,u16 * switch_id,bool * floating,u16 * statistic_index,u16 * vebs_used,u16 * vebs_free,struct i40e_asq_cmd_details * cmd_details)2824 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2825 				u16 veb_seid, u16 *switch_id,
2826 				bool *floating, u16 *statistic_index,
2827 				u16 *vebs_used, u16 *vebs_free,
2828 				struct i40e_asq_cmd_details *cmd_details)
2829 {
2830 	struct i40e_aq_desc desc;
2831 	struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2832 		(struct i40e_aqc_get_veb_parameters_completion *)
2833 		&desc.params.raw;
2834 	enum i40e_status_code status;
2835 
2836 	if (veb_seid == 0)
2837 		return I40E_ERR_PARAM;
2838 
2839 	i40e_fill_default_direct_cmd_desc(&desc,
2840 					  i40e_aqc_opc_get_veb_parameters);
2841 	cmd_resp->seid = CPU_TO_LE16(veb_seid);
2842 
2843 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2844 	if (status)
2845 		goto get_veb_exit;
2846 
2847 	if (switch_id)
2848 		*switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2849 	if (statistic_index)
2850 		*statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2851 	if (vebs_used)
2852 		*vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2853 	if (vebs_free)
2854 		*vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2855 	if (floating) {
2856 		u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2857 
2858 		if (flags & I40E_AQC_ADD_VEB_FLOATING)
2859 			*floating = TRUE;
2860 		else
2861 			*floating = FALSE;
2862 	}
2863 
2864 get_veb_exit:
2865 	return status;
2866 }
2867 
2868 /**
2869  * i40e_aq_add_macvlan
2870  * @hw: pointer to the hw struct
2871  * @seid: VSI for the mac address
2872  * @mv_list: list of macvlans to be added
2873  * @count: length of the list
2874  * @cmd_details: pointer to command details structure or NULL
2875  *
2876  * Add MAC/VLAN addresses to the HW filtering
2877  **/
i40e_aq_add_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2878 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2879 			struct i40e_aqc_add_macvlan_element_data *mv_list,
2880 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2881 {
2882 	struct i40e_aq_desc desc;
2883 	struct i40e_aqc_macvlan *cmd =
2884 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2885 	enum i40e_status_code status;
2886 	u16 buf_size;
2887 	int i;
2888 
2889 	if (count == 0 || !mv_list || !hw)
2890 		return I40E_ERR_PARAM;
2891 
2892 	buf_size = count * sizeof(*mv_list);
2893 
2894 	/* prep the rest of the request */
2895 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2896 	cmd->num_addresses = CPU_TO_LE16(count);
2897 	cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2898 	cmd->seid[1] = 0;
2899 	cmd->seid[2] = 0;
2900 
2901 	for (i = 0; i < count; i++)
2902 		if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2903 			mv_list[i].flags |=
2904 			    CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2905 
2906 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2907 	if (buf_size > I40E_AQ_LARGE_BUF)
2908 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2909 
2910 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2911 				       cmd_details);
2912 
2913 	return status;
2914 }
2915 
2916 /**
2917  * i40e_aq_remove_macvlan
2918  * @hw: pointer to the hw struct
2919  * @seid: VSI for the mac address
2920  * @mv_list: list of macvlans to be removed
2921  * @count: length of the list
2922  * @cmd_details: pointer to command details structure or NULL
2923  *
2924  * Remove MAC/VLAN addresses from the HW filtering
2925  **/
i40e_aq_remove_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_remove_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2926 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2927 			struct i40e_aqc_remove_macvlan_element_data *mv_list,
2928 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2929 {
2930 	struct i40e_aq_desc desc;
2931 	struct i40e_aqc_macvlan *cmd =
2932 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2933 	enum i40e_status_code status;
2934 	u16 buf_size;
2935 
2936 	if (count == 0 || !mv_list || !hw)
2937 		return I40E_ERR_PARAM;
2938 
2939 	buf_size = count * sizeof(*mv_list);
2940 
2941 	/* prep the rest of the request */
2942 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2943 	cmd->num_addresses = CPU_TO_LE16(count);
2944 	cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2945 	cmd->seid[1] = 0;
2946 	cmd->seid[2] = 0;
2947 
2948 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2949 	if (buf_size > I40E_AQ_LARGE_BUF)
2950 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2951 
2952 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2953 				       cmd_details);
2954 
2955 	return status;
2956 }
2957 
2958 /**
2959  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2960  * @hw: pointer to the hw struct
2961  * @opcode: AQ opcode for add or delete mirror rule
2962  * @sw_seid: Switch SEID (to which rule refers)
2963  * @rule_type: Rule Type (ingress/egress/VLAN)
2964  * @id: Destination VSI SEID or Rule ID
2965  * @count: length of the list
2966  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2967  * @cmd_details: pointer to command details structure or NULL
2968  * @rule_id: Rule ID returned from FW
2969  * @rule_used: Number of rules used in internal switch
2970  * @rule_free: Number of rules free in internal switch
2971  *
2972  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2973  * VEBs/VEPA elements only
2974  **/
i40e_mirrorrule_op(struct i40e_hw * hw,u16 opcode,u16 sw_seid,u16 rule_type,u16 id,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rule_id,u16 * rules_used,u16 * rules_free)2975 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2976 			u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2977 			u16 count, __le16 *mr_list,
2978 			struct i40e_asq_cmd_details *cmd_details,
2979 			u16 *rule_id, u16 *rules_used, u16 *rules_free)
2980 {
2981 	struct i40e_aq_desc desc;
2982 	struct i40e_aqc_add_delete_mirror_rule *cmd =
2983 		(struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2984 	struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2985 	(struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2986 	enum i40e_status_code status;
2987 	u16 buf_size;
2988 
2989 	buf_size = count * sizeof(*mr_list);
2990 
2991 	/* prep the rest of the request */
2992 	i40e_fill_default_direct_cmd_desc(&desc, opcode);
2993 	cmd->seid = CPU_TO_LE16(sw_seid);
2994 	cmd->rule_type = CPU_TO_LE16(rule_type &
2995 				     I40E_AQC_MIRROR_RULE_TYPE_MASK);
2996 	cmd->num_entries = CPU_TO_LE16(count);
2997 	/* Dest VSI for add, rule_id for delete */
2998 	cmd->destination = CPU_TO_LE16(id);
2999 	if (mr_list) {
3000 		desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3001 						I40E_AQ_FLAG_RD));
3002 		if (buf_size > I40E_AQ_LARGE_BUF)
3003 			desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3004 	}
3005 
3006 	status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3007 				       cmd_details);
3008 	if (status == I40E_SUCCESS ||
3009 	    hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3010 		if (rule_id)
3011 			*rule_id = LE16_TO_CPU(resp->rule_id);
3012 		if (rules_used)
3013 			*rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3014 		if (rules_free)
3015 			*rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3016 	}
3017 	return status;
3018 }
3019 
3020 /**
3021  * i40e_aq_add_mirrorrule - add a mirror rule
3022  * @hw: pointer to the hw struct
3023  * @sw_seid: Switch SEID (to which rule refers)
3024  * @rule_type: Rule Type (ingress/egress/VLAN)
3025  * @dest_vsi: SEID of VSI to which packets will be mirrored
3026  * @count: length of the list
3027  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3028  * @cmd_details: pointer to command details structure or NULL
3029  * @rule_id: Rule ID returned from FW
3030  * @rule_used: Number of rules used in internal switch
3031  * @rule_free: Number of rules free in internal switch
3032  *
3033  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3034  **/
i40e_aq_add_mirrorrule(struct i40e_hw * hw,u16 sw_seid,u16 rule_type,u16 dest_vsi,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rule_id,u16 * rules_used,u16 * rules_free)3035 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3036 			u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3037 			struct i40e_asq_cmd_details *cmd_details,
3038 			u16 *rule_id, u16 *rules_used, u16 *rules_free)
3039 {
3040 	if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3041 	    rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3042 		if (count == 0 || !mr_list)
3043 			return I40E_ERR_PARAM;
3044 	}
3045 
3046 	return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3047 				  rule_type, dest_vsi, count, mr_list,
3048 				  cmd_details, rule_id, rules_used, rules_free);
3049 }
3050 
3051 /**
3052  * i40e_aq_delete_mirrorrule - delete a mirror rule
3053  * @hw: pointer to the hw struct
3054  * @sw_seid: Switch SEID (to which rule refers)
3055  * @rule_type: Rule Type (ingress/egress/VLAN)
3056  * @count: length of the list
3057  * @rule_id: Rule ID that is returned in the receive desc as part of
3058  *		add_mirrorrule.
3059  * @mr_list: list of mirrored VLAN IDs to be removed
3060  * @cmd_details: pointer to command details structure or NULL
3061  * @rule_used: Number of rules used in internal switch
3062  * @rule_free: Number of rules free in internal switch
3063  *
3064  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3065  **/
i40e_aq_delete_mirrorrule(struct i40e_hw * hw,u16 sw_seid,u16 rule_type,u16 rule_id,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rules_used,u16 * rules_free)3066 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3067 			u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3068 			struct i40e_asq_cmd_details *cmd_details,
3069 			u16 *rules_used, u16 *rules_free)
3070 {
3071 	/* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3072 	if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3073 		/* count and mr_list shall be valid for rule_type INGRESS VLAN
3074 		 * mirroring. For other rule_type, count and rule_type should
3075 		 * not matter.
3076 		 */
3077 		if (count == 0 || !mr_list)
3078 			return I40E_ERR_PARAM;
3079 	}
3080 
3081 	return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3082 				  rule_type, rule_id, count, mr_list,
3083 				  cmd_details, NULL, rules_used, rules_free);
3084 }
3085 
3086 /**
3087  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3088  * @hw: pointer to the hw struct
3089  * @seid: VSI for the vlan filters
3090  * @v_list: list of vlan filters to be added
3091  * @count: length of the list
3092  * @cmd_details: pointer to command details structure or NULL
3093  **/
i40e_aq_add_vlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_vlan_element_data * v_list,u8 count,struct i40e_asq_cmd_details * cmd_details)3094 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3095 			struct i40e_aqc_add_remove_vlan_element_data *v_list,
3096 			u8 count, struct i40e_asq_cmd_details *cmd_details)
3097 {
3098 	struct i40e_aq_desc desc;
3099 	struct i40e_aqc_macvlan *cmd =
3100 		(struct i40e_aqc_macvlan *)&desc.params.raw;
3101 	enum i40e_status_code status;
3102 	u16 buf_size;
3103 
3104 	if (count == 0 || !v_list || !hw)
3105 		return I40E_ERR_PARAM;
3106 
3107 	buf_size = count * sizeof(*v_list);
3108 
3109 	/* prep the rest of the request */
3110 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3111 	cmd->num_addresses = CPU_TO_LE16(count);
3112 	cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3113 	cmd->seid[1] = 0;
3114 	cmd->seid[2] = 0;
3115 
3116 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3117 	if (buf_size > I40E_AQ_LARGE_BUF)
3118 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3119 
3120 	status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3121 				       cmd_details);
3122 
3123 	return status;
3124 }
3125 
3126 /**
3127  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3128  * @hw: pointer to the hw struct
3129  * @seid: VSI for the vlan filters
3130  * @v_list: list of macvlans to be removed
3131  * @count: length of the list
3132  * @cmd_details: pointer to command details structure or NULL
3133  **/
i40e_aq_remove_vlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_vlan_element_data * v_list,u8 count,struct i40e_asq_cmd_details * cmd_details)3134 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3135 			struct i40e_aqc_add_remove_vlan_element_data *v_list,
3136 			u8 count, struct i40e_asq_cmd_details *cmd_details)
3137 {
3138 	struct i40e_aq_desc desc;
3139 	struct i40e_aqc_macvlan *cmd =
3140 		(struct i40e_aqc_macvlan *)&desc.params.raw;
3141 	enum i40e_status_code status;
3142 	u16 buf_size;
3143 
3144 	if (count == 0 || !v_list || !hw)
3145 		return I40E_ERR_PARAM;
3146 
3147 	buf_size = count * sizeof(*v_list);
3148 
3149 	/* prep the rest of the request */
3150 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3151 	cmd->num_addresses = CPU_TO_LE16(count);
3152 	cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3153 	cmd->seid[1] = 0;
3154 	cmd->seid[2] = 0;
3155 
3156 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3157 	if (buf_size > I40E_AQ_LARGE_BUF)
3158 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3159 
3160 	status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3161 				       cmd_details);
3162 
3163 	return status;
3164 }
3165 
3166 /**
3167  * i40e_aq_send_msg_to_vf
3168  * @hw: pointer to the hardware structure
3169  * @vfid: vf id to send msg
3170  * @v_opcode: opcodes for VF-PF communication
3171  * @v_retval: return error code
3172  * @msg: pointer to the msg buffer
3173  * @msglen: msg length
3174  * @cmd_details: pointer to command details
3175  *
3176  * send msg to vf
3177  **/
i40e_aq_send_msg_to_vf(struct i40e_hw * hw,u16 vfid,u32 v_opcode,u32 v_retval,u8 * msg,u16 msglen,struct i40e_asq_cmd_details * cmd_details)3178 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3179 				u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3180 				struct i40e_asq_cmd_details *cmd_details)
3181 {
3182 	struct i40e_aq_desc desc;
3183 	struct i40e_aqc_pf_vf_message *cmd =
3184 		(struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3185 	enum i40e_status_code status;
3186 
3187 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3188 	cmd->id = CPU_TO_LE32(vfid);
3189 	desc.cookie_high = CPU_TO_LE32(v_opcode);
3190 	desc.cookie_low = CPU_TO_LE32(v_retval);
3191 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3192 	if (msglen) {
3193 		desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3194 						I40E_AQ_FLAG_RD));
3195 		if (msglen > I40E_AQ_LARGE_BUF)
3196 			desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3197 		desc.datalen = CPU_TO_LE16(msglen);
3198 	}
3199 	status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3200 
3201 	return status;
3202 }
3203 
3204 /**
3205  * i40e_aq_debug_read_register
3206  * @hw: pointer to the hw struct
3207  * @reg_addr: register address
3208  * @reg_val: register value
3209  * @cmd_details: pointer to command details structure or NULL
3210  *
3211  * Read the register using the admin queue commands
3212  **/
i40e_aq_debug_read_register(struct i40e_hw * hw,u32 reg_addr,u64 * reg_val,struct i40e_asq_cmd_details * cmd_details)3213 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3214 				u32 reg_addr, u64 *reg_val,
3215 				struct i40e_asq_cmd_details *cmd_details)
3216 {
3217 	struct i40e_aq_desc desc;
3218 	struct i40e_aqc_debug_reg_read_write *cmd_resp =
3219 		(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3220 	enum i40e_status_code status;
3221 
3222 	if (reg_val == NULL)
3223 		return I40E_ERR_PARAM;
3224 
3225 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3226 
3227 	cmd_resp->address = CPU_TO_LE32(reg_addr);
3228 
3229 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3230 
3231 	if (status == I40E_SUCCESS) {
3232 		*reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3233 			   (u64)LE32_TO_CPU(cmd_resp->value_low);
3234 	}
3235 
3236 	return status;
3237 }
3238 
3239 /**
3240  * i40e_aq_debug_write_register
3241  * @hw: pointer to the hw struct
3242  * @reg_addr: register address
3243  * @reg_val: register value
3244  * @cmd_details: pointer to command details structure or NULL
3245  *
3246  * Write to a register using the admin queue commands
3247  **/
i40e_aq_debug_write_register(struct i40e_hw * hw,u32 reg_addr,u64 reg_val,struct i40e_asq_cmd_details * cmd_details)3248 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3249 				u32 reg_addr, u64 reg_val,
3250 				struct i40e_asq_cmd_details *cmd_details)
3251 {
3252 	struct i40e_aq_desc desc;
3253 	struct i40e_aqc_debug_reg_read_write *cmd =
3254 		(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3255 	enum i40e_status_code status;
3256 
3257 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3258 
3259 	cmd->address = CPU_TO_LE32(reg_addr);
3260 	cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3261 	cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3262 
3263 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3264 
3265 	return status;
3266 }
3267 
3268 /**
3269  * i40e_aq_request_resource
3270  * @hw: pointer to the hw struct
3271  * @resource: resource id
3272  * @access: access type
3273  * @sdp_number: resource number
3274  * @timeout: the maximum time in ms that the driver may hold the resource
3275  * @cmd_details: pointer to command details structure or NULL
3276  *
3277  * requests common resource using the admin queue commands
3278  **/
i40e_aq_request_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,enum i40e_aq_resource_access_type access,u8 sdp_number,u64 * timeout,struct i40e_asq_cmd_details * cmd_details)3279 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3280 				enum i40e_aq_resources_ids resource,
3281 				enum i40e_aq_resource_access_type access,
3282 				u8 sdp_number, u64 *timeout,
3283 				struct i40e_asq_cmd_details *cmd_details)
3284 {
3285 	struct i40e_aq_desc desc;
3286 	struct i40e_aqc_request_resource *cmd_resp =
3287 		(struct i40e_aqc_request_resource *)&desc.params.raw;
3288 	enum i40e_status_code status;
3289 
3290 	DEBUGFUNC("i40e_aq_request_resource");
3291 
3292 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3293 
3294 	cmd_resp->resource_id = CPU_TO_LE16(resource);
3295 	cmd_resp->access_type = CPU_TO_LE16(access);
3296 	cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3297 
3298 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3299 	/* The completion specifies the maximum time in ms that the driver
3300 	 * may hold the resource in the Timeout field.
3301 	 * If the resource is held by someone else, the command completes with
3302 	 * busy return value and the timeout field indicates the maximum time
3303 	 * the current owner of the resource has to free it.
3304 	 */
3305 	if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3306 		*timeout = LE32_TO_CPU(cmd_resp->timeout);
3307 
3308 	return status;
3309 }
3310 
3311 /**
3312  * i40e_aq_release_resource
3313  * @hw: pointer to the hw struct
3314  * @resource: resource id
3315  * @sdp_number: resource number
3316  * @cmd_details: pointer to command details structure or NULL
3317  *
3318  * release common resource using the admin queue commands
3319  **/
i40e_aq_release_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,u8 sdp_number,struct i40e_asq_cmd_details * cmd_details)3320 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3321 				enum i40e_aq_resources_ids resource,
3322 				u8 sdp_number,
3323 				struct i40e_asq_cmd_details *cmd_details)
3324 {
3325 	struct i40e_aq_desc desc;
3326 	struct i40e_aqc_request_resource *cmd =
3327 		(struct i40e_aqc_request_resource *)&desc.params.raw;
3328 	enum i40e_status_code status;
3329 
3330 	DEBUGFUNC("i40e_aq_release_resource");
3331 
3332 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3333 
3334 	cmd->resource_id = CPU_TO_LE16(resource);
3335 	cmd->resource_number = CPU_TO_LE32(sdp_number);
3336 
3337 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3338 
3339 	return status;
3340 }
3341 
3342 /**
3343  * i40e_aq_read_nvm
3344  * @hw: pointer to the hw struct
3345  * @module_pointer: module pointer location in words from the NVM beginning
3346  * @offset: byte offset from the module beginning
3347  * @length: length of the section to be read (in bytes from the offset)
3348  * @data: command buffer (size [bytes] = length)
3349  * @last_command: tells if this is the last command in a series
3350  * @cmd_details: pointer to command details structure or NULL
3351  *
3352  * Read the NVM using the admin queue commands
3353  **/
i40e_aq_read_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,struct i40e_asq_cmd_details * cmd_details)3354 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3355 				u32 offset, u16 length, void *data,
3356 				bool last_command,
3357 				struct i40e_asq_cmd_details *cmd_details)
3358 {
3359 	struct i40e_aq_desc desc;
3360 	struct i40e_aqc_nvm_update *cmd =
3361 		(struct i40e_aqc_nvm_update *)&desc.params.raw;
3362 	enum i40e_status_code status;
3363 
3364 	DEBUGFUNC("i40e_aq_read_nvm");
3365 
3366 	/* In offset the highest byte must be zeroed. */
3367 	if (offset & 0xFF000000) {
3368 		status = I40E_ERR_PARAM;
3369 		goto i40e_aq_read_nvm_exit;
3370 	}
3371 
3372 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3373 
3374 	/* If this is the last command in a series, set the proper flag. */
3375 	if (last_command)
3376 		cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3377 	cmd->module_pointer = module_pointer;
3378 	cmd->offset = CPU_TO_LE32(offset);
3379 	cmd->length = CPU_TO_LE16(length);
3380 
3381 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3382 	if (length > I40E_AQ_LARGE_BUF)
3383 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3384 
3385 	status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3386 
3387 i40e_aq_read_nvm_exit:
3388 	return status;
3389 }
3390 
3391 /**
3392  * i40e_aq_read_nvm_config - read an nvm config block
3393  * @hw: pointer to the hw struct
3394  * @cmd_flags: NVM access admin command bits
3395  * @field_id: field or feature id
3396  * @data: buffer for result
3397  * @buf_size: buffer size
3398  * @element_count: pointer to count of elements read by FW
3399  * @cmd_details: pointer to command details structure or NULL
3400  **/
i40e_aq_read_nvm_config(struct i40e_hw * hw,u8 cmd_flags,u32 field_id,void * data,u16 buf_size,u16 * element_count,struct i40e_asq_cmd_details * cmd_details)3401 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3402 				u8 cmd_flags, u32 field_id, void *data,
3403 				u16 buf_size, u16 *element_count,
3404 				struct i40e_asq_cmd_details *cmd_details)
3405 {
3406 	struct i40e_aq_desc desc;
3407 	struct i40e_aqc_nvm_config_read *cmd =
3408 		(struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3409 	enum i40e_status_code status;
3410 
3411 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3412 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3413 	if (buf_size > I40E_AQ_LARGE_BUF)
3414 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3415 
3416 	cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3417 	cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3418 	if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3419 		cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3420 	else
3421 		cmd->element_id_msw = 0;
3422 
3423 	status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3424 
3425 	if (!status && element_count)
3426 		*element_count = LE16_TO_CPU(cmd->element_count);
3427 
3428 	return status;
3429 }
3430 
3431 /**
3432  * i40e_aq_write_nvm_config - write an nvm config block
3433  * @hw: pointer to the hw struct
3434  * @cmd_flags: NVM access admin command bits
3435  * @data: buffer for result
3436  * @buf_size: buffer size
3437  * @element_count: count of elements to be written
3438  * @cmd_details: pointer to command details structure or NULL
3439  **/
i40e_aq_write_nvm_config(struct i40e_hw * hw,u8 cmd_flags,void * data,u16 buf_size,u16 element_count,struct i40e_asq_cmd_details * cmd_details)3440 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3441 				u8 cmd_flags, void *data, u16 buf_size,
3442 				u16 element_count,
3443 				struct i40e_asq_cmd_details *cmd_details)
3444 {
3445 	struct i40e_aq_desc desc;
3446 	struct i40e_aqc_nvm_config_write *cmd =
3447 		(struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3448 	enum i40e_status_code status;
3449 
3450 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3451 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3452 	if (buf_size > I40E_AQ_LARGE_BUF)
3453 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3454 
3455 	cmd->element_count = CPU_TO_LE16(element_count);
3456 	cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3457 	status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3458 
3459 	return status;
3460 }
3461 
3462 /**
3463  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3464  * @hw: pointer to the hw struct
3465  * @cmd_details: pointer to command details structure or NULL
3466  **/
i40e_aq_oem_post_update(struct i40e_hw * hw,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3467 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3468 				void *buff, u16 buff_size,
3469 				struct i40e_asq_cmd_details *cmd_details)
3470 {
3471 	struct i40e_aq_desc desc;
3472 	enum i40e_status_code status;
3473 
3474 
3475 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3476 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3477 	if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3478 		status = I40E_ERR_NOT_IMPLEMENTED;
3479 
3480 	return status;
3481 }
3482 
3483 /**
3484  * i40e_aq_erase_nvm
3485  * @hw: pointer to the hw struct
3486  * @module_pointer: module pointer location in words from the NVM beginning
3487  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3488  * @length: length of the section to be erased (expressed in 4 KB)
3489  * @last_command: tells if this is the last command in a series
3490  * @cmd_details: pointer to command details structure or NULL
3491  *
3492  * Erase the NVM sector using the admin queue commands
3493  **/
i40e_aq_erase_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,bool last_command,struct i40e_asq_cmd_details * cmd_details)3494 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3495 				u32 offset, u16 length, bool last_command,
3496 				struct i40e_asq_cmd_details *cmd_details)
3497 {
3498 	struct i40e_aq_desc desc;
3499 	struct i40e_aqc_nvm_update *cmd =
3500 		(struct i40e_aqc_nvm_update *)&desc.params.raw;
3501 	enum i40e_status_code status;
3502 
3503 	DEBUGFUNC("i40e_aq_erase_nvm");
3504 
3505 	/* In offset the highest byte must be zeroed. */
3506 	if (offset & 0xFF000000) {
3507 		status = I40E_ERR_PARAM;
3508 		goto i40e_aq_erase_nvm_exit;
3509 	}
3510 
3511 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3512 
3513 	/* If this is the last command in a series, set the proper flag. */
3514 	if (last_command)
3515 		cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3516 	cmd->module_pointer = module_pointer;
3517 	cmd->offset = CPU_TO_LE32(offset);
3518 	cmd->length = CPU_TO_LE16(length);
3519 
3520 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3521 
3522 i40e_aq_erase_nvm_exit:
3523 	return status;
3524 }
3525 
3526 /**
3527  * i40e_parse_discover_capabilities
3528  * @hw: pointer to the hw struct
3529  * @buff: pointer to a buffer containing device/function capability records
3530  * @cap_count: number of capability records in the list
3531  * @list_type_opc: type of capabilities list to parse
3532  *
3533  * Parse the device/function capabilities list.
3534  **/
i40e_parse_discover_capabilities(struct i40e_hw * hw,void * buff,u32 cap_count,enum i40e_admin_queue_opc list_type_opc)3535 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3536 				     u32 cap_count,
3537 				     enum i40e_admin_queue_opc list_type_opc)
3538 {
3539 	struct i40e_aqc_list_capabilities_element_resp *cap;
3540 	u32 valid_functions, num_functions;
3541 	u32 number, logical_id, phys_id;
3542 	struct i40e_hw_capabilities *p;
3543 	u8 major_rev;
3544 	u32 i = 0;
3545 	u16 id;
3546 
3547 	cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3548 
3549 	if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3550 		p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3551 	else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3552 		p = (struct i40e_hw_capabilities *)&hw->func_caps;
3553 	else
3554 		return;
3555 
3556 	for (i = 0; i < cap_count; i++, cap++) {
3557 		id = LE16_TO_CPU(cap->id);
3558 		number = LE32_TO_CPU(cap->number);
3559 		logical_id = LE32_TO_CPU(cap->logical_id);
3560 		phys_id = LE32_TO_CPU(cap->phys_id);
3561 		major_rev = cap->major_rev;
3562 
3563 		switch (id) {
3564 		case I40E_AQ_CAP_ID_SWITCH_MODE:
3565 			p->switch_mode = number;
3566 			i40e_debug(hw, I40E_DEBUG_INIT,
3567 				   "HW Capability: Switch mode = %d\n",
3568 				   p->switch_mode);
3569 			break;
3570 		case I40E_AQ_CAP_ID_MNG_MODE:
3571 			p->management_mode = number;
3572 			if (major_rev > 1) {
3573 				p->mng_protocols_over_mctp = logical_id;
3574 				i40e_debug(hw, I40E_DEBUG_INIT,
3575 					   "HW Capability: Protocols over MCTP = %d\n",
3576 					   p->mng_protocols_over_mctp);
3577 			} else {
3578 				p->mng_protocols_over_mctp = 0;
3579 			}
3580 			i40e_debug(hw, I40E_DEBUG_INIT,
3581 				   "HW Capability: Management Mode = %d\n",
3582 				   p->management_mode);
3583 			break;
3584 		case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3585 			p->npar_enable = number;
3586 			i40e_debug(hw, I40E_DEBUG_INIT,
3587 				   "HW Capability: NPAR enable = %d\n",
3588 				   p->npar_enable);
3589 			break;
3590 		case I40E_AQ_CAP_ID_OS2BMC_CAP:
3591 			p->os2bmc = number;
3592 			i40e_debug(hw, I40E_DEBUG_INIT,
3593 				   "HW Capability: OS2BMC = %d\n", p->os2bmc);
3594 			break;
3595 		case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3596 			p->valid_functions = number;
3597 			i40e_debug(hw, I40E_DEBUG_INIT,
3598 				   "HW Capability: Valid Functions = %d\n",
3599 				   p->valid_functions);
3600 			break;
3601 		case I40E_AQ_CAP_ID_SRIOV:
3602 			if (number == 1)
3603 				p->sr_iov_1_1 = TRUE;
3604 			i40e_debug(hw, I40E_DEBUG_INIT,
3605 				   "HW Capability: SR-IOV = %d\n",
3606 				   p->sr_iov_1_1);
3607 			break;
3608 		case I40E_AQ_CAP_ID_VF:
3609 			p->num_vfs = number;
3610 			p->vf_base_id = logical_id;
3611 			i40e_debug(hw, I40E_DEBUG_INIT,
3612 				   "HW Capability: VF count = %d\n",
3613 				   p->num_vfs);
3614 			i40e_debug(hw, I40E_DEBUG_INIT,
3615 				   "HW Capability: VF base_id = %d\n",
3616 				   p->vf_base_id);
3617 			break;
3618 		case I40E_AQ_CAP_ID_VMDQ:
3619 			if (number == 1)
3620 				p->vmdq = TRUE;
3621 			i40e_debug(hw, I40E_DEBUG_INIT,
3622 				   "HW Capability: VMDQ = %d\n", p->vmdq);
3623 			break;
3624 		case I40E_AQ_CAP_ID_8021QBG:
3625 			if (number == 1)
3626 				p->evb_802_1_qbg = TRUE;
3627 			i40e_debug(hw, I40E_DEBUG_INIT,
3628 				   "HW Capability: 802.1Qbg = %d\n", number);
3629 			break;
3630 		case I40E_AQ_CAP_ID_8021QBR:
3631 			if (number == 1)
3632 				p->evb_802_1_qbh = TRUE;
3633 			i40e_debug(hw, I40E_DEBUG_INIT,
3634 				   "HW Capability: 802.1Qbh = %d\n", number);
3635 			break;
3636 		case I40E_AQ_CAP_ID_VSI:
3637 			p->num_vsis = number;
3638 			i40e_debug(hw, I40E_DEBUG_INIT,
3639 				   "HW Capability: VSI count = %d\n",
3640 				   p->num_vsis);
3641 			break;
3642 		case I40E_AQ_CAP_ID_DCB:
3643 			if (number == 1) {
3644 				p->dcb = TRUE;
3645 				p->enabled_tcmap = logical_id;
3646 				p->maxtc = phys_id;
3647 			}
3648 			i40e_debug(hw, I40E_DEBUG_INIT,
3649 				   "HW Capability: DCB = %d\n", p->dcb);
3650 			i40e_debug(hw, I40E_DEBUG_INIT,
3651 				   "HW Capability: TC Mapping = %d\n",
3652 				   logical_id);
3653 			i40e_debug(hw, I40E_DEBUG_INIT,
3654 				   "HW Capability: TC Max = %d\n", p->maxtc);
3655 			break;
3656 		case I40E_AQ_CAP_ID_FCOE:
3657 			if (number == 1)
3658 				p->fcoe = TRUE;
3659 			i40e_debug(hw, I40E_DEBUG_INIT,
3660 				   "HW Capability: FCOE = %d\n", p->fcoe);
3661 			break;
3662 		case I40E_AQ_CAP_ID_ISCSI:
3663 			if (number == 1)
3664 				p->iscsi = TRUE;
3665 			i40e_debug(hw, I40E_DEBUG_INIT,
3666 				   "HW Capability: iSCSI = %d\n", p->iscsi);
3667 			break;
3668 		case I40E_AQ_CAP_ID_RSS:
3669 			p->rss = TRUE;
3670 			p->rss_table_size = number;
3671 			p->rss_table_entry_width = logical_id;
3672 			i40e_debug(hw, I40E_DEBUG_INIT,
3673 				   "HW Capability: RSS = %d\n", p->rss);
3674 			i40e_debug(hw, I40E_DEBUG_INIT,
3675 				   "HW Capability: RSS table size = %d\n",
3676 				   p->rss_table_size);
3677 			i40e_debug(hw, I40E_DEBUG_INIT,
3678 				   "HW Capability: RSS table width = %d\n",
3679 				   p->rss_table_entry_width);
3680 			break;
3681 		case I40E_AQ_CAP_ID_RXQ:
3682 			p->num_rx_qp = number;
3683 			p->base_queue = phys_id;
3684 			i40e_debug(hw, I40E_DEBUG_INIT,
3685 				   "HW Capability: Rx QP = %d\n", number);
3686 			i40e_debug(hw, I40E_DEBUG_INIT,
3687 				   "HW Capability: base_queue = %d\n",
3688 				   p->base_queue);
3689 			break;
3690 		case I40E_AQ_CAP_ID_TXQ:
3691 			p->num_tx_qp = number;
3692 			p->base_queue = phys_id;
3693 			i40e_debug(hw, I40E_DEBUG_INIT,
3694 				   "HW Capability: Tx QP = %d\n", number);
3695 			i40e_debug(hw, I40E_DEBUG_INIT,
3696 				   "HW Capability: base_queue = %d\n",
3697 				   p->base_queue);
3698 			break;
3699 		case I40E_AQ_CAP_ID_MSIX:
3700 			p->num_msix_vectors = number;
3701 			i40e_debug(hw, I40E_DEBUG_INIT,
3702 				   "HW Capability: MSIX vector count = %d\n",
3703 				   p->num_msix_vectors);
3704 			break;
3705 		case I40E_AQ_CAP_ID_VF_MSIX:
3706 			p->num_msix_vectors_vf = number;
3707 			i40e_debug(hw, I40E_DEBUG_INIT,
3708 				   "HW Capability: MSIX VF vector count = %d\n",
3709 				   p->num_msix_vectors_vf);
3710 			break;
3711 		case I40E_AQ_CAP_ID_FLEX10:
3712 			if (major_rev == 1) {
3713 				if (number == 1) {
3714 					p->flex10_enable = TRUE;
3715 					p->flex10_capable = TRUE;
3716 				}
3717 			} else {
3718 				/* Capability revision >= 2 */
3719 				if (number & 1)
3720 					p->flex10_enable = TRUE;
3721 				if (number & 2)
3722 					p->flex10_capable = TRUE;
3723 			}
3724 			p->flex10_mode = logical_id;
3725 			p->flex10_status = phys_id;
3726 			i40e_debug(hw, I40E_DEBUG_INIT,
3727 				   "HW Capability: Flex10 mode = %d\n",
3728 				   p->flex10_mode);
3729 			i40e_debug(hw, I40E_DEBUG_INIT,
3730 				   "HW Capability: Flex10 status = %d\n",
3731 				   p->flex10_status);
3732 			break;
3733 		case I40E_AQ_CAP_ID_CEM:
3734 			if (number == 1)
3735 				p->mgmt_cem = TRUE;
3736 			i40e_debug(hw, I40E_DEBUG_INIT,
3737 				   "HW Capability: CEM = %d\n", p->mgmt_cem);
3738 			break;
3739 		case I40E_AQ_CAP_ID_IWARP:
3740 			if (number == 1)
3741 				p->iwarp = TRUE;
3742 			i40e_debug(hw, I40E_DEBUG_INIT,
3743 				   "HW Capability: iWARP = %d\n", p->iwarp);
3744 			break;
3745 		case I40E_AQ_CAP_ID_LED:
3746 			if (phys_id < I40E_HW_CAP_MAX_GPIO)
3747 				p->led[phys_id] = TRUE;
3748 			i40e_debug(hw, I40E_DEBUG_INIT,
3749 				   "HW Capability: LED - PIN %d\n", phys_id);
3750 			break;
3751 		case I40E_AQ_CAP_ID_SDP:
3752 			if (phys_id < I40E_HW_CAP_MAX_GPIO)
3753 				p->sdp[phys_id] = TRUE;
3754 			i40e_debug(hw, I40E_DEBUG_INIT,
3755 				   "HW Capability: SDP - PIN %d\n", phys_id);
3756 			break;
3757 		case I40E_AQ_CAP_ID_MDIO:
3758 			if (number == 1) {
3759 				p->mdio_port_num = phys_id;
3760 				p->mdio_port_mode = logical_id;
3761 			}
3762 			i40e_debug(hw, I40E_DEBUG_INIT,
3763 				   "HW Capability: MDIO port number = %d\n",
3764 				   p->mdio_port_num);
3765 			i40e_debug(hw, I40E_DEBUG_INIT,
3766 				   "HW Capability: MDIO port mode = %d\n",
3767 				   p->mdio_port_mode);
3768 			break;
3769 		case I40E_AQ_CAP_ID_1588:
3770 			if (number == 1)
3771 				p->ieee_1588 = TRUE;
3772 			i40e_debug(hw, I40E_DEBUG_INIT,
3773 				   "HW Capability: IEEE 1588 = %d\n",
3774 				   p->ieee_1588);
3775 			break;
3776 		case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3777 			p->fd = TRUE;
3778 			p->fd_filters_guaranteed = number;
3779 			p->fd_filters_best_effort = logical_id;
3780 			i40e_debug(hw, I40E_DEBUG_INIT,
3781 				   "HW Capability: Flow Director = 1\n");
3782 			i40e_debug(hw, I40E_DEBUG_INIT,
3783 				   "HW Capability: Guaranteed FD filters = %d\n",
3784 				   p->fd_filters_guaranteed);
3785 			break;
3786 		case I40E_AQ_CAP_ID_WSR_PROT:
3787 			p->wr_csr_prot = (u64)number;
3788 			p->wr_csr_prot |= (u64)logical_id << 32;
3789 			i40e_debug(hw, I40E_DEBUG_INIT,
3790 				   "HW Capability: wr_csr_prot = 0x%llX\n\n",
3791 				   (p->wr_csr_prot & 0xffff));
3792 			break;
3793 		case I40E_AQ_CAP_ID_NVM_MGMT:
3794 			if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3795 				p->sec_rev_disabled = TRUE;
3796 			if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3797 				p->update_disabled = TRUE;
3798 			break;
3799 		case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3800 			hw->num_wol_proxy_filters = (u16)number;
3801 			hw->wol_proxy_vsi_seid = (u16)logical_id;
3802 			p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3803 			if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3804 				p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3805 			else
3806 				p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3807 			p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3808 			i40e_debug(hw, I40E_DEBUG_INIT,
3809 				   "HW Capability: WOL proxy filters = %d\n",
3810 				   hw->num_wol_proxy_filters);
3811 			break;
3812 		default:
3813 			break;
3814 		}
3815 	}
3816 
3817 	if (p->fcoe)
3818 		i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3819 
3820 	/* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3821 	p->fcoe = FALSE;
3822 
3823 	/* count the enabled ports (aka the "not disabled" ports) */
3824 	hw->num_ports = 0;
3825 	for (i = 0; i < 4; i++) {
3826 		enum i40e_status_code status;
3827 		u32 port_cfg_reg = I40E_PRTGEN_STATUS + (4 * i);
3828 		u64 port_cfg = 0;
3829 
3830 		/* use AQ read to get the physical register offset instead
3831 		 * of the port relative offset
3832 		 */
3833 		status = i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3834 		if ((status == I40E_SUCCESS) &&
3835 		    (port_cfg & I40E_PRTGEN_STATUS_PORT_VALID_MASK))
3836 			hw->num_ports++;
3837 	}
3838 
3839 	valid_functions = p->valid_functions;
3840 	num_functions = 0;
3841 	while (valid_functions) {
3842 		if (valid_functions & 1)
3843 			num_functions++;
3844 		valid_functions >>= 1;
3845 	}
3846 
3847 	/* partition id is 1-based, and functions are evenly spread
3848 	 * across the ports as partitions
3849 	 */
3850 	if (hw->num_ports != 0) {
3851 		hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3852 		hw->num_partitions = num_functions / hw->num_ports;
3853 	}
3854 
3855 	/* additional HW specific goodies that might
3856 	 * someday be HW version specific
3857 	 */
3858 	p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3859 }
3860 
3861 /**
3862  * i40e_aq_discover_capabilities
3863  * @hw: pointer to the hw struct
3864  * @buff: a virtual buffer to hold the capabilities
3865  * @buff_size: Size of the virtual buffer
3866  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3867  * @list_type_opc: capabilities type to discover - pass in the command opcode
3868  * @cmd_details: pointer to command details structure or NULL
3869  *
3870  * Get the device capabilities descriptions from the firmware
3871  **/
i40e_aq_discover_capabilities(struct i40e_hw * hw,void * buff,u16 buff_size,u16 * data_size,enum i40e_admin_queue_opc list_type_opc,struct i40e_asq_cmd_details * cmd_details)3872 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3873 				void *buff, u16 buff_size, u16 *data_size,
3874 				enum i40e_admin_queue_opc list_type_opc,
3875 				struct i40e_asq_cmd_details *cmd_details)
3876 {
3877 	struct i40e_aqc_list_capabilites *cmd;
3878 	struct i40e_aq_desc desc;
3879 	enum i40e_status_code status = I40E_SUCCESS;
3880 
3881 	cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3882 
3883 	if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3884 		list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3885 		status = I40E_ERR_PARAM;
3886 		goto exit;
3887 	}
3888 
3889 	i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3890 
3891 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3892 	if (buff_size > I40E_AQ_LARGE_BUF)
3893 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3894 
3895 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3896 	*data_size = LE16_TO_CPU(desc.datalen);
3897 
3898 	if (status)
3899 		goto exit;
3900 
3901 	i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3902 					 list_type_opc);
3903 
3904 exit:
3905 	return status;
3906 }
3907 
3908 /**
3909  * i40e_aq_update_nvm
3910  * @hw: pointer to the hw struct
3911  * @module_pointer: module pointer location in words from the NVM beginning
3912  * @offset: byte offset from the module beginning
3913  * @length: length of the section to be written (in bytes from the offset)
3914  * @data: command buffer (size [bytes] = length)
3915  * @last_command: tells if this is the last command in a series
3916  * @cmd_details: pointer to command details structure or NULL
3917  *
3918  * Update the NVM using the admin queue commands
3919  **/
i40e_aq_update_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,struct i40e_asq_cmd_details * cmd_details)3920 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3921 				u32 offset, u16 length, void *data,
3922 				bool last_command,
3923 				struct i40e_asq_cmd_details *cmd_details)
3924 {
3925 	struct i40e_aq_desc desc;
3926 	struct i40e_aqc_nvm_update *cmd =
3927 		(struct i40e_aqc_nvm_update *)&desc.params.raw;
3928 	enum i40e_status_code status;
3929 
3930 	DEBUGFUNC("i40e_aq_update_nvm");
3931 
3932 	/* In offset the highest byte must be zeroed. */
3933 	if (offset & 0xFF000000) {
3934 		status = I40E_ERR_PARAM;
3935 		goto i40e_aq_update_nvm_exit;
3936 	}
3937 
3938 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3939 
3940 	/* If this is the last command in a series, set the proper flag. */
3941 	if (last_command)
3942 		cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3943 	cmd->module_pointer = module_pointer;
3944 	cmd->offset = CPU_TO_LE32(offset);
3945 	cmd->length = CPU_TO_LE16(length);
3946 
3947 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3948 	if (length > I40E_AQ_LARGE_BUF)
3949 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3950 
3951 	status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3952 
3953 i40e_aq_update_nvm_exit:
3954 	return status;
3955 }
3956 
3957 /**
3958  * i40e_aq_get_lldp_mib
3959  * @hw: pointer to the hw struct
3960  * @bridge_type: type of bridge requested
3961  * @mib_type: Local, Remote or both Local and Remote MIBs
3962  * @buff: pointer to a user supplied buffer to store the MIB block
3963  * @buff_size: size of the buffer (in bytes)
3964  * @local_len : length of the returned Local LLDP MIB
3965  * @remote_len: length of the returned Remote LLDP MIB
3966  * @cmd_details: pointer to command details structure or NULL
3967  *
3968  * Requests the complete LLDP MIB (entire packet).
3969  **/
i40e_aq_get_lldp_mib(struct i40e_hw * hw,u8 bridge_type,u8 mib_type,void * buff,u16 buff_size,u16 * local_len,u16 * remote_len,struct i40e_asq_cmd_details * cmd_details)3970 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3971 				u8 mib_type, void *buff, u16 buff_size,
3972 				u16 *local_len, u16 *remote_len,
3973 				struct i40e_asq_cmd_details *cmd_details)
3974 {
3975 	struct i40e_aq_desc desc;
3976 	struct i40e_aqc_lldp_get_mib *cmd =
3977 		(struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3978 	struct i40e_aqc_lldp_get_mib *resp =
3979 		(struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3980 	enum i40e_status_code status;
3981 
3982 	if (buff_size == 0 || !buff)
3983 		return I40E_ERR_PARAM;
3984 
3985 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3986 	/* Indirect Command */
3987 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3988 
3989 	cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3990 	cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3991 		       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3992 
3993 	desc.datalen = CPU_TO_LE16(buff_size);
3994 
3995 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3996 	if (buff_size > I40E_AQ_LARGE_BUF)
3997 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3998 
3999 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4000 	if (!status) {
4001 		if (local_len != NULL)
4002 			*local_len = LE16_TO_CPU(resp->local_len);
4003 		if (remote_len != NULL)
4004 			*remote_len = LE16_TO_CPU(resp->remote_len);
4005 	}
4006 
4007 	return status;
4008 }
4009 
4010  /**
4011  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4012  * @hw: pointer to the hw struct
4013  * @mib_type: Local, Remote or both Local and Remote MIBs
4014  * @buff: pointer to a user supplied buffer to store the MIB block
4015  * @buff_size: size of the buffer (in bytes)
4016  * @cmd_details: pointer to command details structure or NULL
4017  *
4018  * Set the LLDP MIB.
4019  **/
i40e_aq_set_lldp_mib(struct i40e_hw * hw,u8 mib_type,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)4020 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4021 				u8 mib_type, void *buff, u16 buff_size,
4022 				struct i40e_asq_cmd_details *cmd_details)
4023 {
4024 	struct i40e_aq_desc desc;
4025 	struct i40e_aqc_lldp_set_local_mib *cmd =
4026 		(struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4027 	enum i40e_status_code status;
4028 
4029 	if (buff_size == 0 || !buff)
4030 		return I40E_ERR_PARAM;
4031 
4032 	i40e_fill_default_direct_cmd_desc(&desc,
4033 				i40e_aqc_opc_lldp_set_local_mib);
4034 	/* Indirect Command */
4035 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4036 	if (buff_size > I40E_AQ_LARGE_BUF)
4037 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4038 	desc.datalen = CPU_TO_LE16(buff_size);
4039 
4040 	cmd->type = mib_type;
4041 	cmd->length = CPU_TO_LE16(buff_size);
4042 	cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((uintptr_t)buff));
4043 	cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buff));
4044 
4045 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4046 	return status;
4047 }
4048 
4049 /**
4050  * i40e_aq_cfg_lldp_mib_change_event
4051  * @hw: pointer to the hw struct
4052  * @enable_update: Enable or Disable event posting
4053  * @cmd_details: pointer to command details structure or NULL
4054  *
4055  * Enable or Disable posting of an event on ARQ when LLDP MIB
4056  * associated with the interface changes
4057  **/
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw * hw,bool enable_update,struct i40e_asq_cmd_details * cmd_details)4058 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4059 				bool enable_update,
4060 				struct i40e_asq_cmd_details *cmd_details)
4061 {
4062 	struct i40e_aq_desc desc;
4063 	struct i40e_aqc_lldp_update_mib *cmd =
4064 		(struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4065 	enum i40e_status_code status;
4066 
4067 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4068 
4069 	if (!enable_update)
4070 		cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4071 
4072 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4073 
4074 	return status;
4075 }
4076 
4077 /**
4078  * i40e_aq_add_lldp_tlv
4079  * @hw: pointer to the hw struct
4080  * @bridge_type: type of bridge
4081  * @buff: buffer with TLV to add
4082  * @buff_size: length of the buffer
4083  * @tlv_len: length of the TLV to be added
4084  * @mib_len: length of the LLDP MIB returned in response
4085  * @cmd_details: pointer to command details structure or NULL
4086  *
4087  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4088  * it is responsibility of the caller to make sure that the TLV is not
4089  * already present in the LLDPDU.
4090  * In return firmware will write the complete LLDP MIB with the newly
4091  * added TLV in the response buffer.
4092  **/
i40e_aq_add_lldp_tlv(struct i40e_hw * hw,u8 bridge_type,void * buff,u16 buff_size,u16 tlv_len,u16 * mib_len,struct i40e_asq_cmd_details * cmd_details)4093 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4094 				void *buff, u16 buff_size, u16 tlv_len,
4095 				u16 *mib_len,
4096 				struct i40e_asq_cmd_details *cmd_details)
4097 {
4098 	struct i40e_aq_desc desc;
4099 	struct i40e_aqc_lldp_add_tlv *cmd =
4100 		(struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4101 	enum i40e_status_code status;
4102 
4103 	if (buff_size == 0 || !buff || tlv_len == 0)
4104 		return I40E_ERR_PARAM;
4105 
4106 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4107 
4108 	/* Indirect Command */
4109 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4110 	if (buff_size > I40E_AQ_LARGE_BUF)
4111 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4112 	desc.datalen = CPU_TO_LE16(buff_size);
4113 
4114 	cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4115 		      I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4116 	cmd->len = CPU_TO_LE16(tlv_len);
4117 
4118 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4119 	if (!status) {
4120 		if (mib_len != NULL)
4121 			*mib_len = LE16_TO_CPU(desc.datalen);
4122 	}
4123 
4124 	return status;
4125 }
4126 
4127 /**
4128  * i40e_aq_update_lldp_tlv
4129  * @hw: pointer to the hw struct
4130  * @bridge_type: type of bridge
4131  * @buff: buffer with TLV to update
4132  * @buff_size: size of the buffer holding original and updated TLVs
4133  * @old_len: Length of the Original TLV
4134  * @new_len: Length of the Updated TLV
4135  * @offset: offset of the updated TLV in the buff
4136  * @mib_len: length of the returned LLDP MIB
4137  * @cmd_details: pointer to command details structure or NULL
4138  *
4139  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4140  * Firmware will place the complete LLDP MIB in response buffer with the
4141  * updated TLV.
4142  **/
i40e_aq_update_lldp_tlv(struct i40e_hw * hw,u8 bridge_type,void * buff,u16 buff_size,u16 old_len,u16 new_len,u16 offset,u16 * mib_len,struct i40e_asq_cmd_details * cmd_details)4143 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4144 				u8 bridge_type, void *buff, u16 buff_size,
4145 				u16 old_len, u16 new_len, u16 offset,
4146 				u16 *mib_len,
4147 				struct i40e_asq_cmd_details *cmd_details)
4148 {
4149 	struct i40e_aq_desc desc;
4150 	struct i40e_aqc_lldp_update_tlv *cmd =
4151 		(struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4152 	enum i40e_status_code status;
4153 
4154 	if (buff_size == 0 || !buff || offset == 0 ||
4155 	    old_len == 0 || new_len == 0)
4156 		return I40E_ERR_PARAM;
4157 
4158 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4159 
4160 	/* Indirect Command */
4161 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4162 	if (buff_size > I40E_AQ_LARGE_BUF)
4163 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4164 	desc.datalen = CPU_TO_LE16(buff_size);
4165 
4166 	cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4167 		      I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4168 	cmd->old_len = CPU_TO_LE16(old_len);
4169 	cmd->new_offset = CPU_TO_LE16(offset);
4170 	cmd->new_len = CPU_TO_LE16(new_len);
4171 
4172 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4173 	if (!status) {
4174 		if (mib_len != NULL)
4175 			*mib_len = LE16_TO_CPU(desc.datalen);
4176 	}
4177 
4178 	return status;
4179 }
4180 
4181 /**
4182  * i40e_aq_delete_lldp_tlv
4183  * @hw: pointer to the hw struct
4184  * @bridge_type: type of bridge
4185  * @buff: pointer to a user supplied buffer that has the TLV
4186  * @buff_size: length of the buffer
4187  * @tlv_len: length of the TLV to be deleted
4188  * @mib_len: length of the returned LLDP MIB
4189  * @cmd_details: pointer to command details structure or NULL
4190  *
4191  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4192  * The firmware places the entire LLDP MIB in the response buffer.
4193  **/
i40e_aq_delete_lldp_tlv(struct i40e_hw * hw,u8 bridge_type,void * buff,u16 buff_size,u16 tlv_len,u16 * mib_len,struct i40e_asq_cmd_details * cmd_details)4194 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4195 				u8 bridge_type, void *buff, u16 buff_size,
4196 				u16 tlv_len, u16 *mib_len,
4197 				struct i40e_asq_cmd_details *cmd_details)
4198 {
4199 	struct i40e_aq_desc desc;
4200 	struct i40e_aqc_lldp_add_tlv *cmd =
4201 		(struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4202 	enum i40e_status_code status;
4203 
4204 	if (buff_size == 0 || !buff)
4205 		return I40E_ERR_PARAM;
4206 
4207 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4208 
4209 	/* Indirect Command */
4210 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4211 	if (buff_size > I40E_AQ_LARGE_BUF)
4212 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4213 	desc.datalen = CPU_TO_LE16(buff_size);
4214 	cmd->len = CPU_TO_LE16(tlv_len);
4215 	cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4216 		      I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4217 
4218 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4219 	if (!status) {
4220 		if (mib_len != NULL)
4221 			*mib_len = LE16_TO_CPU(desc.datalen);
4222 	}
4223 
4224 	return status;
4225 }
4226 
4227 /**
4228  * i40e_aq_stop_lldp
4229  * @hw: pointer to the hw struct
4230  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4231  * @cmd_details: pointer to command details structure or NULL
4232  *
4233  * Stop or Shutdown the embedded LLDP Agent
4234  **/
i40e_aq_stop_lldp(struct i40e_hw * hw,bool shutdown_agent,struct i40e_asq_cmd_details * cmd_details)4235 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4236 				struct i40e_asq_cmd_details *cmd_details)
4237 {
4238 	struct i40e_aq_desc desc;
4239 	struct i40e_aqc_lldp_stop *cmd =
4240 		(struct i40e_aqc_lldp_stop *)&desc.params.raw;
4241 	enum i40e_status_code status;
4242 
4243 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4244 
4245 	if (shutdown_agent)
4246 		cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4247 
4248 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4249 
4250 	return status;
4251 }
4252 
4253 /**
4254  * i40e_aq_start_lldp
4255  * @hw: pointer to the hw struct
4256  * @cmd_details: pointer to command details structure or NULL
4257  *
4258  * Start the embedded LLDP Agent on all ports.
4259  **/
i40e_aq_start_lldp(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)4260 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4261 				struct i40e_asq_cmd_details *cmd_details)
4262 {
4263 	struct i40e_aq_desc desc;
4264 	struct i40e_aqc_lldp_start *cmd =
4265 		(struct i40e_aqc_lldp_start *)&desc.params.raw;
4266 	enum i40e_status_code status;
4267 
4268 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4269 
4270 	cmd->command = I40E_AQ_LLDP_AGENT_START;
4271 
4272 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4273 
4274 	return status;
4275 }
4276 
4277 /**
4278  * i40e_aq_get_cee_dcb_config
4279  * @hw: pointer to the hw struct
4280  * @buff: response buffer that stores CEE operational configuration
4281  * @buff_size: size of the buffer passed
4282  * @cmd_details: pointer to command details structure or NULL
4283  *
4284  * Get CEE DCBX mode operational configuration from firmware
4285  **/
i40e_aq_get_cee_dcb_config(struct i40e_hw * hw,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)4286 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4287 				void *buff, u16 buff_size,
4288 				struct i40e_asq_cmd_details *cmd_details)
4289 {
4290 	struct i40e_aq_desc desc;
4291 	enum i40e_status_code status;
4292 
4293 	if (buff_size == 0 || !buff)
4294 		return I40E_ERR_PARAM;
4295 
4296 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4297 
4298 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4299 	status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4300 				       cmd_details);
4301 
4302 	return status;
4303 }
4304 
4305 /**
4306  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4307  * @hw: pointer to the hw struct
4308  * @start_agent: True if DCBx Agent needs to be Started
4309  *				False if DCBx Agent needs to be Stopped
4310  * @cmd_details: pointer to command details structure or NULL
4311  *
4312  * Start/Stop the embedded dcbx Agent
4313  **/
i40e_aq_start_stop_dcbx(struct i40e_hw * hw,bool start_agent,struct i40e_asq_cmd_details * cmd_details)4314 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4315 				bool start_agent,
4316 				struct i40e_asq_cmd_details *cmd_details)
4317 {
4318 	struct i40e_aq_desc desc;
4319 	struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4320 		(struct i40e_aqc_lldp_stop_start_specific_agent *)
4321 				&desc.params.raw;
4322 	enum i40e_status_code status;
4323 
4324 	i40e_fill_default_direct_cmd_desc(&desc,
4325 				i40e_aqc_opc_lldp_stop_start_spec_agent);
4326 
4327 	if (start_agent)
4328 		cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4329 
4330 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4331 
4332 	return status;
4333 }
4334 
4335 /**
4336  * i40e_aq_add_udp_tunnel
4337  * @hw: pointer to the hw struct
4338  * @udp_port: the UDP port to add
4339  * @header_len: length of the tunneling header length in DWords
4340  * @protocol_index: protocol index type
4341  * @filter_index: pointer to filter index
4342  * @cmd_details: pointer to command details structure or NULL
4343  **/
i40e_aq_add_udp_tunnel(struct i40e_hw * hw,u16 udp_port,u8 protocol_index,u8 * filter_index,struct i40e_asq_cmd_details * cmd_details)4344 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4345 				u16 udp_port, u8 protocol_index,
4346 				u8 *filter_index,
4347 				struct i40e_asq_cmd_details *cmd_details)
4348 {
4349 	struct i40e_aq_desc desc;
4350 	struct i40e_aqc_add_udp_tunnel *cmd =
4351 		(struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4352 	struct i40e_aqc_del_udp_tunnel_completion *resp =
4353 		(struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4354 	enum i40e_status_code status;
4355 
4356 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4357 
4358 	cmd->udp_port = CPU_TO_LE16(udp_port);
4359 	cmd->protocol_type = protocol_index;
4360 
4361 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4362 
4363 	if (!status && filter_index)
4364 		*filter_index = resp->index;
4365 
4366 	return status;
4367 }
4368 
4369 /**
4370  * i40e_aq_del_udp_tunnel
4371  * @hw: pointer to the hw struct
4372  * @index: filter index
4373  * @cmd_details: pointer to command details structure or NULL
4374  **/
i40e_aq_del_udp_tunnel(struct i40e_hw * hw,u8 index,struct i40e_asq_cmd_details * cmd_details)4375 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4376 				struct i40e_asq_cmd_details *cmd_details)
4377 {
4378 	struct i40e_aq_desc desc;
4379 	struct i40e_aqc_remove_udp_tunnel *cmd =
4380 		(struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4381 	enum i40e_status_code status;
4382 
4383 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4384 
4385 	cmd->index = index;
4386 
4387 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4388 
4389 	return status;
4390 }
4391 
4392 /**
4393  * i40e_aq_get_switch_resource_alloc (0x0204)
4394  * @hw: pointer to the hw struct
4395  * @num_entries: pointer to u8 to store the number of resource entries returned
4396  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4397  *        to store the resource information for all resource types.  Each
4398  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4399  * @count: size, in bytes, of the buffer provided
4400  * @cmd_details: pointer to command details structure or NULL
4401  *
4402  * Query the resources allocated to a function.
4403  **/
i40e_aq_get_switch_resource_alloc(struct i40e_hw * hw,u8 * num_entries,struct i40e_aqc_switch_resource_alloc_element_resp * buf,u16 count,struct i40e_asq_cmd_details * cmd_details)4404 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4405 			u8 *num_entries,
4406 			struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4407 			u16 count,
4408 			struct i40e_asq_cmd_details *cmd_details)
4409 {
4410 	struct i40e_aq_desc desc;
4411 	struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4412 		(struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4413 	enum i40e_status_code status;
4414 	u16 length = count * sizeof(*buf);
4415 
4416 	i40e_fill_default_direct_cmd_desc(&desc,
4417 					i40e_aqc_opc_get_switch_resource_alloc);
4418 
4419 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4420 	if (length > I40E_AQ_LARGE_BUF)
4421 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4422 
4423 	status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4424 
4425 	if (!status && num_entries)
4426 		*num_entries = cmd_resp->num_entries;
4427 
4428 	return status;
4429 }
4430 
4431 /**
4432  * i40e_aq_delete_element - Delete switch element
4433  * @hw: pointer to the hw struct
4434  * @seid: the SEID to delete from the switch
4435  * @cmd_details: pointer to command details structure or NULL
4436  *
4437  * This deletes a switch element from the switch.
4438  **/
i40e_aq_delete_element(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)4439 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4440 				struct i40e_asq_cmd_details *cmd_details)
4441 {
4442 	struct i40e_aq_desc desc;
4443 	struct i40e_aqc_switch_seid *cmd =
4444 		(struct i40e_aqc_switch_seid *)&desc.params.raw;
4445 	enum i40e_status_code status;
4446 
4447 	if (seid == 0)
4448 		return I40E_ERR_PARAM;
4449 
4450 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4451 
4452 	cmd->seid = CPU_TO_LE16(seid);
4453 
4454 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4455 
4456 	return status;
4457 }
4458 
4459 /**
4460  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4461  * @hw: pointer to the hw struct
4462  * @flags: component flags
4463  * @mac_seid: uplink seid (MAC SEID)
4464  * @vsi_seid: connected vsi seid
4465  * @ret_seid: seid of create pv component
4466  *
4467  * This instantiates an i40e port virtualizer with specified flags.
4468  * Depending on specified flags the port virtualizer can act as a
4469  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4470  */
i40e_aq_add_pvirt(struct i40e_hw * hw,u16 flags,u16 mac_seid,u16 vsi_seid,u16 * ret_seid)4471 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4472 				       u16 mac_seid, u16 vsi_seid,
4473 				       u16 *ret_seid)
4474 {
4475 	struct i40e_aq_desc desc;
4476 	struct i40e_aqc_add_update_pv *cmd =
4477 		(struct i40e_aqc_add_update_pv *)&desc.params.raw;
4478 	struct i40e_aqc_add_update_pv_completion *resp =
4479 		(struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4480 	enum i40e_status_code status;
4481 
4482 	if (vsi_seid == 0)
4483 		return I40E_ERR_PARAM;
4484 
4485 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4486 	cmd->command_flags = CPU_TO_LE16(flags);
4487 	cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4488 	cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4489 
4490 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4491 	if (!status && ret_seid)
4492 		*ret_seid = LE16_TO_CPU(resp->pv_seid);
4493 
4494 	return status;
4495 }
4496 
4497 /**
4498  * i40e_aq_add_tag - Add an S/E-tag
4499  * @hw: pointer to the hw struct
4500  * @direct_to_queue: should s-tag direct flow to a specific queue
4501  * @vsi_seid: VSI SEID to use this tag
4502  * @tag: value of the tag
4503  * @queue_num: queue number, only valid is direct_to_queue is TRUE
4504  * @tags_used: return value, number of tags in use by this PF
4505  * @tags_free: return value, number of unallocated tags
4506  * @cmd_details: pointer to command details structure or NULL
4507  *
4508  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4509  * the number of tags allocated by the PF, and the number of unallocated
4510  * tags available.
4511  **/
i40e_aq_add_tag(struct i40e_hw * hw,bool direct_to_queue,u16 vsi_seid,u16 tag,u16 queue_num,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4512 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4513 				u16 vsi_seid, u16 tag, u16 queue_num,
4514 				u16 *tags_used, u16 *tags_free,
4515 				struct i40e_asq_cmd_details *cmd_details)
4516 {
4517 	struct i40e_aq_desc desc;
4518 	struct i40e_aqc_add_tag *cmd =
4519 		(struct i40e_aqc_add_tag *)&desc.params.raw;
4520 	struct i40e_aqc_add_remove_tag_completion *resp =
4521 		(struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4522 	enum i40e_status_code status;
4523 
4524 	if (vsi_seid == 0)
4525 		return I40E_ERR_PARAM;
4526 
4527 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4528 
4529 	cmd->seid = CPU_TO_LE16(vsi_seid);
4530 	cmd->tag = CPU_TO_LE16(tag);
4531 	if (direct_to_queue) {
4532 		cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4533 		cmd->queue_number = CPU_TO_LE16(queue_num);
4534 	}
4535 
4536 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4537 
4538 	if (!status) {
4539 		if (tags_used != NULL)
4540 			*tags_used = LE16_TO_CPU(resp->tags_used);
4541 		if (tags_free != NULL)
4542 			*tags_free = LE16_TO_CPU(resp->tags_free);
4543 	}
4544 
4545 	return status;
4546 }
4547 
4548 /**
4549  * i40e_aq_remove_tag - Remove an S- or E-tag
4550  * @hw: pointer to the hw struct
4551  * @vsi_seid: VSI SEID this tag is associated with
4552  * @tag: value of the S-tag to delete
4553  * @tags_used: return value, number of tags in use by this PF
4554  * @tags_free: return value, number of unallocated tags
4555  * @cmd_details: pointer to command details structure or NULL
4556  *
4557  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4558  * the number of tags allocated by the PF, and the number of unallocated
4559  * tags available.
4560  **/
i40e_aq_remove_tag(struct i40e_hw * hw,u16 vsi_seid,u16 tag,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4561 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4562 				u16 tag, u16 *tags_used, u16 *tags_free,
4563 				struct i40e_asq_cmd_details *cmd_details)
4564 {
4565 	struct i40e_aq_desc desc;
4566 	struct i40e_aqc_remove_tag *cmd =
4567 		(struct i40e_aqc_remove_tag *)&desc.params.raw;
4568 	struct i40e_aqc_add_remove_tag_completion *resp =
4569 		(struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4570 	enum i40e_status_code status;
4571 
4572 	if (vsi_seid == 0)
4573 		return I40E_ERR_PARAM;
4574 
4575 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4576 
4577 	cmd->seid = CPU_TO_LE16(vsi_seid);
4578 	cmd->tag = CPU_TO_LE16(tag);
4579 
4580 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4581 
4582 	if (!status) {
4583 		if (tags_used != NULL)
4584 			*tags_used = LE16_TO_CPU(resp->tags_used);
4585 		if (tags_free != NULL)
4586 			*tags_free = LE16_TO_CPU(resp->tags_free);
4587 	}
4588 
4589 	return status;
4590 }
4591 
4592 /**
4593  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4594  * @hw: pointer to the hw struct
4595  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4596  * @etag: value of E-tag to add
4597  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4598  * @buf: address of indirect buffer
4599  * @tags_used: return value, number of E-tags in use by this port
4600  * @tags_free: return value, number of unallocated M-tags
4601  * @cmd_details: pointer to command details structure or NULL
4602  *
4603  * This associates a multicast E-tag to a port virtualizer.  It will return
4604  * the number of tags allocated by the PF, and the number of unallocated
4605  * tags available.
4606  *
4607  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4608  * num_tags_in_buf long.
4609  **/
i40e_aq_add_mcast_etag(struct i40e_hw * hw,u16 pv_seid,u16 etag,u8 num_tags_in_buf,void * buf,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4610 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4611 				u16 etag, u8 num_tags_in_buf, void *buf,
4612 				u16 *tags_used, u16 *tags_free,
4613 				struct i40e_asq_cmd_details *cmd_details)
4614 {
4615 	struct i40e_aq_desc desc;
4616 	struct i40e_aqc_add_remove_mcast_etag *cmd =
4617 		(struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4618 	struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4619 	   (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4620 	enum i40e_status_code status;
4621 	u16 length = sizeof(u16) * num_tags_in_buf;
4622 
4623 	if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4624 		return I40E_ERR_PARAM;
4625 
4626 	i40e_fill_default_direct_cmd_desc(&desc,
4627 					  i40e_aqc_opc_add_multicast_etag);
4628 
4629 	cmd->pv_seid = CPU_TO_LE16(pv_seid);
4630 	cmd->etag = CPU_TO_LE16(etag);
4631 	cmd->num_unicast_etags = num_tags_in_buf;
4632 
4633 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4634 	if (length > I40E_AQ_LARGE_BUF)
4635 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4636 
4637 	status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4638 
4639 	if (!status) {
4640 		if (tags_used != NULL)
4641 			*tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4642 		if (tags_free != NULL)
4643 			*tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4644 	}
4645 
4646 	return status;
4647 }
4648 
4649 /**
4650  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4651  * @hw: pointer to the hw struct
4652  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4653  * @etag: value of the E-tag to remove
4654  * @tags_used: return value, number of tags in use by this port
4655  * @tags_free: return value, number of unallocated tags
4656  * @cmd_details: pointer to command details structure or NULL
4657  *
4658  * This deletes an E-tag from the port virtualizer.  It will return
4659  * the number of tags allocated by the port, and the number of unallocated
4660  * tags available.
4661  **/
i40e_aq_remove_mcast_etag(struct i40e_hw * hw,u16 pv_seid,u16 etag,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4662 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4663 				u16 etag, u16 *tags_used, u16 *tags_free,
4664 				struct i40e_asq_cmd_details *cmd_details)
4665 {
4666 	struct i40e_aq_desc desc;
4667 	struct i40e_aqc_add_remove_mcast_etag *cmd =
4668 		(struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4669 	struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4670 	   (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4671 	enum i40e_status_code status;
4672 
4673 
4674 	if (pv_seid == 0)
4675 		return I40E_ERR_PARAM;
4676 
4677 	i40e_fill_default_direct_cmd_desc(&desc,
4678 					  i40e_aqc_opc_remove_multicast_etag);
4679 
4680 	cmd->pv_seid = CPU_TO_LE16(pv_seid);
4681 	cmd->etag = CPU_TO_LE16(etag);
4682 
4683 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4684 
4685 	if (!status) {
4686 		if (tags_used != NULL)
4687 			*tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4688 		if (tags_free != NULL)
4689 			*tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4690 	}
4691 
4692 	return status;
4693 }
4694 
4695 /**
4696  * i40e_aq_update_tag - Update an S/E-tag
4697  * @hw: pointer to the hw struct
4698  * @vsi_seid: VSI SEID using this S-tag
4699  * @old_tag: old tag value
4700  * @new_tag: new tag value
4701  * @tags_used: return value, number of tags in use by this PF
4702  * @tags_free: return value, number of unallocated tags
4703  * @cmd_details: pointer to command details structure or NULL
4704  *
4705  * This updates the value of the tag currently attached to this VSI
4706  * in the switch complex.  It will return the number of tags allocated
4707  * by the PF, and the number of unallocated tags available.
4708  **/
i40e_aq_update_tag(struct i40e_hw * hw,u16 vsi_seid,u16 old_tag,u16 new_tag,u16 * tags_used,u16 * tags_free,struct i40e_asq_cmd_details * cmd_details)4709 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4710 				u16 old_tag, u16 new_tag, u16 *tags_used,
4711 				u16 *tags_free,
4712 				struct i40e_asq_cmd_details *cmd_details)
4713 {
4714 	struct i40e_aq_desc desc;
4715 	struct i40e_aqc_update_tag *cmd =
4716 		(struct i40e_aqc_update_tag *)&desc.params.raw;
4717 	struct i40e_aqc_update_tag_completion *resp =
4718 		(struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4719 	enum i40e_status_code status;
4720 
4721 	if (vsi_seid == 0)
4722 		return I40E_ERR_PARAM;
4723 
4724 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4725 
4726 	cmd->seid = CPU_TO_LE16(vsi_seid);
4727 	cmd->old_tag = CPU_TO_LE16(old_tag);
4728 	cmd->new_tag = CPU_TO_LE16(new_tag);
4729 
4730 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4731 
4732 	if (!status) {
4733 		if (tags_used != NULL)
4734 			*tags_used = LE16_TO_CPU(resp->tags_used);
4735 		if (tags_free != NULL)
4736 			*tags_free = LE16_TO_CPU(resp->tags_free);
4737 	}
4738 
4739 	return status;
4740 }
4741 
4742 /**
4743  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4744  * @hw: pointer to the hw struct
4745  * @tcmap: TC map for request/release any ignore PFC condition
4746  * @request: request or release ignore PFC condition
4747  * @tcmap_ret: return TCs for which PFC is currently ignored
4748  * @cmd_details: pointer to command details structure or NULL
4749  *
4750  * This sends out request/release to ignore PFC condition for a TC.
4751  * It will return the TCs for which PFC is currently ignored.
4752  **/
i40e_aq_dcb_ignore_pfc(struct i40e_hw * hw,u8 tcmap,bool request,u8 * tcmap_ret,struct i40e_asq_cmd_details * cmd_details)4753 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4754 				bool request, u8 *tcmap_ret,
4755 				struct i40e_asq_cmd_details *cmd_details)
4756 {
4757 	struct i40e_aq_desc desc;
4758 	struct i40e_aqc_pfc_ignore *cmd_resp =
4759 		(struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4760 	enum i40e_status_code status;
4761 
4762 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4763 
4764 	if (request)
4765 		cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4766 
4767 	cmd_resp->tc_bitmap = tcmap;
4768 
4769 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4770 
4771 	if (!status) {
4772 		if (tcmap_ret != NULL)
4773 			*tcmap_ret = cmd_resp->tc_bitmap;
4774 	}
4775 
4776 	return status;
4777 }
4778 
4779 /**
4780  * i40e_aq_dcb_updated - DCB Updated Command
4781  * @hw: pointer to the hw struct
4782  * @cmd_details: pointer to command details structure or NULL
4783  *
4784  * When LLDP is handled in PF this command is used by the PF
4785  * to notify EMP that a DCB setting is modified.
4786  * When LLDP is handled in EMP this command is used by the PF
4787  * to notify EMP whenever one of the following parameters get
4788  * modified:
4789  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4790  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4791  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4792  * EMP will return when the shared RPB settings have been
4793  * recomputed and modified. The retval field in the descriptor
4794  * will be set to 0 when RPB is modified.
4795  **/
i40e_aq_dcb_updated(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)4796 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4797 				struct i40e_asq_cmd_details *cmd_details)
4798 {
4799 	struct i40e_aq_desc desc;
4800 	enum i40e_status_code status;
4801 
4802 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4803 
4804 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4805 
4806 	return status;
4807 }
4808 
4809 /**
4810  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4811  * @hw: pointer to the hw struct
4812  * @seid: defines the SEID of the switch for which the stats are requested
4813  * @vlan_id: the VLAN ID for which the statistics are requested
4814  * @stat_index: index of the statistics counters block assigned to this VLAN
4815  * @cmd_details: pointer to command details structure or NULL
4816  *
4817  * XL710 supports 128 smonVlanStats counters.This command is used to
4818  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4819  * switch.
4820  **/
i40e_aq_add_statistics(struct i40e_hw * hw,u16 seid,u16 vlan_id,u16 * stat_index,struct i40e_asq_cmd_details * cmd_details)4821 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4822 				u16 vlan_id, u16 *stat_index,
4823 				struct i40e_asq_cmd_details *cmd_details)
4824 {
4825 	struct i40e_aq_desc desc;
4826 	struct i40e_aqc_add_remove_statistics *cmd_resp =
4827 		(struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4828 	enum i40e_status_code status;
4829 
4830 	if ((seid == 0) || (stat_index == NULL))
4831 		return I40E_ERR_PARAM;
4832 
4833 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4834 
4835 	cmd_resp->seid = CPU_TO_LE16(seid);
4836 	cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4837 
4838 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4839 
4840 	if (!status && stat_index)
4841 		*stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4842 
4843 	return status;
4844 }
4845 
4846 /**
4847  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4848  * @hw: pointer to the hw struct
4849  * @seid: defines the SEID of the switch for which the stats are requested
4850  * @vlan_id: the VLAN ID for which the statistics are requested
4851  * @stat_index: index of the statistics counters block assigned to this VLAN
4852  * @cmd_details: pointer to command details structure or NULL
4853  *
4854  * XL710 supports 128 smonVlanStats counters.This command is used to
4855  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4856  * switch.
4857  **/
i40e_aq_remove_statistics(struct i40e_hw * hw,u16 seid,u16 vlan_id,u16 stat_index,struct i40e_asq_cmd_details * cmd_details)4858 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4859 				u16 vlan_id, u16 stat_index,
4860 				struct i40e_asq_cmd_details *cmd_details)
4861 {
4862 	struct i40e_aq_desc desc;
4863 	struct i40e_aqc_add_remove_statistics *cmd =
4864 		(struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4865 	enum i40e_status_code status;
4866 
4867 	if (seid == 0)
4868 		return I40E_ERR_PARAM;
4869 
4870 	i40e_fill_default_direct_cmd_desc(&desc,
4871 					  i40e_aqc_opc_remove_statistics);
4872 
4873 	cmd->seid = CPU_TO_LE16(seid);
4874 	cmd->vlan  = CPU_TO_LE16(vlan_id);
4875 	cmd->stat_index = CPU_TO_LE16(stat_index);
4876 
4877 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4878 
4879 	return status;
4880 }
4881 
4882 /**
4883  * i40e_aq_set_port_parameters - set physical port parameters.
4884  * @hw: pointer to the hw struct
4885  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4886  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4887  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4888  * @double_vlan: if set double VLAN is enabled
4889  * @cmd_details: pointer to command details structure or NULL
4890  **/
i40e_aq_set_port_parameters(struct i40e_hw * hw,u16 bad_frame_vsi,bool save_bad_pac,bool pad_short_pac,bool double_vlan,struct i40e_asq_cmd_details * cmd_details)4891 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4892 				u16 bad_frame_vsi, bool save_bad_pac,
4893 				bool pad_short_pac, bool double_vlan,
4894 				struct i40e_asq_cmd_details *cmd_details)
4895 {
4896 	struct i40e_aqc_set_port_parameters *cmd;
4897 	enum i40e_status_code status;
4898 	struct i40e_aq_desc desc;
4899 	u16 command_flags = 0;
4900 
4901 	cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4902 
4903 	i40e_fill_default_direct_cmd_desc(&desc,
4904 					  i40e_aqc_opc_set_port_parameters);
4905 
4906 	cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4907 	if (save_bad_pac)
4908 		command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4909 	if (pad_short_pac)
4910 		command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4911 	if (double_vlan)
4912 		command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4913 	cmd->command_flags = CPU_TO_LE16(command_flags);
4914 
4915 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4916 
4917 	return status;
4918 }
4919 
4920 /**
4921  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4922  * @hw: pointer to the hw struct
4923  * @seid: seid for the physical port/switching component/vsi
4924  * @buff: Indirect buffer to hold data parameters and response
4925  * @buff_size: Indirect buffer size
4926  * @opcode: Tx scheduler AQ command opcode
4927  * @cmd_details: pointer to command details structure or NULL
4928  *
4929  * Generic command handler for Tx scheduler AQ commands
4930  **/
i40e_aq_tx_sched_cmd(struct i40e_hw * hw,u16 seid,void * buff,u16 buff_size,enum i40e_admin_queue_opc opcode,struct i40e_asq_cmd_details * cmd_details)4931 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4932 				void *buff, u16 buff_size,
4933 				 enum i40e_admin_queue_opc opcode,
4934 				struct i40e_asq_cmd_details *cmd_details)
4935 {
4936 	struct i40e_aq_desc desc;
4937 	struct i40e_aqc_tx_sched_ind *cmd =
4938 		(struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4939 	enum i40e_status_code status;
4940 	bool cmd_param_flag = FALSE;
4941 
4942 	switch (opcode) {
4943 	case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4944 	case i40e_aqc_opc_configure_vsi_tc_bw:
4945 	case i40e_aqc_opc_enable_switching_comp_ets:
4946 	case i40e_aqc_opc_modify_switching_comp_ets:
4947 	case i40e_aqc_opc_disable_switching_comp_ets:
4948 	case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4949 	case i40e_aqc_opc_configure_switching_comp_bw_config:
4950 		cmd_param_flag = TRUE;
4951 		break;
4952 	case i40e_aqc_opc_query_vsi_bw_config:
4953 	case i40e_aqc_opc_query_vsi_ets_sla_config:
4954 	case i40e_aqc_opc_query_switching_comp_ets_config:
4955 	case i40e_aqc_opc_query_port_ets_config:
4956 	case i40e_aqc_opc_query_switching_comp_bw_config:
4957 		cmd_param_flag = FALSE;
4958 		break;
4959 	default:
4960 		return I40E_ERR_PARAM;
4961 	}
4962 
4963 	i40e_fill_default_direct_cmd_desc(&desc, opcode);
4964 
4965 	/* Indirect command */
4966 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4967 	if (cmd_param_flag)
4968 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4969 	if (buff_size > I40E_AQ_LARGE_BUF)
4970 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4971 
4972 	desc.datalen = CPU_TO_LE16(buff_size);
4973 
4974 	cmd->vsi_seid = CPU_TO_LE16(seid);
4975 
4976 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4977 
4978 	return status;
4979 }
4980 
4981 /**
4982  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4983  * @hw: pointer to the hw struct
4984  * @seid: VSI seid
4985  * @credit: BW limit credits (0 = disabled)
4986  * @max_credit: Max BW limit credits
4987  * @cmd_details: pointer to command details structure or NULL
4988  **/
i40e_aq_config_vsi_bw_limit(struct i40e_hw * hw,u16 seid,u16 credit,u8 max_credit,struct i40e_asq_cmd_details * cmd_details)4989 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4990 				u16 seid, u16 credit, u8 max_credit,
4991 				struct i40e_asq_cmd_details *cmd_details)
4992 {
4993 	struct i40e_aq_desc desc;
4994 	struct i40e_aqc_configure_vsi_bw_limit *cmd =
4995 		(struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4996 	enum i40e_status_code status;
4997 
4998 	i40e_fill_default_direct_cmd_desc(&desc,
4999 					  i40e_aqc_opc_configure_vsi_bw_limit);
5000 
5001 	cmd->vsi_seid = CPU_TO_LE16(seid);
5002 	cmd->credit = CPU_TO_LE16(credit);
5003 	cmd->max_credit = max_credit;
5004 
5005 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5006 
5007 	return status;
5008 }
5009 
5010 /**
5011  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5012  * @hw: pointer to the hw struct
5013  * @seid: switching component seid
5014  * @credit: BW limit credits (0 = disabled)
5015  * @max_bw: Max BW limit credits
5016  * @cmd_details: pointer to command details structure or NULL
5017  **/
i40e_aq_config_switch_comp_bw_limit(struct i40e_hw * hw,u16 seid,u16 credit,u8 max_bw,struct i40e_asq_cmd_details * cmd_details)5018 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5019 				u16 seid, u16 credit, u8 max_bw,
5020 				struct i40e_asq_cmd_details *cmd_details)
5021 {
5022 	struct i40e_aq_desc desc;
5023 	struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5024 	  (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5025 	enum i40e_status_code status;
5026 
5027 	i40e_fill_default_direct_cmd_desc(&desc,
5028 				i40e_aqc_opc_configure_switching_comp_bw_limit);
5029 
5030 	cmd->seid = CPU_TO_LE16(seid);
5031 	cmd->credit = CPU_TO_LE16(credit);
5032 	cmd->max_bw = max_bw;
5033 
5034 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5035 
5036 	return status;
5037 }
5038 
5039 /**
5040  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5041  * @hw: pointer to the hw struct
5042  * @seid: VSI seid
5043  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5044  * @cmd_details: pointer to command details structure or NULL
5045  **/
i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_vsi_ets_sla_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)5046 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5047 			u16 seid,
5048 			struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5049 			struct i40e_asq_cmd_details *cmd_details)
5050 {
5051 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5052 				    i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5053 				    cmd_details);
5054 }
5055 
5056 /**
5057  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5058  * @hw: pointer to the hw struct
5059  * @seid: VSI seid
5060  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5061  * @cmd_details: pointer to command details structure or NULL
5062  **/
i40e_aq_config_vsi_tc_bw(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_vsi_tc_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)5063 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5064 			u16 seid,
5065 			struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5066 			struct i40e_asq_cmd_details *cmd_details)
5067 {
5068 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5069 				    i40e_aqc_opc_configure_vsi_tc_bw,
5070 				    cmd_details);
5071 }
5072 
5073 /**
5074  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5075  * @hw: pointer to the hw struct
5076  * @seid: seid of the switching component
5077  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5078  * @cmd_details: pointer to command details structure or NULL
5079  **/
i40e_aq_config_switch_comp_ets_bw_limit(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_switching_comp_ets_bw_limit_data * bw_data,struct i40e_asq_cmd_details * cmd_details)5080 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5081 	struct i40e_hw *hw, u16 seid,
5082 	struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5083 	struct i40e_asq_cmd_details *cmd_details)
5084 {
5085 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5086 			    i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5087 			    cmd_details);
5088 }
5089 
5090 /**
5091  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5092  * @hw: pointer to the hw struct
5093  * @seid: seid of the VSI
5094  * @bw_data: Buffer to hold VSI BW configuration
5095  * @cmd_details: pointer to command details structure or NULL
5096  **/
i40e_aq_query_vsi_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)5097 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5098 			u16 seid,
5099 			struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5100 			struct i40e_asq_cmd_details *cmd_details)
5101 {
5102 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5103 				    i40e_aqc_opc_query_vsi_bw_config,
5104 				    cmd_details);
5105 }
5106 
5107 /**
5108  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5109  * @hw: pointer to the hw struct
5110  * @seid: seid of the VSI
5111  * @bw_data: Buffer to hold VSI BW configuration per TC
5112  * @cmd_details: pointer to command details structure or NULL
5113  **/
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_ets_sla_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)5114 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5115 			u16 seid,
5116 			struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5117 			struct i40e_asq_cmd_details *cmd_details)
5118 {
5119 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5120 				    i40e_aqc_opc_query_vsi_ets_sla_config,
5121 				    cmd_details);
5122 }
5123 
5124 /**
5125  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5126  * @hw: pointer to the hw struct
5127  * @seid: seid of the switching component
5128  * @bw_data: Buffer to hold switching component's per TC BW config
5129  * @cmd_details: pointer to command details structure or NULL
5130  **/
i40e_aq_query_switch_comp_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)5131 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5132 		u16 seid,
5133 		struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5134 		struct i40e_asq_cmd_details *cmd_details)
5135 {
5136 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5137 				   i40e_aqc_opc_query_switching_comp_ets_config,
5138 				   cmd_details);
5139 }
5140 
5141 /**
5142  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5143  * @hw: pointer to the hw struct
5144  * @seid: seid of the VSI or switching component connected to Physical Port
5145  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5146  * @cmd_details: pointer to command details structure or NULL
5147  **/
i40e_aq_query_port_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_port_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)5148 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5149 			u16 seid,
5150 			struct i40e_aqc_query_port_ets_config_resp *bw_data,
5151 			struct i40e_asq_cmd_details *cmd_details)
5152 {
5153 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5154 				    i40e_aqc_opc_query_port_ets_config,
5155 				    cmd_details);
5156 }
5157 
5158 /**
5159  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5160  * @hw: pointer to the hw struct
5161  * @seid: seid of the switching component
5162  * @bw_data: Buffer to hold switching component's BW configuration
5163  * @cmd_details: pointer to command details structure or NULL
5164  **/
i40e_aq_query_switch_comp_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)5165 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5166 		u16 seid,
5167 		struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5168 		struct i40e_asq_cmd_details *cmd_details)
5169 {
5170 	return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5171 				    i40e_aqc_opc_query_switching_comp_bw_config,
5172 				    cmd_details);
5173 }
5174 
5175 /**
5176  * i40e_validate_filter_settings
5177  * @hw: pointer to the hardware structure
5178  * @settings: Filter control settings
5179  *
5180  * Check and validate the filter control settings passed.
5181  * The function checks for the valid filter/context sizes being
5182  * passed for FCoE and PE.
5183  *
5184  * Returns I40E_SUCCESS if the values passed are valid and within
5185  * range else returns an error.
5186  **/
i40e_validate_filter_settings(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)5187 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5188 				struct i40e_filter_control_settings *settings)
5189 {
5190 	u32 fcoe_cntx_size, fcoe_filt_size;
5191 	u32 pe_cntx_size, pe_filt_size;
5192 	u32 fcoe_fmax;
5193 
5194 	u32 val;
5195 
5196 	/* Validate FCoE settings passed */
5197 	switch (settings->fcoe_filt_num) {
5198 	case I40E_HASH_FILTER_SIZE_1K:
5199 	case I40E_HASH_FILTER_SIZE_2K:
5200 	case I40E_HASH_FILTER_SIZE_4K:
5201 	case I40E_HASH_FILTER_SIZE_8K:
5202 	case I40E_HASH_FILTER_SIZE_16K:
5203 	case I40E_HASH_FILTER_SIZE_32K:
5204 		fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5205 		fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5206 		break;
5207 	default:
5208 		return I40E_ERR_PARAM;
5209 	}
5210 
5211 	switch (settings->fcoe_cntx_num) {
5212 	case I40E_DMA_CNTX_SIZE_512:
5213 	case I40E_DMA_CNTX_SIZE_1K:
5214 	case I40E_DMA_CNTX_SIZE_2K:
5215 	case I40E_DMA_CNTX_SIZE_4K:
5216 		fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5217 		fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5218 		break;
5219 	default:
5220 		return I40E_ERR_PARAM;
5221 	}
5222 
5223 	/* Validate PE settings passed */
5224 	switch (settings->pe_filt_num) {
5225 	case I40E_HASH_FILTER_SIZE_1K:
5226 	case I40E_HASH_FILTER_SIZE_2K:
5227 	case I40E_HASH_FILTER_SIZE_4K:
5228 	case I40E_HASH_FILTER_SIZE_8K:
5229 	case I40E_HASH_FILTER_SIZE_16K:
5230 	case I40E_HASH_FILTER_SIZE_32K:
5231 	case I40E_HASH_FILTER_SIZE_64K:
5232 	case I40E_HASH_FILTER_SIZE_128K:
5233 	case I40E_HASH_FILTER_SIZE_256K:
5234 	case I40E_HASH_FILTER_SIZE_512K:
5235 	case I40E_HASH_FILTER_SIZE_1M:
5236 		pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5237 		pe_filt_size <<= (u32)settings->pe_filt_num;
5238 		break;
5239 	default:
5240 		return I40E_ERR_PARAM;
5241 	}
5242 
5243 	switch (settings->pe_cntx_num) {
5244 	case I40E_DMA_CNTX_SIZE_512:
5245 	case I40E_DMA_CNTX_SIZE_1K:
5246 	case I40E_DMA_CNTX_SIZE_2K:
5247 	case I40E_DMA_CNTX_SIZE_4K:
5248 	case I40E_DMA_CNTX_SIZE_8K:
5249 	case I40E_DMA_CNTX_SIZE_16K:
5250 	case I40E_DMA_CNTX_SIZE_32K:
5251 	case I40E_DMA_CNTX_SIZE_64K:
5252 	case I40E_DMA_CNTX_SIZE_128K:
5253 	case I40E_DMA_CNTX_SIZE_256K:
5254 		pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5255 		pe_cntx_size <<= (u32)settings->pe_cntx_num;
5256 		break;
5257 	default:
5258 		return I40E_ERR_PARAM;
5259 	}
5260 
5261 	/* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5262 	val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5263 	fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5264 		     >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5265 	if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5266 		return I40E_ERR_INVALID_SIZE;
5267 
5268 	return I40E_SUCCESS;
5269 }
5270 
5271 /**
5272  * i40e_set_filter_control
5273  * @hw: pointer to the hardware structure
5274  * @settings: Filter control settings
5275  *
5276  * Set the Queue Filters for PE/FCoE and enable filters required
5277  * for a single PF. It is expected that these settings are programmed
5278  * at the driver initialization time.
5279  **/
i40e_set_filter_control(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)5280 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5281 				struct i40e_filter_control_settings *settings)
5282 {
5283 	enum i40e_status_code ret = I40E_SUCCESS;
5284 	u32 hash_lut_size = 0;
5285 	u32 val;
5286 
5287 	if (!settings)
5288 		return I40E_ERR_PARAM;
5289 
5290 	/* Validate the input settings */
5291 	ret = i40e_validate_filter_settings(hw, settings);
5292 	if (ret)
5293 		return ret;
5294 
5295 	/* Read the PF Queue Filter control register */
5296 	val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5297 
5298 	/* Program required PE hash buckets for the PF */
5299 	val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5300 	val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5301 		I40E_PFQF_CTL_0_PEHSIZE_MASK;
5302 	/* Program required PE contexts for the PF */
5303 	val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5304 	val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5305 		I40E_PFQF_CTL_0_PEDSIZE_MASK;
5306 
5307 	/* Program required FCoE hash buckets for the PF */
5308 	val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5309 	val |= ((u32)settings->fcoe_filt_num <<
5310 			I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5311 		I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5312 	/* Program required FCoE DDP contexts for the PF */
5313 	val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5314 	val |= ((u32)settings->fcoe_cntx_num <<
5315 			I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5316 		I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5317 
5318 	/* Program Hash LUT size for the PF */
5319 	val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5320 	if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5321 		hash_lut_size = 1;
5322 	val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5323 		I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5324 
5325 	/* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5326 	if (settings->enable_fdir)
5327 		val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5328 	if (settings->enable_ethtype)
5329 		val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5330 	if (settings->enable_macvlan)
5331 		val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5332 
5333 	i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5334 
5335 	return I40E_SUCCESS;
5336 }
5337 
5338 /**
5339  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5340  * @hw: pointer to the hw struct
5341  * @mac_addr: MAC address to use in the filter
5342  * @ethtype: Ethertype to use in the filter
5343  * @flags: Flags that needs to be applied to the filter
5344  * @vsi_seid: seid of the control VSI
5345  * @queue: VSI queue number to send the packet to
5346  * @is_add: Add control packet filter if True else remove
5347  * @stats: Structure to hold information on control filter counts
5348  * @cmd_details: pointer to command details structure or NULL
5349  *
5350  * This command will Add or Remove control packet filter for a control VSI.
5351  * In return it will update the total number of perfect filter count in
5352  * the stats member.
5353  **/
i40e_aq_add_rem_control_packet_filter(struct i40e_hw * hw,u8 * mac_addr,u16 ethtype,u16 flags,u16 vsi_seid,u16 queue,bool is_add,struct i40e_control_filter_stats * stats,struct i40e_asq_cmd_details * cmd_details)5354 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5355 				u8 *mac_addr, u16 ethtype, u16 flags,
5356 				u16 vsi_seid, u16 queue, bool is_add,
5357 				struct i40e_control_filter_stats *stats,
5358 				struct i40e_asq_cmd_details *cmd_details)
5359 {
5360 	struct i40e_aq_desc desc;
5361 	struct i40e_aqc_add_remove_control_packet_filter *cmd =
5362 		(struct i40e_aqc_add_remove_control_packet_filter *)
5363 		&desc.params.raw;
5364 	struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5365 		(struct i40e_aqc_add_remove_control_packet_filter_completion *)
5366 		&desc.params.raw;
5367 	enum i40e_status_code status;
5368 
5369 	if (vsi_seid == 0)
5370 		return I40E_ERR_PARAM;
5371 
5372 	if (is_add) {
5373 		i40e_fill_default_direct_cmd_desc(&desc,
5374 				i40e_aqc_opc_add_control_packet_filter);
5375 		cmd->queue = CPU_TO_LE16(queue);
5376 	} else {
5377 		i40e_fill_default_direct_cmd_desc(&desc,
5378 				i40e_aqc_opc_remove_control_packet_filter);
5379 	}
5380 
5381 	if (mac_addr)
5382 		i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5383 			    I40E_NONDMA_TO_NONDMA);
5384 
5385 	cmd->etype = CPU_TO_LE16(ethtype);
5386 	cmd->flags = CPU_TO_LE16(flags);
5387 	cmd->seid = CPU_TO_LE16(vsi_seid);
5388 
5389 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5390 
5391 	if (!status && stats) {
5392 		stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5393 		stats->etype_used = LE16_TO_CPU(resp->etype_used);
5394 		stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5395 		stats->etype_free = LE16_TO_CPU(resp->etype_free);
5396 	}
5397 
5398 	return status;
5399 }
5400 
5401 /**
5402  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5403  * @hw: pointer to the hw struct
5404  * @seid: VSI seid to add ethertype filter from
5405  **/
5406 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw * hw,u16 seid)5407 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5408 						    u16 seid)
5409 {
5410 	u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5411 		   I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5412 		   I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5413 	u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5414 	enum i40e_status_code status;
5415 
5416 	status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5417 						       seid, 0, TRUE, NULL,
5418 						       NULL);
5419 	if (status)
5420 		DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5421 }
5422 
5423 /**
5424  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5425  * @filters: list of cloud filters
5426  * @filter_count: length of list
5427  *
5428  * There's an issue in the device where the Geneve VNI layout needs
5429  * to be shifted 1 byte over from the VxLAN VNI
5430  **/
i40e_fix_up_geneve_vni(struct i40e_aqc_add_remove_cloud_filters_element_data * filters,u8 filter_count)5431 static void i40e_fix_up_geneve_vni(
5432 	struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5433 	u8 filter_count)
5434 {
5435 	struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5436 	int i;
5437 
5438 	for (i = 0; i < filter_count; i++) {
5439 		u16 tnl_type;
5440 		u32 ti;
5441 
5442 		tnl_type = (LE16_TO_CPU(f[i].flags) &
5443 			   I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5444 			   I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5445 		if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5446 			ti = LE32_TO_CPU(f[i].tenant_id);
5447 			f[i].tenant_id = CPU_TO_LE32(ti << 8);
5448 		}
5449 	}
5450 }
5451 
5452 /**
5453  * i40e_aq_add_cloud_filters
5454  * @hw: pointer to the hardware structure
5455  * @seid: VSI seid to add cloud filters from
5456  * @filters: Buffer which contains the filters to be added
5457  * @filter_count: number of filters contained in the buffer
5458  *
5459  * Set the cloud filters for a given VSI.  The contents of the
5460  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5461  * in by the caller of the function.
5462  *
5463  **/
i40e_aq_add_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_cloud_filters_element_data * filters,u8 filter_count)5464 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5465 	u16 seid,
5466 	struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5467 	u8 filter_count)
5468 {
5469 	struct i40e_aq_desc desc;
5470 	struct i40e_aqc_add_remove_cloud_filters *cmd =
5471 	(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5472 	enum i40e_status_code status;
5473 	u16 buff_len;
5474 
5475 	i40e_fill_default_direct_cmd_desc(&desc,
5476 					  i40e_aqc_opc_add_cloud_filters);
5477 
5478 	buff_len = filter_count * sizeof(*filters);
5479 	desc.datalen = CPU_TO_LE16(buff_len);
5480 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5481 	cmd->num_filters = filter_count;
5482 	cmd->seid = CPU_TO_LE16(seid);
5483 
5484 	i40e_fix_up_geneve_vni(filters, filter_count);
5485 
5486 	status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5487 
5488 	return status;
5489 }
5490 
5491 /**
5492  * i40e_aq_remove_cloud_filters
5493  * @hw: pointer to the hardware structure
5494  * @seid: VSI seid to remove cloud filters from
5495  * @filters: Buffer which contains the filters to be removed
5496  * @filter_count: number of filters contained in the buffer
5497  *
5498  * Remove the cloud filters for a given VSI.  The contents of the
5499  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5500  * in by the caller of the function.
5501  *
5502  **/
i40e_aq_remove_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_remove_cloud_filters_element_data * filters,u8 filter_count)5503 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5504 		u16 seid,
5505 		struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5506 		u8 filter_count)
5507 {
5508 	struct i40e_aq_desc desc;
5509 	struct i40e_aqc_add_remove_cloud_filters *cmd =
5510 	(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5511 	enum i40e_status_code status;
5512 	u16 buff_len;
5513 
5514 	i40e_fill_default_direct_cmd_desc(&desc,
5515 					  i40e_aqc_opc_remove_cloud_filters);
5516 
5517 	buff_len = filter_count * sizeof(*filters);
5518 	desc.datalen = CPU_TO_LE16(buff_len);
5519 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5520 	cmd->num_filters = filter_count;
5521 	cmd->seid = CPU_TO_LE16(seid);
5522 
5523 	i40e_fix_up_geneve_vni(filters, filter_count);
5524 
5525 	status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5526 
5527 	return status;
5528 }
5529 
5530 /**
5531  * i40e_aq_alternate_write
5532  * @hw: pointer to the hardware structure
5533  * @reg_addr0: address of first dword to be read
5534  * @reg_val0: value to be written under 'reg_addr0'
5535  * @reg_addr1: address of second dword to be read
5536  * @reg_val1: value to be written under 'reg_addr1'
5537  *
5538  * Write one or two dwords to alternate structure. Fields are indicated
5539  * by 'reg_addr0' and 'reg_addr1' register numbers.
5540  *
5541  **/
i40e_aq_alternate_write(struct i40e_hw * hw,u32 reg_addr0,u32 reg_val0,u32 reg_addr1,u32 reg_val1)5542 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5543 				u32 reg_addr0, u32 reg_val0,
5544 				u32 reg_addr1, u32 reg_val1)
5545 {
5546 	struct i40e_aq_desc desc;
5547 	struct i40e_aqc_alternate_write *cmd_resp =
5548 		(struct i40e_aqc_alternate_write *)&desc.params.raw;
5549 	enum i40e_status_code status;
5550 
5551 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5552 	cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5553 	cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5554 	cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5555 	cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5556 
5557 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5558 
5559 	return status;
5560 }
5561 
5562 /**
5563  * i40e_aq_alternate_write_indirect
5564  * @hw: pointer to the hardware structure
5565  * @addr: address of a first register to be modified
5566  * @dw_count: number of alternate structure fields to write
5567  * @buffer: pointer to the command buffer
5568  *
5569  * Write 'dw_count' dwords from 'buffer' to alternate structure
5570  * starting at 'addr'.
5571  *
5572  **/
i40e_aq_alternate_write_indirect(struct i40e_hw * hw,u32 addr,u32 dw_count,void * buffer)5573 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5574 				u32 addr, u32 dw_count, void *buffer)
5575 {
5576 	struct i40e_aq_desc desc;
5577 	struct i40e_aqc_alternate_ind_write *cmd_resp =
5578 		(struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5579 	enum i40e_status_code status;
5580 
5581 	if (buffer == NULL)
5582 		return I40E_ERR_PARAM;
5583 
5584 	/* Indirect command */
5585 	i40e_fill_default_direct_cmd_desc(&desc,
5586 					 i40e_aqc_opc_alternate_write_indirect);
5587 
5588 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5589 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5590 	if (dw_count > (I40E_AQ_LARGE_BUF/4))
5591 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5592 
5593 	cmd_resp->address = CPU_TO_LE32(addr);
5594 	cmd_resp->length = CPU_TO_LE32(dw_count);
5595 
5596 	status = i40e_asq_send_command(hw, &desc, buffer,
5597 				       I40E_LO_DWORD(4*dw_count), NULL);
5598 
5599 	return status;
5600 }
5601 
5602 /**
5603  * i40e_aq_alternate_read
5604  * @hw: pointer to the hardware structure
5605  * @reg_addr0: address of first dword to be read
5606  * @reg_val0: pointer for data read from 'reg_addr0'
5607  * @reg_addr1: address of second dword to be read
5608  * @reg_val1: pointer for data read from 'reg_addr1'
5609  *
5610  * Read one or two dwords from alternate structure. Fields are indicated
5611  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5612  * is not passed then only register at 'reg_addr0' is read.
5613  *
5614  **/
i40e_aq_alternate_read(struct i40e_hw * hw,u32 reg_addr0,u32 * reg_val0,u32 reg_addr1,u32 * reg_val1)5615 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5616 				u32 reg_addr0, u32 *reg_val0,
5617 				u32 reg_addr1, u32 *reg_val1)
5618 {
5619 	struct i40e_aq_desc desc;
5620 	struct i40e_aqc_alternate_write *cmd_resp =
5621 		(struct i40e_aqc_alternate_write *)&desc.params.raw;
5622 	enum i40e_status_code status;
5623 
5624 	if (reg_val0 == NULL)
5625 		return I40E_ERR_PARAM;
5626 
5627 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5628 	cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5629 	cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5630 
5631 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5632 
5633 	if (status == I40E_SUCCESS) {
5634 		*reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5635 
5636 		if (reg_val1 != NULL)
5637 			*reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5638 	}
5639 
5640 	return status;
5641 }
5642 
5643 /**
5644  * i40e_aq_alternate_read_indirect
5645  * @hw: pointer to the hardware structure
5646  * @addr: address of the alternate structure field
5647  * @dw_count: number of alternate structure fields to read
5648  * @buffer: pointer to the command buffer
5649  *
5650  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5651  * place them in 'buffer'. The buffer should be allocated by caller.
5652  *
5653  **/
i40e_aq_alternate_read_indirect(struct i40e_hw * hw,u32 addr,u32 dw_count,void * buffer)5654 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5655 				u32 addr, u32 dw_count, void *buffer)
5656 {
5657 	struct i40e_aq_desc desc;
5658 	struct i40e_aqc_alternate_ind_write *cmd_resp =
5659 		(struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5660 	enum i40e_status_code status;
5661 
5662 	if (buffer == NULL)
5663 		return I40E_ERR_PARAM;
5664 
5665 	/* Indirect command */
5666 	i40e_fill_default_direct_cmd_desc(&desc,
5667 		i40e_aqc_opc_alternate_read_indirect);
5668 
5669 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5670 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5671 	if (dw_count > (I40E_AQ_LARGE_BUF/4))
5672 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5673 
5674 	cmd_resp->address = CPU_TO_LE32(addr);
5675 	cmd_resp->length = CPU_TO_LE32(dw_count);
5676 
5677 	status = i40e_asq_send_command(hw, &desc, buffer,
5678 				       I40E_LO_DWORD(4*dw_count), NULL);
5679 
5680 	return status;
5681 }
5682 
5683 /**
5684  *  i40e_aq_alternate_clear
5685  *  @hw: pointer to the HW structure.
5686  *
5687  *  Clear the alternate structures of the port from which the function
5688  *  is called.
5689  *
5690  **/
i40e_aq_alternate_clear(struct i40e_hw * hw)5691 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5692 {
5693 	struct i40e_aq_desc desc;
5694 	enum i40e_status_code status;
5695 
5696 	i40e_fill_default_direct_cmd_desc(&desc,
5697 					  i40e_aqc_opc_alternate_clear_port);
5698 
5699 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5700 
5701 	return status;
5702 }
5703 
5704 /**
5705  *  i40e_aq_alternate_write_done
5706  *  @hw: pointer to the HW structure.
5707  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5708  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5709  *
5710  *  Indicates to the FW that alternate structures have been changed.
5711  *
5712  **/
i40e_aq_alternate_write_done(struct i40e_hw * hw,u8 bios_mode,bool * reset_needed)5713 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5714 		u8 bios_mode, bool *reset_needed)
5715 {
5716 	struct i40e_aq_desc desc;
5717 	struct i40e_aqc_alternate_write_done *cmd =
5718 		(struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5719 	enum i40e_status_code status;
5720 
5721 	if (reset_needed == NULL)
5722 		return I40E_ERR_PARAM;
5723 
5724 	i40e_fill_default_direct_cmd_desc(&desc,
5725 					  i40e_aqc_opc_alternate_write_done);
5726 
5727 	cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5728 
5729 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5730 	if (!status && reset_needed)
5731 		*reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5732 				 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5733 
5734 	return status;
5735 }
5736 
5737 /**
5738  *  i40e_aq_set_oem_mode
5739  *  @hw: pointer to the HW structure.
5740  *  @oem_mode: the OEM mode to be used
5741  *
5742  *  Sets the device to a specific operating mode. Currently the only supported
5743  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5744  *
5745  **/
i40e_aq_set_oem_mode(struct i40e_hw * hw,u8 oem_mode)5746 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5747 		u8 oem_mode)
5748 {
5749 	struct i40e_aq_desc desc;
5750 	struct i40e_aqc_alternate_write_done *cmd =
5751 		(struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5752 	enum i40e_status_code status;
5753 
5754 	i40e_fill_default_direct_cmd_desc(&desc,
5755 					  i40e_aqc_opc_alternate_set_mode);
5756 
5757 	cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5758 
5759 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5760 
5761 	return status;
5762 }
5763 
5764 /**
5765  * i40e_aq_resume_port_tx
5766  * @hw: pointer to the hardware structure
5767  * @cmd_details: pointer to command details structure or NULL
5768  *
5769  * Resume port's Tx traffic
5770  **/
i40e_aq_resume_port_tx(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)5771 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5772 				struct i40e_asq_cmd_details *cmd_details)
5773 {
5774 	struct i40e_aq_desc desc;
5775 	enum i40e_status_code status;
5776 
5777 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5778 
5779 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5780 
5781 	return status;
5782 }
5783 
5784 /**
5785  * i40e_set_pci_config_data - store PCI bus info
5786  * @hw: pointer to hardware structure
5787  * @link_status: the link status word from PCI config space
5788  *
5789  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5790  **/
i40e_set_pci_config_data(struct i40e_hw * hw,u16 link_status)5791 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5792 {
5793 	hw->bus.type = i40e_bus_type_pci_express;
5794 
5795 	switch (link_status & I40E_PCI_LINK_WIDTH) {
5796 	case I40E_PCI_LINK_WIDTH_1:
5797 		hw->bus.width = i40e_bus_width_pcie_x1;
5798 		break;
5799 	case I40E_PCI_LINK_WIDTH_2:
5800 		hw->bus.width = i40e_bus_width_pcie_x2;
5801 		break;
5802 	case I40E_PCI_LINK_WIDTH_4:
5803 		hw->bus.width = i40e_bus_width_pcie_x4;
5804 		break;
5805 	case I40E_PCI_LINK_WIDTH_8:
5806 		hw->bus.width = i40e_bus_width_pcie_x8;
5807 		break;
5808 	default:
5809 		hw->bus.width = i40e_bus_width_unknown;
5810 		break;
5811 	}
5812 
5813 	switch (link_status & I40E_PCI_LINK_SPEED) {
5814 	case I40E_PCI_LINK_SPEED_2500:
5815 		hw->bus.speed = i40e_bus_speed_2500;
5816 		break;
5817 	case I40E_PCI_LINK_SPEED_5000:
5818 		hw->bus.speed = i40e_bus_speed_5000;
5819 		break;
5820 	case I40E_PCI_LINK_SPEED_8000:
5821 		hw->bus.speed = i40e_bus_speed_8000;
5822 		break;
5823 	default:
5824 		hw->bus.speed = i40e_bus_speed_unknown;
5825 		break;
5826 	}
5827 }
5828 
5829 /**
5830  * i40e_aq_debug_dump
5831  * @hw: pointer to the hardware structure
5832  * @cluster_id: specific cluster to dump
5833  * @table_id: table id within cluster
5834  * @start_index: index of line in the block to read
5835  * @buff_size: dump buffer size
5836  * @buff: dump buffer
5837  * @ret_buff_size: actual buffer size returned
5838  * @ret_next_table: next block to read
5839  * @ret_next_index: next index to read
5840  *
5841  * Dump internal FW/HW data for debug purposes.
5842  *
5843  **/
i40e_aq_debug_dump(struct i40e_hw * hw,u8 cluster_id,u8 table_id,u32 start_index,u16 buff_size,void * buff,u16 * ret_buff_size,u8 * ret_next_table,u32 * ret_next_index,struct i40e_asq_cmd_details * cmd_details)5844 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5845 				u8 table_id, u32 start_index, u16 buff_size,
5846 				void *buff, u16 *ret_buff_size,
5847 				u8 *ret_next_table, u32 *ret_next_index,
5848 				struct i40e_asq_cmd_details *cmd_details)
5849 {
5850 	struct i40e_aq_desc desc;
5851 	struct i40e_aqc_debug_dump_internals *cmd =
5852 		(struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5853 	struct i40e_aqc_debug_dump_internals *resp =
5854 		(struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5855 	enum i40e_status_code status;
5856 
5857 	if (buff_size == 0 || !buff)
5858 		return I40E_ERR_PARAM;
5859 
5860 	i40e_fill_default_direct_cmd_desc(&desc,
5861 					  i40e_aqc_opc_debug_dump_internals);
5862 	/* Indirect Command */
5863 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5864 	if (buff_size > I40E_AQ_LARGE_BUF)
5865 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5866 
5867 	cmd->cluster_id = cluster_id;
5868 	cmd->table_id = table_id;
5869 	cmd->idx = CPU_TO_LE32(start_index);
5870 
5871 	desc.datalen = CPU_TO_LE16(buff_size);
5872 
5873 	status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5874 	if (!status) {
5875 		if (ret_buff_size != NULL)
5876 			*ret_buff_size = LE16_TO_CPU(desc.datalen);
5877 		if (ret_next_table != NULL)
5878 			*ret_next_table = resp->table_id;
5879 		if (ret_next_index != NULL)
5880 			*ret_next_index = LE32_TO_CPU(resp->idx);
5881 	}
5882 
5883 	return status;
5884 }
5885 
5886 /**
5887  * i40e_read_bw_from_alt_ram
5888  * @hw: pointer to the hardware structure
5889  * @max_bw: pointer for max_bw read
5890  * @min_bw: pointer for min_bw read
5891  * @min_valid: pointer for bool that is TRUE if min_bw is a valid value
5892  * @max_valid: pointer for bool that is TRUE if max_bw is a valid value
5893  *
5894  * Read bw from the alternate ram for the given pf
5895  **/
i40e_read_bw_from_alt_ram(struct i40e_hw * hw,u32 * max_bw,u32 * min_bw,bool * min_valid,bool * max_valid)5896 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5897 					u32 *max_bw, u32 *min_bw,
5898 					bool *min_valid, bool *max_valid)
5899 {
5900 	enum i40e_status_code status;
5901 	u32 max_bw_addr, min_bw_addr;
5902 
5903 	/* Calculate the address of the min/max bw registers */
5904 	max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5905 		      I40E_ALT_STRUCT_MAX_BW_OFFSET +
5906 		      (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5907 	min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5908 		      I40E_ALT_STRUCT_MIN_BW_OFFSET +
5909 		      (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5910 
5911 	/* Read the bandwidths from alt ram */
5912 	status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5913 					min_bw_addr, min_bw);
5914 
5915 	if (*min_bw & I40E_ALT_BW_VALID_MASK)
5916 		*min_valid = TRUE;
5917 	else
5918 		*min_valid = FALSE;
5919 
5920 	if (*max_bw & I40E_ALT_BW_VALID_MASK)
5921 		*max_valid = TRUE;
5922 	else
5923 		*max_valid = FALSE;
5924 
5925 	return status;
5926 }
5927 
5928 /**
5929  * i40e_aq_configure_partition_bw
5930  * @hw: pointer to the hardware structure
5931  * @bw_data: Buffer holding valid pfs and bw limits
5932  * @cmd_details: pointer to command details
5933  *
5934  * Configure partitions guaranteed/max bw
5935  **/
i40e_aq_configure_partition_bw(struct i40e_hw * hw,struct i40e_aqc_configure_partition_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)5936 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5937 			struct i40e_aqc_configure_partition_bw_data *bw_data,
5938 			struct i40e_asq_cmd_details *cmd_details)
5939 {
5940 	enum i40e_status_code status;
5941 	struct i40e_aq_desc desc;
5942 	u16 bwd_size = sizeof(*bw_data);
5943 
5944 	i40e_fill_default_direct_cmd_desc(&desc,
5945 				i40e_aqc_opc_configure_partition_bw);
5946 
5947 	/* Indirect command */
5948 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5949 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5950 
5951 	desc.datalen = CPU_TO_LE16(bwd_size);
5952 
5953 	status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5954 
5955 	return status;
5956 }
5957 
5958 /**
5959  * i40e_read_phy_register_clause22
5960  * @hw: pointer to the HW structure
5961  * @reg: register address in the page
5962  * @phy_adr: PHY address on MDIO interface
5963  * @value: PHY register value
5964  *
5965  * Reads specified PHY register value
5966  **/
i40e_read_phy_register_clause22(struct i40e_hw * hw,u16 reg,u8 phy_addr,u16 * value)5967 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
5968 					u16 reg, u8 phy_addr, u16 *value)
5969 {
5970 	enum i40e_status_code status = I40E_ERR_TIMEOUT;
5971 	u8 port_num = (u8)hw->func_caps.mdio_port_num;
5972 	u32 command = 0;
5973 	u16 retry = 1000;
5974 
5975 	command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5976 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5977 		  (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
5978 		  (I40E_MDIO_CLAUSE22_STCODE_MASK) |
5979 		  (I40E_GLGEN_MSCA_MDICMD_MASK);
5980 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
5981 	do {
5982 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
5983 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
5984 			status = I40E_SUCCESS;
5985 			break;
5986 		}
5987 		i40e_usec_delay(10);
5988 		retry--;
5989 	} while (retry);
5990 
5991 	if (status) {
5992 		i40e_debug(hw, I40E_DEBUG_PHY,
5993 			   "PHY: Can't write command to external PHY.\n");
5994 	} else {
5995 		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
5996 		*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
5997 			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
5998 	}
5999 
6000 	return status;
6001 }
6002 
6003 /**
6004  * i40e_write_phy_register_clause22
6005  * @hw: pointer to the HW structure
6006  * @reg: register address in the page
6007  * @phy_adr: PHY address on MDIO interface
6008  * @value: PHY register value
6009  *
6010  * Writes specified PHY register value
6011  **/
i40e_write_phy_register_clause22(struct i40e_hw * hw,u16 reg,u8 phy_addr,u16 value)6012 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6013 					u16 reg, u8 phy_addr, u16 value)
6014 {
6015 	enum i40e_status_code status = I40E_ERR_TIMEOUT;
6016 	u8 port_num = (u8)hw->func_caps.mdio_port_num;
6017 	u32 command  = 0;
6018 	u16 retry = 1000;
6019 
6020 	command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6021 	wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6022 
6023 	command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6024 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6025 		  (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6026 		  (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6027 		  (I40E_GLGEN_MSCA_MDICMD_MASK);
6028 
6029 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6030 	do {
6031 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6032 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6033 			status = I40E_SUCCESS;
6034 			break;
6035 		}
6036 		i40e_usec_delay(10);
6037 		retry--;
6038 	} while (retry);
6039 
6040 	return status;
6041 }
6042 
6043 /**
6044  * i40e_read_phy_register_clause45
6045  * @hw: pointer to the HW structure
6046  * @page: registers page number
6047  * @reg: register address in the page
6048  * @phy_adr: PHY address on MDIO interface
6049  * @value: PHY register value
6050  *
6051  * Reads specified PHY register value
6052  **/
i40e_read_phy_register_clause45(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 * value)6053 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6054 				u8 page, u16 reg, u8 phy_addr, u16 *value)
6055 {
6056 	enum i40e_status_code status = I40E_ERR_TIMEOUT;
6057 	u32 command  = 0;
6058 	u16 retry = 1000;
6059 	u8 port_num = (u8)hw->func_caps.mdio_port_num;
6060 
6061 	command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6062 		  (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6063 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6064 		  (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6065 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6066 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
6067 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6068 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6069 	do {
6070 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6071 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6072 			status = I40E_SUCCESS;
6073 			break;
6074 		}
6075 		i40e_usec_delay(10);
6076 		retry--;
6077 	} while (retry);
6078 
6079 	if (status) {
6080 		i40e_debug(hw, I40E_DEBUG_PHY,
6081 			   "PHY: Can't write command to external PHY.\n");
6082 		goto phy_read_end;
6083 	}
6084 
6085 	command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6086 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6087 		  (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6088 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6089 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
6090 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6091 	status = I40E_ERR_TIMEOUT;
6092 	retry = 1000;
6093 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6094 	do {
6095 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6096 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6097 			status = I40E_SUCCESS;
6098 			break;
6099 		}
6100 		i40e_usec_delay(10);
6101 		retry--;
6102 	} while (retry);
6103 
6104 	if (!status) {
6105 		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6106 		*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6107 			 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6108 	} else {
6109 		i40e_debug(hw, I40E_DEBUG_PHY,
6110 			   "PHY: Can't read register value from external PHY.\n");
6111 	}
6112 
6113 phy_read_end:
6114 	return status;
6115 }
6116 
6117 /**
6118  * i40e_write_phy_register_clause45
6119  * @hw: pointer to the HW structure
6120  * @page: registers page number
6121  * @reg: register address in the page
6122  * @phy_adr: PHY address on MDIO interface
6123  * @value: PHY register value
6124  *
6125  * Writes value to specified PHY register
6126  **/
i40e_write_phy_register_clause45(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 value)6127 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6128 				u8 page, u16 reg, u8 phy_addr, u16 value)
6129 {
6130 	enum i40e_status_code status = I40E_ERR_TIMEOUT;
6131 	u32 command  = 0;
6132 	u16 retry = 1000;
6133 	u8 port_num = (u8)hw->func_caps.mdio_port_num;
6134 
6135 	command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6136 		  (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6137 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6138 		  (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6139 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6140 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
6141 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6142 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6143 	do {
6144 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6145 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6146 			status = I40E_SUCCESS;
6147 			break;
6148 		}
6149 		i40e_usec_delay(10);
6150 		retry--;
6151 	} while (retry);
6152 	if (status) {
6153 		i40e_debug(hw, I40E_DEBUG_PHY,
6154 			   "PHY: Can't write command to external PHY.\n");
6155 		goto phy_write_end;
6156 	}
6157 
6158 	command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6159 	wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6160 
6161 	command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6162 		  (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6163 		  (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6164 		  (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6165 		  (I40E_GLGEN_MSCA_MDICMD_MASK) |
6166 		  (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6167 	status = I40E_ERR_TIMEOUT;
6168 	retry = 1000;
6169 	wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6170 	do {
6171 		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6172 		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6173 			status = I40E_SUCCESS;
6174 			break;
6175 		}
6176 		i40e_usec_delay(10);
6177 		retry--;
6178 	} while (retry);
6179 
6180 phy_write_end:
6181 	return status;
6182 }
6183 
6184 /**
6185  * i40e_write_phy_register
6186  * @hw: pointer to the HW structure
6187  * @page: registers page number
6188  * @reg: register address in the page
6189  * @phy_adr: PHY address on MDIO interface
6190  * @value: PHY register value
6191  *
6192  * Writes value to specified PHY register
6193  **/
i40e_write_phy_register(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 value)6194 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6195 				u8 page, u16 reg, u8 phy_addr, u16 value)
6196 {
6197 	enum i40e_status_code status;
6198 
6199 	switch (hw->device_id) {
6200 	case I40E_DEV_ID_1G_BASE_T_X722:
6201 		status = i40e_write_phy_register_clause22(hw,
6202 			reg, phy_addr, value);
6203 		break;
6204 	case I40E_DEV_ID_10G_BASE_T:
6205 	case I40E_DEV_ID_10G_BASE_T4:
6206 	case I40E_DEV_ID_10G_BASE_T_X722:
6207 	case I40E_DEV_ID_25G_B:
6208 	case I40E_DEV_ID_25G_SFP28:
6209 		status = i40e_write_phy_register_clause45(hw,
6210 			page, reg, phy_addr, value);
6211 		break;
6212 	default:
6213 		status = I40E_ERR_UNKNOWN_PHY;
6214 		break;
6215 	}
6216 
6217 	return status;
6218 }
6219 
6220 /**
6221  * i40e_read_phy_register
6222  * @hw: pointer to the HW structure
6223  * @page: registers page number
6224  * @reg: register address in the page
6225  * @phy_adr: PHY address on MDIO interface
6226  * @value: PHY register value
6227  *
6228  * Reads specified PHY register value
6229  **/
i40e_read_phy_register(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 * value)6230 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6231 				u8 page, u16 reg, u8 phy_addr, u16 *value)
6232 {
6233 	enum i40e_status_code status;
6234 
6235 	switch (hw->device_id) {
6236 	case I40E_DEV_ID_1G_BASE_T_X722:
6237 		status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6238 							 value);
6239 		break;
6240 	case I40E_DEV_ID_10G_BASE_T:
6241 	case I40E_DEV_ID_10G_BASE_T4:
6242 	case I40E_DEV_ID_10G_BASE_T_X722:
6243 	case I40E_DEV_ID_25G_B:
6244 	case I40E_DEV_ID_25G_SFP28:
6245 		status = i40e_read_phy_register_clause45(hw, page, reg,
6246 							 phy_addr, value);
6247 		break;
6248 	default:
6249 		status = I40E_ERR_UNKNOWN_PHY;
6250 		break;
6251 	}
6252 
6253 	return status;
6254 }
6255 
6256 /**
6257  * i40e_get_phy_address
6258  * @hw: pointer to the HW structure
6259  * @dev_num: PHY port num that address we want
6260  * @phy_addr: Returned PHY address
6261  *
6262  * Gets PHY address for current port
6263  **/
i40e_get_phy_address(struct i40e_hw * hw,u8 dev_num)6264 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6265 {
6266 	u8 port_num = (u8)hw->func_caps.mdio_port_num;
6267 	u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6268 
6269 	return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6270 }
6271 
6272 /**
6273  * i40e_blink_phy_led
6274  * @hw: pointer to the HW structure
6275  * @time: time how long led will blinks in secs
6276  * @interval: gap between LED on and off in msecs
6277  *
6278  * Blinks PHY link LED
6279  **/
i40e_blink_phy_link_led(struct i40e_hw * hw,u32 time,u32 interval)6280 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6281 					      u32 time, u32 interval)
6282 {
6283 	enum i40e_status_code status = I40E_SUCCESS;
6284 	u32 i;
6285 	u16 led_ctl = 0;
6286 	u16 gpio_led_port;
6287 	u16 led_reg;
6288 	u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6289 	u8 phy_addr = 0;
6290 	u8 port_num;
6291 
6292 	i = rd32(hw, I40E_PFGEN_PORTNUM);
6293 	port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6294 	phy_addr = i40e_get_phy_address(hw, port_num);
6295 
6296 	for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6297 	     led_addr++) {
6298 		status = i40e_read_phy_register_clause45(hw,
6299 							 I40E_PHY_COM_REG_PAGE,
6300 							 led_addr, phy_addr,
6301 							 &led_reg);
6302 		if (status)
6303 			goto phy_blinking_end;
6304 		led_ctl = led_reg;
6305 		if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6306 			led_reg = 0;
6307 			status = i40e_write_phy_register_clause45(hw,
6308 							 I40E_PHY_COM_REG_PAGE,
6309 							 led_addr, phy_addr,
6310 							 led_reg);
6311 			if (status)
6312 				goto phy_blinking_end;
6313 			break;
6314 		}
6315 	}
6316 
6317 	if (time > 0 && interval > 0) {
6318 		for (i = 0; i < time * 1000; i += interval) {
6319 			status = i40e_read_phy_register_clause45(hw,
6320 						I40E_PHY_COM_REG_PAGE,
6321 						led_addr, phy_addr, &led_reg);
6322 			if (status)
6323 				goto restore_config;
6324 			if (led_reg & I40E_PHY_LED_MANUAL_ON)
6325 				led_reg = 0;
6326 			else
6327 				led_reg = I40E_PHY_LED_MANUAL_ON;
6328 			status = i40e_write_phy_register_clause45(hw,
6329 						I40E_PHY_COM_REG_PAGE,
6330 						led_addr, phy_addr, led_reg);
6331 			if (status)
6332 				goto restore_config;
6333 			i40e_msec_delay(interval);
6334 		}
6335 	}
6336 
6337 restore_config:
6338 	status = i40e_write_phy_register_clause45(hw,
6339 						  I40E_PHY_COM_REG_PAGE,
6340 						  led_addr, phy_addr, led_ctl);
6341 
6342 phy_blinking_end:
6343 	return status;
6344 }
6345 
6346 /**
6347  * i40e_led_get_phy - return current on/off mode
6348  * @hw: pointer to the hw struct
6349  * @led_addr: address of led register to use
6350  * @val: original value of register to use
6351  *
6352  **/
i40e_led_get_phy(struct i40e_hw * hw,u16 * led_addr,u16 * val)6353 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6354 				       u16 *val)
6355 {
6356 	enum i40e_status_code status = I40E_SUCCESS;
6357 	u16 gpio_led_port;
6358 	u8 phy_addr = 0;
6359 	u16 reg_val;
6360 	u16 temp_addr;
6361 	u8 port_num;
6362 	u32 i;
6363 
6364 	temp_addr = I40E_PHY_LED_PROV_REG_1;
6365 	i = rd32(hw, I40E_PFGEN_PORTNUM);
6366 	port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6367 	phy_addr = i40e_get_phy_address(hw, port_num);
6368 
6369 	for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6370 	     temp_addr++) {
6371 		status = i40e_read_phy_register_clause45(hw,
6372 							 I40E_PHY_COM_REG_PAGE,
6373 							 temp_addr, phy_addr,
6374 							 &reg_val);
6375 		if (status)
6376 			return status;
6377 		*val = reg_val;
6378 		if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6379 			*led_addr = temp_addr;
6380 			break;
6381 		}
6382 	}
6383 	return status;
6384 }
6385 
6386 /**
6387  * i40e_led_set_phy
6388  * @hw: pointer to the HW structure
6389  * @on: TRUE or FALSE
6390  * @mode: original val plus bit for set or ignore
6391  * Set led's on or off when controlled by the PHY
6392  *
6393  **/
i40e_led_set_phy(struct i40e_hw * hw,bool on,u16 led_addr,u32 mode)6394 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6395 				       u16 led_addr, u32 mode)
6396 {
6397 	enum i40e_status_code status = I40E_SUCCESS;
6398 	u16 led_ctl = 0;
6399 	u16 led_reg = 0;
6400 	u8 phy_addr = 0;
6401 	u8 port_num;
6402 	u32 i;
6403 
6404 	i = rd32(hw, I40E_PFGEN_PORTNUM);
6405 	port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6406 	phy_addr = i40e_get_phy_address(hw, port_num);
6407 	status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6408 						 led_addr, phy_addr, &led_reg);
6409 	if (status)
6410 		return status;
6411 	led_ctl = led_reg;
6412 	if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6413 		led_reg = 0;
6414 		status = i40e_write_phy_register_clause45(hw,
6415 							  I40E_PHY_COM_REG_PAGE,
6416 							  led_addr, phy_addr,
6417 							  led_reg);
6418 		if (status)
6419 			return status;
6420 	}
6421 	status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6422 						 led_addr, phy_addr, &led_reg);
6423 	if (status)
6424 		goto restore_config;
6425 	if (on)
6426 		led_reg = I40E_PHY_LED_MANUAL_ON;
6427 	else
6428 		led_reg = 0;
6429 	status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6430 						  led_addr, phy_addr, led_reg);
6431 	if (status)
6432 		goto restore_config;
6433 	if (mode & I40E_PHY_LED_MODE_ORIG) {
6434 		led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6435 		status = i40e_write_phy_register_clause45(hw,
6436 						 I40E_PHY_COM_REG_PAGE,
6437 						 led_addr, phy_addr, led_ctl);
6438 	}
6439 	return status;
6440 restore_config:
6441 	status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6442 						  led_addr, phy_addr, led_ctl);
6443 	return status;
6444 }
6445 
6446 /**
6447  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6448  * @hw: pointer to the hw struct
6449  * @reg_addr: register address
6450  * @reg_val: ptr to register value
6451  * @cmd_details: pointer to command details structure or NULL
6452  *
6453  * Use the firmware to read the Rx control register,
6454  * especially useful if the Rx unit is under heavy pressure
6455  **/
i40e_aq_rx_ctl_read_register(struct i40e_hw * hw,u32 reg_addr,u32 * reg_val,struct i40e_asq_cmd_details * cmd_details)6456 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6457 				u32 reg_addr, u32 *reg_val,
6458 				struct i40e_asq_cmd_details *cmd_details)
6459 {
6460 	struct i40e_aq_desc desc;
6461 	struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6462 		(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6463 	enum i40e_status_code status;
6464 
6465 	if (reg_val == NULL)
6466 		return I40E_ERR_PARAM;
6467 
6468 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6469 
6470 	cmd_resp->address = CPU_TO_LE32(reg_addr);
6471 
6472 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6473 
6474 	if (status == I40E_SUCCESS)
6475 		*reg_val = LE32_TO_CPU(cmd_resp->value);
6476 
6477 	return status;
6478 }
6479 
6480 /**
6481  * i40e_read_rx_ctl - read from an Rx control register
6482  * @hw: pointer to the hw struct
6483  * @reg_addr: register address
6484  **/
i40e_read_rx_ctl(struct i40e_hw * hw,u32 reg_addr)6485 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6486 {
6487 	enum i40e_status_code status = I40E_SUCCESS;
6488 	bool use_register;
6489 	int retry = 5;
6490 	u32 val = 0;
6491 
6492 	use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6493 	if (!use_register) {
6494 do_retry:
6495 		status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6496 		if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6497 			i40e_msec_delay(1);
6498 			retry--;
6499 			goto do_retry;
6500 		}
6501 	}
6502 
6503 	/* if the AQ access failed, try the old-fashioned way */
6504 	if (status || use_register)
6505 		val = rd32(hw, reg_addr);
6506 
6507 	return val;
6508 }
6509 
6510 /**
6511  * i40e_aq_rx_ctl_write_register
6512  * @hw: pointer to the hw struct
6513  * @reg_addr: register address
6514  * @reg_val: register value
6515  * @cmd_details: pointer to command details structure or NULL
6516  *
6517  * Use the firmware to write to an Rx control register,
6518  * especially useful if the Rx unit is under heavy pressure
6519  **/
i40e_aq_rx_ctl_write_register(struct i40e_hw * hw,u32 reg_addr,u32 reg_val,struct i40e_asq_cmd_details * cmd_details)6520 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6521 				u32 reg_addr, u32 reg_val,
6522 				struct i40e_asq_cmd_details *cmd_details)
6523 {
6524 	struct i40e_aq_desc desc;
6525 	struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6526 		(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6527 	enum i40e_status_code status;
6528 
6529 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6530 
6531 	cmd->address = CPU_TO_LE32(reg_addr);
6532 	cmd->value = CPU_TO_LE32(reg_val);
6533 
6534 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6535 
6536 	return status;
6537 }
6538 
6539 /**
6540  * i40e_write_rx_ctl - write to an Rx control register
6541  * @hw: pointer to the hw struct
6542  * @reg_addr: register address
6543  * @reg_val: register value
6544  **/
i40e_write_rx_ctl(struct i40e_hw * hw,u32 reg_addr,u32 reg_val)6545 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6546 {
6547 	enum i40e_status_code status = I40E_SUCCESS;
6548 	bool use_register;
6549 	int retry = 5;
6550 
6551 	use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6552 	if (!use_register) {
6553 do_retry:
6554 		status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6555 						       reg_val, NULL);
6556 		if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6557 			i40e_msec_delay(1);
6558 			retry--;
6559 			goto do_retry;
6560 		}
6561 	}
6562 
6563 	/* if the AQ access failed, try the old-fashioned way */
6564 	if (status || use_register)
6565 		wr32(hw, reg_addr, reg_val);
6566 }
6567 
6568 /**
6569  * i40e_aq_set_arp_proxy_config
6570  * @hw: pointer to the HW structure
6571  * @proxy_config - pointer to proxy config command table struct
6572  * @cmd_details: pointer to command details
6573  *
6574  * Set ARP offload parameters from pre-populated
6575  * i40e_aqc_arp_proxy_data struct
6576  **/
i40e_aq_set_arp_proxy_config(struct i40e_hw * hw,struct i40e_aqc_arp_proxy_data * proxy_config,struct i40e_asq_cmd_details * cmd_details)6577 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6578 				struct i40e_aqc_arp_proxy_data *proxy_config,
6579 				struct i40e_asq_cmd_details *cmd_details)
6580 {
6581 	struct i40e_aq_desc desc;
6582 	enum i40e_status_code status;
6583 
6584 	if (!proxy_config)
6585 		return I40E_ERR_PARAM;
6586 
6587 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6588 
6589 	desc.params.external.addr_high =
6590 				  CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)proxy_config));
6591 	desc.params.external.addr_low =
6592 				  CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)proxy_config));
6593 
6594 	status = i40e_asq_send_command(hw, &desc, proxy_config,
6595 				       sizeof(struct i40e_aqc_arp_proxy_data),
6596 				       cmd_details);
6597 
6598 	return status;
6599 }
6600 
6601 /**
6602  * i40e_aq_opc_set_ns_proxy_table_entry
6603  * @hw: pointer to the HW structure
6604  * @ns_proxy_table_entry: pointer to NS table entry command struct
6605  * @cmd_details: pointer to command details
6606  *
6607  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6608  * from pre-populated i40e_aqc_ns_proxy_data struct
6609  **/
i40e_aq_set_ns_proxy_table_entry(struct i40e_hw * hw,struct i40e_aqc_ns_proxy_data * ns_proxy_table_entry,struct i40e_asq_cmd_details * cmd_details)6610 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6611 			struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6612 			struct i40e_asq_cmd_details *cmd_details)
6613 {
6614 	struct i40e_aq_desc desc;
6615 	enum i40e_status_code status;
6616 
6617 	if (!ns_proxy_table_entry)
6618 		return I40E_ERR_PARAM;
6619 
6620 	i40e_fill_default_direct_cmd_desc(&desc,
6621 				i40e_aqc_opc_set_ns_proxy_table_entry);
6622 
6623 	desc.params.external.addr_high =
6624 		CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)ns_proxy_table_entry));
6625 	desc.params.external.addr_low =
6626 		CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)ns_proxy_table_entry));
6627 
6628 	status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6629 				       sizeof(struct i40e_aqc_ns_proxy_data),
6630 				       cmd_details);
6631 
6632 	return status;
6633 }
6634 
6635 /**
6636  * i40e_aq_set_clear_wol_filter
6637  * @hw: pointer to the hw struct
6638  * @filter_index: index of filter to modify (0-7)
6639  * @filter: buffer containing filter to be set
6640  * @set_filter: TRUE to set filter, FALSE to clear filter
6641  * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up
6642  *		if FALSE, pass through packets may cause wake-up
6643  * @filter_valid: TRUE if filter action is valid
6644  * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid
6645  * @cmd_details: pointer to command details structure or NULL
6646  *
6647  * Set or clear WoL filter for port attached to the PF
6648  **/
i40e_aq_set_clear_wol_filter(struct i40e_hw * hw,u8 filter_index,struct i40e_aqc_set_wol_filter_data * filter,bool set_filter,bool no_wol_tco,bool filter_valid,bool no_wol_tco_valid,struct i40e_asq_cmd_details * cmd_details)6649 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6650 				u8 filter_index,
6651 				struct i40e_aqc_set_wol_filter_data *filter,
6652 				bool set_filter, bool no_wol_tco,
6653 				bool filter_valid, bool no_wol_tco_valid,
6654 				struct i40e_asq_cmd_details *cmd_details)
6655 {
6656 	struct i40e_aq_desc desc;
6657 	struct i40e_aqc_set_wol_filter *cmd =
6658 		(struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6659 	enum i40e_status_code status;
6660 	u16 cmd_flags = 0;
6661 	u16 valid_flags = 0;
6662 	u16 buff_len = 0;
6663 
6664 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6665 
6666 	if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6667 		return  I40E_ERR_PARAM;
6668 	cmd->filter_index = CPU_TO_LE16(filter_index);
6669 
6670 	if (set_filter) {
6671 		if (!filter)
6672 			return  I40E_ERR_PARAM;
6673 		cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6674 		buff_len = sizeof(*filter);
6675 	}
6676 	if (no_wol_tco)
6677 		cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6678 	cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6679 
6680 	if (filter_valid)
6681 		valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6682 	if (no_wol_tco_valid)
6683 		valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6684 	cmd->valid_flags = CPU_TO_LE16(valid_flags);
6685 
6686 	cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)filter));
6687 	cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)filter));
6688 
6689 	status = i40e_asq_send_command(hw, &desc, filter,
6690 				       buff_len, cmd_details);
6691 
6692 	return status;
6693 }
6694 
6695 /**
6696  * i40e_aq_get_wake_event_reason
6697  * @hw: pointer to the hw struct
6698  * @wake_reason: return value, index of matching filter
6699  * @cmd_details: pointer to command details structure or NULL
6700  *
6701  * Get information for the reason of a Wake Up event
6702  **/
i40e_aq_get_wake_event_reason(struct i40e_hw * hw,u16 * wake_reason,struct i40e_asq_cmd_details * cmd_details)6703 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6704 				u16 *wake_reason,
6705 				struct i40e_asq_cmd_details *cmd_details)
6706 {
6707 	struct i40e_aq_desc desc;
6708 	struct i40e_aqc_get_wake_reason_completion *resp =
6709 		(struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6710 	enum i40e_status_code status;
6711 
6712 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6713 
6714 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6715 
6716 	if (status == I40E_SUCCESS)
6717 		*wake_reason = LE16_TO_CPU(resp->wake_reason);
6718 
6719 	return status;
6720 }
6721 
6722