1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "timing_generator.h"
29 #include "hw_sequencer.h"
30 #include "hw_sequencer_private.h"
31 #include "basics/dc_common.h"
32 #include "resource.h"
33 #include "dc_dmub_srv.h"
34 #include "dc_state_priv.h"
35
36 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
37
38 /* used as index in array of black_color_format */
39 enum black_color_format {
40 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
41 BLACK_COLOR_FORMAT_RGB_LIMITED,
42 BLACK_COLOR_FORMAT_YUV_TV,
43 BLACK_COLOR_FORMAT_YUV_CV,
44 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
45 BLACK_COLOR_FORMAT_DEBUG,
46 };
47
48 enum dc_color_space_type {
49 COLOR_SPACE_RGB_TYPE,
50 COLOR_SPACE_RGB_LIMITED_TYPE,
51 COLOR_SPACE_YCBCR601_TYPE,
52 COLOR_SPACE_YCBCR709_TYPE,
53 COLOR_SPACE_YCBCR2020_TYPE,
54 COLOR_SPACE_YCBCR601_LIMITED_TYPE,
55 COLOR_SPACE_YCBCR709_LIMITED_TYPE,
56 COLOR_SPACE_YCBCR709_BLACK_TYPE,
57 };
58
59 static const struct tg_color black_color_format[] = {
60 /* BlackColorFormat_RGB_FullRange */
61 {0, 0, 0},
62 /* BlackColorFormat_RGB_Limited */
63 {0x40, 0x40, 0x40},
64 /* BlackColorFormat_YUV_TV */
65 {0x200, 0x40, 0x200},
66 /* BlackColorFormat_YUV_CV */
67 {0x1f4, 0x40, 0x1f4},
68 /* BlackColorFormat_YUV_SuperAA */
69 {0x1a2, 0x20, 0x1a2},
70 /* visual confirm debug */
71 {0xff, 0xff, 0},
72 };
73
74 struct out_csc_color_matrix_type {
75 enum dc_color_space_type color_space_type;
76 uint16_t regval[12];
77 };
78
79 static const struct out_csc_color_matrix_type output_csc_matrix[] = {
80 { COLOR_SPACE_RGB_TYPE,
81 { 0x2000, 0, 0, 0,
82 0, 0x2000, 0, 0,
83 0, 0, 0x2000, 0} },
84 { COLOR_SPACE_RGB_LIMITED_TYPE,
85 { 0x1B67, 0, 0, 0x201,
86 0, 0x1B67, 0, 0x201,
87 0, 0, 0x1B67, 0x201} },
88 { COLOR_SPACE_YCBCR601_TYPE,
89 { 0xE04, 0xF444, 0xFDB9, 0x1004,
90 0x831, 0x1016, 0x320, 0x201,
91 0xFB45, 0xF6B7, 0xE04, 0x1004} },
92 { COLOR_SPACE_YCBCR709_TYPE,
93 { 0xE04, 0xF345, 0xFEB7, 0x1004,
94 0x5D3, 0x1399, 0x1FA, 0x201,
95 0xFCCA, 0xF533, 0xE04, 0x1004} },
96 /* TODO: correct values below */
97 { COLOR_SPACE_YCBCR601_LIMITED_TYPE,
98 { 0xE00, 0xF447, 0xFDB9, 0x1000,
99 0x991, 0x12C9, 0x3A6, 0x200,
100 0xFB47, 0xF6B9, 0xE00, 0x1000} },
101 { COLOR_SPACE_YCBCR709_LIMITED_TYPE,
102 { 0xE00, 0xF349, 0xFEB7, 0x1000,
103 0x6CE, 0x16E3, 0x24F, 0x200,
104 0xFCCB, 0xF535, 0xE00, 0x1000} },
105 { COLOR_SPACE_YCBCR2020_TYPE,
106 { 0x1000, 0xF149, 0xFEB7, 0x1004,
107 0x0868, 0x15B2, 0x01E6, 0x201,
108 0xFB88, 0xF478, 0x1000, 0x1004} },
109 { COLOR_SPACE_YCBCR709_BLACK_TYPE,
110 { 0x0000, 0x0000, 0x0000, 0x1000,
111 0x0000, 0x0000, 0x0000, 0x0200,
112 0x0000, 0x0000, 0x0000, 0x1000} },
113 };
114
is_rgb_type(enum dc_color_space color_space)115 static bool is_rgb_type(
116 enum dc_color_space color_space)
117 {
118 bool ret = false;
119
120 if (color_space == COLOR_SPACE_SRGB ||
121 color_space == COLOR_SPACE_XR_RGB ||
122 color_space == COLOR_SPACE_MSREF_SCRGB ||
123 color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
124 color_space == COLOR_SPACE_ADOBERGB ||
125 color_space == COLOR_SPACE_DCIP3 ||
126 color_space == COLOR_SPACE_DOLBYVISION)
127 ret = true;
128 return ret;
129 }
130
is_rgb_limited_type(enum dc_color_space color_space)131 static bool is_rgb_limited_type(
132 enum dc_color_space color_space)
133 {
134 bool ret = false;
135
136 if (color_space == COLOR_SPACE_SRGB_LIMITED ||
137 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
138 ret = true;
139 return ret;
140 }
141
is_ycbcr601_type(enum dc_color_space color_space)142 static bool is_ycbcr601_type(
143 enum dc_color_space color_space)
144 {
145 bool ret = false;
146
147 if (color_space == COLOR_SPACE_YCBCR601 ||
148 color_space == COLOR_SPACE_XV_YCC_601)
149 ret = true;
150 return ret;
151 }
152
is_ycbcr601_limited_type(enum dc_color_space color_space)153 static bool is_ycbcr601_limited_type(
154 enum dc_color_space color_space)
155 {
156 bool ret = false;
157
158 if (color_space == COLOR_SPACE_YCBCR601_LIMITED)
159 ret = true;
160 return ret;
161 }
162
is_ycbcr709_type(enum dc_color_space color_space)163 static bool is_ycbcr709_type(
164 enum dc_color_space color_space)
165 {
166 bool ret = false;
167
168 if (color_space == COLOR_SPACE_YCBCR709 ||
169 color_space == COLOR_SPACE_XV_YCC_709)
170 ret = true;
171 return ret;
172 }
173
is_ycbcr2020_type(enum dc_color_space color_space)174 static bool is_ycbcr2020_type(
175 enum dc_color_space color_space)
176 {
177 bool ret = false;
178
179 if (color_space == COLOR_SPACE_2020_YCBCR)
180 ret = true;
181 return ret;
182 }
183
is_ycbcr709_limited_type(enum dc_color_space color_space)184 static bool is_ycbcr709_limited_type(
185 enum dc_color_space color_space)
186 {
187 bool ret = false;
188
189 if (color_space == COLOR_SPACE_YCBCR709_LIMITED)
190 ret = true;
191 return ret;
192 }
193
get_color_space_type(enum dc_color_space color_space)194 static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space)
195 {
196 enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE;
197
198 if (is_rgb_type(color_space))
199 type = COLOR_SPACE_RGB_TYPE;
200 else if (is_rgb_limited_type(color_space))
201 type = COLOR_SPACE_RGB_LIMITED_TYPE;
202 else if (is_ycbcr601_type(color_space))
203 type = COLOR_SPACE_YCBCR601_TYPE;
204 else if (is_ycbcr709_type(color_space))
205 type = COLOR_SPACE_YCBCR709_TYPE;
206 else if (is_ycbcr601_limited_type(color_space))
207 type = COLOR_SPACE_YCBCR601_LIMITED_TYPE;
208 else if (is_ycbcr709_limited_type(color_space))
209 type = COLOR_SPACE_YCBCR709_LIMITED_TYPE;
210 else if (is_ycbcr2020_type(color_space))
211 type = COLOR_SPACE_YCBCR2020_TYPE;
212 else if (color_space == COLOR_SPACE_YCBCR709)
213 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
214 else if (color_space == COLOR_SPACE_YCBCR709_BLACK)
215 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
216 return type;
217 }
218
find_color_matrix(enum dc_color_space color_space,uint32_t * array_size)219 const uint16_t *find_color_matrix(enum dc_color_space color_space,
220 uint32_t *array_size)
221 {
222 int i;
223 enum dc_color_space_type type;
224 const uint16_t *val = NULL;
225 int arr_size = NUM_ELEMENTS(output_csc_matrix);
226
227 type = get_color_space_type(color_space);
228 for (i = 0; i < arr_size; i++)
229 if (output_csc_matrix[i].color_space_type == type) {
230 val = output_csc_matrix[i].regval;
231 *array_size = 12;
232 break;
233 }
234
235 return val;
236 }
237
238
color_space_to_black_color(const struct dc * dc,enum dc_color_space colorspace,struct tg_color * black_color)239 void color_space_to_black_color(
240 const struct dc *dc,
241 enum dc_color_space colorspace,
242 struct tg_color *black_color)
243 {
244 switch (colorspace) {
245 case COLOR_SPACE_YCBCR601:
246 case COLOR_SPACE_YCBCR709:
247 case COLOR_SPACE_YCBCR709_BLACK:
248 case COLOR_SPACE_YCBCR601_LIMITED:
249 case COLOR_SPACE_YCBCR709_LIMITED:
250 case COLOR_SPACE_2020_YCBCR:
251 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
252 break;
253
254 case COLOR_SPACE_SRGB_LIMITED:
255 *black_color =
256 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
257 break;
258
259 /**
260 * Remove default and add case for all color space
261 * so when we forget to add new color space
262 * compiler will give a warning
263 */
264 case COLOR_SPACE_UNKNOWN:
265 case COLOR_SPACE_SRGB:
266 case COLOR_SPACE_XR_RGB:
267 case COLOR_SPACE_MSREF_SCRGB:
268 case COLOR_SPACE_XV_YCC_709:
269 case COLOR_SPACE_XV_YCC_601:
270 case COLOR_SPACE_2020_RGB_FULLRANGE:
271 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
272 case COLOR_SPACE_ADOBERGB:
273 case COLOR_SPACE_DCIP3:
274 case COLOR_SPACE_DISPLAYNATIVE:
275 case COLOR_SPACE_DOLBYVISION:
276 case COLOR_SPACE_APPCTRL:
277 case COLOR_SPACE_CUSTOMPOINTS:
278 /* fefault is sRGB black (full range). */
279 *black_color =
280 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
281 /* default is sRGB black 0. */
282 break;
283 }
284 }
285
hwss_wait_for_blank_complete(struct timing_generator * tg)286 bool hwss_wait_for_blank_complete(
287 struct timing_generator *tg)
288 {
289 int counter;
290
291 /* Not applicable if the pipe is not primary, save 300ms of boot time */
292 if (!tg->funcs->is_blanked)
293 return true;
294 for (counter = 0; counter < 100; counter++) {
295 if (tg->funcs->is_blanked(tg))
296 break;
297
298 msleep(1);
299 }
300
301 if (counter == 100) {
302 dm_error("DC: failed to blank crtc!\n");
303 return false;
304 }
305
306 return true;
307 }
308
get_mpctree_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)309 void get_mpctree_visual_confirm_color(
310 struct pipe_ctx *pipe_ctx,
311 struct tg_color *color)
312 {
313 const struct tg_color pipe_colors[6] = {
314 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */
315 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
316 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
317 {0, MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE}, /* cyan */
318 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
319 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, /* magenta */
320 };
321
322 struct pipe_ctx *top_pipe = pipe_ctx;
323
324 while (top_pipe->top_pipe)
325 top_pipe = top_pipe->top_pipe;
326
327 *color = pipe_colors[top_pipe->pipe_idx];
328 }
329
get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)330 void get_surface_visual_confirm_color(
331 const struct pipe_ctx *pipe_ctx,
332 struct tg_color *color)
333 {
334 uint32_t color_value = MAX_TG_COLOR_VALUE;
335
336 switch (pipe_ctx->plane_res.scl_data.format) {
337 case PIXEL_FORMAT_ARGB8888:
338 /* set border color to red */
339 color->color_r_cr = color_value;
340 if (pipe_ctx->plane_state->layer_index > 0) {
341 /* set border color to pink */
342 color->color_b_cb = color_value;
343 color->color_g_y = color_value * 0.5;
344 }
345 break;
346
347 case PIXEL_FORMAT_ARGB2101010:
348 /* set border color to blue */
349 color->color_b_cb = color_value;
350 if (pipe_ctx->plane_state->layer_index > 0) {
351 /* set border color to cyan */
352 color->color_g_y = color_value;
353 }
354 break;
355 case PIXEL_FORMAT_420BPP8:
356 /* set border color to green */
357 color->color_g_y = color_value;
358 break;
359 case PIXEL_FORMAT_420BPP10:
360 /* set border color to yellow */
361 color->color_g_y = color_value;
362 color->color_r_cr = color_value;
363 break;
364 case PIXEL_FORMAT_FP16:
365 /* set border color to white */
366 color->color_r_cr = color_value;
367 color->color_b_cb = color_value;
368 color->color_g_y = color_value;
369 if (pipe_ctx->plane_state->layer_index > 0) {
370 /* set border color to orange */
371 color->color_g_y = 0.22 * color_value;
372 color->color_b_cb = 0;
373 }
374 break;
375 default:
376 break;
377 }
378 }
379
get_hdr_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)380 void get_hdr_visual_confirm_color(
381 struct pipe_ctx *pipe_ctx,
382 struct tg_color *color)
383 {
384 uint32_t color_value = MAX_TG_COLOR_VALUE;
385 bool is_sdr = false;
386
387 /* Determine the overscan color based on the top-most (desktop) plane's context */
388 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
389
390 while (top_pipe_ctx->top_pipe != NULL)
391 top_pipe_ctx = top_pipe_ctx->top_pipe;
392
393 switch (top_pipe_ctx->plane_res.scl_data.format) {
394 case PIXEL_FORMAT_ARGB2101010:
395 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
396 /* HDR10, ARGB2101010 - set border color to red */
397 color->color_r_cr = color_value;
398 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
399 /* FreeSync 2 ARGB2101010 - set border color to pink */
400 color->color_r_cr = color_value;
401 color->color_b_cb = color_value;
402 } else
403 is_sdr = true;
404 break;
405 case PIXEL_FORMAT_FP16:
406 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
407 /* HDR10, FP16 - set border color to blue */
408 color->color_b_cb = color_value;
409 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
410 /* FreeSync 2 HDR - set border color to green */
411 color->color_g_y = color_value;
412 } else
413 is_sdr = true;
414 break;
415 default:
416 is_sdr = true;
417 break;
418 }
419
420 if (is_sdr) {
421 /* SDR - set border color to Gray */
422 color->color_r_cr = color_value/2;
423 color->color_b_cb = color_value/2;
424 color->color_g_y = color_value/2;
425 }
426 }
427
428 /* Visual Confirm color definition for VABC */
get_vabc_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)429 void get_vabc_visual_confirm_color(
430 struct pipe_ctx *pipe_ctx,
431 struct tg_color *color)
432 {
433 uint32_t color_value = MAX_TG_COLOR_VALUE;
434 struct dc_link *edp_link = NULL;
435
436 if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link) {
437 if (pipe_ctx->stream->link->connector_signal == SIGNAL_TYPE_EDP)
438 edp_link = pipe_ctx->stream->link;
439 }
440
441 if (edp_link) {
442 switch (edp_link->backlight_control_type) {
443 case BACKLIGHT_CONTROL_PWM:
444 color->color_r_cr = color_value;
445 color->color_g_y = 0;
446 color->color_b_cb = 0;
447 break;
448 case BACKLIGHT_CONTROL_AMD_AUX:
449 color->color_r_cr = 0;
450 color->color_g_y = color_value;
451 color->color_b_cb = 0;
452 break;
453 case BACKLIGHT_CONTROL_VESA_AUX:
454 color->color_r_cr = 0;
455 color->color_g_y = 0;
456 color->color_b_cb = color_value;
457 break;
458 }
459 } else {
460 color->color_r_cr = 0;
461 color->color_g_y = 0;
462 color->color_b_cb = 0;
463 }
464 }
465
get_subvp_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)466 void get_subvp_visual_confirm_color(
467 struct pipe_ctx *pipe_ctx,
468 struct tg_color *color)
469 {
470 uint32_t color_value = MAX_TG_COLOR_VALUE;
471 if (pipe_ctx) {
472 switch (pipe_ctx->p_state_type) {
473 case P_STATE_SUB_VP:
474 color->color_r_cr = color_value;
475 color->color_g_y = 0;
476 color->color_b_cb = 0;
477 break;
478 case P_STATE_DRR_SUB_VP:
479 color->color_r_cr = 0;
480 color->color_g_y = color_value;
481 color->color_b_cb = 0;
482 break;
483 case P_STATE_V_BLANK_SUB_VP:
484 color->color_r_cr = 0;
485 color->color_g_y = 0;
486 color->color_b_cb = color_value;
487 break;
488 default:
489 break;
490 }
491 }
492 }
493
get_mclk_switch_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)494 void get_mclk_switch_visual_confirm_color(
495 struct pipe_ctx *pipe_ctx,
496 struct tg_color *color)
497 {
498 uint32_t color_value = MAX_TG_COLOR_VALUE;
499
500 if (pipe_ctx) {
501 switch (pipe_ctx->p_state_type) {
502 case P_STATE_V_BLANK:
503 color->color_r_cr = color_value;
504 color->color_g_y = color_value;
505 color->color_b_cb = 0;
506 break;
507 case P_STATE_FPO:
508 color->color_r_cr = 0;
509 color->color_g_y = color_value;
510 color->color_b_cb = color_value;
511 break;
512 case P_STATE_V_ACTIVE:
513 color->color_r_cr = color_value;
514 color->color_g_y = 0;
515 color->color_b_cb = color_value;
516 break;
517 case P_STATE_SUB_VP:
518 color->color_r_cr = color_value;
519 color->color_g_y = 0;
520 color->color_b_cb = 0;
521 break;
522 case P_STATE_DRR_SUB_VP:
523 color->color_r_cr = 0;
524 color->color_g_y = color_value;
525 color->color_b_cb = 0;
526 break;
527 case P_STATE_V_BLANK_SUB_VP:
528 color->color_r_cr = 0;
529 color->color_g_y = 0;
530 color->color_b_cb = color_value;
531 break;
532 default:
533 break;
534 }
535 }
536 }
537
get_cursor_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)538 void get_cursor_visual_confirm_color(
539 struct pipe_ctx *pipe_ctx,
540 struct tg_color *color)
541 {
542 uint32_t color_value = MAX_TG_COLOR_VALUE;
543
544 if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {
545 color->color_r_cr = color_value;
546 color->color_g_y = 0;
547 color->color_b_cb = 0;
548 } else {
549 color->color_r_cr = 0;
550 color->color_g_y = 0;
551 color->color_b_cb = color_value;
552 }
553 }
554
set_p_state_switch_method(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)555 void set_p_state_switch_method(
556 struct dc *dc,
557 struct dc_state *context,
558 struct pipe_ctx *pipe_ctx)
559 {
560 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
561 bool enable_subvp;
562
563 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
564 return;
565
566 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
567 dm_dram_clock_change_unsupported) {
568 /* MCLK switching is supported */
569 if (!pipe_ctx->has_vactive_margin) {
570 /* In Vblank - yellow */
571 pipe_ctx->p_state_type = P_STATE_V_BLANK;
572
573 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
574 /* FPO + Vblank - cyan */
575 pipe_ctx->p_state_type = P_STATE_FPO;
576 }
577 } else {
578 /* In Vactive - pink */
579 pipe_ctx->p_state_type = P_STATE_V_ACTIVE;
580 }
581
582 /* SubVP */
583 enable_subvp = false;
584
585 for (int i = 0; i < dc->res_pool->pipe_count; i++) {
586 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
587
588 if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&
589 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
590 /* SubVP enable - red */
591 pipe_ctx->p_state_type = P_STATE_SUB_VP;
592 enable_subvp = true;
593
594 if (pipe_ctx->stream == pipe->stream)
595 return;
596 break;
597 }
598 }
599
600 if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {
601 if (pipe_ctx->stream->allow_freesync == 1) {
602 /* SubVP enable and DRR on - green */
603 pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;
604 } else {
605 /* SubVP enable and No DRR - blue */
606 pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;
607 }
608 }
609 }
610 }
611
get_fams2_visual_confirm_color(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx,struct tg_color * color)612 void get_fams2_visual_confirm_color(
613 struct dc *dc,
614 struct dc_state *context,
615 struct pipe_ctx *pipe_ctx,
616 struct tg_color *color)
617 {
618 uint32_t color_value = MAX_TG_COLOR_VALUE;
619
620 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)
621 return;
622
623 /* driver only handles visual confirm when FAMS2 is disabled */
624 if (!dc_state_is_fams2_in_use(dc, context)) {
625 /* when FAMS2 is disabled, all pipes are grey */
626 color->color_g_y = color_value / 2;
627 color->color_b_cb = color_value / 2;
628 color->color_r_cr = color_value / 2;
629 }
630 }
631
hwss_build_fast_sequence(struct dc * dc,struct dc_dmub_cmd * dc_dmub_cmd,unsigned int dmub_cmd_count,struct block_sequence block_sequence[],unsigned int * num_steps,struct pipe_ctx * pipe_ctx,struct dc_stream_status * stream_status,struct dc_state * context)632 void hwss_build_fast_sequence(struct dc *dc,
633 struct dc_dmub_cmd *dc_dmub_cmd,
634 unsigned int dmub_cmd_count,
635 struct block_sequence block_sequence[],
636 unsigned int *num_steps,
637 struct pipe_ctx *pipe_ctx,
638 struct dc_stream_status *stream_status,
639 struct dc_state *context)
640 {
641 struct dc_plane_state *plane = pipe_ctx->plane_state;
642 struct dc_stream_state *stream = pipe_ctx->stream;
643 struct dce_hwseq *hws = dc->hwseq;
644 struct pipe_ctx *current_pipe = NULL;
645 struct pipe_ctx *current_mpc_pipe = NULL;
646 unsigned int i = 0;
647
648 *num_steps = 0; // Initialize to 0
649
650 if (!plane || !stream)
651 return;
652
653 if (dc->hwss.wait_for_dcc_meta_propagation) {
654 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
655 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;
656 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
657 (*num_steps)++;
658 }
659 if (dc->hwss.subvp_pipe_control_lock_fast) {
660 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
661 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
662 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
663 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
664 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
665 (*num_steps)++;
666 }
667 if (dc->hwss.fams2_global_control_lock_fast) {
668 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
669 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true;
670 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
671 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
672 (*num_steps)++;
673 }
674 if (dc->hwss.pipe_control_lock) {
675 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
676 block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
677 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
678 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
679 (*num_steps)++;
680 }
681
682 for (i = 0; i < dmub_cmd_count; i++) {
683 block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
684 block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
685 block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
686 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
687 (*num_steps)++;
688 }
689
690 current_pipe = pipe_ctx;
691 while (current_pipe) {
692 current_mpc_pipe = current_pipe;
693 while (current_mpc_pipe) {
694 if (current_mpc_pipe->plane_state) {
695 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {
696 block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;
697 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
698 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
699 (*num_steps)++;
700 }
701 if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
702 block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
703 block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
704 block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
705 block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
706 (*num_steps)++;
707 }
708 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
709 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
710 stream_status->mall_stream_config.type == SUBVP_MAIN) {
711 block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
712 block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address;
713 block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
714 block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
715 (*num_steps)++;
716 }
717
718 block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
719 block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
720 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
721 (*num_steps)++;
722 }
723
724 if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
725 block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
726 block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
727 block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
728 block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
729 (*num_steps)++;
730 }
731
732 if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
733 block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
734 block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
735 (*num_steps)++;
736 }
737 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
738 block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
739 block_sequence[*num_steps].func = DPP_SETUP_DPP;
740 (*num_steps)++;
741 }
742 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
743 block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
744 block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
745 (*num_steps)++;
746 }
747 }
748 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
749 block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
750 block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
751 block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
752 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
753 (*num_steps)++;
754 }
755
756 if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
757 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
758 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
759 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
760 block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
761 (*num_steps)++;
762
763 if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
764 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
765 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
766 block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
767 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
768 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
769 (*num_steps)++;
770 } else {
771 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
772 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
773 block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
774 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
775 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
776 (*num_steps)++;
777 }
778 }
779 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
780 }
781 current_pipe = current_pipe->next_odm_pipe;
782 }
783
784 if (dc->hwss.pipe_control_lock) {
785 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
786 block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
787 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
788 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
789 (*num_steps)++;
790 }
791 if (dc->hwss.subvp_pipe_control_lock_fast) {
792 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
793 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
794 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
795 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
796 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
797 (*num_steps)++;
798 }
799 if (dc->hwss.fams2_global_control_lock_fast) {
800 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
801 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = false;
802 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
803 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
804 (*num_steps)++;
805 }
806
807 current_pipe = pipe_ctx;
808 while (current_pipe) {
809 current_mpc_pipe = current_pipe;
810
811 while (current_mpc_pipe) {
812 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe &&
813 current_mpc_pipe->stream && current_mpc_pipe->plane_state &&
814 current_mpc_pipe->plane_state->update_flags.bits.addr_update &&
815 !current_mpc_pipe->plane_state->skip_manual_trigger) {
816 block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
817 block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
818 (*num_steps)++;
819 }
820 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
821 }
822 current_pipe = current_pipe->next_odm_pipe;
823 }
824 }
825
hwss_execute_sequence(struct dc * dc,struct block_sequence block_sequence[],int num_steps)826 void hwss_execute_sequence(struct dc *dc,
827 struct block_sequence block_sequence[],
828 int num_steps)
829 {
830 unsigned int i;
831 union block_sequence_params *params;
832 struct dce_hwseq *hws = dc->hwseq;
833
834 for (i = 0; i < num_steps; i++) {
835 params = &(block_sequence[i].params);
836 switch (block_sequence[i].func) {
837
838 case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST:
839 dc->hwss.subvp_pipe_control_lock_fast(params);
840 break;
841 case OPTC_PIPE_CONTROL_LOCK:
842 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,
843 params->pipe_control_lock_params.pipe_ctx,
844 params->pipe_control_lock_params.lock);
845 break;
846 case HUBP_SET_FLIP_CONTROL_GSL:
847 dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx,
848 params->set_flip_control_gsl_params.flip_immediate);
849 break;
850 case HUBP_PROGRAM_TRIPLEBUFFER:
851 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,
852 params->program_triplebuffer_params.pipe_ctx,
853 params->program_triplebuffer_params.enableTripleBuffer);
854 break;
855 case HUBP_UPDATE_PLANE_ADDR:
856 dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,
857 params->update_plane_addr_params.pipe_ctx);
858 break;
859 case DPP_SET_INPUT_TRANSFER_FUNC:
860 hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,
861 params->set_input_transfer_func_params.pipe_ctx,
862 params->set_input_transfer_func_params.plane_state);
863 break;
864 case DPP_PROGRAM_GAMUT_REMAP:
865 dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
866 break;
867 case DPP_SETUP_DPP:
868 hwss_setup_dpp(params);
869 break;
870 case DPP_PROGRAM_BIAS_AND_SCALE:
871 hwss_program_bias_and_scale(params);
872 break;
873 case OPTC_PROGRAM_MANUAL_TRIGGER:
874 hwss_program_manual_trigger(params);
875 break;
876 case DPP_SET_OUTPUT_TRANSFER_FUNC:
877 hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,
878 params->set_output_transfer_func_params.pipe_ctx,
879 params->set_output_transfer_func_params.stream);
880 break;
881 case MPC_UPDATE_VISUAL_CONFIRM:
882 dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,
883 params->update_visual_confirm_params.pipe_ctx,
884 params->update_visual_confirm_params.mpcc_id);
885 break;
886 case MPC_POWER_ON_MPC_MEM_PWR:
887 hwss_power_on_mpc_mem_pwr(params);
888 break;
889 case MPC_SET_OUTPUT_CSC:
890 hwss_set_output_csc(params);
891 break;
892 case MPC_SET_OCSC_DEFAULT:
893 hwss_set_ocsc_default(params);
894 break;
895 case DMUB_SEND_DMCUB_CMD:
896 hwss_send_dmcub_cmd(params);
897 break;
898 case DMUB_SUBVP_SAVE_SURF_ADDR:
899 hwss_subvp_save_surf_addr(params);
900 break;
901 case HUBP_WAIT_FOR_DCC_META_PROP:
902 dc->hwss.wait_for_dcc_meta_propagation(
903 params->wait_for_dcc_meta_propagation_params.dc,
904 params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);
905 break;
906 case DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST:
907 dc->hwss.fams2_global_control_lock_fast(params);
908 break;
909 default:
910 ASSERT(false);
911 break;
912 }
913 }
914 }
915
hwss_send_dmcub_cmd(union block_sequence_params * params)916 void hwss_send_dmcub_cmd(union block_sequence_params *params)
917 {
918 struct dc_context *ctx = params->send_dmcub_cmd_params.ctx;
919 union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd;
920 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type;
921
922 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);
923 }
924
hwss_program_manual_trigger(union block_sequence_params * params)925 void hwss_program_manual_trigger(union block_sequence_params *params)
926 {
927 struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;
928
929 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
930 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
931 }
932
hwss_setup_dpp(union block_sequence_params * params)933 void hwss_setup_dpp(union block_sequence_params *params)
934 {
935 struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;
936 struct dpp *dpp = pipe_ctx->plane_res.dpp;
937 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
938
939 if (!plane_state)
940 return;
941
942 if (dpp && dpp->funcs->dpp_setup) {
943 // program the input csc
944 dpp->funcs->dpp_setup(dpp,
945 plane_state->format,
946 EXPANSION_MODE_ZERO,
947 plane_state->input_csc_color_matrix,
948 plane_state->color_space,
949 NULL);
950 }
951
952 if (dpp && dpp->funcs->set_cursor_matrix) {
953 dpp->funcs->set_cursor_matrix(dpp,
954 plane_state->color_space,
955 plane_state->cursor_csc_color_matrix);
956 }
957 }
958
hwss_program_bias_and_scale(union block_sequence_params * params)959 void hwss_program_bias_and_scale(union block_sequence_params *params)
960 {
961 struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
962 struct dpp *dpp = pipe_ctx->plane_res.dpp;
963 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
964 struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
965
966 //TODO :for CNVC set scale and bias registers if necessary
967 if (dpp->funcs->dpp_program_bias_and_scale) {
968 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
969 }
970 }
971
hwss_power_on_mpc_mem_pwr(union block_sequence_params * params)972 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
973 {
974 struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
975 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
976 bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
977
978 if (mpc->funcs->power_on_mpc_mem_pwr)
979 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
980 }
981
hwss_set_output_csc(union block_sequence_params * params)982 void hwss_set_output_csc(union block_sequence_params *params)
983 {
984 struct mpc *mpc = params->set_output_csc_params.mpc;
985 int opp_id = params->set_output_csc_params.opp_id;
986 const uint16_t *matrix = params->set_output_csc_params.regval;
987 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
988
989 if (mpc->funcs->set_output_csc != NULL)
990 mpc->funcs->set_output_csc(mpc,
991 opp_id,
992 matrix,
993 ocsc_mode);
994 }
995
hwss_set_ocsc_default(union block_sequence_params * params)996 void hwss_set_ocsc_default(union block_sequence_params *params)
997 {
998 struct mpc *mpc = params->set_ocsc_default_params.mpc;
999 int opp_id = params->set_ocsc_default_params.opp_id;
1000 enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
1001 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
1002
1003 if (mpc->funcs->set_ocsc_default != NULL)
1004 mpc->funcs->set_ocsc_default(mpc,
1005 opp_id,
1006 colorspace,
1007 ocsc_mode);
1008 }
1009
hwss_subvp_save_surf_addr(union block_sequence_params * params)1010 void hwss_subvp_save_surf_addr(union block_sequence_params *params)
1011 {
1012 struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv;
1013 const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr;
1014 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index;
1015
1016 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);
1017 }
1018
get_surface_tile_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)1019 void get_surface_tile_visual_confirm_color(
1020 struct pipe_ctx *pipe_ctx,
1021 struct tg_color *color)
1022 {
1023 uint32_t color_value = MAX_TG_COLOR_VALUE;
1024 /* Determine the overscan color based on the bottom-most plane's context */
1025 struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
1026
1027 while (bottom_pipe_ctx->bottom_pipe != NULL)
1028 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
1029
1030 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
1031 case DC_SW_LINEAR:
1032 /* LINEAR Surface - set border color to red */
1033 color->color_r_cr = color_value;
1034 break;
1035 default:
1036 break;
1037 }
1038 }
1039
1040 /**
1041 * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank
1042 * pattern updates
1043 *
1044 * @dc: [in] dc reference
1045 * @context: [in] hardware context in use
1046 */
hwss_wait_for_all_blank_complete(struct dc * dc,struct dc_state * context)1047 void hwss_wait_for_all_blank_complete(struct dc *dc,
1048 struct dc_state *context)
1049 {
1050 struct pipe_ctx *opp_head;
1051 struct dce_hwseq *hws = dc->hwseq;
1052 int i;
1053
1054 if (!hws->funcs.wait_for_blank_complete)
1055 return;
1056
1057 for (i = 0; i < MAX_PIPES; i++) {
1058 opp_head = &context->res_ctx.pipe_ctx[i];
1059
1060 if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
1061 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)
1062 continue;
1063
1064 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
1065 }
1066 }
1067
hwss_wait_for_odm_update_pending_complete(struct dc * dc,struct dc_state * context)1068 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)
1069 {
1070 struct pipe_ctx *otg_master;
1071 struct timing_generator *tg;
1072 int i;
1073
1074 for (i = 0; i < MAX_PIPES; i++) {
1075 otg_master = &context->res_ctx.pipe_ctx[i];
1076 if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
1077 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)
1078 continue;
1079 tg = otg_master->stream_res.tg;
1080 if (tg->funcs->wait_odm_doublebuffer_pending_clear)
1081 tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
1082 }
1083
1084 /* ODM update may require to reprogram blank pattern for each OPP */
1085 hwss_wait_for_all_blank_complete(dc, context);
1086 }
1087
hwss_wait_for_no_pipes_pending(struct dc * dc,struct dc_state * context)1088 void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1089 {
1090 int i;
1091 for (i = 0; i < MAX_PIPES; i++) {
1092 int count = 0;
1093 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1094
1095 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1096 continue;
1097
1098 /* Timeout 100 ms */
1099 while (count < 100000) {
1100 /* Must set to false to start with, due to OR in update function */
1101 pipe->plane_state->status.is_flip_pending = false;
1102 dc->hwss.update_pending_status(pipe);
1103 if (!pipe->plane_state->status.is_flip_pending)
1104 break;
1105 udelay(1);
1106 count++;
1107 }
1108 ASSERT(!pipe->plane_state->status.is_flip_pending);
1109 }
1110 }
1111
hwss_wait_for_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1112 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1113 {
1114 /*
1115 * This function calls HWSS to wait for any potentially double buffered
1116 * operations to complete. It should be invoked as a pre-amble prior
1117 * to full update programming before asserting any HW locks.
1118 */
1119 int pipe_idx;
1120 int opp_inst;
1121 int opp_count = dc->res_pool->res_cap->num_opp;
1122 struct hubp *hubp;
1123 int mpcc_inst;
1124 const struct pipe_ctx *pipe_ctx;
1125
1126 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
1127 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
1128
1129 if (!pipe_ctx->stream)
1130 continue;
1131
1132 /* For full update we must wait for all double buffer updates, not just DRR updates. This
1133 * is particularly important for minimal transitions. Only check for OTG_MASTER pipes,
1134 * as non-OTG Master pipes share the same OTG as
1135 */
1136 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) {
1137 dc->hwss.wait_for_all_pending_updates(pipe_ctx);
1138 }
1139
1140 hubp = pipe_ctx->plane_res.hubp;
1141 if (!hubp)
1142 continue;
1143
1144 mpcc_inst = hubp->inst;
1145 // MPCC inst is equal to pipe index in practice
1146 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1147 if ((dc->res_pool->opps[opp_inst] != NULL) &&
1148 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
1149 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1150 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1151 break;
1152 }
1153 }
1154 }
1155 hwss_wait_for_odm_update_pending_complete(dc, dc_context);
1156 }
1157
hwss_process_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1158 void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1159 {
1160 /* wait for outstanding updates */
1161 hwss_wait_for_outstanding_hw_updates(dc, dc_context);
1162
1163 /* perform outstanding post update programming */
1164 if (dc->hwss.program_outstanding_updates)
1165 dc->hwss.program_outstanding_updates(dc, dc_context);
1166 }
1167