1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * core.c - ChipIdea USB IP core family device controller 4 * 5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2020 NXP 7 * 8 * Author: David Lopo 9 * Peter Chen <peter.chen@nxp.com> 10 * 11 * Main Features: 12 * - Four transfers are supported, usbtest is passed 13 * - USB Certification for gadget: CH9 and Mass Storage are passed 14 * - Low power mode 15 * - USB wakeup 16 */ 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/extcon.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/module.h> 24 #include <linux/idr.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/slab.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/pm_domain.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/usb/ch9.h> 33 #include <linux/usb/gadget.h> 34 #include <linux/usb/otg.h> 35 #include <linux/usb/chipidea.h> 36 #include <linux/usb/of.h> 37 #include <linux/of.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/usb/ehci_def.h> 40 41 #include "ci.h" 42 #include "udc.h" 43 #include "bits.h" 44 #include "host.h" 45 #include "otg.h" 46 #include "otg_fsm.h" 47 48 /* Controller register map */ 49 static const u8 ci_regs_nolpm[] = { 50 [CAP_CAPLENGTH] = 0x00U, 51 [CAP_HCCPARAMS] = 0x08U, 52 [CAP_DCCPARAMS] = 0x24U, 53 [CAP_TESTMODE] = 0x38U, 54 [OP_USBCMD] = 0x00U, 55 [OP_USBSTS] = 0x04U, 56 [OP_USBINTR] = 0x08U, 57 [OP_FRINDEX] = 0x0CU, 58 [OP_DEVICEADDR] = 0x14U, 59 [OP_ENDPTLISTADDR] = 0x18U, 60 [OP_TTCTRL] = 0x1CU, 61 [OP_BURSTSIZE] = 0x20U, 62 [OP_ULPI_VIEWPORT] = 0x30U, 63 [OP_PORTSC] = 0x44U, 64 [OP_DEVLC] = 0x84U, 65 [OP_OTGSC] = 0x64U, 66 [OP_USBMODE] = 0x68U, 67 [OP_ENDPTSETUPSTAT] = 0x6CU, 68 [OP_ENDPTPRIME] = 0x70U, 69 [OP_ENDPTFLUSH] = 0x74U, 70 [OP_ENDPTSTAT] = 0x78U, 71 [OP_ENDPTCOMPLETE] = 0x7CU, 72 [OP_ENDPTCTRL] = 0x80U, 73 }; 74 75 static const u8 ci_regs_lpm[] = { 76 [CAP_CAPLENGTH] = 0x00U, 77 [CAP_HCCPARAMS] = 0x08U, 78 [CAP_DCCPARAMS] = 0x24U, 79 [CAP_TESTMODE] = 0xFCU, 80 [OP_USBCMD] = 0x00U, 81 [OP_USBSTS] = 0x04U, 82 [OP_USBINTR] = 0x08U, 83 [OP_FRINDEX] = 0x0CU, 84 [OP_DEVICEADDR] = 0x14U, 85 [OP_ENDPTLISTADDR] = 0x18U, 86 [OP_TTCTRL] = 0x1CU, 87 [OP_BURSTSIZE] = 0x20U, 88 [OP_ULPI_VIEWPORT] = 0x30U, 89 [OP_PORTSC] = 0x44U, 90 [OP_DEVLC] = 0x84U, 91 [OP_OTGSC] = 0xC4U, 92 [OP_USBMODE] = 0xC8U, 93 [OP_ENDPTSETUPSTAT] = 0xD8U, 94 [OP_ENDPTPRIME] = 0xDCU, 95 [OP_ENDPTFLUSH] = 0xE0U, 96 [OP_ENDPTSTAT] = 0xE4U, 97 [OP_ENDPTCOMPLETE] = 0xE8U, 98 [OP_ENDPTCTRL] = 0xECU, 99 }; 100 101 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) 102 { 103 int i; 104 105 for (i = 0; i < OP_ENDPTCTRL; i++) 106 ci->hw_bank.regmap[i] = 107 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + 108 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); 109 110 for (; i <= OP_LAST; i++) 111 ci->hw_bank.regmap[i] = ci->hw_bank.op + 112 4 * (i - OP_ENDPTCTRL) + 113 (is_lpm 114 ? ci_regs_lpm[OP_ENDPTCTRL] 115 : ci_regs_nolpm[OP_ENDPTCTRL]); 116 117 } 118 119 static enum ci_revision ci_get_revision(struct ci_hdrc *ci) 120 { 121 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); 122 enum ci_revision rev = CI_REVISION_UNKNOWN; 123 124 if (ver == 0x2) { 125 rev = hw_read_id_reg(ci, ID_ID, REVISION) 126 >> __ffs(REVISION); 127 rev += CI_REVISION_20; 128 } else if (ver == 0x0) { 129 rev = CI_REVISION_1X; 130 } 131 132 return rev; 133 } 134 135 /** 136 * hw_read_intr_enable: returns interrupt enable register 137 * 138 * @ci: the controller 139 * 140 * This function returns register data 141 */ 142 u32 hw_read_intr_enable(struct ci_hdrc *ci) 143 { 144 return hw_read(ci, OP_USBINTR, ~0); 145 } 146 147 /** 148 * hw_read_intr_status: returns interrupt status register 149 * 150 * @ci: the controller 151 * 152 * This function returns register data 153 */ 154 u32 hw_read_intr_status(struct ci_hdrc *ci) 155 { 156 return hw_read(ci, OP_USBSTS, ~0); 157 } 158 159 /** 160 * hw_port_test_set: writes port test mode (execute without interruption) 161 * @ci: the controller 162 * @mode: new value 163 * 164 * This function returns an error code 165 */ 166 int hw_port_test_set(struct ci_hdrc *ci, u8 mode) 167 { 168 const u8 TEST_MODE_MAX = 7; 169 170 if (mode > TEST_MODE_MAX) 171 return -EINVAL; 172 173 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); 174 return 0; 175 } 176 177 /** 178 * hw_port_test_get: reads port test mode value 179 * 180 * @ci: the controller 181 * 182 * This function returns port test mode value 183 */ 184 u8 hw_port_test_get(struct ci_hdrc *ci) 185 { 186 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); 187 } 188 189 static void hw_wait_phy_stable(void) 190 { 191 /* 192 * The phy needs some delay to output the stable status from low 193 * power mode. And for OTGSC, the status inputs are debounced 194 * using a 1 ms time constant, so, delay 2ms for controller to get 195 * the stable status, like vbus and id when the phy leaves low power. 196 */ 197 usleep_range(2000, 2500); 198 } 199 200 /* The PHY enters/leaves low power mode */ 201 static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable) 202 { 203 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; 204 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); 205 206 if (enable && !lpm) 207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 208 PORTSC_PHCD(ci->hw_bank.lpm)); 209 else if (!enable && lpm) 210 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 211 0); 212 } 213 214 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) 215 { 216 return ci->platdata->enter_lpm(ci, enable); 217 } 218 219 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) 220 { 221 u32 reg; 222 223 /* bank is a module variable */ 224 ci->hw_bank.abs = base; 225 226 ci->hw_bank.cap = ci->hw_bank.abs; 227 ci->hw_bank.cap += ci->platdata->capoffset; 228 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); 229 230 hw_alloc_regmap(ci, false); 231 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> 232 __ffs(HCCPARAMS_LEN); 233 ci->hw_bank.lpm = reg; 234 if (reg) 235 hw_alloc_regmap(ci, !!reg); 236 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; 237 ci->hw_bank.size += OP_LAST; 238 ci->hw_bank.size /= sizeof(u32); 239 240 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> 241 __ffs(DCCPARAMS_DEN); 242 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ 243 244 if (ci->hw_ep_max > ENDPT_MAX) 245 return -ENODEV; 246 247 ci_hdrc_enter_lpm(ci, false); 248 249 /* Disable all interrupts bits */ 250 hw_write(ci, OP_USBINTR, 0xffffffff, 0); 251 252 /* Clear all interrupts status bits*/ 253 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); 254 255 ci->rev = ci_get_revision(ci); 256 257 dev_dbg(ci->dev, 258 "revision: %d, lpm: %d; cap: %px op: %px\n", 259 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); 260 261 /* setup lock mode ? */ 262 263 /* ENDPTSETUPSTAT is '0' by default */ 264 265 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ 266 267 return 0; 268 } 269 270 void hw_phymode_configure(struct ci_hdrc *ci) 271 { 272 u32 portsc, lpm, sts = 0; 273 274 switch (ci->platdata->phy_mode) { 275 case USBPHY_INTERFACE_MODE_UTMI: 276 portsc = PORTSC_PTS(PTS_UTMI); 277 lpm = DEVLC_PTS(PTS_UTMI); 278 break; 279 case USBPHY_INTERFACE_MODE_UTMIW: 280 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; 281 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; 282 break; 283 case USBPHY_INTERFACE_MODE_ULPI: 284 portsc = PORTSC_PTS(PTS_ULPI); 285 lpm = DEVLC_PTS(PTS_ULPI); 286 break; 287 case USBPHY_INTERFACE_MODE_SERIAL: 288 portsc = PORTSC_PTS(PTS_SERIAL); 289 lpm = DEVLC_PTS(PTS_SERIAL); 290 sts = 1; 291 break; 292 case USBPHY_INTERFACE_MODE_HSIC: 293 portsc = PORTSC_PTS(PTS_HSIC); 294 lpm = DEVLC_PTS(PTS_HSIC); 295 break; 296 default: 297 return; 298 } 299 300 if (ci->hw_bank.lpm) { 301 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); 302 if (sts) 303 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); 304 } else { 305 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); 306 if (sts) 307 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); 308 } 309 } 310 EXPORT_SYMBOL_GPL(hw_phymode_configure); 311 312 /** 313 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy 314 * interfaces 315 * @ci: the controller 316 * 317 * This function returns an error code if the phy failed to init 318 */ 319 static int _ci_usb_phy_init(struct ci_hdrc *ci) 320 { 321 int ret; 322 323 if (ci->phy) { 324 ret = phy_init(ci->phy); 325 if (ret) 326 return ret; 327 328 ret = phy_power_on(ci->phy); 329 if (ret) { 330 phy_exit(ci->phy); 331 return ret; 332 } 333 } else { 334 ret = usb_phy_init(ci->usb_phy); 335 } 336 337 return ret; 338 } 339 340 /** 341 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy 342 * interfaces 343 * @ci: the controller 344 */ 345 static void ci_usb_phy_exit(struct ci_hdrc *ci) 346 { 347 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 348 return; 349 350 if (ci->phy) { 351 phy_power_off(ci->phy); 352 phy_exit(ci->phy); 353 } else { 354 usb_phy_shutdown(ci->usb_phy); 355 } 356 } 357 358 /** 359 * ci_usb_phy_init: initialize phy according to different phy type 360 * @ci: the controller 361 * 362 * This function returns an error code if usb_phy_init has failed 363 */ 364 static int ci_usb_phy_init(struct ci_hdrc *ci) 365 { 366 int ret; 367 368 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) 369 return 0; 370 371 switch (ci->platdata->phy_mode) { 372 case USBPHY_INTERFACE_MODE_UTMI: 373 case USBPHY_INTERFACE_MODE_UTMIW: 374 case USBPHY_INTERFACE_MODE_HSIC: 375 ret = _ci_usb_phy_init(ci); 376 if (!ret) 377 hw_wait_phy_stable(); 378 else 379 return ret; 380 hw_phymode_configure(ci); 381 break; 382 case USBPHY_INTERFACE_MODE_ULPI: 383 case USBPHY_INTERFACE_MODE_SERIAL: 384 hw_phymode_configure(ci); 385 ret = _ci_usb_phy_init(ci); 386 if (ret) 387 return ret; 388 break; 389 default: 390 ret = _ci_usb_phy_init(ci); 391 if (!ret) 392 hw_wait_phy_stable(); 393 } 394 395 return ret; 396 } 397 398 399 /** 400 * ci_platform_configure: do controller configure 401 * @ci: the controller 402 * 403 */ 404 void ci_platform_configure(struct ci_hdrc *ci) 405 { 406 bool is_device_mode, is_host_mode; 407 408 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; 409 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; 410 411 if (is_device_mode) { 412 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE); 413 414 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING) 415 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 416 USBMODE_CI_SDIS); 417 } 418 419 if (is_host_mode) { 420 phy_set_mode(ci->phy, PHY_MODE_USB_HOST); 421 422 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING) 423 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, 424 USBMODE_CI_SDIS); 425 } 426 427 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { 428 if (ci->hw_bank.lpm) 429 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); 430 else 431 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); 432 } 433 434 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) 435 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); 436 437 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); 438 439 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) 440 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, 441 ci->platdata->ahb_burst_config); 442 443 /* override burst size, take effect only when ahb_burst_config is 0 */ 444 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { 445 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) 446 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, 447 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); 448 449 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) 450 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, 451 ci->platdata->rx_burst_size); 452 } 453 } 454 455 /** 456 * hw_controller_reset: do controller reset 457 * @ci: the controller 458 * 459 * This function returns an error code 460 */ 461 static int hw_controller_reset(struct ci_hdrc *ci) 462 { 463 int count = 0; 464 465 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); 466 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { 467 udelay(10); 468 if (count++ > 1000) 469 return -ETIMEDOUT; 470 } 471 472 return 0; 473 } 474 475 /** 476 * hw_device_reset: resets chip (execute without interruption) 477 * @ci: the controller 478 * 479 * This function returns an error code 480 */ 481 int hw_device_reset(struct ci_hdrc *ci) 482 { 483 int ret; 484 485 /* should flush & stop before reset */ 486 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); 487 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 488 489 ret = hw_controller_reset(ci); 490 if (ret) { 491 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); 492 return ret; 493 } 494 495 if (ci->platdata->notify_event) { 496 ret = ci->platdata->notify_event(ci, 497 CI_HDRC_CONTROLLER_RESET_EVENT); 498 if (ret) 499 return ret; 500 } 501 502 /* USBMODE should be configured step by step */ 503 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); 504 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); 505 /* HW >= 2.3 */ 506 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); 507 508 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { 509 dev_err(ci->dev, "cannot enter in %s device mode\n", 510 ci_role(ci)->name); 511 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm); 512 return -ENODEV; 513 } 514 515 ci_platform_configure(ci); 516 517 return 0; 518 } 519 520 static irqreturn_t ci_irq_handler(int irq, void *data) 521 { 522 struct ci_hdrc *ci = data; 523 irqreturn_t ret = IRQ_NONE; 524 u32 otgsc = 0; 525 526 if (ci->in_lpm) { 527 /* 528 * If we already have a wakeup irq pending there, 529 * let's just return to wait resume finished firstly. 530 */ 531 if (ci->wakeup_int) 532 return IRQ_HANDLED; 533 534 disable_irq_nosync(irq); 535 ci->wakeup_int = true; 536 pm_runtime_get(ci->dev); 537 return IRQ_HANDLED; 538 } 539 540 if (ci->is_otg) { 541 otgsc = hw_read_otgsc(ci, ~0); 542 if (ci_otg_is_fsm_mode(ci)) { 543 ret = ci_otg_fsm_irq(ci); 544 if (ret == IRQ_HANDLED) 545 return ret; 546 } 547 548 /* 549 * Handle id change interrupt, it indicates device/host function 550 * switch. 551 */ 552 if ((otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { 553 ci->id_event = true; 554 /* Clear ID change irq status */ 555 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); 556 } 557 558 /* 559 * Handle vbus change interrupt, it indicates device connection 560 * and disconnection events. 561 */ 562 if ((otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { 563 ci->b_sess_valid_event = true; 564 /* Clear BSV irq */ 565 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); 566 } 567 568 if (ci->id_event || ci->b_sess_valid_event) { 569 ci_otg_queue_work(ci); 570 return IRQ_HANDLED; 571 } 572 } 573 574 /* Handle device/host interrupt */ 575 if (ci->role != CI_ROLE_END) 576 ret = ci_role(ci)->irq(ci); 577 578 return ret; 579 } 580 581 static void ci_irq(struct ci_hdrc *ci) 582 { 583 unsigned long flags; 584 585 local_irq_save(flags); 586 ci_irq_handler(ci->irq, ci); 587 local_irq_restore(flags); 588 } 589 590 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, 591 void *ptr) 592 { 593 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); 594 struct ci_hdrc *ci = cbl->ci; 595 596 cbl->connected = event; 597 cbl->changed = true; 598 599 ci_irq(ci); 600 return NOTIFY_DONE; 601 } 602 603 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw) 604 { 605 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 606 enum usb_role role; 607 unsigned long flags; 608 609 spin_lock_irqsave(&ci->lock, flags); 610 role = ci_role_to_usb_role(ci); 611 spin_unlock_irqrestore(&ci->lock, flags); 612 613 return role; 614 } 615 616 static int ci_usb_role_switch_set(struct usb_role_switch *sw, 617 enum usb_role role) 618 { 619 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw); 620 struct ci_hdrc_cable *cable; 621 622 cable = &ci->platdata->id_extcon; 623 cable->changed = true; 624 cable->connected = (role == USB_ROLE_HOST); 625 626 cable = &ci->platdata->vbus_extcon; 627 cable->changed = true; 628 cable->connected = (role == USB_ROLE_DEVICE); 629 630 ci_irq(ci); 631 return 0; 632 } 633 634 static enum ci_role ci_get_role(struct ci_hdrc *ci) 635 { 636 enum ci_role role; 637 638 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { 639 if (ci->is_otg) { 640 role = ci_otg_role(ci); 641 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); 642 } else { 643 /* 644 * If the controller is not OTG capable, but support 645 * role switch, the defalt role is gadget, and the 646 * user can switch it through debugfs. 647 */ 648 role = CI_ROLE_GADGET; 649 } 650 } else { 651 role = ci->roles[CI_ROLE_HOST] ? CI_ROLE_HOST 652 : CI_ROLE_GADGET; 653 } 654 655 return role; 656 } 657 658 static struct usb_role_switch_desc ci_role_switch = { 659 .set = ci_usb_role_switch_set, 660 .get = ci_usb_role_switch_get, 661 .allow_userspace_control = true, 662 }; 663 664 static int ci_get_platdata(struct device *dev, 665 struct ci_hdrc_platform_data *platdata) 666 { 667 struct extcon_dev *ext_vbus, *ext_id; 668 struct ci_hdrc_cable *cable; 669 int ret; 670 671 if (!platdata->phy_mode) 672 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); 673 674 if (!platdata->dr_mode) 675 platdata->dr_mode = usb_get_dr_mode(dev); 676 677 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) 678 platdata->dr_mode = USB_DR_MODE_OTG; 679 680 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { 681 /* Get the vbus regulator */ 682 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus"); 683 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { 684 return -EPROBE_DEFER; 685 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { 686 /* no vbus regulator is needed */ 687 platdata->reg_vbus = NULL; 688 } else if (IS_ERR(platdata->reg_vbus)) { 689 dev_err(dev, "Getting regulator error: %ld\n", 690 PTR_ERR(platdata->reg_vbus)); 691 return PTR_ERR(platdata->reg_vbus); 692 } 693 /* Get TPL support */ 694 if (!platdata->tpl_support) 695 platdata->tpl_support = 696 of_usb_host_tpl_support(dev->of_node); 697 } 698 699 if (platdata->dr_mode == USB_DR_MODE_OTG) { 700 /* We can support HNP and SRP of OTG 2.0 */ 701 platdata->ci_otg_caps.otg_rev = 0x0200; 702 platdata->ci_otg_caps.hnp_support = true; 703 platdata->ci_otg_caps.srp_support = true; 704 705 /* Update otg capabilities by DT properties */ 706 ret = of_usb_update_otg_caps(dev->of_node, 707 &platdata->ci_otg_caps); 708 if (ret) 709 return ret; 710 } 711 712 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) 713 platdata->flags |= CI_HDRC_FORCE_FULLSPEED; 714 715 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", 716 &platdata->phy_clkgate_delay_us); 717 718 platdata->itc_setting = 1; 719 720 of_property_read_u32(dev->of_node, "itc-setting", 721 &platdata->itc_setting); 722 723 ret = of_property_read_u32(dev->of_node, "ahb-burst-config", 724 &platdata->ahb_burst_config); 725 if (!ret) { 726 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; 727 } else if (ret != -EINVAL) { 728 dev_err(dev, "failed to get ahb-burst-config\n"); 729 return ret; 730 } 731 732 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", 733 &platdata->tx_burst_size); 734 if (!ret) { 735 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; 736 } else if (ret != -EINVAL) { 737 dev_err(dev, "failed to get tx-burst-size-dword\n"); 738 return ret; 739 } 740 741 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", 742 &platdata->rx_burst_size); 743 if (!ret) { 744 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; 745 } else if (ret != -EINVAL) { 746 dev_err(dev, "failed to get rx-burst-size-dword\n"); 747 return ret; 748 } 749 750 if (of_property_read_bool(dev->of_node, "non-zero-ttctrl-ttha")) 751 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; 752 753 ext_id = ERR_PTR(-ENODEV); 754 ext_vbus = ERR_PTR(-ENODEV); 755 if (of_property_present(dev->of_node, "extcon")) { 756 /* Each one of them is not mandatory */ 757 ext_vbus = extcon_get_edev_by_phandle(dev, 0); 758 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) 759 return PTR_ERR(ext_vbus); 760 761 ext_id = extcon_get_edev_by_phandle(dev, 1); 762 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) 763 return PTR_ERR(ext_id); 764 } 765 766 cable = &platdata->vbus_extcon; 767 cable->nb.notifier_call = ci_cable_notifier; 768 cable->edev = ext_vbus; 769 770 if (!IS_ERR(ext_vbus)) { 771 ret = extcon_get_state(cable->edev, EXTCON_USB); 772 if (ret) 773 cable->connected = true; 774 else 775 cable->connected = false; 776 } 777 778 cable = &platdata->id_extcon; 779 cable->nb.notifier_call = ci_cable_notifier; 780 cable->edev = ext_id; 781 782 if (!IS_ERR(ext_id)) { 783 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST); 784 if (ret) 785 cable->connected = true; 786 else 787 cable->connected = false; 788 } 789 790 if (device_property_read_bool(dev, "usb-role-switch")) 791 ci_role_switch.fwnode = dev->fwnode; 792 793 platdata->pctl = devm_pinctrl_get(dev); 794 if (!IS_ERR(platdata->pctl)) { 795 struct pinctrl_state *p; 796 797 p = pinctrl_lookup_state(platdata->pctl, "default"); 798 if (!IS_ERR(p)) 799 platdata->pins_default = p; 800 801 p = pinctrl_lookup_state(platdata->pctl, "host"); 802 if (!IS_ERR(p)) 803 platdata->pins_host = p; 804 805 p = pinctrl_lookup_state(platdata->pctl, "device"); 806 if (!IS_ERR(p)) 807 platdata->pins_device = p; 808 } 809 810 if (!platdata->enter_lpm) 811 platdata->enter_lpm = ci_hdrc_enter_lpm_common; 812 813 return 0; 814 } 815 816 static int ci_extcon_register(struct ci_hdrc *ci) 817 { 818 struct ci_hdrc_cable *id, *vbus; 819 int ret; 820 821 id = &ci->platdata->id_extcon; 822 id->ci = ci; 823 if (!IS_ERR_OR_NULL(id->edev)) { 824 ret = devm_extcon_register_notifier(ci->dev, id->edev, 825 EXTCON_USB_HOST, &id->nb); 826 if (ret < 0) { 827 dev_err(ci->dev, "register ID failed\n"); 828 return ret; 829 } 830 } 831 832 vbus = &ci->platdata->vbus_extcon; 833 vbus->ci = ci; 834 if (!IS_ERR_OR_NULL(vbus->edev)) { 835 ret = devm_extcon_register_notifier(ci->dev, vbus->edev, 836 EXTCON_USB, &vbus->nb); 837 if (ret < 0) { 838 dev_err(ci->dev, "register VBUS failed\n"); 839 return ret; 840 } 841 } 842 843 return 0; 844 } 845 846 static void ci_power_lost_work(struct work_struct *work) 847 { 848 struct ci_hdrc *ci = container_of(work, struct ci_hdrc, power_lost_work); 849 enum ci_role role; 850 851 disable_irq_nosync(ci->irq); 852 pm_runtime_get_sync(ci->dev); 853 if (!ci_otg_is_fsm_mode(ci)) { 854 role = ci_get_role(ci); 855 856 if (ci->role != role) { 857 ci_handle_id_switch(ci); 858 } else if (role == CI_ROLE_GADGET) { 859 if (ci->is_otg && hw_read_otgsc(ci, OTGSC_BSV)) 860 usb_gadget_vbus_connect(&ci->gadget); 861 } 862 } 863 pm_runtime_put_sync(ci->dev); 864 enable_irq(ci->irq); 865 } 866 867 static DEFINE_IDA(ci_ida); 868 869 struct platform_device *ci_hdrc_add_device(struct device *dev, 870 struct resource *res, int nres, 871 struct ci_hdrc_platform_data *platdata) 872 { 873 struct platform_device *pdev; 874 int id, ret; 875 876 ret = ci_get_platdata(dev, platdata); 877 if (ret) 878 return ERR_PTR(ret); 879 880 id = ida_alloc(&ci_ida, GFP_KERNEL); 881 if (id < 0) 882 return ERR_PTR(id); 883 884 pdev = platform_device_alloc("ci_hdrc", id); 885 if (!pdev) { 886 ret = -ENOMEM; 887 goto put_id; 888 } 889 890 pdev->dev.parent = dev; 891 device_set_of_node_from_dev(&pdev->dev, dev); 892 893 ret = platform_device_add_resources(pdev, res, nres); 894 if (ret) 895 goto err; 896 897 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); 898 if (ret) 899 goto err; 900 901 ret = platform_device_add(pdev); 902 if (ret) 903 goto err; 904 905 dev_pm_domain_detach(&pdev->dev, false); 906 907 return pdev; 908 909 err: 910 platform_device_put(pdev); 911 put_id: 912 ida_free(&ci_ida, id); 913 return ERR_PTR(ret); 914 } 915 EXPORT_SYMBOL_GPL(ci_hdrc_add_device); 916 917 void ci_hdrc_remove_device(struct platform_device *pdev) 918 { 919 int id = pdev->id; 920 platform_device_unregister(pdev); 921 ida_free(&ci_ida, id); 922 } 923 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); 924 925 /** 926 * ci_hdrc_query_available_role: get runtime available operation mode 927 * 928 * The glue layer can get current operation mode (host/peripheral/otg) 929 * This function should be called after ci core device has created. 930 * 931 * @pdev: the platform device of ci core. 932 * 933 * Return runtime usb_dr_mode. 934 */ 935 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev) 936 { 937 struct ci_hdrc *ci = platform_get_drvdata(pdev); 938 939 if (!ci) 940 return USB_DR_MODE_UNKNOWN; 941 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) 942 return USB_DR_MODE_OTG; 943 else if (ci->roles[CI_ROLE_HOST]) 944 return USB_DR_MODE_HOST; 945 else if (ci->roles[CI_ROLE_GADGET]) 946 return USB_DR_MODE_PERIPHERAL; 947 else 948 return USB_DR_MODE_UNKNOWN; 949 } 950 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role); 951 952 static inline void ci_role_destroy(struct ci_hdrc *ci) 953 { 954 ci_hdrc_gadget_destroy(ci); 955 ci_hdrc_host_destroy(ci); 956 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 957 ci_hdrc_otg_destroy(ci); 958 } 959 960 static void ci_get_otg_capable(struct ci_hdrc *ci) 961 { 962 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) 963 ci->is_otg = false; 964 else 965 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, 966 DCCPARAMS_DC | DCCPARAMS_HC) 967 == (DCCPARAMS_DC | DCCPARAMS_HC)); 968 if (ci->is_otg) { 969 dev_dbg(ci->dev, "It is OTG capable controller\n"); 970 /* Disable and clear all OTG irq */ 971 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, 972 OTGSC_INT_STATUS_BITS); 973 } 974 } 975 976 static ssize_t role_show(struct device *dev, struct device_attribute *attr, 977 char *buf) 978 { 979 struct ci_hdrc *ci = dev_get_drvdata(dev); 980 981 if (ci->role != CI_ROLE_END) 982 return sprintf(buf, "%s\n", ci_role(ci)->name); 983 984 return 0; 985 } 986 987 static ssize_t role_store(struct device *dev, 988 struct device_attribute *attr, const char *buf, size_t n) 989 { 990 struct ci_hdrc *ci = dev_get_drvdata(dev); 991 enum ci_role role; 992 int ret; 993 994 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) { 995 dev_warn(dev, "Current configuration is not dual-role, quit\n"); 996 return -EPERM; 997 } 998 999 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) 1000 if (!strncmp(buf, ci->roles[role]->name, 1001 strlen(ci->roles[role]->name))) 1002 break; 1003 1004 if (role == CI_ROLE_END) 1005 return -EINVAL; 1006 1007 mutex_lock(&ci->mutex); 1008 1009 if (role == ci->role) { 1010 mutex_unlock(&ci->mutex); 1011 return n; 1012 } 1013 1014 pm_runtime_get_sync(dev); 1015 disable_irq(ci->irq); 1016 ci_role_stop(ci); 1017 ret = ci_role_start(ci, role); 1018 if (!ret && ci->role == CI_ROLE_GADGET) 1019 ci_handle_vbus_change(ci); 1020 enable_irq(ci->irq); 1021 pm_runtime_put_sync(dev); 1022 mutex_unlock(&ci->mutex); 1023 1024 return (ret == 0) ? n : ret; 1025 } 1026 static DEVICE_ATTR_RW(role); 1027 1028 static struct attribute *ci_attrs[] = { 1029 &dev_attr_role.attr, 1030 NULL, 1031 }; 1032 ATTRIBUTE_GROUPS(ci); 1033 1034 static int ci_hdrc_probe(struct platform_device *pdev) 1035 { 1036 struct device *dev = &pdev->dev; 1037 struct ci_hdrc *ci; 1038 struct resource *res; 1039 void __iomem *base; 1040 int ret; 1041 enum usb_dr_mode dr_mode; 1042 1043 if (!dev_get_platdata(dev)) { 1044 dev_err(dev, "platform data missing\n"); 1045 return -ENODEV; 1046 } 1047 1048 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1049 if (IS_ERR(base)) 1050 return PTR_ERR(base); 1051 1052 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); 1053 if (!ci) 1054 return -ENOMEM; 1055 1056 spin_lock_init(&ci->lock); 1057 mutex_init(&ci->mutex); 1058 INIT_WORK(&ci->power_lost_work, ci_power_lost_work); 1059 1060 ci->dev = dev; 1061 ci->platdata = dev_get_platdata(dev); 1062 ci->imx28_write_fix = !!(ci->platdata->flags & 1063 CI_HDRC_IMX28_WRITE_FIX); 1064 ci->supports_runtime_pm = !!(ci->platdata->flags & 1065 CI_HDRC_SUPPORTS_RUNTIME_PM); 1066 ci->has_portsc_pec_bug = !!(ci->platdata->flags & 1067 CI_HDRC_HAS_PORTSC_PEC_MISSED); 1068 ci->has_short_pkt_limit = !!(ci->platdata->flags & 1069 CI_HDRC_HAS_SHORT_PKT_LIMIT); 1070 platform_set_drvdata(pdev, ci); 1071 1072 ret = hw_device_init(ci, base); 1073 if (ret < 0) { 1074 dev_err(dev, "can't initialize hardware\n"); 1075 return -ENODEV; 1076 } 1077 1078 ret = ci_ulpi_init(ci); 1079 if (ret) 1080 return ret; 1081 1082 if (ci->platdata->phy) { 1083 ci->phy = ci->platdata->phy; 1084 } else if (ci->platdata->usb_phy) { 1085 ci->usb_phy = ci->platdata->usb_phy; 1086 } else { 1087 /* Look for a generic PHY first */ 1088 ci->phy = devm_phy_get(dev->parent, "usb-phy"); 1089 1090 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) { 1091 ret = -EPROBE_DEFER; 1092 goto ulpi_exit; 1093 } else if (IS_ERR(ci->phy)) { 1094 ci->phy = NULL; 1095 } 1096 1097 /* Look for a legacy USB PHY from device-tree next */ 1098 if (!ci->phy) { 1099 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, 1100 "phys", 0); 1101 1102 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1103 ret = -EPROBE_DEFER; 1104 goto ulpi_exit; 1105 } else if (IS_ERR(ci->usb_phy)) { 1106 ci->usb_phy = NULL; 1107 } 1108 } 1109 1110 /* Look for any registered legacy USB PHY as last resort */ 1111 if (!ci->phy && !ci->usb_phy) { 1112 ci->usb_phy = devm_usb_get_phy(dev->parent, 1113 USB_PHY_TYPE_USB2); 1114 1115 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) { 1116 ret = -EPROBE_DEFER; 1117 goto ulpi_exit; 1118 } else if (IS_ERR(ci->usb_phy)) { 1119 ci->usb_phy = NULL; 1120 } 1121 } 1122 1123 /* No USB PHY was found in the end */ 1124 if (!ci->phy && !ci->usb_phy) { 1125 ret = -ENXIO; 1126 goto ulpi_exit; 1127 } 1128 } 1129 1130 ret = ci_usb_phy_init(ci); 1131 if (ret) { 1132 dev_err(dev, "unable to init phy: %d\n", ret); 1133 goto ulpi_exit; 1134 } 1135 1136 ci->hw_bank.phys = res->start; 1137 1138 ci->irq = platform_get_irq(pdev, 0); 1139 if (ci->irq < 0) { 1140 ret = ci->irq; 1141 goto deinit_phy; 1142 } 1143 1144 ci_get_otg_capable(ci); 1145 1146 dr_mode = ci->platdata->dr_mode; 1147 /* initialize role(s) before the interrupt is requested */ 1148 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { 1149 ret = ci_hdrc_host_init(ci); 1150 if (ret) { 1151 if (ret == -ENXIO) 1152 dev_info(dev, "doesn't support host\n"); 1153 else 1154 goto deinit_phy; 1155 } 1156 } 1157 1158 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { 1159 ret = ci_hdrc_gadget_init(ci); 1160 if (ret) { 1161 if (ret == -ENXIO) 1162 dev_info(dev, "doesn't support gadget\n"); 1163 else 1164 goto deinit_host; 1165 } 1166 } 1167 1168 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { 1169 dev_err(dev, "no supported roles\n"); 1170 ret = -ENODEV; 1171 goto deinit_gadget; 1172 } 1173 1174 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { 1175 ret = ci_hdrc_otg_init(ci); 1176 if (ret) { 1177 dev_err(dev, "init otg fails, ret = %d\n", ret); 1178 goto deinit_gadget; 1179 } 1180 } 1181 1182 if (ci_role_switch.fwnode) { 1183 ci_role_switch.driver_data = ci; 1184 ci->role_switch = usb_role_switch_register(dev, 1185 &ci_role_switch); 1186 if (IS_ERR(ci->role_switch)) { 1187 ret = PTR_ERR(ci->role_switch); 1188 goto deinit_otg; 1189 } 1190 } 1191 1192 ci->role = ci_get_role(ci); 1193 if (!ci_otg_is_fsm_mode(ci)) { 1194 /* only update vbus status for peripheral */ 1195 if (ci->role == CI_ROLE_GADGET) { 1196 /* Pull down DP for possible charger detection */ 1197 hw_write(ci, OP_USBCMD, USBCMD_RS, 0); 1198 ci_handle_vbus_change(ci); 1199 } 1200 1201 ret = ci_role_start(ci, ci->role); 1202 if (ret) { 1203 dev_err(dev, "can't start %s role\n", 1204 ci_role(ci)->name); 1205 goto stop; 1206 } 1207 } 1208 1209 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED, 1210 ci->platdata->name, ci); 1211 if (ret) 1212 goto stop; 1213 1214 ret = ci_extcon_register(ci); 1215 if (ret) 1216 goto stop; 1217 1218 if (ci->supports_runtime_pm) { 1219 pm_runtime_set_active(&pdev->dev); 1220 pm_runtime_enable(&pdev->dev); 1221 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1222 pm_runtime_mark_last_busy(ci->dev); 1223 pm_runtime_use_autosuspend(&pdev->dev); 1224 } 1225 1226 if (ci_otg_is_fsm_mode(ci)) 1227 ci_hdrc_otg_fsm_start(ci); 1228 1229 device_set_wakeup_capable(&pdev->dev, true); 1230 dbg_create_files(ci); 1231 1232 return 0; 1233 1234 stop: 1235 if (ci->role_switch) 1236 usb_role_switch_unregister(ci->role_switch); 1237 deinit_otg: 1238 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) 1239 ci_hdrc_otg_destroy(ci); 1240 deinit_gadget: 1241 ci_hdrc_gadget_destroy(ci); 1242 deinit_host: 1243 ci_hdrc_host_destroy(ci); 1244 deinit_phy: 1245 ci_usb_phy_exit(ci); 1246 ulpi_exit: 1247 ci_ulpi_exit(ci); 1248 1249 return ret; 1250 } 1251 1252 static void ci_hdrc_remove(struct platform_device *pdev) 1253 { 1254 struct ci_hdrc *ci = platform_get_drvdata(pdev); 1255 1256 if (ci->role_switch) 1257 usb_role_switch_unregister(ci->role_switch); 1258 1259 if (ci->supports_runtime_pm) { 1260 pm_runtime_get_sync(&pdev->dev); 1261 pm_runtime_disable(&pdev->dev); 1262 pm_runtime_put_noidle(&pdev->dev); 1263 } 1264 1265 dbg_remove_files(ci); 1266 ci_role_destroy(ci); 1267 ci_hdrc_enter_lpm(ci, true); 1268 ci_usb_phy_exit(ci); 1269 ci_ulpi_exit(ci); 1270 } 1271 1272 #ifdef CONFIG_PM 1273 /* Prepare wakeup by SRP before suspend */ 1274 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) 1275 { 1276 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1277 !hw_read_otgsc(ci, OTGSC_ID)) { 1278 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 1279 PORTSC_PP); 1280 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, 1281 PORTSC_WKCN); 1282 } 1283 } 1284 1285 /* Handle SRP when wakeup by data pulse */ 1286 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) 1287 { 1288 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && 1289 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { 1290 if (!hw_read_otgsc(ci, OTGSC_ID)) { 1291 ci->fsm.a_srp_det = 1; 1292 ci->fsm.a_bus_drop = 0; 1293 } else { 1294 ci->fsm.id = 1; 1295 } 1296 ci_otg_queue_work(ci); 1297 } 1298 } 1299 1300 static void ci_controller_suspend(struct ci_hdrc *ci) 1301 { 1302 disable_irq(ci->irq); 1303 ci_hdrc_enter_lpm(ci, true); 1304 if (ci->platdata->phy_clkgate_delay_us) 1305 usleep_range(ci->platdata->phy_clkgate_delay_us, 1306 ci->platdata->phy_clkgate_delay_us + 50); 1307 usb_phy_set_suspend(ci->usb_phy, 1); 1308 ci->in_lpm = true; 1309 enable_irq(ci->irq); 1310 } 1311 1312 /* 1313 * Handle the wakeup interrupt triggered by extcon connector 1314 * We need to call ci_irq again for extcon since the first 1315 * interrupt (wakeup int) only let the controller be out of 1316 * low power mode, but not handle any interrupts. 1317 */ 1318 static void ci_extcon_wakeup_int(struct ci_hdrc *ci) 1319 { 1320 struct ci_hdrc_cable *cable_id, *cable_vbus; 1321 u32 otgsc = hw_read_otgsc(ci, ~0); 1322 1323 cable_id = &ci->platdata->id_extcon; 1324 cable_vbus = &ci->platdata->vbus_extcon; 1325 1326 if ((!IS_ERR(cable_id->edev) || ci->role_switch) 1327 && ci->is_otg && 1328 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) 1329 ci_irq(ci); 1330 1331 if ((!IS_ERR(cable_vbus->edev) || ci->role_switch) 1332 && ci->is_otg && 1333 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) 1334 ci_irq(ci); 1335 } 1336 1337 static int ci_controller_resume(struct device *dev) 1338 { 1339 struct ci_hdrc *ci = dev_get_drvdata(dev); 1340 int ret; 1341 1342 dev_dbg(dev, "at %s\n", __func__); 1343 1344 if (!ci->in_lpm) { 1345 WARN_ON(1); 1346 return 0; 1347 } 1348 1349 ci_hdrc_enter_lpm(ci, false); 1350 1351 ret = ci_ulpi_resume(ci); 1352 if (ret) 1353 return ret; 1354 1355 if (ci->usb_phy) { 1356 usb_phy_set_suspend(ci->usb_phy, 0); 1357 usb_phy_set_wakeup(ci->usb_phy, false); 1358 hw_wait_phy_stable(); 1359 } 1360 1361 ci->in_lpm = false; 1362 if (ci->wakeup_int) { 1363 ci->wakeup_int = false; 1364 pm_runtime_put_autosuspend(ci->dev); 1365 enable_irq(ci->irq); 1366 if (ci_otg_is_fsm_mode(ci)) 1367 ci_otg_fsm_wakeup_by_srp(ci); 1368 ci_extcon_wakeup_int(ci); 1369 } 1370 1371 return 0; 1372 } 1373 1374 #ifdef CONFIG_PM_SLEEP 1375 static int ci_suspend(struct device *dev) 1376 { 1377 struct ci_hdrc *ci = dev_get_drvdata(dev); 1378 1379 if (ci->wq) 1380 flush_workqueue(ci->wq); 1381 /* 1382 * Controller needs to be active during suspend, otherwise the core 1383 * may run resume when the parent is at suspend if other driver's 1384 * suspend fails, it occurs before parent's suspend has not started, 1385 * but the core suspend has finished. 1386 */ 1387 if (ci->in_lpm) 1388 pm_runtime_resume(dev); 1389 1390 if (ci->in_lpm) { 1391 WARN_ON(1); 1392 return 0; 1393 } 1394 1395 /* Extra routine per role before system suspend */ 1396 if (ci->role != CI_ROLE_END && ci_role(ci)->suspend) 1397 ci_role(ci)->suspend(ci); 1398 1399 if (device_may_wakeup(dev)) { 1400 if (ci_otg_is_fsm_mode(ci)) 1401 ci_otg_fsm_suspend_for_srp(ci); 1402 1403 usb_phy_set_wakeup(ci->usb_phy, true); 1404 enable_irq_wake(ci->irq); 1405 } 1406 1407 ci_controller_suspend(ci); 1408 1409 return 0; 1410 } 1411 1412 static int ci_resume(struct device *dev) 1413 { 1414 struct ci_hdrc *ci = dev_get_drvdata(dev); 1415 bool power_lost; 1416 int ret; 1417 1418 /* Since ASYNCLISTADDR (host mode) and ENDPTLISTADDR (device 1419 * mode) share the same register address. We can check if 1420 * controller resume from power lost based on this address 1421 * due to this register will be reset after power lost. 1422 */ 1423 power_lost = !hw_read(ci, OP_ENDPTLISTADDR, ~0); 1424 1425 if (device_may_wakeup(dev)) 1426 disable_irq_wake(ci->irq); 1427 1428 ret = ci_controller_resume(dev); 1429 if (ret) 1430 return ret; 1431 1432 if (power_lost) { 1433 /* shutdown and re-init for phy */ 1434 ci_usb_phy_exit(ci); 1435 ci_usb_phy_init(ci); 1436 } 1437 1438 /* Extra routine per role after system resume */ 1439 if (ci->role != CI_ROLE_END && ci_role(ci)->resume) 1440 ci_role(ci)->resume(ci, power_lost); 1441 1442 if (power_lost) 1443 queue_work(system_freezable_wq, &ci->power_lost_work); 1444 1445 if (ci->supports_runtime_pm) { 1446 pm_runtime_disable(dev); 1447 pm_runtime_set_active(dev); 1448 pm_runtime_enable(dev); 1449 } 1450 1451 return ret; 1452 } 1453 #endif /* CONFIG_PM_SLEEP */ 1454 1455 static int ci_runtime_suspend(struct device *dev) 1456 { 1457 struct ci_hdrc *ci = dev_get_drvdata(dev); 1458 1459 dev_dbg(dev, "at %s\n", __func__); 1460 1461 if (ci->in_lpm) { 1462 WARN_ON(1); 1463 return 0; 1464 } 1465 1466 if (ci_otg_is_fsm_mode(ci)) 1467 ci_otg_fsm_suspend_for_srp(ci); 1468 1469 usb_phy_set_wakeup(ci->usb_phy, true); 1470 ci_controller_suspend(ci); 1471 1472 return 0; 1473 } 1474 1475 static int ci_runtime_resume(struct device *dev) 1476 { 1477 return ci_controller_resume(dev); 1478 } 1479 1480 #endif /* CONFIG_PM */ 1481 static const struct dev_pm_ops ci_pm_ops = { 1482 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) 1483 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) 1484 }; 1485 1486 static struct platform_driver ci_hdrc_driver = { 1487 .probe = ci_hdrc_probe, 1488 .remove = ci_hdrc_remove, 1489 .driver = { 1490 .name = "ci_hdrc", 1491 .pm = &ci_pm_ops, 1492 .dev_groups = ci_groups, 1493 }, 1494 }; 1495 1496 static int __init ci_hdrc_platform_register(void) 1497 { 1498 ci_hdrc_host_driver_init(); 1499 return platform_driver_register(&ci_hdrc_driver); 1500 } 1501 module_init(ci_hdrc_platform_register); 1502 1503 static void __exit ci_hdrc_platform_unregister(void) 1504 { 1505 platform_driver_unregister(&ci_hdrc_driver); 1506 } 1507 module_exit(ci_hdrc_platform_unregister); 1508 1509 MODULE_ALIAS("platform:ci_hdrc"); 1510 MODULE_LICENSE("GPL v2"); 1511 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); 1512 MODULE_DESCRIPTION("ChipIdea HDRC Driver"); 1513