1 /*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41 #include <sys/cdefs.h>
42 #include "opt_cpu.h"
43
44 #include <sys/param.h>
45 #include <sys/bus.h>
46 #include <sys/cpu.h>
47 #include <sys/eventhandler.h>
48 #include <sys/limits.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/sysctl.h>
52 #include <sys/power.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <machine/asmacros.h>
58 #include <machine/clock.h>
59 #include <machine/cputypes.h>
60 #include <machine/frame.h>
61 #include <machine/intr_machdep.h>
62 #include <machine/md_var.h>
63 #include <machine/segments.h>
64 #include <machine/specialreg.h>
65
66 #include <amd64/vmm/intel/vmx_controls.h>
67 #include <x86/isa/icu.h>
68 #include <x86/vmware.h>
69
70 #ifdef XENHVM
71 #include <xen/xen-os.h>
72 #endif
73
74 #ifdef __i386__
75 #define IDENTBLUE_CYRIX486 0
76 #define IDENTBLUE_IBMCPU 1
77 #define IDENTBLUE_CYRIXM2 2
78
79 static void identifycyrix(void);
80 static void print_transmeta_info(void);
81 #endif
82 static u_int find_cpu_vendor_id(void);
83 static void print_AMD_info(void);
84 static void print_INTEL_info(void);
85 static void print_INTEL_TLB(u_int data);
86 static void print_hypervisor_info(void);
87 static void print_svm_info(void);
88 static void print_via_padlock_info(void);
89 static void print_vmx_info(void);
90
91 #ifdef __i386__
92 int cpu; /* Are we 386, 386sx, 486, etc? */
93 int cpu_class;
94 #endif
95 u_int cpu_feature; /* Feature flags */
96 u_int cpu_feature2; /* Feature flags */
97 u_int amd_feature; /* AMD feature flags */
98 u_int amd_feature2; /* AMD feature flags */
99 u_int amd_rascap; /* AMD RAS capabilities */
100 u_int amd_pminfo; /* AMD advanced power management info */
101 u_int amd_extended_feature_extensions;
102 u_int via_feature_rng; /* VIA RNG features */
103 u_int via_feature_xcrypt; /* VIA ACE features */
104 u_int cpu_high; /* Highest arg to CPUID */
105 u_int cpu_exthigh; /* Highest arg to extended CPUID */
106 u_int cpu_id; /* Stepping ID */
107 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
108 u_int cpu_procinfo2; /* Multicore info */
109 u_int cpu_procinfo3;
110 char cpu_vendor[20]; /* CPU Origin code */
111 u_int cpu_vendor_id; /* CPU vendor ID */
112 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
113 u_int cpu_clflush_line_size = 32;
114 u_int cpu_stdext_feature; /* %ebx */
115 u_int cpu_stdext_feature2; /* %ecx */
116 u_int cpu_stdext_feature3; /* %edx */
117 uint64_t cpu_ia32_arch_caps;
118 u_int cpu_max_ext_state_size;
119 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
120 u_int cpu_mon_mwait_edx; /* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */
121 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
122 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
123 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
124 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */
125 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */
126 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */
127 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */
128 const char machine[] = MACHINE;
129
130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
131 &via_feature_rng, 0,
132 "VIA RNG feature available in CPU");
133 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
134 &via_feature_xcrypt, 0,
135 "VIA xcrypt feature available in CPU");
136
137 #ifdef __amd64__
138 #ifdef SCTL_MASK32
139 extern int adaptive_machine_arch;
140 #endif
141
142 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)143 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
144 {
145 #ifdef SCTL_MASK32
146 static const char machine32[] = "i386";
147 #endif
148 int error;
149
150 #ifdef SCTL_MASK32
151 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
152 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
153 else
154 #endif
155 error = SYSCTL_OUT(req, machine, sizeof(machine));
156 return (error);
157
158 }
159 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
160 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
161 #else
162 SYSCTL_CONST_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD,
163 machine, "Machine class");
164 #endif
165
166 char cpu_model[128];
167 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
168 cpu_model, 0, "Machine model");
169
170 static int hw_clockrate;
171 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
172 &hw_clockrate, 0, "CPU instruction clock rate");
173
174 u_int hv_base;
175 u_int hv_high;
176 char hv_vendor[16];
177 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD, hv_vendor,
178 0, "Hypervisor vendor");
179
180 static eventhandler_tag tsc_post_tag;
181
182 static char cpu_brand[48];
183
184 #ifdef __i386__
185 #define MAX_BRAND_INDEX 8
186
187 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
188 NULL, /* No brand */
189 "Intel Celeron",
190 "Intel Pentium III",
191 "Intel Pentium III Xeon",
192 NULL,
193 NULL,
194 NULL,
195 NULL,
196 "Intel Pentium 4"
197 };
198
199 static struct {
200 char *cpu_name;
201 int cpu_class;
202 } cpus[] = {
203 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
204 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
205 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
206 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
207 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
208 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
209 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
210 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
211 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
212 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
213 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
214 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
215 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
216 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
217 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
218 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
219 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
220 };
221 #endif
222
223 static struct {
224 char *vendor;
225 u_int vendor_id;
226 } cpu_vendors[] = {
227 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
228 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
229 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */
230 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
231 #ifdef __i386__
232 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
233 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
234 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
235 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
236 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
237 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
238 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
239 #if 0
240 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
241 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
242 #endif
243 #endif
244 };
245
246 void
printcpuinfo(void)247 printcpuinfo(void)
248 {
249 u_int regs[4], i;
250 char *brand;
251
252 printf("CPU: ");
253 #ifdef __i386__
254 cpu_class = cpus[cpu].cpu_class;
255 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
256 #else
257 strncpy(cpu_model, "Hammer", sizeof (cpu_model));
258 #endif
259
260 /* Check for extended CPUID information and a processor name. */
261 if (cpu_exthigh >= 0x80000004) {
262 brand = cpu_brand;
263 for (i = 0x80000002; i < 0x80000005; i++) {
264 do_cpuid(i, regs);
265 memcpy(brand, regs, sizeof(regs));
266 brand += sizeof(regs);
267 }
268 }
269
270 switch (cpu_vendor_id) {
271 case CPU_VENDOR_INTEL:
272 #ifdef __i386__
273 if ((cpu_id & 0xf00) > 0x300) {
274 u_int brand_index;
275
276 cpu_model[0] = '\0';
277
278 switch (cpu_id & 0x3000) {
279 case 0x1000:
280 strcpy(cpu_model, "Overdrive ");
281 break;
282 case 0x2000:
283 strcpy(cpu_model, "Dual ");
284 break;
285 }
286
287 switch (cpu_id & 0xf00) {
288 case 0x400:
289 strcat(cpu_model, "i486 ");
290 /* Check the particular flavor of 486 */
291 switch (cpu_id & 0xf0) {
292 case 0x00:
293 case 0x10:
294 strcat(cpu_model, "DX");
295 break;
296 case 0x20:
297 strcat(cpu_model, "SX");
298 break;
299 case 0x30:
300 strcat(cpu_model, "DX2");
301 break;
302 case 0x40:
303 strcat(cpu_model, "SL");
304 break;
305 case 0x50:
306 strcat(cpu_model, "SX2");
307 break;
308 case 0x70:
309 strcat(cpu_model,
310 "DX2 Write-Back Enhanced");
311 break;
312 case 0x80:
313 strcat(cpu_model, "DX4");
314 break;
315 }
316 break;
317 case 0x500:
318 /* Check the particular flavor of 586 */
319 strcat(cpu_model, "Pentium");
320 switch (cpu_id & 0xf0) {
321 case 0x00:
322 strcat(cpu_model, " A-step");
323 break;
324 case 0x10:
325 strcat(cpu_model, "/P5");
326 break;
327 case 0x20:
328 strcat(cpu_model, "/P54C");
329 break;
330 case 0x30:
331 strcat(cpu_model, "/P24T");
332 break;
333 case 0x40:
334 strcat(cpu_model, "/P55C");
335 break;
336 case 0x70:
337 strcat(cpu_model, "/P54C");
338 break;
339 case 0x80:
340 strcat(cpu_model, "/P55C (quarter-micron)");
341 break;
342 default:
343 /* nothing */
344 break;
345 }
346 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
347 /*
348 * XXX - If/when Intel fixes the bug, this
349 * should also check the version of the
350 * CPU, not just that it's a Pentium.
351 */
352 has_f00f_bug = 1;
353 #endif
354 break;
355 case 0x600:
356 /* Check the particular flavor of 686 */
357 switch (cpu_id & 0xf0) {
358 case 0x00:
359 strcat(cpu_model, "Pentium Pro A-step");
360 break;
361 case 0x10:
362 strcat(cpu_model, "Pentium Pro");
363 break;
364 case 0x30:
365 case 0x50:
366 case 0x60:
367 strcat(cpu_model,
368 "Pentium II/Pentium II Xeon/Celeron");
369 cpu = CPU_PII;
370 break;
371 case 0x70:
372 case 0x80:
373 case 0xa0:
374 case 0xb0:
375 strcat(cpu_model,
376 "Pentium III/Pentium III Xeon/Celeron");
377 cpu = CPU_PIII;
378 break;
379 default:
380 strcat(cpu_model, "Unknown 80686");
381 break;
382 }
383 break;
384 case 0xf00:
385 strcat(cpu_model, "Pentium 4");
386 cpu = CPU_P4;
387 break;
388 default:
389 strcat(cpu_model, "unknown");
390 break;
391 }
392
393 /*
394 * If we didn't get a brand name from the extended
395 * CPUID, try to look it up in the brand table.
396 */
397 if (cpu_high > 0 && *cpu_brand == '\0') {
398 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
399 if (brand_index <= MAX_BRAND_INDEX &&
400 cpu_brandtable[brand_index] != NULL)
401 strcpy(cpu_brand,
402 cpu_brandtable[brand_index]);
403 }
404 }
405 #else
406 /* Please make up your mind folks! */
407 strcat(cpu_model, "EM64T");
408 #endif
409 break;
410 case CPU_VENDOR_AMD:
411 /*
412 * Values taken from AMD Processor Recognition
413 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
414 * (also describes ``Features'' encodings.
415 */
416 strcpy(cpu_model, "AMD ");
417 #ifdef __i386__
418 switch (cpu_id & 0xFF0) {
419 case 0x410:
420 strcat(cpu_model, "Standard Am486DX");
421 break;
422 case 0x430:
423 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
424 break;
425 case 0x470:
426 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
427 break;
428 case 0x480:
429 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
430 break;
431 case 0x490:
432 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
433 break;
434 case 0x4E0:
435 strcat(cpu_model, "Am5x86 Write-Through");
436 break;
437 case 0x4F0:
438 strcat(cpu_model, "Am5x86 Write-Back");
439 break;
440 case 0x500:
441 strcat(cpu_model, "K5 model 0");
442 break;
443 case 0x510:
444 strcat(cpu_model, "K5 model 1");
445 break;
446 case 0x520:
447 strcat(cpu_model, "K5 PR166 (model 2)");
448 break;
449 case 0x530:
450 strcat(cpu_model, "K5 PR200 (model 3)");
451 break;
452 case 0x560:
453 strcat(cpu_model, "K6");
454 break;
455 case 0x570:
456 strcat(cpu_model, "K6 266 (model 1)");
457 break;
458 case 0x580:
459 strcat(cpu_model, "K6-2");
460 break;
461 case 0x590:
462 strcat(cpu_model, "K6-III");
463 break;
464 case 0x5a0:
465 strcat(cpu_model, "Geode LX");
466 break;
467 default:
468 strcat(cpu_model, "Unknown");
469 break;
470 }
471 #else
472 if ((cpu_id & 0xf00) == 0xf00)
473 strcat(cpu_model, "AMD64 Processor");
474 else
475 strcat(cpu_model, "Unknown");
476 #endif
477 break;
478 #ifdef __i386__
479 case CPU_VENDOR_CYRIX:
480 strcpy(cpu_model, "Cyrix ");
481 switch (cpu_id & 0xff0) {
482 case 0x440:
483 strcat(cpu_model, "MediaGX");
484 break;
485 case 0x520:
486 strcat(cpu_model, "6x86");
487 break;
488 case 0x540:
489 cpu_class = CPUCLASS_586;
490 strcat(cpu_model, "GXm");
491 break;
492 case 0x600:
493 strcat(cpu_model, "6x86MX");
494 break;
495 default:
496 /*
497 * Even though CPU supports the cpuid
498 * instruction, it can be disabled.
499 * Therefore, this routine supports all Cyrix
500 * CPUs.
501 */
502 switch (cyrix_did & 0xf0) {
503 case 0x00:
504 switch (cyrix_did & 0x0f) {
505 case 0x00:
506 strcat(cpu_model, "486SLC");
507 break;
508 case 0x01:
509 strcat(cpu_model, "486DLC");
510 break;
511 case 0x02:
512 strcat(cpu_model, "486SLC2");
513 break;
514 case 0x03:
515 strcat(cpu_model, "486DLC2");
516 break;
517 case 0x04:
518 strcat(cpu_model, "486SRx");
519 break;
520 case 0x05:
521 strcat(cpu_model, "486DRx");
522 break;
523 case 0x06:
524 strcat(cpu_model, "486SRx2");
525 break;
526 case 0x07:
527 strcat(cpu_model, "486DRx2");
528 break;
529 case 0x08:
530 strcat(cpu_model, "486SRu");
531 break;
532 case 0x09:
533 strcat(cpu_model, "486DRu");
534 break;
535 case 0x0a:
536 strcat(cpu_model, "486SRu2");
537 break;
538 case 0x0b:
539 strcat(cpu_model, "486DRu2");
540 break;
541 default:
542 strcat(cpu_model, "Unknown");
543 break;
544 }
545 break;
546 case 0x10:
547 switch (cyrix_did & 0x0f) {
548 case 0x00:
549 strcat(cpu_model, "486S");
550 break;
551 case 0x01:
552 strcat(cpu_model, "486S2");
553 break;
554 case 0x02:
555 strcat(cpu_model, "486Se");
556 break;
557 case 0x03:
558 strcat(cpu_model, "486S2e");
559 break;
560 case 0x0a:
561 strcat(cpu_model, "486DX");
562 break;
563 case 0x0b:
564 strcat(cpu_model, "486DX2");
565 break;
566 case 0x0f:
567 strcat(cpu_model, "486DX4");
568 break;
569 default:
570 strcat(cpu_model, "Unknown");
571 break;
572 }
573 break;
574 case 0x20:
575 if ((cyrix_did & 0x0f) < 8)
576 strcat(cpu_model, "6x86"); /* Where did you get it? */
577 else
578 strcat(cpu_model, "5x86");
579 break;
580 case 0x30:
581 strcat(cpu_model, "6x86");
582 break;
583 case 0x40:
584 if ((cyrix_did & 0xf000) == 0x3000) {
585 cpu_class = CPUCLASS_586;
586 strcat(cpu_model, "GXm");
587 } else
588 strcat(cpu_model, "MediaGX");
589 break;
590 case 0x50:
591 strcat(cpu_model, "6x86MX");
592 break;
593 case 0xf0:
594 switch (cyrix_did & 0x0f) {
595 case 0x0d:
596 strcat(cpu_model, "Overdrive CPU");
597 break;
598 case 0x0e:
599 strcpy(cpu_model, "Texas Instruments 486SXL");
600 break;
601 case 0x0f:
602 strcat(cpu_model, "486SLC/DLC");
603 break;
604 default:
605 strcat(cpu_model, "Unknown");
606 break;
607 }
608 break;
609 default:
610 strcat(cpu_model, "Unknown");
611 break;
612 }
613 break;
614 }
615 break;
616 case CPU_VENDOR_RISE:
617 strcpy(cpu_model, "Rise ");
618 switch (cpu_id & 0xff0) {
619 case 0x500: /* 6401 and 6441 (Kirin) */
620 case 0x520: /* 6510 (Lynx) */
621 strcat(cpu_model, "mP6");
622 break;
623 default:
624 strcat(cpu_model, "Unknown");
625 }
626 break;
627 #endif
628 case CPU_VENDOR_CENTAUR:
629 #ifdef __i386__
630 switch (cpu_id & 0xff0) {
631 case 0x540:
632 strcpy(cpu_model, "IDT WinChip C6");
633 break;
634 case 0x580:
635 strcpy(cpu_model, "IDT WinChip 2");
636 break;
637 case 0x590:
638 strcpy(cpu_model, "IDT WinChip 3");
639 break;
640 case 0x660:
641 strcpy(cpu_model, "VIA C3 Samuel");
642 break;
643 case 0x670:
644 if (cpu_id & 0x8)
645 strcpy(cpu_model, "VIA C3 Ezra");
646 else
647 strcpy(cpu_model, "VIA C3 Samuel 2");
648 break;
649 case 0x680:
650 strcpy(cpu_model, "VIA C3 Ezra-T");
651 break;
652 case 0x690:
653 strcpy(cpu_model, "VIA C3 Nehemiah");
654 break;
655 case 0x6a0:
656 case 0x6d0:
657 strcpy(cpu_model, "VIA C7 Esther");
658 break;
659 case 0x6f0:
660 strcpy(cpu_model, "VIA Nano");
661 break;
662 default:
663 strcpy(cpu_model, "VIA/IDT Unknown");
664 }
665 #else
666 strcpy(cpu_model, "VIA ");
667 if ((cpu_id & 0xff0) == 0x6f0)
668 strcat(cpu_model, "Nano Processor");
669 else
670 strcat(cpu_model, "Unknown");
671 #endif
672 break;
673 #ifdef __i386__
674 case CPU_VENDOR_IBM:
675 strcpy(cpu_model, "Blue Lightning CPU");
676 break;
677 case CPU_VENDOR_NSC:
678 switch (cpu_id & 0xff0) {
679 case 0x540:
680 strcpy(cpu_model, "Geode SC1100");
681 cpu = CPU_GEODE1100;
682 break;
683 default:
684 strcpy(cpu_model, "Geode/NSC unknown");
685 break;
686 }
687 break;
688 #endif
689 case CPU_VENDOR_HYGON:
690 strcpy(cpu_model, "Hygon ");
691 #ifdef __i386__
692 strcat(cpu_model, "Unknown");
693 #else
694 if ((cpu_id & 0xf00) == 0xf00)
695 strcat(cpu_model, "AMD64 Processor");
696 else
697 strcat(cpu_model, "Unknown");
698 #endif
699 break;
700
701 default:
702 strcat(cpu_model, "Unknown");
703 break;
704 }
705
706 /*
707 * Replace cpu_model with cpu_brand minus leading spaces if
708 * we have one.
709 */
710 brand = cpu_brand;
711 while (*brand == ' ')
712 ++brand;
713 if (*brand != '\0')
714 strcpy(cpu_model, brand);
715
716 printf("%s (", cpu_model);
717 if (tsc_freq != 0) {
718 hw_clockrate = (tsc_freq + 5000) / 1000000;
719 printf("%jd.%02d-MHz ",
720 (intmax_t)(tsc_freq + 4999) / 1000000,
721 (u_int)((tsc_freq + 4999) / 10000) % 100);
722 }
723 #ifdef __i386__
724 switch(cpu_class) {
725 case CPUCLASS_286:
726 printf("286");
727 break;
728 case CPUCLASS_386:
729 printf("386");
730 break;
731 #if defined(I486_CPU)
732 case CPUCLASS_486:
733 printf("486");
734 break;
735 #endif
736 #if defined(I586_CPU)
737 case CPUCLASS_586:
738 printf("586");
739 break;
740 #endif
741 #if defined(I686_CPU)
742 case CPUCLASS_686:
743 printf("686");
744 break;
745 #endif
746 default:
747 printf("Unknown"); /* will panic below... */
748 }
749 #else
750 printf("K8");
751 #endif
752 printf("-class CPU)\n");
753 if (*cpu_vendor)
754 printf(" Origin=\"%s\"", cpu_vendor);
755 if (cpu_id)
756 printf(" Id=0x%x", cpu_id);
757
758 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
759 cpu_vendor_id == CPU_VENDOR_AMD ||
760 cpu_vendor_id == CPU_VENDOR_HYGON ||
761 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
762 #ifdef __i386__
763 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
764 cpu_vendor_id == CPU_VENDOR_RISE ||
765 cpu_vendor_id == CPU_VENDOR_NSC ||
766 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
767 #endif
768 0) {
769 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id));
770 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id));
771 printf(" Stepping=%u", cpu_id & CPUID_STEPPING);
772 #ifdef __i386__
773 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
774 printf("\n DIR=0x%04x", cyrix_did);
775 #endif
776
777 /*
778 * AMD CPUID Specification
779 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
780 *
781 * Intel Processor Identification and CPUID Instruction
782 * http://www.intel.com/assets/pdf/appnote/241618.pdf
783 */
784 if (cpu_high > 0) {
785 /*
786 * Here we should probably set up flags indicating
787 * whether or not various features are available.
788 * The interesting ones are probably VME, PSE, PAE,
789 * and PGE. The code already assumes without bothering
790 * to check that all CPUs >= Pentium have a TSC and
791 * MSRs.
792 */
793 printf("\n Features=0x%b", cpu_feature,
794 "\020"
795 "\001FPU" /* Integral FPU */
796 "\002VME" /* Extended VM86 mode support */
797 "\003DE" /* Debugging Extensions (CR4.DE) */
798 "\004PSE" /* 4MByte page tables */
799 "\005TSC" /* Timestamp counter */
800 "\006MSR" /* Machine specific registers */
801 "\007PAE" /* Physical address extension */
802 "\010MCE" /* Machine Check support */
803 "\011CX8" /* CMPEXCH8 instruction */
804 "\012APIC" /* SMP local APIC */
805 "\013oldMTRR" /* Previous implementation of MTRR */
806 "\014SEP" /* Fast System Call */
807 "\015MTRR" /* Memory Type Range Registers */
808 "\016PGE" /* PG_G (global bit) support */
809 "\017MCA" /* Machine Check Architecture */
810 "\020CMOV" /* CMOV instruction */
811 "\021PAT" /* Page attributes table */
812 "\022PSE36" /* 36 bit address space support */
813 "\023PN" /* Processor Serial number */
814 "\024CLFLUSH" /* Has the CLFLUSH instruction */
815 "\025<b20>"
816 "\026DTS" /* Debug Trace Store */
817 "\027ACPI" /* ACPI support */
818 "\030MMX" /* MMX instructions */
819 "\031FXSR" /* FXSAVE/FXRSTOR */
820 "\032SSE" /* Streaming SIMD Extensions */
821 "\033SSE2" /* Streaming SIMD Extensions #2 */
822 "\034SS" /* Self snoop */
823 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
824 "\036TM" /* Thermal Monitor clock slowdown */
825 "\037IA64" /* CPU can execute IA64 instructions */
826 "\040PBE" /* Pending Break Enable */
827 );
828
829 if (cpu_feature2 != 0) {
830 printf("\n Features2=0x%b", cpu_feature2,
831 "\020"
832 "\001SSE3" /* SSE3 */
833 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
834 "\003DTES64" /* 64-bit Debug Trace */
835 "\004MON" /* MONITOR/MWAIT Instructions */
836 "\005DS_CPL" /* CPL Qualified Debug Store */
837 "\006VMX" /* Virtual Machine Extensions */
838 "\007SMX" /* Safer Mode Extensions */
839 "\010EST" /* Enhanced SpeedStep */
840 "\011TM2" /* Thermal Monitor 2 */
841 "\012SSSE3" /* SSSE3 */
842 "\013CNXT-ID" /* L1 context ID available */
843 "\014SDBG" /* IA32 silicon debug */
844 "\015FMA" /* Fused Multiply Add */
845 "\016CX16" /* CMPXCHG16B Instruction */
846 "\017xTPR" /* Send Task Priority Messages*/
847 "\020PDCM" /* Perf/Debug Capability MSR */
848 "\021<b16>"
849 "\022PCID" /* Process-context Identifiers*/
850 "\023DCA" /* Direct Cache Access */
851 "\024SSE4.1" /* SSE 4.1 */
852 "\025SSE4.2" /* SSE 4.2 */
853 "\026x2APIC" /* xAPIC Extensions */
854 "\027MOVBE" /* MOVBE Instruction */
855 "\030POPCNT" /* POPCNT Instruction */
856 "\031TSCDLT" /* TSC-Deadline Timer */
857 "\032AESNI" /* AES Crypto */
858 "\033XSAVE" /* XSAVE/XRSTOR States */
859 "\034OSXSAVE" /* OS-Enabled State Management*/
860 "\035AVX" /* Advanced Vector Extensions */
861 "\036F16C" /* Half-precision conversions */
862 "\037RDRAND" /* RDRAND Instruction */
863 "\040HV" /* Hypervisor */
864 );
865 }
866
867 if (amd_feature != 0) {
868 printf("\n AMD Features=0x%b", amd_feature,
869 "\020" /* in hex */
870 "\001<s0>" /* Same */
871 "\002<s1>" /* Same */
872 "\003<s2>" /* Same */
873 "\004<s3>" /* Same */
874 "\005<s4>" /* Same */
875 "\006<s5>" /* Same */
876 "\007<s6>" /* Same */
877 "\010<s7>" /* Same */
878 "\011<s8>" /* Same */
879 "\012<s9>" /* Same */
880 "\013<b10>" /* Undefined */
881 "\014SYSCALL" /* Have SYSCALL/SYSRET */
882 "\015<s12>" /* Same */
883 "\016<s13>" /* Same */
884 "\017<s14>" /* Same */
885 "\020<s15>" /* Same */
886 "\021<s16>" /* Same */
887 "\022<s17>" /* Same */
888 "\023<b18>" /* Reserved, unknown */
889 "\024MP" /* Multiprocessor Capable */
890 "\025NX" /* Has EFER.NXE, NX */
891 "\026<b21>" /* Undefined */
892 "\027MMX+" /* AMD MMX Extensions */
893 "\030<s23>" /* Same */
894 "\031<s24>" /* Same */
895 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
896 "\033Page1GB" /* 1-GB large page support */
897 "\034RDTSCP" /* RDTSCP */
898 "\035<b28>" /* Undefined */
899 "\036LM" /* 64 bit long mode */
900 "\0373DNow!+" /* AMD 3DNow! Extensions */
901 "\0403DNow!" /* AMD 3DNow! */
902 );
903 }
904
905 if (amd_feature2 != 0) {
906 printf("\n AMD Features2=0x%b", amd_feature2,
907 "\020"
908 "\001LAHF" /* LAHF/SAHF in long mode */
909 "\002CMP" /* CMP legacy */
910 "\003SVM" /* Secure Virtual Mode */
911 "\004ExtAPIC" /* Extended APIC register */
912 "\005CR8" /* CR8 in legacy mode */
913 "\006ABM" /* LZCNT instruction */
914 "\007SSE4A" /* SSE4A */
915 "\010MAS" /* Misaligned SSE mode */
916 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
917 "\012OSVW" /* OS visible workaround */
918 "\013IBS" /* Instruction based sampling */
919 "\014XOP" /* XOP extended instructions */
920 "\015SKINIT" /* SKINIT/STGI */
921 "\016WDT" /* Watchdog timer */
922 "\017<b14>"
923 "\020LWP" /* Lightweight Profiling */
924 "\021FMA4" /* 4-operand FMA instructions */
925 "\022TCE" /* Translation Cache Extension */
926 "\023<b18>"
927 "\024NodeId" /* NodeId MSR support */
928 "\025<b20>"
929 "\026TBM" /* Trailing Bit Manipulation */
930 "\027Topology" /* Topology Extensions */
931 "\030PCXC" /* Core perf count */
932 "\031PNXC" /* NB perf count */
933 "\032<b25>"
934 "\033DBE" /* Data Breakpoint extension */
935 "\034PTSC" /* Performance TSC */
936 "\035PL2I" /* L2I perf count */
937 "\036MWAITX" /* MONITORX/MWAITX instructions */
938 "\037ADMSKX" /* Address mask extension */
939 "\040<b31>"
940 );
941 }
942
943 if (cpu_stdext_feature != 0) {
944 printf("\n Structured Extended Features=0x%b",
945 cpu_stdext_feature,
946 "\020"
947 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
948 "\001FSGSBASE"
949 "\002TSCADJ"
950 "\003SGX"
951 /* Bit Manipulation Instructions */
952 "\004BMI1"
953 /* Hardware Lock Elision */
954 "\005HLE"
955 /* Advanced Vector Instructions 2 */
956 "\006AVX2"
957 /* FDP_EXCPTN_ONLY */
958 "\007FDPEXC"
959 /* Supervisor Mode Execution Prot. */
960 "\010SMEP"
961 /* Bit Manipulation Instructions */
962 "\011BMI2"
963 "\012ERMS"
964 /* Invalidate Processor Context ID */
965 "\013INVPCID"
966 /* Restricted Transactional Memory */
967 "\014RTM"
968 "\015PQM"
969 "\016NFPUSG"
970 /* Intel Memory Protection Extensions */
971 "\017MPX"
972 "\020PQE"
973 /* AVX512 Foundation */
974 "\021AVX512F"
975 "\022AVX512DQ"
976 /* Enhanced NRBG */
977 "\023RDSEED"
978 /* ADCX + ADOX */
979 "\024ADX"
980 /* Supervisor Mode Access Prevention */
981 "\025SMAP"
982 "\026AVX512IFMA"
983 /* Formerly PCOMMIT */
984 "\027<b22>"
985 "\030CLFLUSHOPT"
986 "\031CLWB"
987 "\032PROCTRACE"
988 "\033AVX512PF"
989 "\034AVX512ER"
990 "\035AVX512CD"
991 "\036SHA"
992 "\037AVX512BW"
993 "\040AVX512VL"
994 );
995 }
996
997 if (cpu_stdext_feature2 != 0) {
998 printf("\n Structured Extended Features2=0x%b",
999 cpu_stdext_feature2,
1000 "\020"
1001 "\001PREFETCHWT1"
1002 "\002AVX512VBMI"
1003 "\003UMIP"
1004 "\004PKU"
1005 "\005OSPKE"
1006 "\006WAITPKG"
1007 "\007AVX512VBMI2"
1008 "\011GFNI"
1009 "\012VAES"
1010 "\013VPCLMULQDQ"
1011 "\014AVX512VNNI"
1012 "\015AVX512BITALG"
1013 "\016TME"
1014 "\017AVX512VPOPCNTDQ"
1015 "\021LA57"
1016 "\027RDPID"
1017 "\032CLDEMOTE"
1018 "\034MOVDIRI"
1019 "\035MOVDIR64B"
1020 "\036ENQCMD"
1021 "\037SGXLC"
1022 );
1023 }
1024
1025 if (cpu_stdext_feature3 != 0) {
1026 printf("\n Structured Extended Features3=0x%b",
1027 cpu_stdext_feature3,
1028 "\020"
1029 "\003AVX512_4VNNIW"
1030 "\004AVX512_4FMAPS"
1031 "\005FSRM"
1032 "\011AVX512VP2INTERSECT"
1033 "\012MCUOPT"
1034 "\013MD_CLEAR"
1035 "\016TSXFA"
1036 "\023PCONFIG"
1037 "\025IBT"
1038 "\033IBPB"
1039 "\034STIBP"
1040 "\035L1DFL"
1041 "\036ARCH_CAP"
1042 "\037CORE_CAP"
1043 "\040SSBD"
1044 );
1045 }
1046
1047 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1048 cpuid_count(0xd, 0x1, regs);
1049 if (regs[0] != 0) {
1050 printf("\n XSAVE Features=0x%b",
1051 regs[0],
1052 "\020"
1053 "\001XSAVEOPT"
1054 "\002XSAVEC"
1055 "\003XINUSE"
1056 "\004XSAVES");
1057 }
1058 }
1059
1060 if (cpu_ia32_arch_caps != 0) {
1061 printf("\n IA32_ARCH_CAPS=0x%b",
1062 (u_int)cpu_ia32_arch_caps,
1063 "\020"
1064 "\001RDCL_NO"
1065 "\002IBRS_ALL"
1066 "\003RSBA"
1067 "\004SKIP_L1DFL_VME"
1068 "\005SSB_NO"
1069 "\006MDS_NO"
1070 "\010TSX_CTRL"
1071 "\011TAA_NO"
1072 );
1073 }
1074
1075 if (amd_extended_feature_extensions != 0) {
1076 u_int amd_fe_masked;
1077
1078 amd_fe_masked = amd_extended_feature_extensions;
1079 if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1080 amd_fe_masked &=
1081 ~(AMDFEID_IBRS_ALWAYSON |
1082 AMDFEID_PREFER_IBRS);
1083 if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1084 amd_fe_masked &=
1085 ~AMDFEID_STIBP_ALWAYSON;
1086
1087 printf("\n "
1088 "AMD Extended Feature Extensions ID EBX="
1089 "0x%b", amd_fe_masked,
1090 "\020"
1091 "\001CLZERO"
1092 "\002IRPerf"
1093 "\003XSaveErPtr"
1094 "\004INVLPGB"
1095 "\005RDPRU"
1096 "\007BE"
1097 "\011MCOMMIT"
1098 "\012WBNOINVD"
1099 "\015IBPB"
1100 "\016INT_WBINVD"
1101 "\017IBRS"
1102 "\020STIBP"
1103 "\021IBRS_ALWAYSON"
1104 "\022STIBP_ALWAYSON"
1105 "\023PREFER_IBRS"
1106 "\024SAMEMODE_IBRS"
1107 "\025NOLMSLE"
1108 "\026INVLPGBNEST"
1109 "\030PPIN"
1110 "\031SSBD"
1111 "\032VIRT_SSBD"
1112 "\033SSB_NO"
1113 "\034CPPC"
1114 "\035PSFD"
1115 "\036BTC_NO"
1116 "\037IBPB_RET"
1117 );
1118 }
1119
1120 if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1121 print_via_padlock_info();
1122
1123 if (cpu_feature2 & CPUID2_VMX)
1124 print_vmx_info();
1125
1126 if (amd_feature2 & AMDID2_SVM)
1127 print_svm_info();
1128
1129 if ((cpu_feature & CPUID_HTT) &&
1130 (cpu_vendor_id == CPU_VENDOR_AMD ||
1131 cpu_vendor_id == CPU_VENDOR_HYGON))
1132 cpu_feature &= ~CPUID_HTT;
1133
1134 /*
1135 * If this CPU supports P-state invariant TSC then
1136 * mention the capability.
1137 */
1138 if (tsc_is_invariant) {
1139 printf("\n TSC: P-state invariant");
1140 if (tsc_perf_stat)
1141 printf(", performance statistics");
1142 }
1143 }
1144 #ifdef __i386__
1145 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1146 printf(" DIR=0x%04x", cyrix_did);
1147 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
1148 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
1149 #ifndef CYRIX_CACHE_REALLY_WORKS
1150 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1151 printf("\n CPU cache: write-through mode");
1152 #endif
1153 #endif
1154 }
1155
1156 /* Avoid ugly blank lines: only print newline when we have to. */
1157 if (*cpu_vendor || cpu_id)
1158 printf("\n");
1159
1160 if (bootverbose) {
1161 if (cpu_vendor_id == CPU_VENDOR_AMD ||
1162 cpu_vendor_id == CPU_VENDOR_HYGON)
1163 print_AMD_info();
1164 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1165 print_INTEL_info();
1166 #ifdef __i386__
1167 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1168 print_transmeta_info();
1169 #endif
1170 }
1171
1172 print_hypervisor_info();
1173 }
1174
1175 #ifdef __i386__
1176 void
panicifcpuunsupported(void)1177 panicifcpuunsupported(void)
1178 {
1179
1180 #if !defined(lint)
1181 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1182 #error This kernel is not configured for one of the supported CPUs
1183 #endif
1184 #else /* lint */
1185 #endif /* lint */
1186 /*
1187 * Now that we have told the user what they have,
1188 * let them know if that machine type isn't configured.
1189 */
1190 switch (cpu_class) {
1191 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
1192 case CPUCLASS_386:
1193 #if !defined(I486_CPU)
1194 case CPUCLASS_486:
1195 #endif
1196 #if !defined(I586_CPU)
1197 case CPUCLASS_586:
1198 #endif
1199 #if !defined(I686_CPU)
1200 case CPUCLASS_686:
1201 #endif
1202 panic("CPU class not configured");
1203 default:
1204 break;
1205 }
1206 }
1207
1208 static volatile u_int trap_by_rdmsr;
1209
1210 /*
1211 * Special exception 6 handler.
1212 * The rdmsr instruction generates invalid opcodes fault on 486-class
1213 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
1214 * function identblue() when this handler is called. Stacked eip should
1215 * be advanced.
1216 */
1217 inthand_t bluetrap6;
1218 __asm
1219 (" \n\
1220 .text \n\
1221 .p2align 2,0x90 \n\
1222 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
1223 " __XSTRING(CNAME(bluetrap6)) ": \n\
1224 ss \n\
1225 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1226 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1227 iret \n\
1228 ");
1229
1230 /*
1231 * Special exception 13 handler.
1232 * Accessing non-existent MSR generates general protection fault.
1233 */
1234 inthand_t bluetrap13;
1235 __asm
1236 (" \n\
1237 .text \n\
1238 .p2align 2,0x90 \n\
1239 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
1240 " __XSTRING(CNAME(bluetrap13)) ": \n\
1241 ss \n\
1242 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
1243 popl %eax /* discard error code */ \n\
1244 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
1245 iret \n\
1246 ");
1247
1248 /*
1249 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1250 * support cpuid instruction. This function should be called after
1251 * loading interrupt descriptor table register.
1252 *
1253 * I don't like this method that handles fault, but I couldn't get
1254 * information for any other methods. Does blue giant know?
1255 */
1256 static int
identblue(void)1257 identblue(void)
1258 {
1259
1260 trap_by_rdmsr = 0;
1261
1262 /*
1263 * Cyrix 486-class CPU does not support rdmsr instruction.
1264 * The rdmsr instruction generates invalid opcode fault, and exception
1265 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
1266 * bluetrap6() set the magic number to trap_by_rdmsr.
1267 */
1268 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1269 GSEL(GCODE_SEL, SEL_KPL));
1270
1271 /*
1272 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1273 * In this case, rdmsr generates general protection fault, and
1274 * exception will be trapped by bluetrap13().
1275 */
1276 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1277 GSEL(GCODE_SEL, SEL_KPL));
1278
1279 rdmsr(0x1002); /* Cyrix CPU generates fault. */
1280
1281 if (trap_by_rdmsr == 0xa8c1d)
1282 return IDENTBLUE_CYRIX486;
1283 else if (trap_by_rdmsr == 0xa89c4)
1284 return IDENTBLUE_CYRIXM2;
1285 return IDENTBLUE_IBMCPU;
1286 }
1287
1288 /*
1289 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1290 *
1291 * F E D C B A 9 8 7 6 5 4 3 2 1 0
1292 * +-------+-------+---------------+
1293 * | SID | RID | Device ID |
1294 * | (DIR 1) | (DIR 0) |
1295 * +-------+-------+---------------+
1296 */
1297 static void
identifycyrix(void)1298 identifycyrix(void)
1299 {
1300 register_t saveintr;
1301 int ccr2_test = 0, dir_test = 0;
1302 u_char ccr2, ccr3;
1303
1304 saveintr = intr_disable();
1305
1306 ccr2 = read_cyrix_reg(CCR2);
1307 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1308 read_cyrix_reg(CCR2);
1309 if (read_cyrix_reg(CCR2) != ccr2)
1310 ccr2_test = 1;
1311 write_cyrix_reg(CCR2, ccr2);
1312
1313 ccr3 = read_cyrix_reg(CCR3);
1314 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1315 read_cyrix_reg(CCR3);
1316 if (read_cyrix_reg(CCR3) != ccr3)
1317 dir_test = 1; /* CPU supports DIRs. */
1318 write_cyrix_reg(CCR3, ccr3);
1319
1320 if (dir_test) {
1321 /* Device ID registers are available. */
1322 cyrix_did = read_cyrix_reg(DIR1) << 8;
1323 cyrix_did += read_cyrix_reg(DIR0);
1324 } else if (ccr2_test)
1325 cyrix_did = 0x0010; /* 486S A-step */
1326 else
1327 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
1328
1329 intr_restore(saveintr);
1330 }
1331 #endif
1332
1333 /* Update TSC freq with the value indicated by the caller. */
1334 static void
tsc_freq_changed(void * arg __unused,const struct cf_level * level,int status)1335 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1336 {
1337
1338 /* If there was an error during the transition, don't do anything. */
1339 if (status != 0)
1340 return;
1341
1342 /* Total setting for this level gives the new frequency in MHz. */
1343 hw_clockrate = level->total_set.freq;
1344 }
1345
1346 static void
hook_tsc_freq(void * arg __unused)1347 hook_tsc_freq(void *arg __unused)
1348 {
1349
1350 if (tsc_is_invariant)
1351 return;
1352
1353 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1354 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1355 }
1356
1357 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1358
1359 static struct {
1360 const char *vm_cpuid;
1361 int vm_guest;
1362 void (*init)(void);
1363 } vm_cpuids[] = {
1364 { "XenVMMXenVMM", VM_GUEST_XEN,
1365 #ifdef XENHVM
1366 &xen_early_init,
1367 #endif
1368 }, /* XEN */
1369 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */
1370 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */
1371 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */
1372 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */
1373 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */
1374 { "___ NVMM ___", VM_GUEST_NVMM }, /* NVMM */
1375 };
1376
1377 static void
identify_hypervisor_cpuid_base(void)1378 identify_hypervisor_cpuid_base(void)
1379 {
1380 void (*init_fn)(void) = NULL;
1381 u_int leaf, regs[4];
1382 int i;
1383
1384 /*
1385 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1386 * http://lkml.org/lkml/2008/10/1/246
1387 *
1388 * KB1009458: Mechanisms to determine if software is running in
1389 * a VMware virtual machine
1390 * http://kb.vmware.com/kb/1009458
1391 *
1392 * Search for a hypervisor that we recognize. If we cannot find
1393 * a specific hypervisor, return the first information about the
1394 * hypervisor that we found, as others may be able to use.
1395 */
1396 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1397 do_cpuid(leaf, regs);
1398
1399 /*
1400 * KVM from Linux kernels prior to commit
1401 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1402 * to 0 rather than a valid hv_high value. Check for
1403 * the KVM signature bytes and fixup %eax to the
1404 * highest supported leaf in that case.
1405 */
1406 if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1407 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1408 regs[0] = leaf + 1;
1409
1410 if (regs[0] >= leaf) {
1411 enum VM_GUEST prev_vm_guest = vm_guest;
1412
1413 for (i = 0; i < nitems(vm_cpuids); i++)
1414 if (strncmp((const char *)®s[1],
1415 vm_cpuids[i].vm_cpuid, 12) == 0) {
1416 vm_guest = vm_cpuids[i].vm_guest;
1417 init_fn = vm_cpuids[i].init;
1418 break;
1419 }
1420
1421 /*
1422 * If this is the first entry or we found a
1423 * specific hypervisor, record the base, high value,
1424 * and vendor identifier.
1425 */
1426 if (vm_guest != prev_vm_guest || leaf == 0x40000000) {
1427 hv_base = leaf;
1428 hv_high = regs[0];
1429 ((u_int *)&hv_vendor)[0] = regs[1];
1430 ((u_int *)&hv_vendor)[1] = regs[2];
1431 ((u_int *)&hv_vendor)[2] = regs[3];
1432 hv_vendor[12] = '\0';
1433
1434 /*
1435 * If we found a specific hypervisor, then
1436 * we are finished.
1437 */
1438 if (vm_guest != VM_GUEST_VM &&
1439 /*
1440 * Xen and other hypervisors can expose the
1441 * HyperV signature in addition to the
1442 * native one in order to support Viridian
1443 * extensions for Windows guests.
1444 *
1445 * Do the full cpuid scan if HyperV is
1446 * detected, as the native hypervisor is
1447 * preferred.
1448 */
1449 vm_guest != VM_GUEST_HV)
1450 break;
1451 }
1452 }
1453 }
1454
1455 if (init_fn != NULL)
1456 init_fn();
1457 }
1458
1459 void
identify_hypervisor(void)1460 identify_hypervisor(void)
1461 {
1462 u_int regs[4];
1463 char *p;
1464
1465 TSENTER();
1466 /*
1467 * If CPUID2_HV is set, we are running in a hypervisor environment.
1468 */
1469 if (cpu_feature2 & CPUID2_HV) {
1470 vm_guest = VM_GUEST_VM;
1471 identify_hypervisor_cpuid_base();
1472
1473 /* If we have a definitive vendor, we can return now. */
1474 if (*hv_vendor != '\0') {
1475 TSEXIT();
1476 return;
1477 }
1478 }
1479
1480 /*
1481 * Examine SMBIOS strings for older hypervisors.
1482 */
1483 p = kern_getenv("smbios.system.serial");
1484 if (p != NULL) {
1485 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1486 vmware_hvcall(0, VMW_HVCMD_GETVERSION,
1487 VMW_HVCMD_DEFAULT_PARAM, regs);
1488 if (regs[1] == VMW_HVMAGIC) {
1489 vm_guest = VM_GUEST_VMWARE;
1490 freeenv(p);
1491 TSEXIT();
1492 return;
1493 }
1494 }
1495 freeenv(p);
1496 }
1497 TSEXIT();
1498 }
1499
1500 bool
fix_cpuid(void)1501 fix_cpuid(void)
1502 {
1503 uint64_t msr;
1504
1505 /*
1506 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1507 * get the largest standard CPUID function number again if it is set
1508 * from BIOS. It is necessary for probing correct CPU topology later
1509 * and for the correct operation of the AVX-aware userspace.
1510 */
1511 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1512 ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1513 CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1514 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1515 CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1516 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1517 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1518 msr &= ~IA32_MISC_EN_LIMCPUID;
1519 wrmsr(MSR_IA32_MISC_ENABLE, msr);
1520 return (true);
1521 }
1522 }
1523
1524 /*
1525 * Re-enable AMD Topology Extension that could be disabled by BIOS
1526 * on some notebook processors. Without the extension it's really
1527 * hard to determine the correct CPU cache topology.
1528 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
1529 * Models 60h-6Fh Processors, Publication # 50742.
1530 */
1531 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1532 CPUID_TO_FAMILY(cpu_id) == 0x15) {
1533 msr = rdmsr(MSR_EXTFEATURES);
1534 if ((msr & ((uint64_t)1 << 54)) == 0) {
1535 msr |= (uint64_t)1 << 54;
1536 wrmsr(MSR_EXTFEATURES, msr);
1537 return (true);
1538 }
1539 }
1540 return (false);
1541 }
1542
1543 void
identify_cpu1(void)1544 identify_cpu1(void)
1545 {
1546 u_int regs[4];
1547
1548 do_cpuid(0, regs);
1549 cpu_high = regs[0];
1550 ((u_int *)&cpu_vendor)[0] = regs[1];
1551 ((u_int *)&cpu_vendor)[1] = regs[3];
1552 ((u_int *)&cpu_vendor)[2] = regs[2];
1553 cpu_vendor[12] = '\0';
1554
1555 do_cpuid(1, regs);
1556 cpu_id = regs[0];
1557 cpu_procinfo = regs[1];
1558 cpu_feature = regs[3];
1559 cpu_feature2 = regs[2];
1560 }
1561
1562 void
identify_cpu2(void)1563 identify_cpu2(void)
1564 {
1565 u_int regs[4], cpu_stdext_disable;
1566
1567 if (cpu_high >= 6) {
1568 cpuid_count(6, 0, regs);
1569 cpu_power_eax = regs[0];
1570 cpu_power_ebx = regs[1];
1571 cpu_power_ecx = regs[2];
1572 cpu_power_edx = regs[3];
1573 }
1574
1575 if (cpu_high >= 7) {
1576 cpuid_count(7, 0, regs);
1577 cpu_stdext_feature = regs[1];
1578
1579 /*
1580 * Some hypervisors failed to filter out unsupported
1581 * extended features. Allow to disable the
1582 * extensions, activation of which requires setting a
1583 * bit in CR4, and which VM monitors do not support.
1584 */
1585 cpu_stdext_disable = 0;
1586 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1587 cpu_stdext_feature &= ~cpu_stdext_disable;
1588
1589 cpu_stdext_feature2 = regs[2];
1590 cpu_stdext_feature3 = regs[3];
1591
1592 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1593 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1594 }
1595 }
1596
1597 void
identify_cpu_ext_features(void)1598 identify_cpu_ext_features(void)
1599 {
1600 u_int regs[4];
1601
1602 if (cpu_high >= 7) {
1603 cpuid_count(7, 0, regs);
1604 cpu_stdext_feature2 = regs[2];
1605 cpu_stdext_feature3 = regs[3];
1606 }
1607 }
1608
1609 void
identify_cpu_fixup_bsp(void)1610 identify_cpu_fixup_bsp(void)
1611 {
1612 u_int regs[4];
1613
1614 cpu_vendor_id = find_cpu_vendor_id();
1615
1616 if (fix_cpuid()) {
1617 do_cpuid(0, regs);
1618 cpu_high = regs[0];
1619 }
1620 }
1621
1622 /*
1623 * Final stage of CPU identification.
1624 */
1625 void
finishidentcpu(void)1626 finishidentcpu(void)
1627 {
1628 u_int regs[4];
1629 #ifdef __i386__
1630 u_char ccr3;
1631 #endif
1632
1633 identify_cpu_fixup_bsp();
1634
1635 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1636 do_cpuid(5, regs);
1637 cpu_mon_mwait_flags = regs[2];
1638 cpu_mon_mwait_edx = regs[3];
1639 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE;
1640 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE;
1641 }
1642
1643 identify_cpu2();
1644
1645 #ifdef __i386__
1646 if (cpu_high > 0 &&
1647 (cpu_vendor_id == CPU_VENDOR_INTEL ||
1648 cpu_vendor_id == CPU_VENDOR_AMD ||
1649 cpu_vendor_id == CPU_VENDOR_HYGON ||
1650 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1651 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1652 cpu_vendor_id == CPU_VENDOR_NSC)) {
1653 do_cpuid(0x80000000, regs);
1654 if (regs[0] >= 0x80000000)
1655 cpu_exthigh = regs[0];
1656 }
1657 #else
1658 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1659 cpu_vendor_id == CPU_VENDOR_AMD ||
1660 cpu_vendor_id == CPU_VENDOR_HYGON ||
1661 cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1662 do_cpuid(0x80000000, regs);
1663 cpu_exthigh = regs[0];
1664 }
1665 #endif
1666 if (cpu_exthigh >= 0x80000001) {
1667 do_cpuid(0x80000001, regs);
1668 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1669 amd_feature2 = regs[2];
1670 }
1671 if (cpu_exthigh >= 0x80000007) {
1672 do_cpuid(0x80000007, regs);
1673 amd_rascap = regs[1];
1674 amd_pminfo = regs[3];
1675 }
1676 if (cpu_exthigh >= 0x80000008) {
1677 do_cpuid(0x80000008, regs);
1678 cpu_maxphyaddr = regs[0] & 0xff;
1679 amd_extended_feature_extensions = regs[1];
1680 cpu_procinfo2 = regs[2];
1681 cpu_procinfo3 = regs[3];
1682 } else {
1683 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1684 }
1685
1686 #ifdef __i386__
1687 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1688 if (cpu == CPU_486) {
1689 /*
1690 * These conditions are equivalent to:
1691 * - CPU does not support cpuid instruction.
1692 * - Cyrix/IBM CPU is detected.
1693 */
1694 if (identblue() == IDENTBLUE_IBMCPU) {
1695 strcpy(cpu_vendor, "IBM");
1696 cpu_vendor_id = CPU_VENDOR_IBM;
1697 cpu = CPU_BLUE;
1698 return;
1699 }
1700 }
1701 switch (cpu_id & 0xf00) {
1702 case 0x600:
1703 /*
1704 * Cyrix's datasheet does not describe DIRs.
1705 * Therefor, I assume it does not have them
1706 * and use the result of the cpuid instruction.
1707 * XXX they seem to have it for now at least. -Peter
1708 */
1709 identifycyrix();
1710 cpu = CPU_M2;
1711 break;
1712 default:
1713 identifycyrix();
1714 /*
1715 * This routine contains a trick.
1716 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1717 */
1718 switch (cyrix_did & 0x00f0) {
1719 case 0x00:
1720 case 0xf0:
1721 cpu = CPU_486DLC;
1722 break;
1723 case 0x10:
1724 cpu = CPU_CY486DX;
1725 break;
1726 case 0x20:
1727 if ((cyrix_did & 0x000f) < 8)
1728 cpu = CPU_M1;
1729 else
1730 cpu = CPU_M1SC;
1731 break;
1732 case 0x30:
1733 cpu = CPU_M1;
1734 break;
1735 case 0x40:
1736 /* MediaGX CPU */
1737 cpu = CPU_M1SC;
1738 break;
1739 default:
1740 /* M2 and later CPUs are treated as M2. */
1741 cpu = CPU_M2;
1742
1743 /*
1744 * enable cpuid instruction.
1745 */
1746 ccr3 = read_cyrix_reg(CCR3);
1747 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1748 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1749 write_cyrix_reg(CCR3, ccr3);
1750
1751 do_cpuid(0, regs);
1752 cpu_high = regs[0]; /* eax */
1753 do_cpuid(1, regs);
1754 cpu_id = regs[0]; /* eax */
1755 cpu_feature = regs[3]; /* edx */
1756 break;
1757 }
1758 }
1759 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1760 /*
1761 * There are BlueLightning CPUs that do not change
1762 * undefined flags by dividing 5 by 2. In this case,
1763 * the CPU identification routine in locore.s leaves
1764 * cpu_vendor null string and puts CPU_486 into the
1765 * cpu.
1766 */
1767 if (identblue() == IDENTBLUE_IBMCPU) {
1768 strcpy(cpu_vendor, "IBM");
1769 cpu_vendor_id = CPU_VENDOR_IBM;
1770 cpu = CPU_BLUE;
1771 return;
1772 }
1773 }
1774 #endif
1775 }
1776
1777 int
pti_get_default(void)1778 pti_get_default(void)
1779 {
1780
1781 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1782 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1783 return (0);
1784 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1785 return (0);
1786 return (1);
1787 }
1788
1789 static u_int
find_cpu_vendor_id(void)1790 find_cpu_vendor_id(void)
1791 {
1792 int i;
1793
1794 for (i = 0; i < nitems(cpu_vendors); i++)
1795 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1796 return (cpu_vendors[i].vendor_id);
1797 return (0);
1798 }
1799
1800 static void
print_AMD_assoc(int i)1801 print_AMD_assoc(int i)
1802 {
1803 if (i == 255)
1804 printf(", fully associative\n");
1805 else
1806 printf(", %d-way associative\n", i);
1807 }
1808
1809 static void
print_AMD_l2_assoc(int i)1810 print_AMD_l2_assoc(int i)
1811 {
1812 switch (i & 0x0f) {
1813 case 0: printf(", disabled/not present\n"); break;
1814 case 1: printf(", direct mapped\n"); break;
1815 case 2: printf(", 2-way associative\n"); break;
1816 case 4: printf(", 4-way associative\n"); break;
1817 case 6: printf(", 8-way associative\n"); break;
1818 case 8: printf(", 16-way associative\n"); break;
1819 case 15: printf(", fully associative\n"); break;
1820 default: printf(", reserved configuration\n"); break;
1821 }
1822 }
1823
1824 static void
print_AMD_info(void)1825 print_AMD_info(void)
1826 {
1827 #ifdef __i386__
1828 uint64_t amd_whcr;
1829 #endif
1830 u_int regs[4];
1831
1832 if (cpu_exthigh >= 0x80000005) {
1833 do_cpuid(0x80000005, regs);
1834 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1835 print_AMD_assoc(regs[0] >> 24);
1836
1837 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1838 print_AMD_assoc((regs[0] >> 8) & 0xff);
1839
1840 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1841 print_AMD_assoc(regs[1] >> 24);
1842
1843 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1844 print_AMD_assoc((regs[1] >> 8) & 0xff);
1845
1846 printf("L1 data cache: %d kbytes", regs[2] >> 24);
1847 printf(", %d bytes/line", regs[2] & 0xff);
1848 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1849 print_AMD_assoc((regs[2] >> 16) & 0xff);
1850
1851 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1852 printf(", %d bytes/line", regs[3] & 0xff);
1853 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1854 print_AMD_assoc((regs[3] >> 16) & 0xff);
1855 }
1856
1857 if (cpu_exthigh >= 0x80000006) {
1858 do_cpuid(0x80000006, regs);
1859 if ((regs[0] >> 16) != 0) {
1860 printf("L2 2MB data TLB: %d entries",
1861 (regs[0] >> 16) & 0xfff);
1862 print_AMD_l2_assoc(regs[0] >> 28);
1863 printf("L2 2MB instruction TLB: %d entries",
1864 regs[0] & 0xfff);
1865 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1866 } else {
1867 printf("L2 2MB unified TLB: %d entries",
1868 regs[0] & 0xfff);
1869 print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1870 }
1871 if ((regs[1] >> 16) != 0) {
1872 printf("L2 4KB data TLB: %d entries",
1873 (regs[1] >> 16) & 0xfff);
1874 print_AMD_l2_assoc(regs[1] >> 28);
1875
1876 printf("L2 4KB instruction TLB: %d entries",
1877 (regs[1] >> 16) & 0xfff);
1878 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1879 } else {
1880 printf("L2 4KB unified TLB: %d entries",
1881 (regs[1] >> 16) & 0xfff);
1882 print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1883 }
1884 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1885 printf(", %d bytes/line", regs[2] & 0xff);
1886 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1887 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1888 }
1889
1890 #ifdef __i386__
1891 if (((cpu_id & 0xf00) == 0x500)
1892 && (((cpu_id & 0x0f0) > 0x80)
1893 || (((cpu_id & 0x0f0) == 0x80)
1894 && (cpu_id & 0x00f) > 0x07))) {
1895 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1896 amd_whcr = rdmsr(0xc0000082);
1897 if (!(amd_whcr & (0x3ff << 22))) {
1898 printf("Write Allocate Disable\n");
1899 } else {
1900 printf("Write Allocate Enable Limit: %dM bytes\n",
1901 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1902 printf("Write Allocate 15-16M bytes: %s\n",
1903 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1904 }
1905 } else if (((cpu_id & 0xf00) == 0x500)
1906 && ((cpu_id & 0x0f0) > 0x50)) {
1907 /* K6, K6-2(old core) */
1908 amd_whcr = rdmsr(0xc0000082);
1909 if (!(amd_whcr & (0x7f << 1))) {
1910 printf("Write Allocate Disable\n");
1911 } else {
1912 printf("Write Allocate Enable Limit: %dM bytes\n",
1913 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1914 printf("Write Allocate 15-16M bytes: %s\n",
1915 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1916 printf("Hardware Write Allocate Control: %s\n",
1917 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1918 }
1919 }
1920 #endif
1921 /*
1922 * Opteron Rev E shows a bug as in very rare occasions a read memory
1923 * barrier is not performed as expected if it is followed by a
1924 * non-atomic read-modify-write instruction.
1925 * As long as that bug pops up very rarely (intensive machine usage
1926 * on other operating systems generally generates one unexplainable
1927 * crash any 2 months) and as long as a model specific fix would be
1928 * impractical at this stage, print out a warning string if the broken
1929 * model and family are identified.
1930 */
1931 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1932 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1933 printf("WARNING: This architecture revision has known SMP "
1934 "hardware bugs which may cause random instability\n");
1935 }
1936
1937 static void
print_INTEL_info(void)1938 print_INTEL_info(void)
1939 {
1940 u_int regs[4];
1941 u_int rounds, regnum;
1942 u_int nwaycode, nway;
1943
1944 if (cpu_high >= 2) {
1945 rounds = 0;
1946 do {
1947 do_cpuid(0x2, regs);
1948 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1949 break; /* we have a buggy CPU */
1950
1951 for (regnum = 0; regnum <= 3; ++regnum) {
1952 if (regs[regnum] & (1<<31))
1953 continue;
1954 if (regnum != 0)
1955 print_INTEL_TLB(regs[regnum] & 0xff);
1956 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1957 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1958 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1959 }
1960 } while (--rounds > 0);
1961 }
1962
1963 if (cpu_exthigh >= 0x80000006) {
1964 do_cpuid(0x80000006, regs);
1965 nwaycode = (regs[2] >> 12) & 0x0f;
1966 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1967 nway = 1 << (nwaycode / 2);
1968 else
1969 nway = 0;
1970 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1971 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1972 }
1973 }
1974
1975 static void
print_INTEL_TLB(u_int data)1976 print_INTEL_TLB(u_int data)
1977 {
1978 switch (data) {
1979 case 0x0:
1980 case 0x40:
1981 default:
1982 break;
1983 case 0x1:
1984 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1985 break;
1986 case 0x2:
1987 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1988 break;
1989 case 0x3:
1990 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1991 break;
1992 case 0x4:
1993 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1994 break;
1995 case 0x6:
1996 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1997 break;
1998 case 0x8:
1999 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2000 break;
2001 case 0x9:
2002 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2003 break;
2004 case 0xa:
2005 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2006 break;
2007 case 0xb:
2008 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2009 break;
2010 case 0xc:
2011 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2012 break;
2013 case 0xd:
2014 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2015 break;
2016 case 0xe:
2017 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2018 break;
2019 case 0x1d:
2020 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2021 break;
2022 case 0x21:
2023 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2024 break;
2025 case 0x22:
2026 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2027 break;
2028 case 0x23:
2029 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2030 break;
2031 case 0x24:
2032 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2033 break;
2034 case 0x25:
2035 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2036 break;
2037 case 0x29:
2038 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2039 break;
2040 case 0x2c:
2041 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2042 break;
2043 case 0x30:
2044 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2045 break;
2046 case 0x39: /* De-listed in SDM rev. 54 */
2047 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2048 break;
2049 case 0x3b: /* De-listed in SDM rev. 54 */
2050 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2051 break;
2052 case 0x3c: /* De-listed in SDM rev. 54 */
2053 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2054 break;
2055 case 0x41:
2056 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2057 break;
2058 case 0x42:
2059 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2060 break;
2061 case 0x43:
2062 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2063 break;
2064 case 0x44:
2065 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2066 break;
2067 case 0x45:
2068 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2069 break;
2070 case 0x46:
2071 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2072 break;
2073 case 0x47:
2074 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2075 break;
2076 case 0x48:
2077 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2078 break;
2079 case 0x49:
2080 if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2081 CPUID_TO_MODEL(cpu_id) == 0x6)
2082 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2083 else
2084 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2085 break;
2086 case 0x4a:
2087 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2088 break;
2089 case 0x4b:
2090 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2091 break;
2092 case 0x4c:
2093 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2094 break;
2095 case 0x4d:
2096 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2097 break;
2098 case 0x4e:
2099 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2100 break;
2101 case 0x4f:
2102 printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2103 break;
2104 case 0x50:
2105 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2106 break;
2107 case 0x51:
2108 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2109 break;
2110 case 0x52:
2111 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2112 break;
2113 case 0x55:
2114 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2115 break;
2116 case 0x56:
2117 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2118 break;
2119 case 0x57:
2120 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2121 break;
2122 case 0x59:
2123 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2124 break;
2125 case 0x5a:
2126 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2127 break;
2128 case 0x5b:
2129 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2130 break;
2131 case 0x5c:
2132 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2133 break;
2134 case 0x5d:
2135 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2136 break;
2137 case 0x60:
2138 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2139 break;
2140 case 0x61:
2141 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2142 break;
2143 case 0x63:
2144 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2145 break;
2146 case 0x64:
2147 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2148 break;
2149 case 0x66:
2150 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2151 break;
2152 case 0x67:
2153 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2154 break;
2155 case 0x68:
2156 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2157 break;
2158 case 0x6a:
2159 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2160 break;
2161 case 0x6b:
2162 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2163 break;
2164 case 0x6c:
2165 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2166 break;
2167 case 0x6d:
2168 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2169 break;
2170 case 0x70:
2171 printf("Trace cache: 12K-uops, 8-way set associative\n");
2172 break;
2173 case 0x71:
2174 printf("Trace cache: 16K-uops, 8-way set associative\n");
2175 break;
2176 case 0x72:
2177 printf("Trace cache: 32K-uops, 8-way set associative\n");
2178 break;
2179 case 0x76:
2180 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2181 break;
2182 case 0x78:
2183 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2184 break;
2185 case 0x79:
2186 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2187 break;
2188 case 0x7a:
2189 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2190 break;
2191 case 0x7b:
2192 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2193 break;
2194 case 0x7c:
2195 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2196 break;
2197 case 0x7d:
2198 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2199 break;
2200 case 0x7f:
2201 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2202 break;
2203 case 0x80:
2204 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2205 break;
2206 case 0x82:
2207 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2208 break;
2209 case 0x83:
2210 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2211 break;
2212 case 0x84:
2213 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2214 break;
2215 case 0x85:
2216 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2217 break;
2218 case 0x86:
2219 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2220 break;
2221 case 0x87:
2222 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2223 break;
2224 case 0xa0:
2225 printf("DTLB: 4k pages, fully associative, 32 entries\n");
2226 break;
2227 case 0xb0:
2228 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2229 break;
2230 case 0xb1:
2231 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2232 break;
2233 case 0xb2:
2234 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2235 break;
2236 case 0xb3:
2237 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2238 break;
2239 case 0xb4:
2240 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2241 break;
2242 case 0xb5:
2243 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2244 break;
2245 case 0xb6:
2246 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2247 break;
2248 case 0xba:
2249 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2250 break;
2251 case 0xc0:
2252 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2253 break;
2254 case 0xc1:
2255 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2256 break;
2257 case 0xc2:
2258 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2259 break;
2260 case 0xc3:
2261 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2262 break;
2263 case 0xc4:
2264 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2265 break;
2266 case 0xca:
2267 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2268 break;
2269 case 0xd0:
2270 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2271 break;
2272 case 0xd1:
2273 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2274 break;
2275 case 0xd2:
2276 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2277 break;
2278 case 0xd6:
2279 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2280 break;
2281 case 0xd7:
2282 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2283 break;
2284 case 0xd8:
2285 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2286 break;
2287 case 0xdc:
2288 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2289 break;
2290 case 0xdd:
2291 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2292 break;
2293 case 0xde:
2294 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2295 break;
2296 case 0xe2:
2297 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2298 break;
2299 case 0xe3:
2300 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2301 break;
2302 case 0xe4:
2303 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2304 break;
2305 case 0xea:
2306 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2307 break;
2308 case 0xeb:
2309 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2310 break;
2311 case 0xec:
2312 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2313 break;
2314 case 0xf0:
2315 printf("64-Byte prefetching\n");
2316 break;
2317 case 0xf1:
2318 printf("128-Byte prefetching\n");
2319 break;
2320 }
2321 }
2322
2323 static void
print_svm_info(void)2324 print_svm_info(void)
2325 {
2326 u_int features, regs[4];
2327 uint64_t msr;
2328 int comma;
2329
2330 printf("\n SVM: ");
2331 do_cpuid(0x8000000A, regs);
2332 features = regs[3];
2333
2334 msr = rdmsr(MSR_VM_CR);
2335 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2336 printf("(disabled in BIOS) ");
2337
2338 if (!bootverbose) {
2339 comma = 0;
2340 if (features & (1 << 0)) {
2341 printf("%sNP", comma ? "," : "");
2342 comma = 1;
2343 }
2344 if (features & (1 << 3)) {
2345 printf("%sNRIP", comma ? "," : "");
2346 comma = 1;
2347 }
2348 if (features & (1 << 5)) {
2349 printf("%sVClean", comma ? "," : "");
2350 comma = 1;
2351 }
2352 if (features & (1 << 6)) {
2353 printf("%sAFlush", comma ? "," : "");
2354 comma = 1;
2355 }
2356 if (features & (1 << 7)) {
2357 printf("%sDAssist", comma ? "," : "");
2358 comma = 1;
2359 }
2360 printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2361 return;
2362 }
2363
2364 printf("Features=0x%b", features,
2365 "\020"
2366 "\001NP" /* Nested paging */
2367 "\002LbrVirt" /* LBR virtualization */
2368 "\003SVML" /* SVM lock */
2369 "\004NRIPS" /* NRIP save */
2370 "\005TscRateMsr" /* MSR based TSC rate control */
2371 "\006VmcbClean" /* VMCB clean bits */
2372 "\007FlushByAsid" /* Flush by ASID */
2373 "\010DecodeAssist" /* Decode assist */
2374 "\011<b8>"
2375 "\012<b9>"
2376 "\013PauseFilter" /* PAUSE intercept filter */
2377 "\014EncryptedMcodePatch"
2378 "\015PauseFilterThreshold" /* PAUSE filter threshold */
2379 "\016AVIC" /* virtual interrupt controller */
2380 "\017<b14>"
2381 "\020V_VMSAVE_VMLOAD"
2382 "\021vGIF"
2383 "\022GMET" /* Guest Mode Execute Trap */
2384 "\023<b18>"
2385 "\024<b19>"
2386 "\025GuesSpecCtl" /* Guest Spec_ctl */
2387 "\026<b21>"
2388 "\027<b22>"
2389 "\030<b23>"
2390 "\031<b24>"
2391 "\032<b25>"
2392 "\033<b26>"
2393 "\034<b27>"
2394 "\035<b28>"
2395 "\036<b29>"
2396 "\037<b30>"
2397 "\040<b31>"
2398 );
2399 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2400 }
2401
2402 #ifdef __i386__
2403 static void
print_transmeta_info(void)2404 print_transmeta_info(void)
2405 {
2406 u_int regs[4], nreg = 0;
2407
2408 do_cpuid(0x80860000, regs);
2409 nreg = regs[0];
2410 if (nreg >= 0x80860001) {
2411 do_cpuid(0x80860001, regs);
2412 printf(" Processor revision %u.%u.%u.%u\n",
2413 (regs[1] >> 24) & 0xff,
2414 (regs[1] >> 16) & 0xff,
2415 (regs[1] >> 8) & 0xff,
2416 regs[1] & 0xff);
2417 }
2418 if (nreg >= 0x80860002) {
2419 do_cpuid(0x80860002, regs);
2420 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
2421 (regs[1] >> 24) & 0xff,
2422 (regs[1] >> 16) & 0xff,
2423 (regs[1] >> 8) & 0xff,
2424 regs[1] & 0xff,
2425 regs[2]);
2426 }
2427 if (nreg >= 0x80860006) {
2428 char info[65];
2429 do_cpuid(0x80860003, (u_int*) &info[0]);
2430 do_cpuid(0x80860004, (u_int*) &info[16]);
2431 do_cpuid(0x80860005, (u_int*) &info[32]);
2432 do_cpuid(0x80860006, (u_int*) &info[48]);
2433 info[64] = 0;
2434 printf(" %s\n", info);
2435 }
2436 }
2437 #endif
2438
2439 static void
print_via_padlock_info(void)2440 print_via_padlock_info(void)
2441 {
2442 u_int regs[4];
2443
2444 do_cpuid(0xc0000001, regs);
2445 printf("\n VIA Padlock Features=0x%b", regs[3],
2446 "\020"
2447 "\003RNG" /* RNG */
2448 "\007AES" /* ACE */
2449 "\011AES-CTR" /* ACE2 */
2450 "\013SHA1,SHA256" /* PHE */
2451 "\015RSA" /* PMM */
2452 );
2453 }
2454
2455 static uint32_t
vmx_settable(uint64_t basic,int msr,int true_msr)2456 vmx_settable(uint64_t basic, int msr, int true_msr)
2457 {
2458 uint64_t val;
2459
2460 if (basic & (1ULL << 55))
2461 val = rdmsr(true_msr);
2462 else
2463 val = rdmsr(msr);
2464
2465 /* Just report the controls that can be set to 1. */
2466 return (val >> 32);
2467 }
2468
2469 static void
print_vmx_info(void)2470 print_vmx_info(void)
2471 {
2472 uint64_t basic, msr;
2473 uint32_t entry, exit, mask, pin, proc, proc2;
2474 int comma;
2475
2476 printf("\n VT-x: ");
2477 msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2478 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2479 printf("(disabled in BIOS) ");
2480 basic = rdmsr(MSR_VMX_BASIC);
2481 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2482 MSR_VMX_TRUE_PINBASED_CTLS);
2483 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2484 MSR_VMX_TRUE_PROCBASED_CTLS);
2485 if (proc & PROCBASED_SECONDARY_CONTROLS)
2486 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2487 MSR_VMX_PROCBASED_CTLS2);
2488 else
2489 proc2 = 0;
2490 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2491 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2492
2493 if (!bootverbose) {
2494 comma = 0;
2495 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2496 entry & VM_ENTRY_LOAD_PAT) {
2497 printf("%sPAT", comma ? "," : "");
2498 comma = 1;
2499 }
2500 if (proc & PROCBASED_HLT_EXITING) {
2501 printf("%sHLT", comma ? "," : "");
2502 comma = 1;
2503 }
2504 if (proc & PROCBASED_MTF) {
2505 printf("%sMTF", comma ? "," : "");
2506 comma = 1;
2507 }
2508 if (proc & PROCBASED_PAUSE_EXITING) {
2509 printf("%sPAUSE", comma ? "," : "");
2510 comma = 1;
2511 }
2512 if (proc2 & PROCBASED2_ENABLE_EPT) {
2513 printf("%sEPT", comma ? "," : "");
2514 comma = 1;
2515 }
2516 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2517 printf("%sUG", comma ? "," : "");
2518 comma = 1;
2519 }
2520 if (proc2 & PROCBASED2_ENABLE_VPID) {
2521 printf("%sVPID", comma ? "," : "");
2522 comma = 1;
2523 }
2524 if (proc & PROCBASED_USE_TPR_SHADOW &&
2525 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2526 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2527 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2528 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2529 printf("%sVID", comma ? "," : "");
2530 comma = 1;
2531 if (pin & PINBASED_POSTED_INTERRUPT)
2532 printf(",PostIntr");
2533 }
2534 return;
2535 }
2536
2537 mask = basic >> 32;
2538 printf("Basic Features=0x%b", mask,
2539 "\020"
2540 "\02132PA" /* 32-bit physical addresses */
2541 "\022SMM" /* SMM dual-monitor */
2542 "\027INS/OUTS" /* VM-exit info for INS and OUTS */
2543 "\030TRUE" /* TRUE_CTLS MSRs */
2544 );
2545 printf("\n Pin-Based Controls=0x%b", pin,
2546 "\020"
2547 "\001ExtINT" /* External-interrupt exiting */
2548 "\004NMI" /* NMI exiting */
2549 "\006VNMI" /* Virtual NMIs */
2550 "\007PreTmr" /* Activate VMX-preemption timer */
2551 "\010PostIntr" /* Process posted interrupts */
2552 );
2553 printf("\n Primary Processor Controls=0x%b", proc,
2554 "\020"
2555 "\003INTWIN" /* Interrupt-window exiting */
2556 "\004TSCOff" /* Use TSC offsetting */
2557 "\010HLT" /* HLT exiting */
2558 "\012INVLPG" /* INVLPG exiting */
2559 "\013MWAIT" /* MWAIT exiting */
2560 "\014RDPMC" /* RDPMC exiting */
2561 "\015RDTSC" /* RDTSC exiting */
2562 "\020CR3-LD" /* CR3-load exiting */
2563 "\021CR3-ST" /* CR3-store exiting */
2564 "\024CR8-LD" /* CR8-load exiting */
2565 "\025CR8-ST" /* CR8-store exiting */
2566 "\026TPR" /* Use TPR shadow */
2567 "\027NMIWIN" /* NMI-window exiting */
2568 "\030MOV-DR" /* MOV-DR exiting */
2569 "\031IO" /* Unconditional I/O exiting */
2570 "\032IOmap" /* Use I/O bitmaps */
2571 "\034MTF" /* Monitor trap flag */
2572 "\035MSRmap" /* Use MSR bitmaps */
2573 "\036MONITOR" /* MONITOR exiting */
2574 "\037PAUSE" /* PAUSE exiting */
2575 );
2576 if (proc & PROCBASED_SECONDARY_CONTROLS)
2577 printf("\n Secondary Processor Controls=0x%b", proc2,
2578 "\020"
2579 "\001APIC" /* Virtualize APIC accesses */
2580 "\002EPT" /* Enable EPT */
2581 "\003DT" /* Descriptor-table exiting */
2582 "\004RDTSCP" /* Enable RDTSCP */
2583 "\005x2APIC" /* Virtualize x2APIC mode */
2584 "\006VPID" /* Enable VPID */
2585 "\007WBINVD" /* WBINVD exiting */
2586 "\010UG" /* Unrestricted guest */
2587 "\011APIC-reg" /* APIC-register virtualization */
2588 "\012VID" /* Virtual-interrupt delivery */
2589 "\013PAUSE-loop" /* PAUSE-loop exiting */
2590 "\014RDRAND" /* RDRAND exiting */
2591 "\015INVPCID" /* Enable INVPCID */
2592 "\016VMFUNC" /* Enable VM functions */
2593 "\017VMCS" /* VMCS shadowing */
2594 "\020EPT#VE" /* EPT-violation #VE */
2595 "\021XSAVES" /* Enable XSAVES/XRSTORS */
2596 );
2597 printf("\n Exit Controls=0x%b", mask,
2598 "\020"
2599 "\003DR" /* Save debug controls */
2600 /* Ignore Host address-space size */
2601 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2602 "\020AckInt" /* Acknowledge interrupt on exit */
2603 "\023PAT-SV" /* Save MSR_PAT */
2604 "\024PAT-LD" /* Load MSR_PAT */
2605 "\025EFER-SV" /* Save MSR_EFER */
2606 "\026EFER-LD" /* Load MSR_EFER */
2607 "\027PTMR-SV" /* Save VMX-preemption timer value */
2608 );
2609 printf("\n Entry Controls=0x%b", mask,
2610 "\020"
2611 "\003DR" /* Save debug controls */
2612 /* Ignore IA-32e mode guest */
2613 /* Ignore Entry to SMM */
2614 /* Ignore Deactivate dual-monitor treatment */
2615 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */
2616 "\017PAT" /* Load MSR_PAT */
2617 "\020EFER" /* Load MSR_EFER */
2618 );
2619 if (proc & PROCBASED_SECONDARY_CONTROLS &&
2620 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2621 msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2622 mask = msr;
2623 printf("\n EPT Features=0x%b", mask,
2624 "\020"
2625 "\001XO" /* Execute-only translations */
2626 "\007PW4" /* Page-walk length of 4 */
2627 "\011UC" /* EPT paging-structure mem can be UC */
2628 "\017WB" /* EPT paging-structure mem can be WB */
2629 "\0212M" /* EPT PDE can map a 2-Mbyte page */
2630 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */
2631 "\025INVEPT" /* INVEPT is supported */
2632 "\026AD" /* Accessed and dirty flags for EPT */
2633 "\032single" /* INVEPT single-context type */
2634 "\033all" /* INVEPT all-context type */
2635 );
2636 mask = msr >> 32;
2637 printf("\n VPID Features=0x%b", mask,
2638 "\020"
2639 "\001INVVPID" /* INVVPID is supported */
2640 "\011individual" /* INVVPID individual-address type */
2641 "\012single" /* INVVPID single-context type */
2642 "\013all" /* INVVPID all-context type */
2643 /* INVVPID single-context-retaining-globals type */
2644 "\014single-globals"
2645 );
2646 }
2647 }
2648
2649 static void
print_hypervisor_info(void)2650 print_hypervisor_info(void)
2651 {
2652
2653 if (*hv_vendor != '\0')
2654 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2655 }
2656
2657 /*
2658 * Returns the maximum physical address that can be used with the
2659 * current system.
2660 */
2661 vm_paddr_t
cpu_getmaxphyaddr(void)2662 cpu_getmaxphyaddr(void)
2663 {
2664
2665 #if defined(__i386__)
2666 if (!pae_mode)
2667 return (0xffffffff);
2668 #endif
2669 return ((1ULL << cpu_maxphyaddr) - 1);
2670 }
2671