1 /*
2 * Copyright 2012-2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dcn20_hubp.h"
27
28 #include "dm_services.h"
29 #include "dce_calcs.h"
30 #include "reg_helper.h"
31 #include "basics/conversion.h"
32
33 #define DC_LOGGER \
34 ctx->logger
35 #define DC_LOGGER_INIT(logger)
36
37 #define REG(reg)\
38 hubp2->hubp_regs->reg
39
40 #define CTX \
41 hubp2->base.ctx
42
43 #undef FN
44 #define FN(reg_name, field_name) \
45 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
46
hubp2_set_vm_system_aperture_settings(struct hubp * hubp,struct vm_system_aperture_param * apt)47 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
48 struct vm_system_aperture_param *apt)
49 {
50 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
51
52 PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
53 PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
54 PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
55
56 // The format of default addr is 48:12 of the 48 bit addr
57 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
58
59 // The format of high/low are 48:18 of the 48 bit addr
60 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
61 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
62
63 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
64 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
65 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
66
67 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
68 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
69
70 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
71 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
72
73 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
74 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
75
76 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
77 ENABLE_L1_TLB, 1,
78 SYSTEM_ACCESS_MODE, 0x3);
79 }
80
hubp2_program_deadline(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)81 void hubp2_program_deadline(
82 struct hubp *hubp,
83 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
84 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
85 {
86 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
87
88 /* DLG - Per hubp */
89 REG_SET_2(BLANK_OFFSET_0, 0,
90 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
91 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
92
93 REG_SET(BLANK_OFFSET_1, 0,
94 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
95
96 REG_SET(DST_DIMENSIONS, 0,
97 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
98
99 REG_SET_2(DST_AFTER_SCALER, 0,
100 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
101 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
102
103 REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
104 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
105
106 /* DLG - Per luma/chroma */
107 REG_SET(VBLANK_PARAMETERS_1, 0,
108 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
109
110 if (REG(NOM_PARAMETERS_0))
111 REG_SET(NOM_PARAMETERS_0, 0,
112 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
113
114 if (REG(NOM_PARAMETERS_1))
115 REG_SET(NOM_PARAMETERS_1, 0,
116 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
117
118 REG_SET(NOM_PARAMETERS_4, 0,
119 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
120
121 REG_SET(NOM_PARAMETERS_5, 0,
122 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
123
124 REG_SET_2(PER_LINE_DELIVERY, 0,
125 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
126 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
127
128 REG_SET(VBLANK_PARAMETERS_2, 0,
129 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
130
131 if (REG(NOM_PARAMETERS_2))
132 REG_SET(NOM_PARAMETERS_2, 0,
133 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
134
135 if (REG(NOM_PARAMETERS_3))
136 REG_SET(NOM_PARAMETERS_3, 0,
137 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
138
139 REG_SET(NOM_PARAMETERS_6, 0,
140 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
141
142 REG_SET(NOM_PARAMETERS_7, 0,
143 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
144
145 /* TTU - per hubp */
146 REG_SET_2(DCN_TTU_QOS_WM, 0,
147 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
148 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
149
150 /* TTU - per luma/chroma */
151 /* Assumed surf0 is luma and 1 is chroma */
152
153 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
154 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
155 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
156 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
157
158 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
159 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
160 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
161 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
162
163 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
164 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
165 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
166 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
167
168 REG_SET(FLIP_PARAMETERS_1, 0,
169 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
170 }
171
hubp2_vready_at_or_After_vsync(struct hubp * hubp,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)172 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
173 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
174 {
175 uint32_t value = 0;
176 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
177 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */
178 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
179 /*
180 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
181 <= OTG_V_BLANK_END
182 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1
183 else
184 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0
185 */
186 if (pipe_dest->htotal != 0) {
187 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
188 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
189 value = 1;
190 } else
191 value = 0;
192 }
193
194 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
195 }
196
hubp2_program_requestor(struct hubp * hubp,struct _vcs_dpi_display_rq_regs_st * rq_regs)197 static void hubp2_program_requestor(struct hubp *hubp,
198 struct _vcs_dpi_display_rq_regs_st *rq_regs)
199 {
200 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
201
202 REG_UPDATE(HUBPRET_CONTROL,
203 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
204 REG_SET_4(DCN_EXPANSION_MODE, 0,
205 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
206 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
207 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
208 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
209 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
211 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
212 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
213 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
214 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
215 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
216 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
217 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
218 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
219 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
220 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
221 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
222 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
223 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
224 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
225 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
226 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
227 }
228
hubp2_setup(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)229 static void hubp2_setup(
230 struct hubp *hubp,
231 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
232 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
233 struct _vcs_dpi_display_rq_regs_st *rq_regs,
234 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
235 {
236 /* otg is locked when this func is called. Register are double buffered.
237 * disable the requestors is not needed
238 */
239
240 hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
241 hubp2_program_requestor(hubp, rq_regs);
242 hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
243
244 }
245
hubp2_setup_interdependent(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)246 void hubp2_setup_interdependent(
247 struct hubp *hubp,
248 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
249 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
250 {
251 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
252
253 REG_SET_2(PREFETCH_SETTINGS, 0,
254 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
255 VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
256
257 REG_SET(PREFETCH_SETTINGS_C, 0,
258 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
259
260 REG_SET_2(VBLANK_PARAMETERS_0, 0,
261 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
262 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
263
264 REG_SET_2(FLIP_PARAMETERS_0, 0,
265 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,
266 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
267
268 REG_SET(VBLANK_PARAMETERS_3, 0,
269 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
270
271 REG_SET(VBLANK_PARAMETERS_4, 0,
272 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
273
274 REG_SET(FLIP_PARAMETERS_2, 0,
275 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);
276
277 REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
278 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
279 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
280
281 REG_SET(DCN_SURF0_TTU_CNTL1, 0,
282 REFCYC_PER_REQ_DELIVERY_PRE,
283 ttu_attr->refcyc_per_req_delivery_pre_l);
284 REG_SET(DCN_SURF1_TTU_CNTL1, 0,
285 REFCYC_PER_REQ_DELIVERY_PRE,
286 ttu_attr->refcyc_per_req_delivery_pre_c);
287 REG_SET(DCN_CUR0_TTU_CNTL1, 0,
288 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
289 REG_SET(DCN_CUR1_TTU_CNTL1, 0,
290 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);
291
292 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
293 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
294 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
295 }
296
297 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used:
298 * NUM_BANKS
299 * NUM_SE
300 * NUM_RB_PER_SE
301 * RB_ALIGNED
302 * Other things can be defaulted, since they never change:
303 * PIPE_ALIGNED = 0
304 * META_LINEAR = 0
305 * In GFX10, only these apply:
306 * PIPE_INTERLEAVE
307 * NUM_PIPES
308 * MAX_COMPRESSED_FRAGS
309 * SW_MODE
310 */
hubp2_program_tiling(struct dcn20_hubp * hubp2,const struct dc_tiling_info * info,const enum surface_pixel_format pixel_format)311 static void hubp2_program_tiling(
312 struct dcn20_hubp *hubp2,
313 const struct dc_tiling_info *info,
314 const enum surface_pixel_format pixel_format)
315 {
316 REG_UPDATE_3(DCSURF_ADDR_CONFIG,
317 NUM_PIPES, log_2(info->gfx9.num_pipes),
318 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
319 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
320
321 REG_UPDATE_4(DCSURF_TILING_CONFIG,
322 SW_MODE, info->gfx9.swizzle,
323 META_LINEAR, 0,
324 RB_ALIGNED, 0,
325 PIPE_ALIGNED, 0);
326 }
327
hubp2_program_size(struct hubp * hubp,enum surface_pixel_format format,const struct plane_size * plane_size,struct dc_plane_dcc_param * dcc)328 void hubp2_program_size(
329 struct hubp *hubp,
330 enum surface_pixel_format format,
331 const struct plane_size *plane_size,
332 struct dc_plane_dcc_param *dcc)
333 {
334 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
335 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
336 bool use_pitch_c = false;
337
338 /* Program data and meta surface pitch (calculation from addrlib)
339 * 444 or 420 luma
340 */
341 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
342 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
343 use_pitch_c = use_pitch_c
344 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
345 if (use_pitch_c) {
346 ASSERT(plane_size->chroma_pitch != 0);
347 /* Chroma pitch zero can cause system hang! */
348
349 pitch = plane_size->surface_pitch - 1;
350 meta_pitch = dcc->meta_pitch - 1;
351 pitch_c = plane_size->chroma_pitch - 1;
352 meta_pitch_c = dcc->meta_pitch_c - 1;
353 } else {
354 pitch = plane_size->surface_pitch - 1;
355 meta_pitch = dcc->meta_pitch - 1;
356 pitch_c = 0;
357 meta_pitch_c = 0;
358 }
359
360 if (!dcc->enable) {
361 meta_pitch = 0;
362 meta_pitch_c = 0;
363 }
364
365 REG_UPDATE_2(DCSURF_SURFACE_PITCH,
366 PITCH, pitch, META_PITCH, meta_pitch);
367
368 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
369 use_pitch_c = use_pitch_c
370 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
371 if (use_pitch_c)
372 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
373 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
374 }
375
hubp2_program_rotation(struct hubp * hubp,enum dc_rotation_angle rotation,bool horizontal_mirror)376 void hubp2_program_rotation(
377 struct hubp *hubp,
378 enum dc_rotation_angle rotation,
379 bool horizontal_mirror)
380 {
381 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
382 uint32_t mirror;
383
384
385 if (horizontal_mirror)
386 mirror = 1;
387 else
388 mirror = 0;
389
390 /* Program rotation angle and horz mirror - no mirror */
391 if (rotation == ROTATION_ANGLE_0)
392 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
393 ROTATION_ANGLE, 0,
394 H_MIRROR_EN, mirror);
395 else if (rotation == ROTATION_ANGLE_90)
396 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
397 ROTATION_ANGLE, 1,
398 H_MIRROR_EN, mirror);
399 else if (rotation == ROTATION_ANGLE_180)
400 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
401 ROTATION_ANGLE, 2,
402 H_MIRROR_EN, mirror);
403 else if (rotation == ROTATION_ANGLE_270)
404 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
405 ROTATION_ANGLE, 3,
406 H_MIRROR_EN, mirror);
407 }
408
hubp2_clear_tiling(struct hubp * hubp)409 void hubp2_clear_tiling(struct hubp *hubp)
410 {
411 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
412
413 REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);
414 REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);
415
416 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
417 PRIMARY_SURFACE_DCC_EN, 0,
418 PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,
419 SECONDARY_SURFACE_DCC_EN, 0,
420 SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);
421 }
422
hubp2_dcc_control(struct hubp * hubp,bool enable,enum hubp_ind_block_size independent_64b_blks)423 void hubp2_dcc_control(struct hubp *hubp, bool enable,
424 enum hubp_ind_block_size independent_64b_blks)
425 {
426 uint32_t dcc_en = enable ? 1 : 0;
427 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
428 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
429
430 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
431 PRIMARY_SURFACE_DCC_EN, dcc_en,
432 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
433 SECONDARY_SURFACE_DCC_EN, dcc_en,
434 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
435 }
436
hubp2_program_pixel_format(struct hubp * hubp,enum surface_pixel_format format)437 void hubp2_program_pixel_format(
438 struct hubp *hubp,
439 enum surface_pixel_format format)
440 {
441 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
442 uint32_t red_bar = 3;
443 uint32_t blue_bar = 2;
444
445 /* swap for ABGR format */
446 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
447 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
448 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
449 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
450 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
451 red_bar = 2;
452 blue_bar = 3;
453 }
454
455 REG_UPDATE_2(HUBPRET_CONTROL,
456 CROSSBAR_SRC_CB_B, blue_bar,
457 CROSSBAR_SRC_CR_R, red_bar);
458
459 /* Mapping is same as ipp programming (cnvc) */
460
461 switch (format) {
462 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
463 REG_UPDATE(DCSURF_SURFACE_CONFIG,
464 SURFACE_PIXEL_FORMAT, 1);
465 break;
466 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
467 REG_UPDATE(DCSURF_SURFACE_CONFIG,
468 SURFACE_PIXEL_FORMAT, 3);
469 break;
470 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
471 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
472 REG_UPDATE(DCSURF_SURFACE_CONFIG,
473 SURFACE_PIXEL_FORMAT, 8);
474 break;
475 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
476 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
477 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
478 REG_UPDATE(DCSURF_SURFACE_CONFIG,
479 SURFACE_PIXEL_FORMAT, 10);
480 break;
481 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
482 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
483 REG_UPDATE(DCSURF_SURFACE_CONFIG,
484 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
485 break;
486 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
487 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
488 REG_UPDATE(DCSURF_SURFACE_CONFIG,
489 SURFACE_PIXEL_FORMAT, 24);
490 break;
491
492 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
493 REG_UPDATE(DCSURF_SURFACE_CONFIG,
494 SURFACE_PIXEL_FORMAT, 65);
495 break;
496 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
497 REG_UPDATE(DCSURF_SURFACE_CONFIG,
498 SURFACE_PIXEL_FORMAT, 64);
499 break;
500 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
501 REG_UPDATE(DCSURF_SURFACE_CONFIG,
502 SURFACE_PIXEL_FORMAT, 67);
503 break;
504 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
505 REG_UPDATE(DCSURF_SURFACE_CONFIG,
506 SURFACE_PIXEL_FORMAT, 66);
507 break;
508 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
509 REG_UPDATE(DCSURF_SURFACE_CONFIG,
510 SURFACE_PIXEL_FORMAT, 12);
511 break;
512 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
513 REG_UPDATE(DCSURF_SURFACE_CONFIG,
514 SURFACE_PIXEL_FORMAT, 112);
515 break;
516 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
517 REG_UPDATE(DCSURF_SURFACE_CONFIG,
518 SURFACE_PIXEL_FORMAT, 113);
519 break;
520 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
521 REG_UPDATE(DCSURF_SURFACE_CONFIG,
522 SURFACE_PIXEL_FORMAT, 114);
523 break;
524 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
525 REG_UPDATE(DCSURF_SURFACE_CONFIG,
526 SURFACE_PIXEL_FORMAT, 118);
527 break;
528 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
529 REG_UPDATE(DCSURF_SURFACE_CONFIG,
530 SURFACE_PIXEL_FORMAT, 119);
531 break;
532 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
533 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
534 SURFACE_PIXEL_FORMAT, 116,
535 ALPHA_PLANE_EN, 0);
536 break;
537 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
538 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
539 SURFACE_PIXEL_FORMAT, 116,
540 ALPHA_PLANE_EN, 1);
541 break;
542 default:
543 BREAK_TO_DEBUGGER();
544 break;
545 }
546
547 /* don't see the need of program the xbar in DCN 1.0 */
548 }
549
hubp2_program_surface_config(struct hubp * hubp,enum surface_pixel_format format,struct dc_tiling_info * tiling_info,struct plane_size * plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror,unsigned int compat_level)550 void hubp2_program_surface_config(
551 struct hubp *hubp,
552 enum surface_pixel_format format,
553 struct dc_tiling_info *tiling_info,
554 struct plane_size *plane_size,
555 enum dc_rotation_angle rotation,
556 struct dc_plane_dcc_param *dcc,
557 bool horizontal_mirror,
558 unsigned int compat_level)
559 {
560 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
561
562 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
563 hubp2_program_tiling(hubp2, tiling_info, format);
564 hubp2_program_size(hubp, format, plane_size, dcc);
565 hubp2_program_rotation(hubp, rotation, horizontal_mirror);
566 hubp2_program_pixel_format(hubp, format);
567 }
568
hubp2_get_lines_per_chunk(unsigned int cursor_width,enum dc_cursor_color_format cursor_mode)569 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
570 unsigned int cursor_width,
571 enum dc_cursor_color_format cursor_mode)
572 {
573 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
574
575 if (cursor_mode == CURSOR_MODE_MONO)
576 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
577 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND ||
578 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
579 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
580 if (cursor_width >= 1 && cursor_width <= 32)
581 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
582 else if (cursor_width >= 33 && cursor_width <= 64)
583 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
584 else if (cursor_width >= 65 && cursor_width <= 128)
585 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
586 else if (cursor_width >= 129 && cursor_width <= 256)
587 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
588 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED ||
589 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) {
590 if (cursor_width >= 1 && cursor_width <= 16)
591 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
592 else if (cursor_width >= 17 && cursor_width <= 32)
593 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
594 else if (cursor_width >= 33 && cursor_width <= 64)
595 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
596 else if (cursor_width >= 65 && cursor_width <= 128)
597 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
598 else if (cursor_width >= 129 && cursor_width <= 256)
599 line_per_chunk = CURSOR_LINE_PER_CHUNK_1;
600 }
601
602 return line_per_chunk;
603 }
604
hubp2_cursor_set_attributes(struct hubp * hubp,const struct dc_cursor_attributes * attr)605 void hubp2_cursor_set_attributes(
606 struct hubp *hubp,
607 const struct dc_cursor_attributes *attr)
608 {
609 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
610 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
611 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
612 attr->width, attr->color_format);
613
614 hubp->curs_attr = *attr;
615
616 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
617 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
618 REG_UPDATE(CURSOR_SURFACE_ADDRESS,
619 CURSOR_SURFACE_ADDRESS, attr->address.low_part);
620
621 REG_UPDATE_2(CURSOR_SIZE,
622 CURSOR_WIDTH, attr->width,
623 CURSOR_HEIGHT, attr->height);
624
625 REG_UPDATE_4(CURSOR_CONTROL,
626 CURSOR_MODE, attr->color_format,
627 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
628 CURSOR_PITCH, hw_pitch,
629 CURSOR_LINES_PER_CHUNK, lpc);
630
631 REG_SET_2(CURSOR_SETTINGS, 0,
632 /* no shift of the cursor HDL schedule */
633 CURSOR0_DST_Y_OFFSET, 0,
634 /* used to shift the cursor chunk request deadline */
635 CURSOR0_CHUNK_HDL_ADJUST, 3);
636
637 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part;
638 hubp->att.SURFACE_ADDR = attr->address.low_part;
639 hubp->att.size.bits.width = attr->width;
640 hubp->att.size.bits.height = attr->height;
641 hubp->att.cur_ctl.bits.mode = attr->color_format;
642
643 hubp->cur_rect.w = attr->width;
644 hubp->cur_rect.h = attr->height;
645
646 hubp->att.cur_ctl.bits.pitch = hw_pitch;
647 hubp->att.cur_ctl.bits.line_per_chunk = lpc;
648 hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;
649 hubp->att.settings.bits.dst_y_offset = 0;
650 hubp->att.settings.bits.chunk_hdl_adjust = 3;
651 }
652
hubp2_dmdata_set_attributes(struct hubp * hubp,const struct dc_dmdata_attributes * attr)653 void hubp2_dmdata_set_attributes(
654 struct hubp *hubp,
655 const struct dc_dmdata_attributes *attr)
656 {
657 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
658
659 if (attr->dmdata_mode == DMDATA_HW_MODE) {
660 /* set to HW mode */
661 REG_UPDATE(DMDATA_CNTL,
662 DMDATA_MODE, 1);
663
664 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
665 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
666
667 /* toggle DMDATA_UPDATED and set repeat and size */
668 REG_UPDATE(DMDATA_CNTL,
669 DMDATA_UPDATED, 0);
670 REG_UPDATE_3(DMDATA_CNTL,
671 DMDATA_UPDATED, 1,
672 DMDATA_REPEAT, attr->dmdata_repeat,
673 DMDATA_SIZE, attr->dmdata_size);
674
675 /* set DMDATA address */
676 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
677 REG_UPDATE(DMDATA_ADDRESS_HIGH,
678 DMDATA_ADDRESS_HIGH, attr->address.high_part);
679
680 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
681
682 } else {
683 /* set to SW mode before loading data */
684 REG_SET(DMDATA_CNTL, 0,
685 DMDATA_MODE, 0);
686 /* toggle DMDATA_SW_UPDATED to start loading sequence */
687 REG_UPDATE(DMDATA_SW_CNTL,
688 DMDATA_SW_UPDATED, 0);
689 REG_UPDATE_3(DMDATA_SW_CNTL,
690 DMDATA_SW_UPDATED, 1,
691 DMDATA_SW_REPEAT, attr->dmdata_repeat,
692 DMDATA_SW_SIZE, attr->dmdata_size);
693 /* load data into hubp dmdata buffer */
694 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);
695 }
696
697 /* Note that DL_DELTA must be programmed if we want to use TTU mode */
698 REG_SET_3(DMDATA_QOS_CNTL, 0,
699 DMDATA_QOS_MODE, attr->dmdata_qos_mode,
700 DMDATA_QOS_LEVEL, attr->dmdata_qos_level,
701 DMDATA_DL_DELTA, attr->dmdata_dl_delta);
702 }
703
hubp2_dmdata_load(struct hubp * hubp,uint32_t dmdata_sw_size,const uint32_t * dmdata_sw_data)704 void hubp2_dmdata_load(
705 struct hubp *hubp,
706 uint32_t dmdata_sw_size,
707 const uint32_t *dmdata_sw_data)
708 {
709 int i;
710 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
711
712 /* load dmdata into HUBP buffer in SW mode */
713 for (i = 0; i < dmdata_sw_size / 4; i++)
714 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
715 }
716
hubp2_dmdata_status_done(struct hubp * hubp)717 bool hubp2_dmdata_status_done(struct hubp *hubp)
718 {
719 uint32_t status;
720 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
721
722 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
723 return (status == 1);
724 }
725
hubp2_program_surface_flip_and_addr(struct hubp * hubp,const struct dc_plane_address * address,bool flip_immediate)726 bool hubp2_program_surface_flip_and_addr(
727 struct hubp *hubp,
728 const struct dc_plane_address *address,
729 bool flip_immediate)
730 {
731 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
732
733 //program flip type
734 REG_UPDATE(DCSURF_FLIP_CONTROL,
735 SURFACE_FLIP_TYPE, flip_immediate);
736
737 // Program VMID reg
738 REG_UPDATE(VMID_SETTINGS_0,
739 VMID, address->vmid);
740
741
742 /* HW automatically latch rest of address register on write to
743 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
744 *
745 * program high first and then the low addr, order matters!
746 */
747 switch (address->type) {
748 case PLN_ADDR_TYPE_GRAPHICS:
749 /* DCN1.0 does not support const color
750 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
751 * base on address->grph.dcc_const_color
752 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
753 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
754 */
755
756 if (address->grph.addr.quad_part == 0)
757 break;
758
759 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
760 PRIMARY_SURFACE_TMZ, address->tmz_surface,
761 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
762
763 if (address->grph.meta_addr.quad_part != 0) {
764 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
765 PRIMARY_META_SURFACE_ADDRESS_HIGH,
766 address->grph.meta_addr.high_part);
767
768 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
769 PRIMARY_META_SURFACE_ADDRESS,
770 address->grph.meta_addr.low_part);
771 }
772
773 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
774 PRIMARY_SURFACE_ADDRESS_HIGH,
775 address->grph.addr.high_part);
776
777 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
778 PRIMARY_SURFACE_ADDRESS,
779 address->grph.addr.low_part);
780 break;
781 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
782 if (address->video_progressive.luma_addr.quad_part == 0
783 || address->video_progressive.chroma_addr.quad_part == 0)
784 break;
785
786 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
787 PRIMARY_SURFACE_TMZ, address->tmz_surface,
788 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
789 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
790 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
791
792 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
793 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
794 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
795 address->video_progressive.chroma_meta_addr.high_part);
796
797 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
798 PRIMARY_META_SURFACE_ADDRESS_C,
799 address->video_progressive.chroma_meta_addr.low_part);
800
801 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
802 PRIMARY_META_SURFACE_ADDRESS_HIGH,
803 address->video_progressive.luma_meta_addr.high_part);
804
805 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
806 PRIMARY_META_SURFACE_ADDRESS,
807 address->video_progressive.luma_meta_addr.low_part);
808 }
809
810 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
811 PRIMARY_SURFACE_ADDRESS_HIGH_C,
812 address->video_progressive.chroma_addr.high_part);
813
814 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
815 PRIMARY_SURFACE_ADDRESS_C,
816 address->video_progressive.chroma_addr.low_part);
817
818 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
819 PRIMARY_SURFACE_ADDRESS_HIGH,
820 address->video_progressive.luma_addr.high_part);
821
822 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
823 PRIMARY_SURFACE_ADDRESS,
824 address->video_progressive.luma_addr.low_part);
825 break;
826 case PLN_ADDR_TYPE_GRPH_STEREO:
827 if (address->grph_stereo.left_addr.quad_part == 0)
828 break;
829 if (address->grph_stereo.right_addr.quad_part == 0)
830 break;
831
832 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
833 PRIMARY_SURFACE_TMZ, address->tmz_surface,
834 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
835 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
836 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
837 SECONDARY_SURFACE_TMZ, address->tmz_surface,
838 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
839 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
840 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
841
842 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
843
844 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
845 SECONDARY_META_SURFACE_ADDRESS_HIGH,
846 address->grph_stereo.right_meta_addr.high_part);
847
848 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
849 SECONDARY_META_SURFACE_ADDRESS,
850 address->grph_stereo.right_meta_addr.low_part);
851 }
852 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
853
854 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
855 PRIMARY_META_SURFACE_ADDRESS_HIGH,
856 address->grph_stereo.left_meta_addr.high_part);
857
858 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
859 PRIMARY_META_SURFACE_ADDRESS,
860 address->grph_stereo.left_meta_addr.low_part);
861 }
862
863 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
864 SECONDARY_SURFACE_ADDRESS_HIGH,
865 address->grph_stereo.right_addr.high_part);
866
867 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
868 SECONDARY_SURFACE_ADDRESS,
869 address->grph_stereo.right_addr.low_part);
870
871 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
872 PRIMARY_SURFACE_ADDRESS_HIGH,
873 address->grph_stereo.left_addr.high_part);
874
875 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
876 PRIMARY_SURFACE_ADDRESS,
877 address->grph_stereo.left_addr.low_part);
878 break;
879 default:
880 BREAK_TO_DEBUGGER();
881 break;
882 }
883
884 hubp->request_address = *address;
885
886 return true;
887 }
888
hubp2_enable_triplebuffer(struct hubp * hubp,bool enable)889 void hubp2_enable_triplebuffer(
890 struct hubp *hubp,
891 bool enable)
892 {
893 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
894 uint32_t triple_buffer_en = 0;
895 bool tri_buffer_en;
896
897 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
898 tri_buffer_en = (triple_buffer_en == 1);
899 if (tri_buffer_en != enable) {
900 REG_UPDATE(DCSURF_FLIP_CONTROL2,
901 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);
902 }
903 }
904
hubp2_is_triplebuffer_enabled(struct hubp * hubp)905 bool hubp2_is_triplebuffer_enabled(
906 struct hubp *hubp)
907 {
908 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
909 uint32_t triple_buffer_en = 0;
910
911 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
912
913 return (bool)triple_buffer_en;
914 }
915
hubp2_set_flip_control_surface_gsl(struct hubp * hubp,bool enable)916 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
917 {
918 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
919
920 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
921 }
922
hubp2_is_flip_pending(struct hubp * hubp)923 bool hubp2_is_flip_pending(struct hubp *hubp)
924 {
925 uint32_t flip_pending = 0;
926 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
927 struct dc_plane_address earliest_inuse_address;
928
929 if (hubp && hubp->power_gated)
930 return false;
931
932 REG_GET(DCSURF_FLIP_CONTROL,
933 SURFACE_FLIP_PENDING, &flip_pending);
934
935 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
936 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
937
938 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
939 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
940
941 if (flip_pending)
942 return true;
943
944 if (hubp &&
945 earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
946 return true;
947
948 return false;
949 }
950
hubp2_set_blank(struct hubp * hubp,bool blank)951 void hubp2_set_blank(struct hubp *hubp, bool blank)
952 {
953 hubp2_set_blank_regs(hubp, blank);
954
955 if (blank) {
956 hubp->mpcc_id = 0xf;
957 hubp->opp_id = OPP_ID_INVALID;
958 }
959 }
960
hubp2_set_blank_regs(struct hubp * hubp,bool blank)961 void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
962 {
963 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
964 uint32_t blank_en = blank ? 1 : 0;
965
966 if (blank) {
967 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
968
969 if (reg_val) {
970 /* init sequence workaround: in case HUBP is
971 * power gated, this wait would timeout.
972 *
973 * we just wrote reg_val to non-0, if it stay 0
974 * it means HUBP is gated
975 */
976 REG_WAIT(DCHUBP_CNTL,
977 HUBP_NO_OUTSTANDING_REQ, 1,
978 1, 100000);
979 }
980 }
981
982 REG_UPDATE_2(DCHUBP_CNTL,
983 HUBP_BLANK_EN, blank_en,
984 HUBP_TTU_DISABLE, 0);
985 }
986
hubp2_cursor_set_position(struct hubp * hubp,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param)987 void hubp2_cursor_set_position(
988 struct hubp *hubp,
989 const struct dc_cursor_position *pos,
990 const struct dc_cursor_mi_param *param)
991 {
992 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
993 int x_pos = pos->x - param->viewport.x;
994 int y_pos = pos->y - param->viewport.y;
995 int x_hotspot = pos->x_hotspot;
996 int y_hotspot = pos->y_hotspot;
997 int src_x_offset = x_pos - pos->x_hotspot;
998 int src_y_offset = y_pos - pos->y_hotspot;
999 int cursor_height = (int)hubp->curs_attr.height;
1000 int cursor_width = (int)hubp->curs_attr.width;
1001 uint32_t dst_x_offset;
1002 uint32_t cur_en = pos->enable ? 1 : 0;
1003
1004 hubp->curs_pos = *pos;
1005
1006 /*
1007 * Guard aganst cursor_set_position() from being called with invalid
1008 * attributes
1009 *
1010 * TODO: Look at combining cursor_set_position() and
1011 * cursor_set_attributes() into cursor_update()
1012 */
1013 if (hubp->curs_attr.address.quad_part == 0)
1014 return;
1015
1016 // Transform cursor width / height and hotspots for offset calculations
1017 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
1018 swap(cursor_height, cursor_width);
1019 swap(x_hotspot, y_hotspot);
1020
1021 if (param->rotation == ROTATION_ANGLE_90) {
1022 // hotspot = (-y, x)
1023 src_x_offset = x_pos - (cursor_width - x_hotspot);
1024 src_y_offset = y_pos - y_hotspot;
1025 } else if (param->rotation == ROTATION_ANGLE_270) {
1026 // hotspot = (y, -x)
1027 src_x_offset = x_pos - x_hotspot;
1028 src_y_offset = y_pos - (cursor_height - y_hotspot);
1029 }
1030 } else if (param->rotation == ROTATION_ANGLE_180) {
1031 // hotspot = (-x, -y)
1032 if (!param->mirror)
1033 src_x_offset = x_pos - (cursor_width - x_hotspot);
1034
1035 src_y_offset = y_pos - (cursor_height - y_hotspot);
1036 }
1037
1038 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1039 dst_x_offset *= param->ref_clk_khz;
1040 dst_x_offset /= param->pixel_clk_khz;
1041
1042 ASSERT(param->h_scale_ratio.value);
1043
1044 if (param->h_scale_ratio.value)
1045 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1046 dc_fixpt_from_int(dst_x_offset),
1047 param->h_scale_ratio));
1048
1049 if (src_x_offset >= (int)param->viewport.width)
1050 cur_en = 0; /* not visible beyond right edge*/
1051
1052 if (src_x_offset + cursor_width <= 0)
1053 cur_en = 0; /* not visible beyond left edge*/
1054
1055 if (src_y_offset >= (int)param->viewport.height)
1056 cur_en = 0; /* not visible beyond bottom edge*/
1057
1058 if (src_y_offset + cursor_height <= 0)
1059 cur_en = 0; /* not visible beyond top edge*/
1060
1061 if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {
1062 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1063 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1064
1065 REG_UPDATE(CURSOR_CONTROL,
1066 CURSOR_ENABLE, cur_en);
1067 }
1068
1069 REG_SET_2(CURSOR_POSITION, 0,
1070 CURSOR_X_POSITION, pos->x,
1071 CURSOR_Y_POSITION, pos->y);
1072
1073 REG_SET_2(CURSOR_HOT_SPOT, 0,
1074 CURSOR_HOT_SPOT_X, pos->x_hotspot,
1075 CURSOR_HOT_SPOT_Y, pos->y_hotspot);
1076
1077 REG_SET(CURSOR_DST_OFFSET, 0,
1078 CURSOR_DST_X_OFFSET, dst_x_offset);
1079 /* TODO Handle surface pixel formats other than 4:4:4 */
1080 /* Cursor Position Register Config */
1081 hubp->pos.cur_ctl.bits.cur_enable = cur_en;
1082 hubp->pos.position.bits.x_pos = pos->x;
1083 hubp->pos.position.bits.y_pos = pos->y;
1084 hubp->pos.hot_spot.bits.x_hot = pos->x_hotspot;
1085 hubp->pos.hot_spot.bits.y_hot = pos->y_hotspot;
1086 hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;
1087 /* Cursor Rectangle Cache
1088 * Cursor bitmaps have different hotspot values
1089 * There's a possibility that the above logic returns a negative value,
1090 * so we clamp them to 0
1091 */
1092 if (src_x_offset < 0)
1093 src_x_offset = 0;
1094 if (src_y_offset < 0)
1095 src_y_offset = 0;
1096 /* Save necessary cursor info x, y position. w, h is saved in attribute func. */
1097 if (param->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
1098 param->rotation != ROTATION_ANGLE_0) {
1099 hubp->cur_rect.x = 0;
1100 hubp->cur_rect.y = 0;
1101 hubp->cur_rect.w = param->stream->timing.h_addressable;
1102 hubp->cur_rect.h = param->stream->timing.v_addressable;
1103 } else {
1104 hubp->cur_rect.x = src_x_offset + param->viewport.x;
1105 hubp->cur_rect.y = src_y_offset + param->viewport.y;
1106 }
1107 }
1108
hubp2_clk_cntl(struct hubp * hubp,bool enable)1109 void hubp2_clk_cntl(struct hubp *hubp, bool enable)
1110 {
1111 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1112 uint32_t clk_enable = enable ? 1 : 0;
1113
1114 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1115 }
1116
hubp2_vtg_sel(struct hubp * hubp,uint32_t otg_inst)1117 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1118 {
1119 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1120
1121 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1122 }
1123
hubp2_clear_underflow(struct hubp * hubp)1124 void hubp2_clear_underflow(struct hubp *hubp)
1125 {
1126 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1127
1128 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
1129 }
1130
hubp2_read_state_common(struct hubp * hubp)1131 void hubp2_read_state_common(struct hubp *hubp)
1132 {
1133 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1134 struct dcn_hubp_state *s = &hubp2->state;
1135 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
1136 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
1137 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1138
1139 /* Requester */
1140 REG_GET(HUBPRET_CONTROL,
1141 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
1142 REG_GET_4(DCN_EXPANSION_MODE,
1143 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
1144 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
1145 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
1146 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
1147
1148 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
1149 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);
1150
1151 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
1152 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);
1153
1154 /* DLG - Per hubp */
1155 REG_GET_2(BLANK_OFFSET_0,
1156 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
1157 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
1158
1159 REG_GET(BLANK_OFFSET_1,
1160 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1161
1162 REG_GET(DST_DIMENSIONS,
1163 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
1164
1165 REG_GET_2(DST_AFTER_SCALER,
1166 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
1167 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
1168
1169 if (REG(PREFETCH_SETTINS))
1170 REG_GET_2(PREFETCH_SETTINS,
1171 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1172 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1173 else
1174 REG_GET_2(PREFETCH_SETTINGS,
1175 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1176 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1177
1178 REG_GET_2(VBLANK_PARAMETERS_0,
1179 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
1180 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
1181
1182 REG_GET(REF_FREQ_TO_PIX_FREQ,
1183 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
1184
1185 /* DLG - Per luma/chroma */
1186 REG_GET(VBLANK_PARAMETERS_1,
1187 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
1188
1189 REG_GET(VBLANK_PARAMETERS_3,
1190 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
1191
1192 if (REG(NOM_PARAMETERS_0))
1193 REG_GET(NOM_PARAMETERS_0,
1194 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
1195
1196 if (REG(NOM_PARAMETERS_1))
1197 REG_GET(NOM_PARAMETERS_1,
1198 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
1199
1200 REG_GET(NOM_PARAMETERS_4,
1201 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
1202
1203 REG_GET(NOM_PARAMETERS_5,
1204 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
1205
1206 REG_GET_2(PER_LINE_DELIVERY_PRE,
1207 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
1208 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
1209
1210 REG_GET_2(PER_LINE_DELIVERY,
1211 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
1212 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
1213
1214 if (REG(PREFETCH_SETTINS_C))
1215 REG_GET(PREFETCH_SETTINS_C,
1216 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1217 else
1218 REG_GET(PREFETCH_SETTINGS_C,
1219 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1220
1221 REG_GET(VBLANK_PARAMETERS_2,
1222 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
1223
1224 REG_GET(VBLANK_PARAMETERS_4,
1225 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
1226
1227 if (REG(NOM_PARAMETERS_2))
1228 REG_GET(NOM_PARAMETERS_2,
1229 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
1230
1231 if (REG(NOM_PARAMETERS_3))
1232 REG_GET(NOM_PARAMETERS_3,
1233 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
1234
1235 REG_GET(NOM_PARAMETERS_6,
1236 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
1237
1238 REG_GET(NOM_PARAMETERS_7,
1239 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
1240
1241 /* TTU - per hubp */
1242 REG_GET_2(DCN_TTU_QOS_WM,
1243 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
1244 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1245
1246 REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1247 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1248 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1249
1250 /* TTU - per luma/chroma */
1251 /* Assumed surf0 is luma and 1 is chroma */
1252
1253 REG_GET_3(DCN_SURF0_TTU_CNTL0,
1254 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1255 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1256 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1257
1258 REG_GET(DCN_SURF0_TTU_CNTL1,
1259 REFCYC_PER_REQ_DELIVERY_PRE,
1260 &ttu_attr->refcyc_per_req_delivery_pre_l);
1261
1262 REG_GET_3(DCN_SURF1_TTU_CNTL0,
1263 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1264 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1265 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1266
1267 REG_GET(DCN_SURF1_TTU_CNTL1,
1268 REFCYC_PER_REQ_DELIVERY_PRE,
1269 &ttu_attr->refcyc_per_req_delivery_pre_c);
1270
1271 /* Rest of hubp */
1272 REG_GET(DCSURF_SURFACE_CONFIG,
1273 SURFACE_PIXEL_FORMAT, &s->pixel_format);
1274
1275 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1276 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1277
1278 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1279 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1280
1281 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1282 PRI_VIEWPORT_WIDTH, &s->viewport_width,
1283 PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1284
1285 REG_GET_2(DCSURF_SURFACE_CONFIG,
1286 ROTATION_ANGLE, &s->rotation_angle,
1287 H_MIRROR_EN, &s->h_mirror_en);
1288
1289 REG_GET(DCSURF_TILING_CONFIG,
1290 SW_MODE, &s->sw_mode);
1291
1292 REG_GET(DCSURF_SURFACE_CONTROL,
1293 PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1294
1295 REG_GET_3(DCHUBP_CNTL,
1296 HUBP_BLANK_EN, &s->blank_en,
1297 HUBP_TTU_DISABLE, &s->ttu_disable,
1298 HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1299
1300 REG_GET(HUBP_CLK_CNTL,
1301 HUBP_CLOCK_ENABLE, &s->clock_en);
1302
1303 REG_GET(DCN_GLOBAL_TTU_CNTL,
1304 MIN_TTU_VBLANK, &s->min_ttu_vblank);
1305
1306 REG_GET_2(DCN_TTU_QOS_WM,
1307 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1308 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1309
1310 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1311 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1312
1313 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1314 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1315
1316 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1317 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1318
1319 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1320 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1321 }
1322
hubp2_read_state(struct hubp * hubp)1323 void hubp2_read_state(struct hubp *hubp)
1324 {
1325 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1326 struct dcn_hubp_state *s = &hubp2->state;
1327 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1328
1329 hubp2_read_state_common(hubp);
1330
1331 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1332 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1333 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1334 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1335 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1336 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1337 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1338 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1339 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1340
1341 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1342 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1343 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1344 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1345 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1346 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1347 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1348 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1349 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1350
1351 if (REG(DCHUBP_CNTL))
1352 s->hubp_cntl = REG_READ(DCHUBP_CNTL);
1353
1354 if (REG(DCSURF_FLIP_CONTROL))
1355 s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
1356
1357 }
1358
hubp2_validate_dml_output(struct hubp * hubp,struct dc_context * ctx,struct _vcs_dpi_display_rq_regs_st * dml_rq_regs,struct _vcs_dpi_display_dlg_regs_st * dml_dlg_attr,struct _vcs_dpi_display_ttu_regs_st * dml_ttu_attr)1359 static void hubp2_validate_dml_output(struct hubp *hubp,
1360 struct dc_context *ctx,
1361 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
1362 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
1363 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
1364 {
1365 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1366 struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
1367 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
1368 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
1369 DC_LOGGER_INIT(ctx->logger);
1370 DC_LOG_DEBUG("DML Validation | Running Validation");
1371
1372 /* Requestor Regs */
1373 REG_GET(HUBPRET_CONTROL,
1374 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
1375 REG_GET_4(DCN_EXPANSION_MODE,
1376 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
1377 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
1378 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
1379 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
1380 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1381 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
1382 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
1383 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
1384 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
1385 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
1386 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
1387 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
1388 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
1389 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1390 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
1391 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
1392 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
1393 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
1394 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
1395 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
1396 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
1397 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
1398
1399 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
1400 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
1401 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
1402 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
1403 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
1404 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
1405 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
1406 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
1407 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
1408 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
1409 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n",
1410 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
1411 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
1412 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n",
1413 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
1414
1415 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
1416 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",
1417 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
1418 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
1419 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n",
1420 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
1421 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
1422 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n",
1423 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
1424 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
1425 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n",
1426 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
1427 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
1428 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
1429 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
1430 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
1431 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n",
1432 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
1433 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
1434 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n",
1435 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
1436 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
1437 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n",
1438 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
1439
1440 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
1441 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1442 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
1443 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
1444 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1445 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
1446 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
1447 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1448 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
1449 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
1450 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n",
1451 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
1452 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
1453 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
1454 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
1455 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
1456 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n",
1457 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
1458 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
1459 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n",
1460 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
1461 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
1462 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n",
1463 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
1464
1465 /* DLG - Per hubp */
1466 REG_GET_2(BLANK_OFFSET_0,
1467 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
1468 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
1469 REG_GET(BLANK_OFFSET_1,
1470 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1471 REG_GET(DST_DIMENSIONS,
1472 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
1473 REG_GET_2(DST_AFTER_SCALER,
1474 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
1475 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
1476 REG_GET(REF_FREQ_TO_PIX_FREQ,
1477 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
1478
1479 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
1480 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n",
1481 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
1482 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
1483 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n",
1484 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
1485 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1486 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n",
1487 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
1488 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
1489 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n",
1490 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
1491 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
1492 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n",
1493 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
1494 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
1495 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n",
1496 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
1497 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
1498 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n",
1499 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
1500
1501 /* DLG - Per luma/chroma */
1502 REG_GET(VBLANK_PARAMETERS_1,
1503 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
1504 if (REG(NOM_PARAMETERS_0))
1505 REG_GET(NOM_PARAMETERS_0,
1506 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
1507 if (REG(NOM_PARAMETERS_1))
1508 REG_GET(NOM_PARAMETERS_1,
1509 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
1510 REG_GET(NOM_PARAMETERS_4,
1511 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
1512 REG_GET(NOM_PARAMETERS_5,
1513 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
1514 REG_GET_2(PER_LINE_DELIVERY,
1515 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
1516 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
1517 REG_GET_2(PER_LINE_DELIVERY_PRE,
1518 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
1519 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
1520 REG_GET(VBLANK_PARAMETERS_2,
1521 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
1522 if (REG(NOM_PARAMETERS_2))
1523 REG_GET(NOM_PARAMETERS_2,
1524 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
1525 if (REG(NOM_PARAMETERS_3))
1526 REG_GET(NOM_PARAMETERS_3,
1527 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
1528 REG_GET(NOM_PARAMETERS_6,
1529 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
1530 REG_GET(NOM_PARAMETERS_7,
1531 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
1532 REG_GET(VBLANK_PARAMETERS_3,
1533 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
1534 REG_GET(VBLANK_PARAMETERS_4,
1535 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
1536
1537 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
1538 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n",
1539 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
1540 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
1541 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n",
1542 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
1543 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
1544 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n",
1545 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
1546 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
1547 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n",
1548 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
1549 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
1550 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n",
1551 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
1552 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
1553 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n",
1554 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
1555 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
1556 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n",
1557 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
1558 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
1559 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n",
1560 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
1561 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
1562 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n",
1563 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
1564 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
1565 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n",
1566 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
1567 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
1568 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n",
1569 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
1570 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
1571 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n",
1572 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
1573 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
1574 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n",
1575 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
1576 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
1577 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n",
1578 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
1579 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
1580 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n",
1581 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
1582 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
1583 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n",
1584 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
1585
1586 /* TTU - per hubp */
1587 REG_GET_2(DCN_TTU_QOS_WM,
1588 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
1589 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1590
1591 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
1592 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n",
1593 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
1594 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
1595 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n",
1596 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
1597
1598 /* TTU - per luma/chroma */
1599 /* Assumed surf0 is luma and 1 is chroma */
1600 REG_GET_3(DCN_SURF0_TTU_CNTL0,
1601 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
1602 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
1603 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
1604 REG_GET_3(DCN_SURF1_TTU_CNTL0,
1605 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
1606 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
1607 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
1608 REG_GET_3(DCN_CUR0_TTU_CNTL0,
1609 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
1610 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
1611 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
1612 REG_GET(FLIP_PARAMETERS_1,
1613 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
1614 REG_GET(DCN_CUR0_TTU_CNTL1,
1615 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
1616 REG_GET(DCN_CUR1_TTU_CNTL1,
1617 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
1618 REG_GET(DCN_SURF0_TTU_CNTL1,
1619 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
1620 REG_GET(DCN_SURF1_TTU_CNTL1,
1621 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
1622
1623 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
1624 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
1625 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
1626 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
1627 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
1628 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
1629 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
1630 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
1631 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
1632 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
1633 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
1634 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
1635 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
1636 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
1637 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
1638 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
1639 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
1640 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
1641 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
1642 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n",
1643 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
1644 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
1645 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n",
1646 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
1647 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
1648 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n",
1649 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
1650 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
1651 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n",
1652 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
1653 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
1654 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1655 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
1656 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
1657 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1658 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
1659 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
1660 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1661 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
1662 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
1663 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n",
1664 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
1665 }
1666
1667 static struct hubp_funcs dcn20_hubp_funcs = {
1668 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
1669 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
1670 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
1671 .hubp_program_surface_config = hubp2_program_surface_config,
1672 .hubp_is_flip_pending = hubp2_is_flip_pending,
1673 .hubp_setup = hubp2_setup,
1674 .hubp_setup_interdependent = hubp2_setup_interdependent,
1675 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
1676 .set_blank = hubp2_set_blank,
1677 .set_blank_regs = hubp2_set_blank_regs,
1678 .dcc_control = hubp2_dcc_control,
1679 .hubp_reset = hubp_reset,
1680 .mem_program_viewport = min_set_viewport,
1681 .set_cursor_attributes = hubp2_cursor_set_attributes,
1682 .set_cursor_position = hubp2_cursor_set_position,
1683 .hubp_clk_cntl = hubp2_clk_cntl,
1684 .hubp_vtg_sel = hubp2_vtg_sel,
1685 .dmdata_set_attributes = hubp2_dmdata_set_attributes,
1686 .dmdata_load = hubp2_dmdata_load,
1687 .dmdata_status_done = hubp2_dmdata_status_done,
1688 .hubp_read_state = hubp2_read_state,
1689 .hubp_clear_underflow = hubp2_clear_underflow,
1690 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
1691 .hubp_init = hubp1_init,
1692 .validate_dml_output = hubp2_validate_dml_output,
1693 .hubp_in_blank = hubp1_in_blank,
1694 .hubp_soft_reset = hubp1_soft_reset,
1695 .hubp_set_flip_int = hubp1_set_flip_int,
1696 .hubp_clear_tiling = hubp2_clear_tiling,
1697 };
1698
1699
hubp2_construct(struct dcn20_hubp * hubp2,struct dc_context * ctx,uint32_t inst,const struct dcn_hubp2_registers * hubp_regs,const struct dcn_hubp2_shift * hubp_shift,const struct dcn_hubp2_mask * hubp_mask)1700 bool hubp2_construct(
1701 struct dcn20_hubp *hubp2,
1702 struct dc_context *ctx,
1703 uint32_t inst,
1704 const struct dcn_hubp2_registers *hubp_regs,
1705 const struct dcn_hubp2_shift *hubp_shift,
1706 const struct dcn_hubp2_mask *hubp_mask)
1707 {
1708 hubp2->base.funcs = &dcn20_hubp_funcs;
1709 hubp2->base.ctx = ctx;
1710 hubp2->hubp_regs = hubp_regs;
1711 hubp2->hubp_shift = hubp_shift;
1712 hubp2->hubp_mask = hubp_mask;
1713 hubp2->base.inst = inst;
1714 hubp2->base.opp_id = OPP_ID_INVALID;
1715 hubp2->base.mpcc_id = 0xf;
1716
1717 return true;
1718 }
1719