1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Madhav Chauhan <madhav.chauhan@intel.com>
25 * Jani Nikula <jani.nikula@intel.com>
26 */
27
28 #include <drm/display/drm_dsc_helper.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_fixed.h>
31 #include <drm/drm_mipi_dsi.h>
32 #include <drm/drm_probe_helper.h>
33
34 #include "i915_drv.h"
35 #include "i915_reg.h"
36 #include "icl_dsi.h"
37 #include "icl_dsi_regs.h"
38 #include "intel_atomic.h"
39 #include "intel_backlight.h"
40 #include "intel_backlight_regs.h"
41 #include "intel_combo_phy.h"
42 #include "intel_combo_phy_regs.h"
43 #include "intel_connector.h"
44 #include "intel_crtc.h"
45 #include "intel_ddi.h"
46 #include "intel_de.h"
47 #include "intel_dsi.h"
48 #include "intel_dsi_vbt.h"
49 #include "intel_panel.h"
50 #include "intel_pfit.h"
51 #include "intel_vdsc.h"
52 #include "intel_vdsc_regs.h"
53 #include "skl_scaler.h"
54 #include "skl_universal_plane.h"
55
header_credits_available(struct intel_display * display,enum transcoder dsi_trans)56 static int header_credits_available(struct intel_display *display,
57 enum transcoder dsi_trans)
58 {
59 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
60 >> FREE_HEADER_CREDIT_SHIFT;
61 }
62
payload_credits_available(struct intel_display * display,enum transcoder dsi_trans)63 static int payload_credits_available(struct intel_display *display,
64 enum transcoder dsi_trans)
65 {
66 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
67 >> FREE_PLOAD_CREDIT_SHIFT;
68 }
69
wait_for_header_credits(struct intel_display * display,enum transcoder dsi_trans,int hdr_credit)70 static bool wait_for_header_credits(struct intel_display *display,
71 enum transcoder dsi_trans, int hdr_credit)
72 {
73 if (wait_for_us(header_credits_available(display, dsi_trans) >=
74 hdr_credit, 100)) {
75 drm_err(display->drm, "DSI header credits not released\n");
76 return false;
77 }
78
79 return true;
80 }
81
wait_for_payload_credits(struct intel_display * display,enum transcoder dsi_trans,int payld_credit)82 static bool wait_for_payload_credits(struct intel_display *display,
83 enum transcoder dsi_trans, int payld_credit)
84 {
85 if (wait_for_us(payload_credits_available(display, dsi_trans) >=
86 payld_credit, 100)) {
87 drm_err(display->drm, "DSI payload credits not released\n");
88 return false;
89 }
90
91 return true;
92 }
93
dsi_port_to_transcoder(enum port port)94 static enum transcoder dsi_port_to_transcoder(enum port port)
95 {
96 if (port == PORT_A)
97 return TRANSCODER_DSI_0;
98 else
99 return TRANSCODER_DSI_1;
100 }
101
wait_for_cmds_dispatched_to_panel(struct intel_encoder * encoder)102 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
103 {
104 struct intel_display *display = to_intel_display(encoder);
105 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
106 struct mipi_dsi_device *dsi;
107 enum port port;
108 enum transcoder dsi_trans;
109 int ret;
110
111 /* wait for header/payload credits to be released */
112 for_each_dsi_port(port, intel_dsi->ports) {
113 dsi_trans = dsi_port_to_transcoder(port);
114 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
115 wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
116 }
117
118 /* send nop DCS command */
119 for_each_dsi_port(port, intel_dsi->ports) {
120 dsi = intel_dsi->dsi_hosts[port]->device;
121 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
122 dsi->channel = 0;
123 ret = mipi_dsi_dcs_nop(dsi);
124 if (ret < 0)
125 drm_err(display->drm,
126 "error sending DCS NOP command\n");
127 }
128
129 /* wait for header credits to be released */
130 for_each_dsi_port(port, intel_dsi->ports) {
131 dsi_trans = dsi_port_to_transcoder(port);
132 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
133 }
134
135 /* wait for LP TX in progress bit to be cleared */
136 for_each_dsi_port(port, intel_dsi->ports) {
137 dsi_trans = dsi_port_to_transcoder(port);
138 if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
139 LPTX_IN_PROGRESS), 20))
140 drm_err(display->drm, "LPTX bit not cleared\n");
141 }
142 }
143
dsi_send_pkt_payld(struct intel_dsi_host * host,const struct mipi_dsi_packet * packet)144 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
145 const struct mipi_dsi_packet *packet)
146 {
147 struct intel_dsi *intel_dsi = host->intel_dsi;
148 struct intel_display *display = to_intel_display(&intel_dsi->base);
149 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
150 const u8 *data = packet->payload;
151 u32 len = packet->payload_length;
152 int i, j;
153
154 /* payload queue can accept *256 bytes*, check limit */
155 if (len > MAX_PLOAD_CREDIT * 4) {
156 drm_err(display->drm, "payload size exceeds max queue limit\n");
157 return -EINVAL;
158 }
159
160 for (i = 0; i < len; i += 4) {
161 u32 tmp = 0;
162
163 if (!wait_for_payload_credits(display, dsi_trans, 1))
164 return -EBUSY;
165
166 for (j = 0; j < min_t(u32, len - i, 4); j++)
167 tmp |= *data++ << 8 * j;
168
169 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
170 }
171
172 return 0;
173 }
174
dsi_send_pkt_hdr(struct intel_dsi_host * host,const struct mipi_dsi_packet * packet,bool enable_lpdt)175 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
176 const struct mipi_dsi_packet *packet,
177 bool enable_lpdt)
178 {
179 struct intel_dsi *intel_dsi = host->intel_dsi;
180 struct intel_display *display = to_intel_display(&intel_dsi->base);
181 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
182 u32 tmp;
183
184 if (!wait_for_header_credits(display, dsi_trans, 1))
185 return -EBUSY;
186
187 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
188
189 if (packet->payload)
190 tmp |= PAYLOAD_PRESENT;
191 else
192 tmp &= ~PAYLOAD_PRESENT;
193
194 tmp &= ~VBLANK_FENCE;
195
196 if (enable_lpdt)
197 tmp |= LP_DATA_TRANSFER;
198 else
199 tmp &= ~LP_DATA_TRANSFER;
200
201 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
202 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
203 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
204 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
205 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
206 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
207
208 return 0;
209 }
210
icl_dsi_frame_update(struct intel_crtc_state * crtc_state)211 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
212 {
213 struct intel_display *display = to_intel_display(crtc_state);
214 u32 mode_flags;
215 enum port port;
216
217 mode_flags = crtc_state->mode_flags;
218
219 /*
220 * case 1 also covers dual link
221 * In case of dual link, frame update should be set on
222 * DSI_0
223 */
224 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
225 port = PORT_A;
226 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
227 port = PORT_B;
228 else
229 return;
230
231 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
232 DSI_FRAME_UPDATE_REQUEST);
233 }
234
dsi_program_swing_and_deemphasis(struct intel_encoder * encoder)235 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
236 {
237 struct intel_display *display = to_intel_display(encoder);
238 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
239 enum phy phy;
240 u32 tmp, mask, val;
241 int lane;
242
243 for_each_dsi_phy(phy, intel_dsi->phys) {
244 /*
245 * Program voltage swing and pre-emphasis level values as per
246 * table in BSPEC under DDI buffer programing
247 */
248 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
249 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
250 RTERM_SELECT(0x6);
251 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
252 tmp &= ~mask;
253 tmp |= val;
254 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
255 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
256
257 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
258 RCOMP_SCALAR_MASK;
259 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
260 RCOMP_SCALAR(0x98);
261 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
262 tmp &= ~mask;
263 tmp |= val;
264 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
265 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
266
267 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
268 CURSOR_COEFF_MASK;
269 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
270 CURSOR_COEFF(0x3f);
271 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
272
273 /* Bspec: must not use GRP register for write */
274 for (lane = 0; lane <= 3; lane++)
275 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
276 mask, val);
277 }
278 }
279
configure_dual_link_mode(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)280 static void configure_dual_link_mode(struct intel_encoder *encoder,
281 const struct intel_crtc_state *pipe_config)
282 {
283 struct intel_display *display = to_intel_display(encoder);
284 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
285 i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
286 u32 dss_ctl1;
287
288 /* FIXME: Move all DSS handling to intel_vdsc.c */
289 if (DISPLAY_VER(display) >= 12) {
290 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
291
292 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
293 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
294 } else {
295 dss_ctl1_reg = DSS_CTL1;
296 dss_ctl2_reg = DSS_CTL2;
297 }
298
299 dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
300 dss_ctl1 |= SPLITTER_ENABLE;
301 dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
302 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
303
304 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
305 const struct drm_display_mode *adjusted_mode =
306 &pipe_config->hw.adjusted_mode;
307 u16 hactive = adjusted_mode->crtc_hdisplay;
308 u16 dl_buffer_depth;
309
310 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
311 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
312
313 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
314 drm_err(display->drm,
315 "DL buffer depth exceed max value\n");
316
317 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
318 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
319 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
320 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
321 } else {
322 /* Interleave */
323 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
324 }
325
326 intel_de_write(display, dss_ctl1_reg, dss_ctl1);
327 }
328
329 /* aka DSI 8X clock */
afe_clk(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)330 static int afe_clk(struct intel_encoder *encoder,
331 const struct intel_crtc_state *crtc_state)
332 {
333 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
334 int bpp;
335
336 if (crtc_state->dsc.compression_enable)
337 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
338 else
339 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
340
341 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
342 }
343
gen11_dsi_program_esc_clk_div(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)344 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
345 const struct intel_crtc_state *crtc_state)
346 {
347 struct intel_display *display = to_intel_display(encoder);
348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
349 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
350 enum port port;
351 int afe_clk_khz;
352 int theo_word_clk, act_word_clk;
353 u32 esc_clk_div_m, esc_clk_div_m_phy;
354
355 afe_clk_khz = afe_clk(encoder, crtc_state);
356
357 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
358 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
359 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
360 esc_clk_div_m = act_word_clk * 8;
361 esc_clk_div_m_phy = (act_word_clk - 1) / 2;
362 } else {
363 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
364 }
365
366 for_each_dsi_port(port, intel_dsi->ports) {
367 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
368 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
369 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
370 }
371
372 for_each_dsi_port(port, intel_dsi->ports) {
373 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
374 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
375 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
376 }
377
378 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
379 for_each_dsi_port(port, intel_dsi->ports) {
380 intel_de_write(display, ADL_MIPIO_DW(port, 8),
381 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
382 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
383 }
384 }
385 }
386
get_dsi_io_power_domains(struct intel_dsi * intel_dsi)387 static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi)
388 {
389 struct intel_display *display = to_intel_display(&intel_dsi->base);
390 struct drm_i915_private *dev_priv = to_i915(display->drm);
391 enum port port;
392
393 for_each_dsi_port(port, intel_dsi->ports) {
394 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
395 intel_dsi->io_wakeref[port] =
396 intel_display_power_get(dev_priv,
397 port == PORT_A ?
398 POWER_DOMAIN_PORT_DDI_IO_A :
399 POWER_DOMAIN_PORT_DDI_IO_B);
400 }
401 }
402
gen11_dsi_enable_io_power(struct intel_encoder * encoder)403 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
404 {
405 struct intel_display *display = to_intel_display(encoder);
406 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
407 enum port port;
408
409 for_each_dsi_port(port, intel_dsi->ports)
410 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
411 0, COMBO_PHY_MODE_DSI);
412
413 get_dsi_io_power_domains(intel_dsi);
414 }
415
gen11_dsi_power_up_lanes(struct intel_encoder * encoder)416 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
417 {
418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
420 enum phy phy;
421
422 for_each_dsi_phy(phy, intel_dsi->phys)
423 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
424 intel_dsi->lane_count, false);
425 }
426
gen11_dsi_config_phy_lanes_sequence(struct intel_encoder * encoder)427 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
428 {
429 struct intel_display *display = to_intel_display(encoder);
430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
431 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
432 enum phy phy;
433 u32 tmp;
434 int lane;
435
436 /* Step 4b(i) set loadgen select for transmit and aux lanes */
437 for_each_dsi_phy(phy, intel_dsi->phys) {
438 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
439 LOADGEN_SELECT, 0);
440 for (lane = 0; lane <= 3; lane++)
441 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
442 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
443 }
444
445 /* Step 4b(ii) set latency optimization for transmit and aux lanes */
446 for_each_dsi_phy(phy, intel_dsi->phys) {
447 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
448 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
449 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
450 tmp &= ~FRC_LATENCY_OPTIM_MASK;
451 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
452 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
453
454 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
455 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
456 (DISPLAY_VER(display) >= 12)) {
457 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
458 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
459
460 tmp = intel_de_read(display,
461 ICL_PORT_PCS_DW1_LN(0, phy));
462 tmp &= ~LATENCY_OPTIM_MASK;
463 tmp |= LATENCY_OPTIM_VAL(0x1);
464 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
465 tmp);
466 }
467 }
468
469 }
470
gen11_dsi_voltage_swing_program_seq(struct intel_encoder * encoder)471 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
472 {
473 struct intel_display *display = to_intel_display(encoder);
474 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
475 u32 tmp;
476 enum phy phy;
477
478 /* clear common keeper enable bit */
479 for_each_dsi_phy(phy, intel_dsi->phys) {
480 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
481 tmp &= ~COMMON_KEEPER_EN;
482 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
483 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
484 }
485
486 /*
487 * Set SUS Clock Config bitfield to 11b
488 * Note: loadgen select program is done
489 * as part of lane phy sequence configuration
490 */
491 for_each_dsi_phy(phy, intel_dsi->phys)
492 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
493 SUS_CLOCK_CONFIG);
494
495 /* Clear training enable to change swing values */
496 for_each_dsi_phy(phy, intel_dsi->phys) {
497 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
498 tmp &= ~TX_TRAINING_EN;
499 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
500 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
501 }
502
503 /* Program swing and de-emphasis */
504 dsi_program_swing_and_deemphasis(encoder);
505
506 /* Set training enable to trigger update */
507 for_each_dsi_phy(phy, intel_dsi->phys) {
508 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
509 tmp |= TX_TRAINING_EN;
510 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
511 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
512 }
513 }
514
gen11_dsi_enable_ddi_buffer(struct intel_encoder * encoder)515 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
516 {
517 struct intel_display *display = to_intel_display(encoder);
518 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
519 enum port port;
520
521 for_each_dsi_port(port, intel_dsi->ports) {
522 intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
523
524 if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
525 DDI_BUF_IS_IDLE),
526 500))
527 drm_err(display->drm, "DDI port:%c buffer idle\n",
528 port_name(port));
529 }
530 }
531
532 static void
gen11_dsi_setup_dphy_timings(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)533 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
534 const struct intel_crtc_state *crtc_state)
535 {
536 struct intel_display *display = to_intel_display(encoder);
537 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
538 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
539 enum port port;
540 enum phy phy;
541
542 /* Program DPHY clock lanes timings */
543 for_each_dsi_port(port, intel_dsi->ports)
544 intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
545 intel_dsi->dphy_reg);
546
547 /* Program DPHY data lanes timings */
548 for_each_dsi_port(port, intel_dsi->ports)
549 intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
550 intel_dsi->dphy_data_lane_reg);
551
552 /*
553 * If DSI link operating at or below an 800 MHz,
554 * TA_SURE should be override and programmed to
555 * a value '0' inside TA_PARAM_REGISTERS otherwise
556 * leave all fields at HW default values.
557 */
558 if (DISPLAY_VER(display) == 11) {
559 if (afe_clk(encoder, crtc_state) <= 800000) {
560 for_each_dsi_port(port, intel_dsi->ports)
561 intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
562 TA_SURE_MASK,
563 TA_SURE_OVERRIDE | TA_SURE(0));
564 }
565 }
566
567 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
568 for_each_dsi_phy(phy, intel_dsi->phys)
569 intel_de_rmw(display, ICL_DPHY_CHKN(phy),
570 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
571 }
572 }
573
574 static void
gen11_dsi_setup_timings(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)575 gen11_dsi_setup_timings(struct intel_encoder *encoder,
576 const struct intel_crtc_state *crtc_state)
577 {
578 struct intel_display *display = to_intel_display(encoder);
579 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
580 enum port port;
581
582 /* Program T-INIT master registers */
583 for_each_dsi_port(port, intel_dsi->ports)
584 intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
585 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
586
587 /* shadow register inside display core */
588 for_each_dsi_port(port, intel_dsi->ports)
589 intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
590 intel_dsi->dphy_reg);
591
592 /* shadow register inside display core */
593 for_each_dsi_port(port, intel_dsi->ports)
594 intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
595 intel_dsi->dphy_data_lane_reg);
596
597 /* shadow register inside display core */
598 if (DISPLAY_VER(display) == 11) {
599 if (afe_clk(encoder, crtc_state) <= 800000) {
600 for_each_dsi_port(port, intel_dsi->ports) {
601 intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
602 TA_SURE_MASK,
603 TA_SURE_OVERRIDE | TA_SURE(0));
604 }
605 }
606 }
607 }
608
gen11_dsi_gate_clocks(struct intel_encoder * encoder)609 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
610 {
611 struct intel_display *display = to_intel_display(encoder);
612 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
613 u32 tmp;
614 enum phy phy;
615
616 mutex_lock(&display->dpll.lock);
617 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
618 for_each_dsi_phy(phy, intel_dsi->phys)
619 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
620
621 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
622 mutex_unlock(&display->dpll.lock);
623 }
624
gen11_dsi_ungate_clocks(struct intel_encoder * encoder)625 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
626 {
627 struct intel_display *display = to_intel_display(encoder);
628 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
629 u32 tmp;
630 enum phy phy;
631
632 mutex_lock(&display->dpll.lock);
633 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
634 for_each_dsi_phy(phy, intel_dsi->phys)
635 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
636
637 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
638 mutex_unlock(&display->dpll.lock);
639 }
640
gen11_dsi_is_clock_enabled(struct intel_encoder * encoder)641 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
642 {
643 struct intel_display *display = to_intel_display(encoder);
644 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
645 bool clock_enabled = false;
646 enum phy phy;
647 u32 tmp;
648
649 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
650
651 for_each_dsi_phy(phy, intel_dsi->phys) {
652 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
653 clock_enabled = true;
654 }
655
656 return clock_enabled;
657 }
658
gen11_dsi_map_pll(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)659 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
660 const struct intel_crtc_state *crtc_state)
661 {
662 struct intel_display *display = to_intel_display(encoder);
663 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
664 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
665 enum phy phy;
666 u32 val;
667
668 mutex_lock(&display->dpll.lock);
669
670 val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
671 for_each_dsi_phy(phy, intel_dsi->phys) {
672 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
673 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
674 }
675 intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
676
677 for_each_dsi_phy(phy, intel_dsi->phys) {
678 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
679 }
680 intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
681
682 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
683
684 mutex_unlock(&display->dpll.lock);
685 }
686
687 static void
gen11_dsi_configure_transcoder(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)688 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
689 const struct intel_crtc_state *pipe_config)
690 {
691 struct intel_display *display = to_intel_display(encoder);
692 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
693 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
694 enum pipe pipe = crtc->pipe;
695 u32 tmp;
696 enum port port;
697 enum transcoder dsi_trans;
698
699 for_each_dsi_port(port, intel_dsi->ports) {
700 dsi_trans = dsi_port_to_transcoder(port);
701 tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
702
703 if (intel_dsi->eotp_pkt)
704 tmp &= ~EOTP_DISABLED;
705 else
706 tmp |= EOTP_DISABLED;
707
708 /* enable link calibration if freq > 1.5Gbps */
709 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
710 tmp &= ~LINK_CALIBRATION_MASK;
711 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
712 }
713
714 /* configure continuous clock */
715 tmp &= ~CONTINUOUS_CLK_MASK;
716 if (intel_dsi->clock_stop)
717 tmp |= CLK_ENTER_LP_AFTER_DATA;
718 else
719 tmp |= CLK_HS_CONTINUOUS;
720
721 /* configure buffer threshold limit to minimum */
722 tmp &= ~PIX_BUF_THRESHOLD_MASK;
723 tmp |= PIX_BUF_THRESHOLD_1_4;
724
725 /* set virtual channel to '0' */
726 tmp &= ~PIX_VIRT_CHAN_MASK;
727 tmp |= PIX_VIRT_CHAN(0);
728
729 /* program BGR transmission */
730 if (intel_dsi->bgr_enabled)
731 tmp |= BGR_TRANSMISSION;
732
733 /* select pixel format */
734 tmp &= ~PIX_FMT_MASK;
735 if (pipe_config->dsc.compression_enable) {
736 tmp |= PIX_FMT_COMPRESSED;
737 } else {
738 switch (intel_dsi->pixel_format) {
739 default:
740 MISSING_CASE(intel_dsi->pixel_format);
741 fallthrough;
742 case MIPI_DSI_FMT_RGB565:
743 tmp |= PIX_FMT_RGB565;
744 break;
745 case MIPI_DSI_FMT_RGB666_PACKED:
746 tmp |= PIX_FMT_RGB666_PACKED;
747 break;
748 case MIPI_DSI_FMT_RGB666:
749 tmp |= PIX_FMT_RGB666_LOOSE;
750 break;
751 case MIPI_DSI_FMT_RGB888:
752 tmp |= PIX_FMT_RGB888;
753 break;
754 }
755 }
756
757 if (DISPLAY_VER(display) >= 12) {
758 if (is_vid_mode(intel_dsi))
759 tmp |= BLANKING_PACKET_ENABLE;
760 }
761
762 /* program DSI operation mode */
763 if (is_vid_mode(intel_dsi)) {
764 tmp &= ~OP_MODE_MASK;
765 switch (intel_dsi->video_mode) {
766 default:
767 MISSING_CASE(intel_dsi->video_mode);
768 fallthrough;
769 case NON_BURST_SYNC_EVENTS:
770 tmp |= VIDEO_MODE_SYNC_EVENT;
771 break;
772 case NON_BURST_SYNC_PULSE:
773 tmp |= VIDEO_MODE_SYNC_PULSE;
774 break;
775 }
776 } else {
777 /*
778 * FIXME: Retrieve this info from VBT.
779 * As per the spec when dsi transcoder is operating
780 * in TE GATE mode, TE comes from GPIO
781 * which is UTIL PIN for DSI 0.
782 * Also this GPIO would not be used for other
783 * purposes is an assumption.
784 */
785 tmp &= ~OP_MODE_MASK;
786 tmp |= CMD_MODE_TE_GATE;
787 tmp |= TE_SOURCE_GPIO;
788 }
789
790 intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
791 }
792
793 /* enable port sync mode if dual link */
794 if (intel_dsi->dual_link) {
795 for_each_dsi_port(port, intel_dsi->ports) {
796 dsi_trans = dsi_port_to_transcoder(port);
797 intel_de_rmw(display,
798 TRANS_DDI_FUNC_CTL2(display, dsi_trans),
799 0, PORT_SYNC_MODE_ENABLE);
800 }
801
802 /* configure stream splitting */
803 configure_dual_link_mode(encoder, pipe_config);
804 }
805
806 for_each_dsi_port(port, intel_dsi->ports) {
807 dsi_trans = dsi_port_to_transcoder(port);
808
809 /* select data lane width */
810 tmp = intel_de_read(display,
811 TRANS_DDI_FUNC_CTL(display, dsi_trans));
812 tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
813 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
814
815 /* select input pipe */
816 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
817 switch (pipe) {
818 default:
819 MISSING_CASE(pipe);
820 fallthrough;
821 case PIPE_A:
822 tmp |= TRANS_DDI_EDP_INPUT_A_ON;
823 break;
824 case PIPE_B:
825 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
826 break;
827 case PIPE_C:
828 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
829 break;
830 case PIPE_D:
831 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
832 break;
833 }
834
835 /* enable DDI buffer */
836 tmp |= TRANS_DDI_FUNC_ENABLE;
837 intel_de_write(display,
838 TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
839 }
840
841 /* wait for link ready */
842 for_each_dsi_port(port, intel_dsi->ports) {
843 dsi_trans = dsi_port_to_transcoder(port);
844 if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
845 LINK_READY), 2500))
846 drm_err(display->drm, "DSI link not ready\n");
847 }
848 }
849
850 static void
gen11_dsi_set_transcoder_timings(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)851 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
852 const struct intel_crtc_state *crtc_state)
853 {
854 struct intel_display *display = to_intel_display(encoder);
855 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
856 const struct drm_display_mode *adjusted_mode =
857 &crtc_state->hw.adjusted_mode;
858 enum port port;
859 enum transcoder dsi_trans;
860 /* horizontal timings */
861 u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
862 u16 hback_porch;
863 /* vertical timings */
864 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
865 int mul = 1, div = 1;
866
867 /*
868 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
869 * for slower link speed if DSC is enabled.
870 *
871 * The compression frequency ratio is the ratio between compressed and
872 * non-compressed link speeds, and simplifies down to the ratio between
873 * compressed and non-compressed bpp.
874 */
875 if (crtc_state->dsc.compression_enable) {
876 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
877 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
878 }
879
880 hactive = adjusted_mode->crtc_hdisplay;
881
882 if (is_vid_mode(intel_dsi))
883 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
884 else
885 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
886
887 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
888 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
889 hsync_size = hsync_end - hsync_start;
890 hback_porch = (adjusted_mode->crtc_htotal -
891 adjusted_mode->crtc_hsync_end);
892 vactive = adjusted_mode->crtc_vdisplay;
893
894 if (is_vid_mode(intel_dsi)) {
895 vtotal = adjusted_mode->crtc_vtotal;
896 } else {
897 int bpp, line_time_us, byte_clk_period_ns;
898
899 if (crtc_state->dsc.compression_enable)
900 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
901 else
902 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
903
904 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
905 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
906 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
907 }
908 vsync_start = adjusted_mode->crtc_vsync_start;
909 vsync_end = adjusted_mode->crtc_vsync_end;
910 vsync_shift = hsync_start - htotal / 2;
911
912 if (intel_dsi->dual_link) {
913 hactive /= 2;
914 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
915 hactive += intel_dsi->pixel_overlap;
916 htotal /= 2;
917 }
918
919 /* minimum hactive as per bspec: 256 pixels */
920 if (adjusted_mode->crtc_hdisplay < 256)
921 drm_err(display->drm, "hactive is less then 256 pixels\n");
922
923 /* if RGB666 format, then hactive must be multiple of 4 pixels */
924 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
925 drm_err(display->drm,
926 "hactive pixels are not multiple of 4\n");
927
928 /* program TRANS_HTOTAL register */
929 for_each_dsi_port(port, intel_dsi->ports) {
930 dsi_trans = dsi_port_to_transcoder(port);
931 intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
932 HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
933 }
934
935 /* TRANS_HSYNC register to be programmed only for video mode */
936 if (is_vid_mode(intel_dsi)) {
937 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
938 /* BSPEC: hsync size should be atleast 16 pixels */
939 if (hsync_size < 16)
940 drm_err(display->drm,
941 "hsync size < 16 pixels\n");
942 }
943
944 if (hback_porch < 16)
945 drm_err(display->drm, "hback porch < 16 pixels\n");
946
947 if (intel_dsi->dual_link) {
948 hsync_start /= 2;
949 hsync_end /= 2;
950 }
951
952 for_each_dsi_port(port, intel_dsi->ports) {
953 dsi_trans = dsi_port_to_transcoder(port);
954 intel_de_write(display,
955 TRANS_HSYNC(display, dsi_trans),
956 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
957 }
958 }
959
960 /* program TRANS_VTOTAL register */
961 for_each_dsi_port(port, intel_dsi->ports) {
962 dsi_trans = dsi_port_to_transcoder(port);
963 /*
964 * FIXME: Programing this by assuming progressive mode, since
965 * non-interlaced info from VBT is not saved inside
966 * struct drm_display_mode.
967 * For interlace mode: program required pixel minus 2
968 */
969 intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
970 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
971 }
972
973 if (vsync_end < vsync_start || vsync_end > vtotal)
974 drm_err(display->drm, "Invalid vsync_end value\n");
975
976 if (vsync_start < vactive)
977 drm_err(display->drm, "vsync_start less than vactive\n");
978
979 /* program TRANS_VSYNC register for video mode only */
980 if (is_vid_mode(intel_dsi)) {
981 for_each_dsi_port(port, intel_dsi->ports) {
982 dsi_trans = dsi_port_to_transcoder(port);
983 intel_de_write(display,
984 TRANS_VSYNC(display, dsi_trans),
985 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
986 }
987 }
988
989 /*
990 * FIXME: It has to be programmed only for video modes and interlaced
991 * modes. Put the check condition here once interlaced
992 * info available as described above.
993 * program TRANS_VSYNCSHIFT register
994 */
995 if (is_vid_mode(intel_dsi)) {
996 for_each_dsi_port(port, intel_dsi->ports) {
997 dsi_trans = dsi_port_to_transcoder(port);
998 intel_de_write(display,
999 TRANS_VSYNCSHIFT(display, dsi_trans),
1000 vsync_shift);
1001 }
1002 }
1003
1004 /*
1005 * program TRANS_VBLANK register, should be same as vtotal programmed
1006 *
1007 * FIXME get rid of these local hacks and do it right,
1008 * this will not handle eg. delayed vblank correctly.
1009 */
1010 if (DISPLAY_VER(display) >= 12) {
1011 for_each_dsi_port(port, intel_dsi->ports) {
1012 dsi_trans = dsi_port_to_transcoder(port);
1013 intel_de_write(display,
1014 TRANS_VBLANK(display, dsi_trans),
1015 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
1016 }
1017 }
1018 }
1019
gen11_dsi_enable_transcoder(struct intel_encoder * encoder)1020 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1021 {
1022 struct intel_display *display = to_intel_display(encoder);
1023 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1024 enum port port;
1025 enum transcoder dsi_trans;
1026
1027 for_each_dsi_port(port, intel_dsi->ports) {
1028 dsi_trans = dsi_port_to_transcoder(port);
1029 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
1030 TRANSCONF_ENABLE);
1031
1032 /* wait for transcoder to be enabled */
1033 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
1034 TRANSCONF_STATE_ENABLE, 10))
1035 drm_err(display->drm,
1036 "DSI transcoder not enabled\n");
1037 }
1038 }
1039
gen11_dsi_setup_timeouts(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1040 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1041 const struct intel_crtc_state *crtc_state)
1042 {
1043 struct intel_display *display = to_intel_display(encoder);
1044 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1045 enum port port;
1046 enum transcoder dsi_trans;
1047 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1048
1049 /*
1050 * escape clock count calculation:
1051 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1052 * UI (nsec) = (10^6)/Bitrate
1053 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1054 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
1055 */
1056 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1057 mul = 8 * 1000000;
1058 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1059 divisor);
1060 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1061 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1062
1063 for_each_dsi_port(port, intel_dsi->ports) {
1064 dsi_trans = dsi_port_to_transcoder(port);
1065
1066 /* program hst_tx_timeout */
1067 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
1068 HSTX_TIMEOUT_VALUE_MASK,
1069 HSTX_TIMEOUT_VALUE(hs_tx_timeout));
1070
1071 /* FIXME: DSI_CALIB_TO */
1072
1073 /* program lp_rx_host timeout */
1074 intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
1075 LPRX_TIMEOUT_VALUE_MASK,
1076 LPRX_TIMEOUT_VALUE(lp_rx_timeout));
1077
1078 /* FIXME: DSI_PWAIT_TO */
1079
1080 /* program turn around timeout */
1081 intel_de_rmw(display, DSI_TA_TO(dsi_trans),
1082 TA_TIMEOUT_VALUE_MASK,
1083 TA_TIMEOUT_VALUE(ta_timeout));
1084 }
1085 }
1086
gen11_dsi_config_util_pin(struct intel_encoder * encoder,bool enable)1087 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1088 bool enable)
1089 {
1090 struct intel_display *display = to_intel_display(encoder);
1091 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1092 u32 tmp;
1093
1094 /*
1095 * used as TE i/p for DSI0,
1096 * for dual link/DSI1 TE is from slave DSI1
1097 * through GPIO.
1098 */
1099 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1100 return;
1101
1102 tmp = intel_de_read(display, UTIL_PIN_CTL);
1103
1104 if (enable) {
1105 tmp |= UTIL_PIN_DIRECTION_INPUT;
1106 tmp |= UTIL_PIN_ENABLE;
1107 } else {
1108 tmp &= ~UTIL_PIN_ENABLE;
1109 }
1110 intel_de_write(display, UTIL_PIN_CTL, tmp);
1111 }
1112
1113 static void
gen11_dsi_enable_port_and_phy(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1114 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1115 const struct intel_crtc_state *crtc_state)
1116 {
1117 /* step 4a: power up all lanes of the DDI used by DSI */
1118 gen11_dsi_power_up_lanes(encoder);
1119
1120 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1121 gen11_dsi_config_phy_lanes_sequence(encoder);
1122
1123 /* step 4c: configure voltage swing and skew */
1124 gen11_dsi_voltage_swing_program_seq(encoder);
1125
1126 /* setup D-PHY timings */
1127 gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1128
1129 /* enable DDI buffer */
1130 gen11_dsi_enable_ddi_buffer(encoder);
1131
1132 gen11_dsi_gate_clocks(encoder);
1133
1134 gen11_dsi_setup_timings(encoder, crtc_state);
1135
1136 /* Since transcoder is configured to take events from GPIO */
1137 gen11_dsi_config_util_pin(encoder, true);
1138
1139 /* step 4h: setup DSI protocol timeouts */
1140 gen11_dsi_setup_timeouts(encoder, crtc_state);
1141
1142 /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1143 gen11_dsi_configure_transcoder(encoder, crtc_state);
1144 }
1145
gen11_dsi_powerup_panel(struct intel_encoder * encoder)1146 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1147 {
1148 struct intel_display *display = to_intel_display(encoder);
1149 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1150 struct mipi_dsi_device *dsi;
1151 enum port port;
1152 enum transcoder dsi_trans;
1153 u32 tmp;
1154 int ret;
1155
1156 /* set maximum return packet size */
1157 for_each_dsi_port(port, intel_dsi->ports) {
1158 dsi_trans = dsi_port_to_transcoder(port);
1159
1160 /*
1161 * FIXME: This uses the number of DW's currently in the payload
1162 * receive queue. This is probably not what we want here.
1163 */
1164 tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
1165 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1166 /* multiply "Number Rx Payload DW" by 4 to get max value */
1167 tmp = tmp * 4;
1168 dsi = intel_dsi->dsi_hosts[port]->device;
1169 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1170 if (ret < 0)
1171 drm_err(display->drm,
1172 "error setting max return pkt size%d\n", tmp);
1173 }
1174
1175 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1176
1177 /* ensure all panel commands dispatched before enabling transcoder */
1178 wait_for_cmds_dispatched_to_panel(encoder);
1179 }
1180
gen11_dsi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1181 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1182 struct intel_encoder *encoder,
1183 const struct intel_crtc_state *crtc_state,
1184 const struct drm_connector_state *conn_state)
1185 {
1186 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1187
1188 intel_dsi_wait_panel_power_cycle(intel_dsi);
1189
1190 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1191 msleep(intel_dsi->panel_on_delay);
1192 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1193
1194 /* step2: enable IO power */
1195 gen11_dsi_enable_io_power(encoder);
1196
1197 /* step3: enable DSI PLL */
1198 gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1199 }
1200
gen11_dsi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)1201 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1202 struct intel_encoder *encoder,
1203 const struct intel_crtc_state *pipe_config,
1204 const struct drm_connector_state *conn_state)
1205 {
1206 /* step3b */
1207 gen11_dsi_map_pll(encoder, pipe_config);
1208
1209 /* step4: enable DSI port and DPHY */
1210 gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1211
1212 /* step5: program and powerup panel */
1213 gen11_dsi_powerup_panel(encoder);
1214
1215 intel_dsc_dsi_pps_write(encoder, pipe_config);
1216
1217 /* step6c: configure transcoder timings */
1218 gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1219 }
1220
1221 /*
1222 * Wa_1409054076:icl,jsl,ehl
1223 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1224 * the AMT KVMR feature will incorrectly see pipe A as enabled.
1225 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1226 * it set while DSI is enabled on pipe B
1227 */
icl_apply_kvmr_pipe_a_wa(struct intel_encoder * encoder,enum pipe pipe,bool enable)1228 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1229 enum pipe pipe, bool enable)
1230 {
1231 struct intel_display *display = to_intel_display(encoder);
1232
1233 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
1234 intel_de_rmw(display, CHICKEN_PAR1_1,
1235 IGNORE_KVMR_PIPE_A,
1236 enable ? IGNORE_KVMR_PIPE_A : 0);
1237 }
1238
1239 /*
1240 * Wa_16012360555:adl-p
1241 * SW will have to program the "LP to HS Wakeup Guardband"
1242 * to account for the repeaters on the HS Request/Ready
1243 * PPI signaling between the Display engine and the DPHY.
1244 */
adlp_set_lp_hs_wakeup_gb(struct intel_encoder * encoder)1245 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1246 {
1247 struct intel_display *display = to_intel_display(encoder);
1248 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1249 enum port port;
1250
1251 if (DISPLAY_VER(display) == 13) {
1252 for_each_dsi_port(port, intel_dsi->ports)
1253 intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
1254 TGL_DSI_CHKN_LSHS_GB_MASK,
1255 TGL_DSI_CHKN_LSHS_GB(4));
1256 }
1257 }
1258
gen11_dsi_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1259 static void gen11_dsi_enable(struct intel_atomic_state *state,
1260 struct intel_encoder *encoder,
1261 const struct intel_crtc_state *crtc_state,
1262 const struct drm_connector_state *conn_state)
1263 {
1264 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1266
1267 /* Wa_1409054076:icl,jsl,ehl */
1268 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1269
1270 /* Wa_16012360555:adl-p */
1271 adlp_set_lp_hs_wakeup_gb(encoder);
1272
1273 /* step6d: enable dsi transcoder */
1274 gen11_dsi_enable_transcoder(encoder);
1275
1276 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1277
1278 /* step7: enable backlight */
1279 intel_backlight_enable(crtc_state, conn_state);
1280 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1281
1282 intel_crtc_vblank_on(crtc_state);
1283 }
1284
gen11_dsi_disable_transcoder(struct intel_encoder * encoder)1285 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1286 {
1287 struct intel_display *display = to_intel_display(encoder);
1288 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1289 enum port port;
1290 enum transcoder dsi_trans;
1291
1292 for_each_dsi_port(port, intel_dsi->ports) {
1293 dsi_trans = dsi_port_to_transcoder(port);
1294
1295 /* disable transcoder */
1296 intel_de_rmw(display, TRANSCONF(display, dsi_trans),
1297 TRANSCONF_ENABLE, 0);
1298
1299 /* wait for transcoder to be disabled */
1300 if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
1301 TRANSCONF_STATE_ENABLE, 50))
1302 drm_err(display->drm,
1303 "DSI trancoder not disabled\n");
1304 }
1305 }
1306
gen11_dsi_powerdown_panel(struct intel_encoder * encoder)1307 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1308 {
1309 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1310
1311 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1312
1313 /* ensure cmds dispatched to panel */
1314 wait_for_cmds_dispatched_to_panel(encoder);
1315 }
1316
gen11_dsi_deconfigure_trancoder(struct intel_encoder * encoder)1317 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1318 {
1319 struct intel_display *display = to_intel_display(encoder);
1320 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1321 enum port port;
1322 enum transcoder dsi_trans;
1323 u32 tmp;
1324
1325 /* disable periodic update mode */
1326 if (is_cmd_mode(intel_dsi)) {
1327 for_each_dsi_port(port, intel_dsi->ports)
1328 intel_de_rmw(display, DSI_CMD_FRMCTL(port),
1329 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
1330 }
1331
1332 /* put dsi link in ULPS */
1333 for_each_dsi_port(port, intel_dsi->ports) {
1334 dsi_trans = dsi_port_to_transcoder(port);
1335 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
1336 tmp |= LINK_ENTER_ULPS;
1337 tmp &= ~LINK_ULPS_TYPE_LP11;
1338 intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
1339
1340 if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
1341 LINK_IN_ULPS),
1342 10))
1343 drm_err(display->drm, "DSI link not in ULPS\n");
1344 }
1345
1346 /* disable ddi function */
1347 for_each_dsi_port(port, intel_dsi->ports) {
1348 dsi_trans = dsi_port_to_transcoder(port);
1349 intel_de_rmw(display,
1350 TRANS_DDI_FUNC_CTL(display, dsi_trans),
1351 TRANS_DDI_FUNC_ENABLE, 0);
1352 }
1353
1354 /* disable port sync mode if dual link */
1355 if (intel_dsi->dual_link) {
1356 for_each_dsi_port(port, intel_dsi->ports) {
1357 dsi_trans = dsi_port_to_transcoder(port);
1358 intel_de_rmw(display,
1359 TRANS_DDI_FUNC_CTL2(display, dsi_trans),
1360 PORT_SYNC_MODE_ENABLE, 0);
1361 }
1362 }
1363 }
1364
gen11_dsi_disable_port(struct intel_encoder * encoder)1365 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1366 {
1367 struct intel_display *display = to_intel_display(encoder);
1368 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1369 enum port port;
1370
1371 gen11_dsi_ungate_clocks(encoder);
1372 for_each_dsi_port(port, intel_dsi->ports) {
1373 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1374
1375 if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
1376 DDI_BUF_IS_IDLE),
1377 8))
1378 drm_err(display->drm,
1379 "DDI port:%c buffer not idle\n",
1380 port_name(port));
1381 }
1382 gen11_dsi_gate_clocks(encoder);
1383 }
1384
gen11_dsi_disable_io_power(struct intel_encoder * encoder)1385 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1386 {
1387 struct intel_display *display = to_intel_display(encoder);
1388 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1389 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1390 enum port port;
1391
1392 for_each_dsi_port(port, intel_dsi->ports) {
1393 intel_wakeref_t wakeref;
1394
1395 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1396 intel_display_power_put(dev_priv,
1397 port == PORT_A ?
1398 POWER_DOMAIN_PORT_DDI_IO_A :
1399 POWER_DOMAIN_PORT_DDI_IO_B,
1400 wakeref);
1401 }
1402
1403 /* set mode to DDI */
1404 for_each_dsi_port(port, intel_dsi->ports)
1405 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
1406 COMBO_PHY_MODE_DSI, 0);
1407 }
1408
gen11_dsi_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)1409 static void gen11_dsi_disable(struct intel_atomic_state *state,
1410 struct intel_encoder *encoder,
1411 const struct intel_crtc_state *old_crtc_state,
1412 const struct drm_connector_state *old_conn_state)
1413 {
1414 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1415
1416 /* step1: turn off backlight */
1417 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1418 intel_backlight_disable(old_conn_state);
1419 }
1420
gen11_dsi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)1421 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1422 struct intel_encoder *encoder,
1423 const struct intel_crtc_state *old_crtc_state,
1424 const struct drm_connector_state *old_conn_state)
1425 {
1426 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1427 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1428
1429 intel_crtc_vblank_off(old_crtc_state);
1430
1431 /* step2d,e: disable transcoder and wait */
1432 gen11_dsi_disable_transcoder(encoder);
1433
1434 /* Wa_1409054076:icl,jsl,ehl */
1435 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1436
1437 /* step2f,g: powerdown panel */
1438 gen11_dsi_powerdown_panel(encoder);
1439
1440 /* step2h,i,j: deconfig trancoder */
1441 gen11_dsi_deconfigure_trancoder(encoder);
1442
1443 intel_dsc_disable(old_crtc_state);
1444 skl_scaler_disable(old_crtc_state);
1445
1446 /* step3: disable port */
1447 gen11_dsi_disable_port(encoder);
1448
1449 gen11_dsi_config_util_pin(encoder, false);
1450
1451 /* step4: disable IO power */
1452 gen11_dsi_disable_io_power(encoder);
1453
1454 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1455
1456 msleep(intel_dsi->panel_off_delay);
1457 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1458
1459 intel_dsi->panel_power_off_time = ktime_get_boottime();
1460 }
1461
gen11_dsi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1462 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1463 struct drm_display_mode *mode)
1464 {
1465 struct drm_i915_private *i915 = to_i915(connector->dev);
1466 enum drm_mode_status status;
1467
1468 status = intel_cpu_transcoder_mode_valid(i915, mode);
1469 if (status != MODE_OK)
1470 return status;
1471
1472 /* FIXME: DSC? */
1473 return intel_dsi_mode_valid(connector, mode);
1474 }
1475
gen11_dsi_get_timings(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1476 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1477 struct intel_crtc_state *pipe_config)
1478 {
1479 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1480 struct drm_display_mode *adjusted_mode =
1481 &pipe_config->hw.adjusted_mode;
1482
1483 if (pipe_config->dsc.compressed_bpp_x16) {
1484 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
1485 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1486
1487 adjusted_mode->crtc_htotal =
1488 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1489 adjusted_mode->crtc_hsync_start =
1490 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1491 adjusted_mode->crtc_hsync_end =
1492 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1493 }
1494
1495 if (intel_dsi->dual_link) {
1496 adjusted_mode->crtc_hdisplay *= 2;
1497 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1498 adjusted_mode->crtc_hdisplay -=
1499 intel_dsi->pixel_overlap;
1500 adjusted_mode->crtc_htotal *= 2;
1501 }
1502 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1503 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1504
1505 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1506 if (intel_dsi->dual_link) {
1507 adjusted_mode->crtc_hsync_start *= 2;
1508 adjusted_mode->crtc_hsync_end *= 2;
1509 }
1510 }
1511 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1512 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1513 }
1514
gen11_dsi_is_periodic_cmd_mode(struct intel_dsi * intel_dsi)1515 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1516 {
1517 struct intel_display *display = to_intel_display(&intel_dsi->base);
1518 enum transcoder dsi_trans;
1519 u32 val;
1520
1521 if (intel_dsi->ports == BIT(PORT_B))
1522 dsi_trans = TRANSCODER_DSI_1;
1523 else
1524 dsi_trans = TRANSCODER_DSI_0;
1525
1526 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
1527 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1528 }
1529
gen11_dsi_get_cmd_mode_config(struct intel_dsi * intel_dsi,struct intel_crtc_state * pipe_config)1530 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1531 struct intel_crtc_state *pipe_config)
1532 {
1533 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1534 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1535 I915_MODE_FLAG_DSI_USE_TE0;
1536 else if (intel_dsi->ports == BIT(PORT_B))
1537 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1538 else
1539 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1540 }
1541
gen11_dsi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1542 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1543 struct intel_crtc_state *pipe_config)
1544 {
1545 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1546 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1547
1548 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
1549
1550 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1551 if (intel_dsi->dual_link)
1552 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1553
1554 gen11_dsi_get_timings(encoder, pipe_config);
1555 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1556 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1557
1558 /* Get the details on which TE should be enabled */
1559 if (is_cmd_mode(intel_dsi))
1560 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1561
1562 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1563 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1564 }
1565
gen11_dsi_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1566 static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1567 const struct intel_crtc_state *crtc_state)
1568 {
1569 struct intel_display *display = to_intel_display(encoder);
1570 struct intel_crtc *intel_crtc;
1571 enum pipe pipe;
1572
1573 if (!crtc_state)
1574 return;
1575
1576 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1577 pipe = intel_crtc->pipe;
1578
1579 /* wa verify 1409054076:icl,jsl,ehl */
1580 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
1581 !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1582 drm_dbg_kms(display->drm,
1583 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1584 encoder->base.base.id,
1585 encoder->base.name);
1586 }
1587
gen11_dsi_dsc_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1588 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1589 struct intel_crtc_state *crtc_state)
1590 {
1591 struct intel_display *display = to_intel_display(encoder);
1592 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1593 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
1594 bool use_dsc;
1595 int ret;
1596
1597 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1598 if (!use_dsc)
1599 return 0;
1600
1601 if (crtc_state->pipe_bpp < 8 * 3)
1602 return -EINVAL;
1603
1604 /* FIXME: split only when necessary */
1605 if (crtc_state->dsc.slice_count > 1)
1606 crtc_state->dsc.num_streams = 2;
1607 else
1608 crtc_state->dsc.num_streams = 1;
1609
1610 /* FIXME: initialize from VBT */
1611 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1612
1613 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1614
1615 ret = intel_dsc_compute_params(crtc_state);
1616 if (ret)
1617 return ret;
1618
1619 /* DSI specific sanity checks on the common code */
1620 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
1621 drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
1622 drm_WARN_ON(display->drm,
1623 vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1624 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
1625 drm_WARN_ON(display->drm,
1626 vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1627
1628 ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1629 if (ret)
1630 return ret;
1631
1632 crtc_state->dsc.compression_enable = true;
1633
1634 return 0;
1635 }
1636
gen11_dsi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)1637 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1638 struct intel_crtc_state *pipe_config,
1639 struct drm_connector_state *conn_state)
1640 {
1641 struct intel_display *display = to_intel_display(encoder);
1642 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1643 struct intel_connector *intel_connector = intel_dsi->attached_connector;
1644 struct drm_display_mode *adjusted_mode =
1645 &pipe_config->hw.adjusted_mode;
1646 int ret;
1647
1648 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1649 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1650
1651 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
1652 if (ret)
1653 return ret;
1654
1655 ret = intel_panel_fitting(pipe_config, conn_state);
1656 if (ret)
1657 return ret;
1658
1659 adjusted_mode->flags = 0;
1660
1661 /* Dual link goes to trancoder DSI'0' */
1662 if (intel_dsi->ports == BIT(PORT_B))
1663 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1664 else
1665 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1666
1667 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1668 pipe_config->pipe_bpp = 24;
1669 else
1670 pipe_config->pipe_bpp = 18;
1671
1672 pipe_config->clock_set = true;
1673
1674 if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1675 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
1676
1677 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1678
1679 /*
1680 * In case of TE GATE cmd mode, we
1681 * receive TE from the slave if
1682 * dual link is enabled
1683 */
1684 if (is_cmd_mode(intel_dsi))
1685 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1686
1687 return 0;
1688 }
1689
gen11_dsi_get_power_domains(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1690 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1691 struct intel_crtc_state *crtc_state)
1692 {
1693 get_dsi_io_power_domains(enc_to_intel_dsi(encoder));
1694 }
1695
gen11_dsi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)1696 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1697 enum pipe *pipe)
1698 {
1699 struct intel_display *display = to_intel_display(encoder);
1700 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1701 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1702 enum transcoder dsi_trans;
1703 intel_wakeref_t wakeref;
1704 enum port port;
1705 bool ret = false;
1706 u32 tmp;
1707
1708 wakeref = intel_display_power_get_if_enabled(dev_priv,
1709 encoder->power_domain);
1710 if (!wakeref)
1711 return false;
1712
1713 for_each_dsi_port(port, intel_dsi->ports) {
1714 dsi_trans = dsi_port_to_transcoder(port);
1715 tmp = intel_de_read(display,
1716 TRANS_DDI_FUNC_CTL(display, dsi_trans));
1717 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1718 case TRANS_DDI_EDP_INPUT_A_ON:
1719 *pipe = PIPE_A;
1720 break;
1721 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1722 *pipe = PIPE_B;
1723 break;
1724 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1725 *pipe = PIPE_C;
1726 break;
1727 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1728 *pipe = PIPE_D;
1729 break;
1730 default:
1731 drm_err(display->drm, "Invalid PIPE input\n");
1732 goto out;
1733 }
1734
1735 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
1736 ret = tmp & TRANSCONF_ENABLE;
1737 }
1738 out:
1739 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1740 return ret;
1741 }
1742
gen11_dsi_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)1743 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1744 struct intel_crtc_state *crtc_state)
1745 {
1746 if (crtc_state->dsc.compression_enable) {
1747 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1748 crtc_state->uapi.mode_changed = true;
1749
1750 return false;
1751 }
1752
1753 return true;
1754 }
1755
gen11_dsi_encoder_destroy(struct drm_encoder * encoder)1756 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1757 {
1758 intel_encoder_destroy(encoder);
1759 }
1760
1761 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1762 .destroy = gen11_dsi_encoder_destroy,
1763 };
1764
1765 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1766 .detect = intel_panel_detect,
1767 .late_register = intel_connector_register,
1768 .early_unregister = intel_connector_unregister,
1769 .destroy = intel_connector_destroy,
1770 .fill_modes = drm_helper_probe_single_connector_modes,
1771 .atomic_get_property = intel_digital_connector_atomic_get_property,
1772 .atomic_set_property = intel_digital_connector_atomic_set_property,
1773 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1774 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1775 };
1776
1777 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1778 .get_modes = intel_dsi_get_modes,
1779 .mode_valid = gen11_dsi_mode_valid,
1780 .atomic_check = intel_digital_connector_atomic_check,
1781 };
1782
gen11_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)1783 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1784 struct mipi_dsi_device *dsi)
1785 {
1786 return 0;
1787 }
1788
gen11_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dsi)1789 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1790 struct mipi_dsi_device *dsi)
1791 {
1792 return 0;
1793 }
1794
gen11_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1795 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1796 const struct mipi_dsi_msg *msg)
1797 {
1798 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1799 struct mipi_dsi_packet dsi_pkt;
1800 ssize_t ret;
1801 bool enable_lpdt = false;
1802
1803 ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1804 if (ret < 0)
1805 return ret;
1806
1807 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1808 enable_lpdt = true;
1809
1810 /* only long packet contains payload */
1811 if (mipi_dsi_packet_format_is_long(msg->type)) {
1812 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt);
1813 if (ret < 0)
1814 return ret;
1815 }
1816
1817 /* send packet header */
1818 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt);
1819 if (ret < 0)
1820 return ret;
1821
1822 //TODO: add payload receive code if needed
1823
1824 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1825
1826 return ret;
1827 }
1828
1829 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1830 .attach = gen11_dsi_host_attach,
1831 .detach = gen11_dsi_host_detach,
1832 .transfer = gen11_dsi_host_transfer,
1833 };
1834
1835 #define ICL_PREPARE_CNT_MAX 0x7
1836 #define ICL_CLK_ZERO_CNT_MAX 0xf
1837 #define ICL_TRAIL_CNT_MAX 0x7
1838 #define ICL_TCLK_PRE_CNT_MAX 0x3
1839 #define ICL_TCLK_POST_CNT_MAX 0x7
1840 #define ICL_HS_ZERO_CNT_MAX 0xf
1841 #define ICL_EXIT_ZERO_CNT_MAX 0x7
1842
icl_dphy_param_init(struct intel_dsi * intel_dsi)1843 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1844 {
1845 struct intel_display *display = to_intel_display(&intel_dsi->base);
1846 struct intel_connector *connector = intel_dsi->attached_connector;
1847 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1848 u32 tlpx_ns;
1849 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1850 u32 ths_prepare_ns, tclk_trail_ns;
1851 u32 hs_zero_cnt;
1852 u32 tclk_pre_cnt;
1853
1854 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1855
1856 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1857 ths_prepare_ns = max(mipi_config->ths_prepare,
1858 mipi_config->tclk_prepare);
1859
1860 /*
1861 * prepare cnt in escape clocks
1862 * this field represents a hexadecimal value with a precision
1863 * of 1.2 – i.e. the most significant bit is the integer
1864 * and the least significant 2 bits are fraction bits.
1865 * so, the field can represent a range of 0.25 to 1.75
1866 */
1867 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1868 if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1869 drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n",
1870 prepare_cnt);
1871 prepare_cnt = ICL_PREPARE_CNT_MAX;
1872 }
1873
1874 /* clk zero count in escape clocks */
1875 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1876 ths_prepare_ns, tlpx_ns);
1877 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1878 drm_dbg_kms(display->drm,
1879 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1880 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1881 }
1882
1883 /* trail cnt in escape clocks*/
1884 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1885 if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1886 drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n",
1887 trail_cnt);
1888 trail_cnt = ICL_TRAIL_CNT_MAX;
1889 }
1890
1891 /* tclk pre count in escape clocks */
1892 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1893 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1894 drm_dbg_kms(display->drm,
1895 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1896 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1897 }
1898
1899 /* hs zero cnt in escape clocks */
1900 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1901 ths_prepare_ns, tlpx_ns);
1902 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1903 drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n",
1904 hs_zero_cnt);
1905 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1906 }
1907
1908 /* hs exit zero cnt in escape clocks */
1909 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1910 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1911 drm_dbg_kms(display->drm,
1912 "exit_zero_cnt out of range (%d)\n",
1913 exit_zero_cnt);
1914 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1915 }
1916
1917 /* clock lane dphy timings */
1918 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1919 CLK_PREPARE(prepare_cnt) |
1920 CLK_ZERO_OVERRIDE |
1921 CLK_ZERO(clk_zero_cnt) |
1922 CLK_PRE_OVERRIDE |
1923 CLK_PRE(tclk_pre_cnt) |
1924 CLK_TRAIL_OVERRIDE |
1925 CLK_TRAIL(trail_cnt));
1926
1927 /* data lanes dphy timings */
1928 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1929 HS_PREPARE(prepare_cnt) |
1930 HS_ZERO_OVERRIDE |
1931 HS_ZERO(hs_zero_cnt) |
1932 HS_TRAIL_OVERRIDE |
1933 HS_TRAIL(trail_cnt) |
1934 HS_EXIT_OVERRIDE |
1935 HS_EXIT(exit_zero_cnt));
1936
1937 intel_dsi_log_params(intel_dsi);
1938 }
1939
icl_dsi_add_properties(struct intel_connector * connector)1940 static void icl_dsi_add_properties(struct intel_connector *connector)
1941 {
1942 const struct drm_display_mode *fixed_mode =
1943 intel_panel_preferred_fixed_mode(connector);
1944
1945 intel_attach_scaling_mode_property(&connector->base);
1946
1947 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1948 intel_dsi_get_panel_orientation(connector),
1949 fixed_mode->hdisplay,
1950 fixed_mode->vdisplay);
1951 }
1952
icl_dsi_init(struct intel_display * display,const struct intel_bios_encoder_data * devdata)1953 void icl_dsi_init(struct intel_display *display,
1954 const struct intel_bios_encoder_data *devdata)
1955 {
1956 struct intel_dsi *intel_dsi;
1957 struct intel_encoder *encoder;
1958 struct intel_connector *intel_connector;
1959 struct drm_connector *connector;
1960 enum port port;
1961
1962 port = intel_bios_encoder_port(devdata);
1963 if (port == PORT_NONE)
1964 return;
1965
1966 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1967 if (!intel_dsi)
1968 return;
1969
1970 intel_connector = intel_connector_alloc();
1971 if (!intel_connector) {
1972 kfree(intel_dsi);
1973 return;
1974 }
1975
1976 encoder = &intel_dsi->base;
1977 intel_dsi->attached_connector = intel_connector;
1978 connector = &intel_connector->base;
1979
1980 encoder->devdata = devdata;
1981
1982 /* register DSI encoder with DRM subsystem */
1983 drm_encoder_init(display->drm, &encoder->base,
1984 &gen11_dsi_encoder_funcs,
1985 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1986
1987 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1988 encoder->pre_enable = gen11_dsi_pre_enable;
1989 encoder->enable = gen11_dsi_enable;
1990 encoder->disable = gen11_dsi_disable;
1991 encoder->post_disable = gen11_dsi_post_disable;
1992 encoder->port = port;
1993 encoder->get_config = gen11_dsi_get_config;
1994 encoder->sync_state = gen11_dsi_sync_state;
1995 encoder->update_pipe = intel_backlight_update;
1996 encoder->compute_config = gen11_dsi_compute_config;
1997 encoder->get_hw_state = gen11_dsi_get_hw_state;
1998 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1999 encoder->type = INTEL_OUTPUT_DSI;
2000 encoder->cloneable = 0;
2001 encoder->pipe_mask = ~0;
2002 encoder->power_domain = POWER_DOMAIN_PORT_DSI;
2003 encoder->get_power_domains = gen11_dsi_get_power_domains;
2004 encoder->disable_clock = gen11_dsi_gate_clocks;
2005 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
2006 encoder->shutdown = intel_dsi_shutdown;
2007
2008 /* register DSI connector with DRM subsystem */
2009 drm_connector_init(display->drm, connector,
2010 &gen11_dsi_connector_funcs,
2011 DRM_MODE_CONNECTOR_DSI);
2012 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
2013 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2014 intel_connector->get_hw_state = intel_connector_get_hw_state;
2015
2016 /* attach connector to encoder */
2017 intel_connector_attach_encoder(intel_connector, encoder);
2018
2019 intel_dsi->panel_power_off_time = ktime_get_boottime();
2020
2021 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
2022
2023 mutex_lock(&display->drm->mode_config.mutex);
2024 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
2025 mutex_unlock(&display->drm->mode_config.mutex);
2026
2027 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2028 drm_err(display->drm, "DSI fixed mode info missing\n");
2029 goto err;
2030 }
2031
2032 intel_panel_init(intel_connector, NULL);
2033
2034 intel_backlight_setup(intel_connector, INVALID_PIPE);
2035
2036 if (intel_connector->panel.vbt.dsi.config->dual_link)
2037 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
2038 else
2039 intel_dsi->ports = BIT(port);
2040
2041 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
2042 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
2043
2044 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
2045 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
2046
2047 for_each_dsi_port(port, intel_dsi->ports) {
2048 struct intel_dsi_host *host;
2049
2050 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
2051 if (!host)
2052 goto err;
2053
2054 intel_dsi->dsi_hosts[port] = host;
2055 }
2056
2057 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2058 drm_dbg_kms(display->drm, "no device found\n");
2059 goto err;
2060 }
2061
2062 icl_dphy_param_init(intel_dsi);
2063
2064 icl_dsi_add_properties(intel_connector);
2065 return;
2066
2067 err:
2068 drm_connector_cleanup(connector);
2069 drm_encoder_cleanup(&encoder->base);
2070 kfree(intel_dsi);
2071 kfree(intel_connector);
2072 }
2073