1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #include <hxge_impl.h>
27 #include <hpi_vmac.h>
28
29 #define HXGE_VMAC_RX_STAT_CLEAR 0x1ffULL
30 #define HXGE_VMAC_TX_STAT_CLEAR 0x7ULL
31 #define HXGE_VMAC_RX_MASK_OVERFLOW 0x1fe
32 #define HXGE_VMAC_RX_MASK_FRAME 0x1
33
34 hpi_status_t
hpi_tx_vmac_reset(hpi_handle_t handle)35 hpi_tx_vmac_reset(hpi_handle_t handle)
36 {
37 vmac_rst_t reset;
38
39 HXGE_REG_RD64(handle, VMAC_RST, &(reset.value));
40
41 reset.bits.tx_reset = 1;
42
43 HXGE_REG_WR64(handle, VMAC_RST, reset.value);
44
45 return (HPI_SUCCESS);
46 }
47
48 hpi_status_t
hpi_rx_vmac_reset(hpi_handle_t handle)49 hpi_rx_vmac_reset(hpi_handle_t handle)
50 {
51 vmac_rst_t reset;
52
53 HXGE_REG_RD64(handle, VMAC_RST, &(reset.value));
54
55 reset.bits.rx_reset = 1;
56
57 HXGE_REG_WR64(handle, VMAC_RST, reset.value);
58
59 return (HPI_SUCCESS);
60 }
61
62
63 hpi_status_t
hpi_vmac_tx_config(hpi_handle_t handle,config_op_t op,uint64_t config,uint16_t max_frame_length)64 hpi_vmac_tx_config(hpi_handle_t handle, config_op_t op, uint64_t config,
65 uint16_t max_frame_length)
66 {
67 vmac_tx_cfg_t cfg;
68
69 if (config == 0) {
70 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
71 " hpi_vmac_tx_config Invalid Input: config <0x%x>",
72 config));
73 return (HPI_FAILURE);
74 }
75
76 HXGE_REG_RD64(handle, VMAC_TX_CFG, &cfg.value);
77
78 switch (op) {
79 case ENABLE:
80 if (config & CFG_VMAC_TX_EN)
81 cfg.bits.tx_en = 1;
82 if (config & CFG_VMAC_TX_CRC_INSERT)
83 cfg.bits.crc_insert = 1;
84 if (config & CFG_VMAC_TX_PAD)
85 cfg.bits.tx_pad = 1;
86 if (max_frame_length)
87 cfg.bits.tx_max_frame_length = max_frame_length;
88 break;
89 case DISABLE:
90 if (config & CFG_VMAC_TX_EN)
91 cfg.bits.tx_en = 0;
92 if (config & CFG_VMAC_TX_CRC_INSERT)
93 cfg.bits.crc_insert = 0;
94 if (config & CFG_VMAC_TX_PAD)
95 cfg.bits.tx_pad = 0;
96 break;
97 case INIT:
98 if (config & CFG_VMAC_TX_EN)
99 cfg.bits.tx_en = 1;
100 else
101 cfg.bits.tx_en = 0;
102
103 if (config & CFG_VMAC_TX_CRC_INSERT)
104 cfg.bits.crc_insert = 1;
105 else
106 cfg.bits.crc_insert = 0;
107
108 if (config & CFG_VMAC_TX_PAD)
109 cfg.bits.tx_pad = 1;
110 else
111 cfg.bits.tx_pad = 0;
112
113 if (max_frame_length)
114 cfg.bits.tx_max_frame_length = max_frame_length;
115
116 break;
117 default:
118 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
119 " hpi_vmac_tx_config Invalid Input: op <0x%x>", op));
120 return (HPI_FAILURE);
121 }
122
123 HXGE_REG_WR64(handle, VMAC_TX_CFG, cfg.value);
124
125 return (HPI_SUCCESS);
126 }
127
128 hpi_status_t
hpi_vmac_rx_set_framesize(hpi_handle_t handle,uint16_t max_frame_length)129 hpi_vmac_rx_set_framesize(hpi_handle_t handle, uint16_t max_frame_length)
130 {
131 vmac_rx_cfg_t cfg;
132 uint16_t fsize;
133
134 HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value);
135
136 /*
137 * HW team not sure setting framesize to 0 is problematic
138 * or not.
139 */
140 if (max_frame_length == 0)
141 fsize = 1;
142 else
143 fsize = max_frame_length;
144
145 cfg.bits.rx_max_frame_length = fsize;
146
147 HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value);
148
149 return (HPI_SUCCESS);
150 }
151
152 hpi_status_t
hpi_vmac_rx_config(hpi_handle_t handle,config_op_t op,uint64_t config,uint16_t max_frame_length)153 hpi_vmac_rx_config(hpi_handle_t handle, config_op_t op, uint64_t config,
154 uint16_t max_frame_length)
155 {
156 vmac_rx_cfg_t cfg;
157
158 if (config == 0) {
159 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
160 " hpi_vmac_rx_config Invalid Input: config <0x%x>",
161 config));
162 return (HPI_FAILURE);
163 }
164
165 HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value);
166
167 switch (op) {
168 case ENABLE:
169 if (config & CFG_VMAC_RX_EN)
170 cfg.bits.rx_en = 1;
171 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE)
172 cfg.bits.crc_check_disable = 1;
173 if (config & CFG_VMAC_RX_STRIP_CRC)
174 cfg.bits.strip_crc = 1;
175 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR)
176 cfg.bits.pass_flow_ctrl_fr = 1;
177 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP)
178 cfg.bits.promiscuous_group = 1;
179 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE)
180 cfg.bits.promiscuous_mode = 1;
181 if (config & CFG_VMAC_RX_LOOP_BACK)
182 cfg.bits.loopback = 1;
183 break;
184 case DISABLE:
185 if (config & CFG_VMAC_RX_EN)
186 cfg.bits.rx_en = 0;
187 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE)
188 cfg.bits.crc_check_disable = 0;
189 if (config & CFG_VMAC_RX_STRIP_CRC)
190 cfg.bits.strip_crc = 0;
191 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR)
192 cfg.bits.pass_flow_ctrl_fr = 0;
193 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP)
194 cfg.bits.promiscuous_group = 0;
195 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE)
196 cfg.bits.promiscuous_mode = 0;
197 if (config & CFG_VMAC_RX_LOOP_BACK)
198 cfg.bits.loopback = 0;
199 break;
200 case INIT:
201 if (config & CFG_VMAC_RX_EN)
202 cfg.bits.rx_en = 1;
203 else
204 cfg.bits.rx_en = 0;
205 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE)
206 cfg.bits.crc_check_disable = 1;
207 else
208 cfg.bits.crc_check_disable = 0;
209 if (config & CFG_VMAC_RX_STRIP_CRC)
210 cfg.bits.strip_crc = 1;
211 else
212 cfg.bits.strip_crc = 0;
213 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR)
214 cfg.bits.pass_flow_ctrl_fr = 1;
215 else
216 cfg.bits.pass_flow_ctrl_fr = 0;
217 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP)
218 cfg.bits.promiscuous_group = 1;
219 else
220 cfg.bits.promiscuous_group = 0;
221 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE)
222 cfg.bits.promiscuous_mode = 1;
223 else
224 cfg.bits.promiscuous_mode = 0;
225 if (config & CFG_VMAC_RX_LOOP_BACK)
226 cfg.bits.loopback = 1;
227 else
228 cfg.bits.loopback = 0;
229
230 break;
231 default:
232 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL,
233 " hpi_vmac_rx_config Invalid Input: op <0x%x>", op));
234 return (HPI_FAILURE);
235 }
236
237 if (max_frame_length)
238 cfg.bits.rx_max_frame_length = max_frame_length;
239
240 HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value);
241
242 return (HPI_SUCCESS);
243 }
244
245 hpi_status_t
hpi_vmac_clear_rx_int_stat(hpi_handle_t handle)246 hpi_vmac_clear_rx_int_stat(hpi_handle_t handle)
247 {
248 uint64_t offset;
249
250 offset = VMAC_RX_STAT;
251 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_RX_STAT_CLEAR);
252
253 return (HPI_SUCCESS);
254 }
255
256 hpi_status_t
hpi_vmac_clear_tx_int_stat(hpi_handle_t handle)257 hpi_vmac_clear_tx_int_stat(hpi_handle_t handle)
258 {
259 uint64_t offset;
260
261 offset = VMAC_TX_STAT;
262 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_TX_STAT_CLEAR);
263
264 return (HPI_SUCCESS);
265 }
266
267 hpi_status_t
hpi_pfc_set_rx_int_stat_mask(hpi_handle_t handle,boolean_t overflow_cnt,boolean_t frame_cnt)268 hpi_pfc_set_rx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt,
269 boolean_t frame_cnt)
270 {
271 uint64_t offset;
272 uint64_t value = 0;
273
274 if (overflow_cnt)
275 value |= HXGE_VMAC_RX_MASK_OVERFLOW;
276
277 if (frame_cnt)
278 value |= HXGE_VMAC_RX_MASK_FRAME;
279
280 offset = VMAC_RX_MSK;
281 REG_PIO_WRITE64(handle, offset, value);
282
283 return (HPI_SUCCESS);
284 }
285
286 hpi_status_t
hpi_pfc_set_tx_int_stat_mask(hpi_handle_t handle,boolean_t overflow_cnt,boolean_t frame_cnt)287 hpi_pfc_set_tx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt,
288 boolean_t frame_cnt)
289 {
290 uint64_t offset;
291 uint64_t value = 0;
292 uint64_t overflow_mask = 0x6;
293 uint64_t frame_mask = 0x1;
294
295 if (overflow_cnt)
296 value |= overflow_mask;
297
298 if (frame_cnt)
299 value |= frame_mask;
300
301 offset = VMAC_TX_MSK;
302 REG_PIO_WRITE64(handle, offset, value);
303
304 return (HPI_SUCCESS);
305 }
306