xref: /linux/drivers/crypto/hisilicon/zip/zip_main.c (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #include <linux/acpi.h>
4 #include <linux/bitops.h>
5 #include <linux/debugfs.h>
6 #include <linux/init.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/seq_file.h>
13 #include <linux/topology.h>
14 #include <linux/uacce.h>
15 #include "zip.h"
16 
17 #define CAP_FILE_PERMISSION		0444
18 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF	0xa250
19 
20 #define HZIP_QUEUE_NUM_V1		4096
21 
22 #define HZIP_CLOCK_GATE_CTRL		0x301004
23 #define HZIP_DECOMP_CHECK_ENABLE	BIT(16)
24 #define HZIP_FSM_MAX_CNT		0x301008
25 
26 #define HZIP_PORT_ARCA_CHE_0		0x301040
27 #define HZIP_PORT_ARCA_CHE_1		0x301044
28 #define HZIP_PORT_AWCA_CHE_0		0x301060
29 #define HZIP_PORT_AWCA_CHE_1		0x301064
30 #define HZIP_CACHE_ALL_EN		0xffffffff
31 
32 #define HZIP_BD_RUSER_32_63		0x301110
33 #define HZIP_SGL_RUSER_32_63		0x30111c
34 #define HZIP_DATA_RUSER_32_63		0x301128
35 #define HZIP_DATA_WUSER_32_63		0x301134
36 #define HZIP_BD_WUSER_32_63		0x301140
37 
38 #define HZIP_QM_IDEL_STATUS		0x3040e4
39 
40 #define HZIP_CORE_DFX_BASE		0x301000
41 #define HZIP_CORE_DFX_DECOMP_BASE	0x304000
42 #define HZIP_CORE_DFX_COMP_0		0x302000
43 #define HZIP_CORE_DFX_COMP_1		0x303000
44 #define HZIP_CORE_DFX_DECOMP_0		0x304000
45 #define HZIP_CORE_DFX_DECOMP_1		0x305000
46 #define HZIP_CORE_DFX_DECOMP_2		0x306000
47 #define HZIP_CORE_DFX_DECOMP_3		0x307000
48 #define HZIP_CORE_DFX_DECOMP_4		0x308000
49 #define HZIP_CORE_DFX_DECOMP_5		0x309000
50 #define HZIP_CORE_REGS_BASE_LEN		0xB0
51 #define HZIP_CORE_REGS_DFX_LEN		0x28
52 #define HZIP_CORE_ADDR_INTRVL		0x1000
53 
54 #define HZIP_CORE_INT_SOURCE		0x3010A0
55 #define HZIP_CORE_INT_MASK_REG		0x3010A4
56 #define HZIP_CORE_INT_SET		0x3010A8
57 #define HZIP_CORE_INT_STATUS		0x3010AC
58 #define HZIP_CORE_INT_STATUS_M_ECC	BIT(1)
59 #define HZIP_CORE_SRAM_ECC_ERR_INFO	0x301148
60 #define HZIP_CORE_INT_RAS_CE_ENB	0x301160
61 #define HZIP_CORE_INT_RAS_NFE_ENB	0x301164
62 #define HZIP_CORE_INT_RAS_FE_ENB        0x301168
63 #define HZIP_CORE_INT_RAS_FE_ENB_MASK	0x0
64 #define HZIP_OOO_SHUTDOWN_SEL		0x30120C
65 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT	16
66 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT	24
67 #define HZIP_CORE_INT_MASK_ALL		GENMASK(12, 0)
68 #define HZIP_SQE_SIZE			128
69 #define HZIP_PF_DEF_Q_NUM		64
70 #define HZIP_PF_DEF_Q_BASE		0
71 #define HZIP_CTX_Q_NUM_DEF		2
72 
73 #define HZIP_SOFT_CTRL_CNT_CLR_CE	0x301000
74 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT	BIT(0)
75 #define HZIP_SOFT_CTRL_ZIP_CONTROL	0x30100C
76 #define HZIP_AXI_SHUTDOWN_ENABLE	BIT(14)
77 #define HZIP_WR_PORT			BIT(11)
78 
79 #define HZIP_ALG_ZLIB_BIT		GENMASK(1, 0)
80 #define HZIP_ALG_GZIP_BIT		GENMASK(3, 2)
81 #define HZIP_ALG_DEFLATE_BIT		GENMASK(5, 4)
82 #define HZIP_ALG_LZ77_BIT		GENMASK(7, 6)
83 
84 #define HZIP_BUF_SIZE			22
85 #define HZIP_SQE_MASK_OFFSET		64
86 #define HZIP_SQE_MASK_LEN		48
87 
88 #define HZIP_CNT_CLR_CE_EN		BIT(0)
89 #define HZIP_RO_CNT_CLR_CE_EN		BIT(2)
90 #define HZIP_RD_CNT_CLR_CE_EN		(HZIP_CNT_CLR_CE_EN | \
91 					 HZIP_RO_CNT_CLR_CE_EN)
92 
93 #define HZIP_PREFETCH_CFG		0x3011B0
94 #define HZIP_SVA_TRANS			0x3011C4
95 #define HZIP_PREFETCH_ENABLE		(~(BIT(26) | BIT(17) | BIT(0)))
96 #define HZIP_SVA_PREFETCH_DISABLE	BIT(26)
97 #define HZIP_SVA_DISABLE_READY		(BIT(26) | BIT(30))
98 #define HZIP_SHAPER_RATE_COMPRESS	750
99 #define HZIP_SHAPER_RATE_DECOMPRESS	140
100 #define HZIP_DELAY_1_US		1
101 #define HZIP_POLL_TIMEOUT_US	1000
102 
103 /* clock gating */
104 #define HZIP_PEH_CFG_AUTO_GATE		0x3011A8
105 #define HZIP_PEH_CFG_AUTO_GATE_EN	BIT(0)
106 #define HZIP_CORE_GATED_EN		GENMASK(15, 8)
107 #define HZIP_CORE_GATED_OOO_EN		BIT(29)
108 #define HZIP_CLOCK_GATED_EN		(HZIP_CORE_GATED_EN | \
109 					 HZIP_CORE_GATED_OOO_EN)
110 
111 /* zip comp high performance */
112 #define HZIP_HIGH_PERF_OFFSET		0x301208
113 
114 enum {
115 	HZIP_HIGH_COMP_RATE,
116 	HZIP_HIGH_COMP_PERF,
117 };
118 
119 static const char hisi_zip_name[] = "hisi_zip";
120 static struct dentry *hzip_debugfs_root;
121 
122 struct hisi_zip_hw_error {
123 	u32 int_msk;
124 	const char *msg;
125 };
126 
127 struct zip_dfx_item {
128 	const char *name;
129 	u32 offset;
130 };
131 
132 static const struct qm_dev_alg zip_dev_algs[] = { {
133 		.alg_msk = HZIP_ALG_ZLIB_BIT,
134 		.alg = "zlib\n",
135 	}, {
136 		.alg_msk = HZIP_ALG_GZIP_BIT,
137 		.alg = "gzip\n",
138 	}, {
139 		.alg_msk = HZIP_ALG_DEFLATE_BIT,
140 		.alg = "deflate\n",
141 	}, {
142 		.alg_msk = HZIP_ALG_LZ77_BIT,
143 		.alg = "lz77_zstd\n",
144 	},
145 };
146 
147 static struct hisi_qm_list zip_devices = {
148 	.register_to_crypto	= hisi_zip_register_to_crypto,
149 	.unregister_from_crypto	= hisi_zip_unregister_from_crypto,
150 };
151 
152 static struct zip_dfx_item zip_dfx_files[] = {
153 	{"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)},
154 	{"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)},
155 	{"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)},
156 	{"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)},
157 };
158 
159 static const struct hisi_zip_hw_error zip_hw_error[] = {
160 	{ .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" },
161 	{ .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" },
162 	{ .int_msk = BIT(2), .msg = "zip_axi_rresp_err" },
163 	{ .int_msk = BIT(3), .msg = "zip_axi_bresp_err" },
164 	{ .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" },
165 	{ .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" },
166 	{ .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" },
167 	{ .int_msk = BIT(7), .msg = "zip_pre_in_data_err" },
168 	{ .int_msk = BIT(8), .msg = "zip_com_inf_err" },
169 	{ .int_msk = BIT(9), .msg = "zip_enc_inf_err" },
170 	{ .int_msk = BIT(10), .msg = "zip_pre_out_err" },
171 	{ .int_msk = BIT(11), .msg = "zip_axi_poison_err" },
172 	{ .int_msk = BIT(12), .msg = "zip_sva_err" },
173 	{ /* sentinel */ }
174 };
175 
176 enum ctrl_debug_file_index {
177 	HZIP_CLEAR_ENABLE,
178 	HZIP_DEBUG_FILE_NUM,
179 };
180 
181 static const char * const ctrl_debug_file_name[] = {
182 	[HZIP_CLEAR_ENABLE] = "clear_enable",
183 };
184 
185 struct ctrl_debug_file {
186 	enum ctrl_debug_file_index index;
187 	spinlock_t lock;
188 	struct hisi_zip_ctrl *ctrl;
189 };
190 
191 /*
192  * One ZIP controller has one PF and multiple VFs, some global configurations
193  * which PF has need this structure.
194  *
195  * Just relevant for PF.
196  */
197 struct hisi_zip_ctrl {
198 	struct hisi_zip *hisi_zip;
199 	struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM];
200 };
201 
202 enum zip_cap_type {
203 	ZIP_QM_NFE_MASK_CAP = 0x0,
204 	ZIP_QM_RESET_MASK_CAP,
205 	ZIP_QM_OOO_SHUTDOWN_MASK_CAP,
206 	ZIP_QM_CE_MASK_CAP,
207 	ZIP_NFE_MASK_CAP,
208 	ZIP_RESET_MASK_CAP,
209 	ZIP_OOO_SHUTDOWN_MASK_CAP,
210 	ZIP_CE_MASK_CAP,
211 	ZIP_CLUSTER_NUM_CAP,
212 	ZIP_CORE_TYPE_NUM_CAP,
213 	ZIP_CORE_NUM_CAP,
214 	ZIP_CLUSTER_COMP_NUM_CAP,
215 	ZIP_CLUSTER_DECOMP_NUM_CAP,
216 	ZIP_DECOMP_ENABLE_BITMAP,
217 	ZIP_COMP_ENABLE_BITMAP,
218 	ZIP_DRV_ALG_BITMAP,
219 	ZIP_DEV_ALG_BITMAP,
220 	ZIP_CORE1_ALG_BITMAP,
221 	ZIP_CORE2_ALG_BITMAP,
222 	ZIP_CORE3_ALG_BITMAP,
223 	ZIP_CORE4_ALG_BITMAP,
224 	ZIP_CORE5_ALG_BITMAP,
225 	ZIP_CAP_MAX
226 };
227 
228 static struct hisi_qm_cap_info zip_basic_cap_info[] = {
229 	{ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77},
230 	{ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77},
231 	{ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},
232 	{ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
233 	{ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE},
234 	{ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE},
235 	{ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE},
236 	{ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1},
237 	{ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1},
238 	{ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2},
239 	{ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5},
240 	{ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2},
241 	{ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3},
242 	{ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C},
243 	{ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3},
244 	{ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0x0, 0x0, 0x30},
245 	{ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0x3F},
246 	{ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},
247 	{ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5},
248 	{ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
249 	{ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
250 	{ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A},
251 	{ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0}
252 };
253 
254 static const struct hisi_qm_cap_query_info zip_cap_query_info[] = {
255 	{QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE             ", 0x3124, 0x0, 0x1C57, 0x7C77},
256 	{QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET            ", 0x3128, 0x0, 0xC57, 0x6C77},
257 	{QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE              ", 0x312C, 0x0, 0x8, 0x8},
258 	{ZIP_RAS_NFE_TYPE, "ZIP_RAS_NFE_TYPE            ", 0x3130, 0x0, 0x7FE, 0x1FFE},
259 	{ZIP_RAS_NFE_RESET, "ZIP_RAS_NFE_RESET           ", 0x3134, 0x0, 0x7FE, 0x7FE},
260 	{ZIP_RAS_CE_TYPE, "ZIP_RAS_CE_TYPE             ", 0x3138, 0x0, 0x1, 0x1},
261 	{ZIP_CORE_INFO, "ZIP_CORE_INFO               ", 0x313C, 0x12080206, 0x12080206, 0x12050203},
262 	{ZIP_CORE_EN, "ZIP_CORE_EN                 ", 0x3140, 0xFC0003, 0xFC0003, 0x1C0003},
263 	{ZIP_DRV_ALG_BITMAP_TB, "ZIP_DRV_ALG_BITMAP          ", 0x3144, 0x0, 0x0, 0x30},
264 	{ZIP_ALG_BITMAP, "ZIP_ALG_BITMAP              ", 0x3148, 0xF, 0xF, 0x3F},
265 	{ZIP_CORE1_BITMAP, "ZIP_CORE1_BITMAP            ", 0x314C, 0x5, 0x5, 0xD5},
266 	{ZIP_CORE2_BITMAP, "ZIP_CORE2_BITMAP            ", 0x3150, 0x5, 0x5, 0xD5},
267 	{ZIP_CORE3_BITMAP, "ZIP_CORE3_BITMAP            ", 0x3154, 0xA, 0xA, 0x2A},
268 	{ZIP_CORE4_BITMAP, "ZIP_CORE4_BITMAP            ", 0x3158, 0xA, 0xA, 0x2A},
269 	{ZIP_CORE5_BITMAP, "ZIP_CORE5_BITMAP            ", 0x315C, 0xA, 0xA, 0x2A},
270 };
271 
272 static const struct debugfs_reg32 hzip_dfx_regs[] = {
273 	{"HZIP_GET_BD_NUM                ",  0x00},
274 	{"HZIP_GET_RIGHT_BD              ",  0x04},
275 	{"HZIP_GET_ERROR_BD              ",  0x08},
276 	{"HZIP_DONE_BD_NUM               ",  0x0c},
277 	{"HZIP_WORK_CYCLE                ",  0x10},
278 	{"HZIP_IDLE_CYCLE                ",  0x18},
279 	{"HZIP_MAX_DELAY                 ",  0x20},
280 	{"HZIP_MIN_DELAY                 ",  0x24},
281 	{"HZIP_AVG_DELAY                 ",  0x28},
282 	{"HZIP_MEM_VISIBLE_DATA          ",  0x30},
283 	{"HZIP_MEM_VISIBLE_ADDR          ",  0x34},
284 	{"HZIP_CONSUMED_BYTE             ",  0x38},
285 	{"HZIP_PRODUCED_BYTE             ",  0x40},
286 	{"HZIP_COMP_INF                  ",  0x70},
287 	{"HZIP_PRE_OUT                   ",  0x78},
288 	{"HZIP_BD_RD                     ",  0x7c},
289 	{"HZIP_BD_WR                     ",  0x80},
290 	{"HZIP_GET_BD_AXI_ERR_NUM        ",  0x84},
291 	{"HZIP_GET_BD_PARSE_ERR_NUM      ",  0x88},
292 	{"HZIP_ADD_BD_AXI_ERR_NUM        ",  0x8c},
293 	{"HZIP_DECOMP_STF_RELOAD_CURR_ST ",  0x94},
294 	{"HZIP_DECOMP_LZ77_CURR_ST       ",  0x9c},
295 };
296 
297 static const struct debugfs_reg32 hzip_com_dfx_regs[] = {
298 	{"HZIP_CLOCK_GATE_CTRL           ",  0x301004},
299 	{"HZIP_CORE_INT_RAS_CE_ENB       ",  0x301160},
300 	{"HZIP_CORE_INT_RAS_NFE_ENB      ",  0x301164},
301 	{"HZIP_CORE_INT_RAS_FE_ENB       ",  0x301168},
302 	{"HZIP_UNCOM_ERR_RAS_CTRL        ",  0x30116C},
303 };
304 
305 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = {
306 	{"HZIP_GET_BD_NUM                ",  0x00},
307 	{"HZIP_GET_RIGHT_BD              ",  0x04},
308 	{"HZIP_GET_ERROR_BD              ",  0x08},
309 	{"HZIP_DONE_BD_NUM               ",  0x0c},
310 	{"HZIP_MAX_DELAY                 ",  0x20},
311 };
312 
313 /* define the ZIP's dfx regs region and region length */
314 static struct dfx_diff_registers hzip_diff_regs[] = {
315 	{
316 		.reg_offset = HZIP_CORE_DFX_BASE,
317 		.reg_len = HZIP_CORE_REGS_BASE_LEN,
318 	}, {
319 		.reg_offset = HZIP_CORE_DFX_COMP_0,
320 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
321 	}, {
322 		.reg_offset = HZIP_CORE_DFX_COMP_1,
323 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
324 	}, {
325 		.reg_offset = HZIP_CORE_DFX_DECOMP_0,
326 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
327 	}, {
328 		.reg_offset = HZIP_CORE_DFX_DECOMP_1,
329 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
330 	}, {
331 		.reg_offset = HZIP_CORE_DFX_DECOMP_2,
332 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
333 	}, {
334 		.reg_offset = HZIP_CORE_DFX_DECOMP_3,
335 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
336 	}, {
337 		.reg_offset = HZIP_CORE_DFX_DECOMP_4,
338 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
339 	}, {
340 		.reg_offset = HZIP_CORE_DFX_DECOMP_5,
341 		.reg_len = HZIP_CORE_REGS_DFX_LEN,
342 	},
343 };
344 
hzip_diff_regs_show(struct seq_file * s,void * unused)345 static int hzip_diff_regs_show(struct seq_file *s, void *unused)
346 {
347 	struct hisi_qm *qm = s->private;
348 
349 	hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
350 					ARRAY_SIZE(hzip_diff_regs));
351 
352 	return 0;
353 }
354 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs);
355 
perf_mode_set(const char * val,const struct kernel_param * kp)356 static int perf_mode_set(const char *val, const struct kernel_param *kp)
357 {
358 	int ret;
359 	u32 n;
360 
361 	if (!val)
362 		return -EINVAL;
363 
364 	ret = kstrtou32(val, 10, &n);
365 	if (ret != 0 || (n != HZIP_HIGH_COMP_PERF &&
366 			 n != HZIP_HIGH_COMP_RATE))
367 		return -EINVAL;
368 
369 	return param_set_int(val, kp);
370 }
371 
372 static const struct kernel_param_ops zip_com_perf_ops = {
373 	.set = perf_mode_set,
374 	.get = param_get_int,
375 };
376 
377 /*
378  * perf_mode = 0 means enable high compression rate mode,
379  * perf_mode = 1 means enable high compression performance mode.
380  * These two modes only apply to the compression direction.
381  */
382 static u32 perf_mode = HZIP_HIGH_COMP_RATE;
383 module_param_cb(perf_mode, &zip_com_perf_ops, &perf_mode, 0444);
384 MODULE_PARM_DESC(perf_mode, "ZIP high perf mode 0(default), 1(enable)");
385 
386 static const struct kernel_param_ops zip_uacce_mode_ops = {
387 	.set = uacce_mode_set,
388 	.get = param_get_int,
389 };
390 
391 /*
392  * uacce_mode = 0 means zip only register to crypto,
393  * uacce_mode = 1 means zip both register to crypto and uacce.
394  */
395 static u32 uacce_mode = UACCE_MODE_NOUACCE;
396 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444);
397 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
398 
399 static bool pf_q_num_flag;
pf_q_num_set(const char * val,const struct kernel_param * kp)400 static int pf_q_num_set(const char *val, const struct kernel_param *kp)
401 {
402 	pf_q_num_flag = true;
403 
404 	return hisi_qm_q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF);
405 }
406 
407 static const struct kernel_param_ops pf_q_num_ops = {
408 	.set = pf_q_num_set,
409 	.get = param_get_int,
410 };
411 
412 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM;
413 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444);
414 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
415 
416 static const struct kernel_param_ops vfs_num_ops = {
417 	.set = vfs_num_set,
418 	.get = param_get_int,
419 };
420 
421 static u32 vfs_num;
422 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
423 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
424 
425 static const struct pci_device_id hisi_zip_dev_ids[] = {
426 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) },
427 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) },
428 	{ 0, }
429 };
430 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids);
431 
zip_create_qps(struct hisi_qp ** qps,int qp_num,int node)432 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node)
433 {
434 	if (node == NUMA_NO_NODE)
435 		node = cpu_to_node(raw_smp_processor_id());
436 
437 	return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps);
438 }
439 
hisi_zip_alg_support(struct hisi_qm * qm,u32 alg)440 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)
441 {
442 	u32 cap_val;
443 
444 	cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_TB].cap_val;
445 	if ((alg & cap_val) == alg)
446 		return true;
447 
448 	return false;
449 }
450 
hisi_zip_set_high_perf(struct hisi_qm * qm)451 static int hisi_zip_set_high_perf(struct hisi_qm *qm)
452 {
453 	u32 val;
454 	int ret;
455 
456 	val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET);
457 	if (perf_mode == HZIP_HIGH_COMP_PERF)
458 		val |= HZIP_HIGH_COMP_PERF;
459 	else
460 		val &= ~HZIP_HIGH_COMP_PERF;
461 
462 	/* Set perf mode */
463 	writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET);
464 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET,
465 					 val, val == perf_mode, HZIP_DELAY_1_US,
466 					 HZIP_POLL_TIMEOUT_US);
467 	if (ret)
468 		pci_err(qm->pdev, "failed to set perf mode\n");
469 
470 	return ret;
471 }
472 
hisi_zip_open_sva_prefetch(struct hisi_qm * qm)473 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm)
474 {
475 	u32 val;
476 	int ret;
477 
478 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
479 		return;
480 
481 	/* Enable prefetch */
482 	val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);
483 	val &= HZIP_PREFETCH_ENABLE;
484 	writel(val, qm->io_base + HZIP_PREFETCH_CFG);
485 
486 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG,
487 					 val, !(val & HZIP_SVA_PREFETCH_DISABLE),
488 					 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US);
489 	if (ret)
490 		pci_err(qm->pdev, "failed to open sva prefetch\n");
491 }
492 
hisi_zip_close_sva_prefetch(struct hisi_qm * qm)493 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm)
494 {
495 	u32 val;
496 	int ret;
497 
498 	if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
499 		return;
500 
501 	val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);
502 	val |= HZIP_SVA_PREFETCH_DISABLE;
503 	writel(val, qm->io_base + HZIP_PREFETCH_CFG);
504 
505 	ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS,
506 					 val, !(val & HZIP_SVA_DISABLE_READY),
507 					 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US);
508 	if (ret)
509 		pci_err(qm->pdev, "failed to close sva prefetch\n");
510 }
511 
hisi_zip_enable_clock_gate(struct hisi_qm * qm)512 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm)
513 {
514 	u32 val;
515 
516 	if (qm->ver < QM_HW_V3)
517 		return;
518 
519 	val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL);
520 	val |= HZIP_CLOCK_GATED_EN;
521 	writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL);
522 
523 	val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE);
524 	val |= HZIP_PEH_CFG_AUTO_GATE_EN;
525 	writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE);
526 }
527 
hisi_zip_set_user_domain_and_cache(struct hisi_qm * qm)528 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
529 {
530 	void __iomem *base = qm->io_base;
531 	u32 dcomp_bm, comp_bm;
532 	u32 zip_core_en;
533 
534 	/* qm user domain */
535 	writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
536 	writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
537 	writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
538 	writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
539 	writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
540 
541 	/* qm cache */
542 	writel(AXI_M_CFG, base + QM_AXI_M_CFG);
543 	writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
544 
545 	/* disable FLR triggered by BME(bus master enable) */
546 	writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
547 	writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
548 
549 	/* cache */
550 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
551 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
552 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
553 	writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
554 
555 	/* user domain configurations */
556 	writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
557 	writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
558 
559 	if (qm->use_sva && qm->ver == QM_HW_V2) {
560 		writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
561 		writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
562 		writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63);
563 	} else {
564 		writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
565 		writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
566 		writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
567 	}
568 
569 	/* let's open all compression/decompression cores */
570 
571 	zip_core_en = qm->cap_tables.dev_cap_table[ZIP_CORE_EN].cap_val;
572 	dcomp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].shift) &
573 			zip_basic_cap_info[ZIP_DECOMP_ENABLE_BITMAP].mask;
574 	comp_bm = (zip_core_en >> zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].shift) &
575 			zip_basic_cap_info[ZIP_COMP_ENABLE_BITMAP].mask;
576 	writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL);
577 
578 	/* enable sqc,cqc writeback */
579 	writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
580 	       CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
581 	       FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
582 
583 	hisi_zip_enable_clock_gate(qm);
584 
585 	return 0;
586 }
587 
hisi_zip_master_ooo_ctrl(struct hisi_qm * qm,bool enable)588 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
589 {
590 	u32 val1, val2;
591 
592 	val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
593 	if (enable) {
594 		val1 |= HZIP_AXI_SHUTDOWN_ENABLE;
595 		val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
596 				ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
597 	} else {
598 		val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE;
599 		val2 = 0x0;
600 	}
601 
602 	if (qm->ver > QM_HW_V2)
603 		writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);
604 
605 	writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
606 }
607 
hisi_zip_hw_error_enable(struct hisi_qm * qm)608 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
609 {
610 	u32 nfe, ce;
611 
612 	if (qm->ver == QM_HW_V1) {
613 		writel(HZIP_CORE_INT_MASK_ALL,
614 		       qm->io_base + HZIP_CORE_INT_MASK_REG);
615 		dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
616 		return;
617 	}
618 
619 	nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);
620 	ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver);
621 
622 	/* clear ZIP hw error source if having */
623 	writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE);
624 
625 	/* configure error type */
626 	writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
627 	writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
628 	writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
629 
630 	hisi_zip_master_ooo_ctrl(qm, true);
631 
632 	/* enable ZIP hw error interrupts */
633 	writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
634 }
635 
hisi_zip_hw_error_disable(struct hisi_qm * qm)636 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)
637 {
638 	u32 nfe, ce;
639 
640 	/* disable ZIP hw error interrupts */
641 	nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);
642 	ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver);
643 	writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG);
644 
645 	hisi_zip_master_ooo_ctrl(qm, false);
646 }
647 
file_to_qm(struct ctrl_debug_file * file)648 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file)
649 {
650 	struct hisi_zip *hisi_zip = file->ctrl->hisi_zip;
651 
652 	return &hisi_zip->qm;
653 }
654 
clear_enable_read(struct hisi_qm * qm)655 static u32 clear_enable_read(struct hisi_qm *qm)
656 {
657 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
658 		     HZIP_SOFT_CTRL_CNT_CLR_CE_BIT;
659 }
660 
clear_enable_write(struct hisi_qm * qm,u32 val)661 static int clear_enable_write(struct hisi_qm *qm, u32 val)
662 {
663 	u32 tmp;
664 
665 	if (val != 1 && val != 0)
666 		return -EINVAL;
667 
668 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
669 	       ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val;
670 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
671 
672 	return  0;
673 }
674 
hisi_zip_ctrl_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)675 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf,
676 					size_t count, loff_t *pos)
677 {
678 	struct ctrl_debug_file *file = filp->private_data;
679 	struct hisi_qm *qm = file_to_qm(file);
680 	char tbuf[HZIP_BUF_SIZE];
681 	u32 val;
682 	int ret;
683 
684 	ret = hisi_qm_get_dfx_access(qm);
685 	if (ret)
686 		return ret;
687 
688 	spin_lock_irq(&file->lock);
689 	switch (file->index) {
690 	case HZIP_CLEAR_ENABLE:
691 		val = clear_enable_read(qm);
692 		break;
693 	default:
694 		goto err_input;
695 	}
696 	spin_unlock_irq(&file->lock);
697 
698 	hisi_qm_put_dfx_access(qm);
699 	ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val);
700 	return simple_read_from_buffer(buf, count, pos, tbuf, ret);
701 
702 err_input:
703 	spin_unlock_irq(&file->lock);
704 	hisi_qm_put_dfx_access(qm);
705 	return -EINVAL;
706 }
707 
hisi_zip_ctrl_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)708 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp,
709 					 const char __user *buf,
710 					 size_t count, loff_t *pos)
711 {
712 	struct ctrl_debug_file *file = filp->private_data;
713 	struct hisi_qm *qm = file_to_qm(file);
714 	char tbuf[HZIP_BUF_SIZE];
715 	unsigned long val;
716 	int len, ret;
717 
718 	if (*pos != 0)
719 		return 0;
720 
721 	if (count >= HZIP_BUF_SIZE)
722 		return -ENOSPC;
723 
724 	len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count);
725 	if (len < 0)
726 		return len;
727 
728 	tbuf[len] = '\0';
729 	ret = kstrtoul(tbuf, 0, &val);
730 	if (ret)
731 		return ret;
732 
733 	ret = hisi_qm_get_dfx_access(qm);
734 	if (ret)
735 		return ret;
736 
737 	spin_lock_irq(&file->lock);
738 	switch (file->index) {
739 	case HZIP_CLEAR_ENABLE:
740 		ret = clear_enable_write(qm, val);
741 		if (ret)
742 			goto err_input;
743 		break;
744 	default:
745 		ret = -EINVAL;
746 		goto err_input;
747 	}
748 
749 	ret = count;
750 
751 err_input:
752 	spin_unlock_irq(&file->lock);
753 	hisi_qm_put_dfx_access(qm);
754 	return ret;
755 }
756 
757 static const struct file_operations ctrl_debug_fops = {
758 	.owner = THIS_MODULE,
759 	.open = simple_open,
760 	.read = hisi_zip_ctrl_debug_read,
761 	.write = hisi_zip_ctrl_debug_write,
762 };
763 
zip_debugfs_atomic64_set(void * data,u64 val)764 static int zip_debugfs_atomic64_set(void *data, u64 val)
765 {
766 	if (val)
767 		return -EINVAL;
768 
769 	atomic64_set((atomic64_t *)data, 0);
770 
771 	return 0;
772 }
773 
zip_debugfs_atomic64_get(void * data,u64 * val)774 static int zip_debugfs_atomic64_get(void *data, u64 *val)
775 {
776 	*val = atomic64_read((atomic64_t *)data);
777 
778 	return 0;
779 }
780 
781 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get,
782 			 zip_debugfs_atomic64_set, "%llu\n");
783 
hisi_zip_regs_show(struct seq_file * s,void * unused)784 static int hisi_zip_regs_show(struct seq_file *s, void *unused)
785 {
786 	hisi_qm_regs_dump(s, s->private);
787 
788 	return 0;
789 }
790 
791 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs);
792 
get_zip_core_addr(struct hisi_qm * qm,int core_num)793 static void __iomem *get_zip_core_addr(struct hisi_qm *qm, int core_num)
794 {
795 	u8 zip_comp_core_num;
796 	u32 zip_core_info;
797 
798 	zip_core_info =  qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;
799 	zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) &
800 			     zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask;
801 
802 	if (core_num < zip_comp_core_num)
803 		return qm->io_base + HZIP_CORE_DFX_BASE +
804 			(core_num + 1) * HZIP_CORE_ADDR_INTRVL;
805 
806 	return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE +
807 		(core_num - zip_comp_core_num) * HZIP_CORE_ADDR_INTRVL;
808 }
809 
hisi_zip_core_debug_init(struct hisi_qm * qm)810 static int hisi_zip_core_debug_init(struct hisi_qm *qm)
811 {
812 	u32 zip_core_num, zip_comp_core_num;
813 	struct device *dev = &qm->pdev->dev;
814 	struct debugfs_regset32 *regset;
815 	u32 zip_core_info;
816 	struct dentry *tmp_d;
817 	char buf[HZIP_BUF_SIZE];
818 	int i;
819 
820 	zip_core_info =  qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;
821 	zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) &
822 			zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask;
823 	zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) &
824 			zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask;
825 
826 	for (i = 0; i < zip_core_num; i++) {
827 		if (i < zip_comp_core_num)
828 			scnprintf(buf, sizeof(buf), "comp_core%d", i);
829 		else
830 			scnprintf(buf, sizeof(buf), "decomp_core%d",
831 				  i - zip_comp_core_num);
832 
833 		regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
834 		if (!regset)
835 			return -ENOENT;
836 
837 		regset->regs = hzip_dfx_regs;
838 		regset->nregs = ARRAY_SIZE(hzip_dfx_regs);
839 		regset->base = get_zip_core_addr(qm, i);
840 		regset->dev = dev;
841 
842 		tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
843 		debugfs_create_file("regs", 0444, tmp_d, regset,
844 				    &hisi_zip_regs_fops);
845 	}
846 
847 	return 0;
848 }
849 
zip_cap_regs_show(struct seq_file * s,void * unused)850 static int zip_cap_regs_show(struct seq_file *s, void *unused)
851 {
852 	struct hisi_qm *qm = s->private;
853 	u32 i, size;
854 
855 	size = qm->cap_tables.qm_cap_size;
856 	for (i = 0; i < size; i++)
857 		seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,
858 			   qm->cap_tables.qm_cap_table[i].cap_val);
859 
860 	size = qm->cap_tables.dev_cap_size;
861 	for (i = 0; i < size; i++)
862 		seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,
863 			   qm->cap_tables.dev_cap_table[i].cap_val);
864 
865 	return 0;
866 }
867 
868 DEFINE_SHOW_ATTRIBUTE(zip_cap_regs);
869 
hisi_zip_dfx_debug_init(struct hisi_qm * qm)870 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)
871 {
872 	struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs;
873 	struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
874 	struct hisi_zip_dfx *dfx = &zip->dfx;
875 	struct dentry *tmp_dir;
876 	void *data;
877 	int i;
878 
879 	tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);
880 	for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) {
881 		data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset);
882 		debugfs_create_file(zip_dfx_files[i].name,
883 				    0644, tmp_dir, data,
884 				    &zip_atomic64_ops);
885 	}
886 
887 	if (qm->fun_type == QM_HW_PF && hzip_regs)
888 		debugfs_create_file("diff_regs", 0444, tmp_dir,
889 				      qm, &hzip_diff_regs_fops);
890 
891 	debugfs_create_file("cap_regs", CAP_FILE_PERMISSION,
892 			    qm->debug.debug_root, qm, &zip_cap_regs_fops);
893 }
894 
hisi_zip_ctrl_debug_init(struct hisi_qm * qm)895 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm)
896 {
897 	struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
898 	int i;
899 
900 	for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) {
901 		spin_lock_init(&zip->ctrl->files[i].lock);
902 		zip->ctrl->files[i].ctrl = zip->ctrl;
903 		zip->ctrl->files[i].index = i;
904 
905 		debugfs_create_file(ctrl_debug_file_name[i], 0600,
906 				    qm->debug.debug_root,
907 				    zip->ctrl->files + i,
908 				    &ctrl_debug_fops);
909 	}
910 
911 	return hisi_zip_core_debug_init(qm);
912 }
913 
hisi_zip_debugfs_init(struct hisi_qm * qm)914 static int hisi_zip_debugfs_init(struct hisi_qm *qm)
915 {
916 	struct device *dev = &qm->pdev->dev;
917 	int ret;
918 
919 	ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs));
920 	if (ret) {
921 		dev_warn(dev, "Failed to init ZIP diff regs!\n");
922 		return ret;
923 	}
924 
925 	qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;
926 	qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;
927 	qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
928 							hzip_debugfs_root);
929 
930 	hisi_qm_debug_init(qm);
931 
932 	if (qm->fun_type == QM_HW_PF) {
933 		ret = hisi_zip_ctrl_debug_init(qm);
934 		if (ret)
935 			goto debugfs_remove;
936 	}
937 
938 	hisi_zip_dfx_debug_init(qm);
939 
940 	return 0;
941 
942 debugfs_remove:
943 	debugfs_remove_recursive(qm->debug.debug_root);
944 	hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));
945 	return ret;
946 }
947 
948 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */
hisi_zip_debug_regs_clear(struct hisi_qm * qm)949 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)
950 {
951 	u32 zip_core_info;
952 	u8 zip_core_num;
953 	int i, j;
954 
955 	zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;
956 	zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) &
957 			zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask;
958 
959 	/* enable register read_clear bit */
960 	writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
961 	for (i = 0; i < zip_core_num; i++)
962 		for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++)
963 			readl(get_zip_core_addr(qm, i) +
964 			      hzip_dfx_regs[j].offset);
965 
966 	/* disable register read_clear bit */
967 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
968 
969 	hisi_qm_debug_regs_clear(qm);
970 }
971 
hisi_zip_debugfs_exit(struct hisi_qm * qm)972 static void hisi_zip_debugfs_exit(struct hisi_qm *qm)
973 {
974 	debugfs_remove_recursive(qm->debug.debug_root);
975 
976 	hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));
977 
978 	if (qm->fun_type == QM_HW_PF) {
979 		hisi_zip_debug_regs_clear(qm);
980 		qm->debug.curr_qm_qp_num = 0;
981 	}
982 }
983 
hisi_zip_show_last_regs_init(struct hisi_qm * qm)984 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm)
985 {
986 	int core_dfx_regs_num =  ARRAY_SIZE(hzip_dump_dfx_regs);
987 	int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs);
988 	struct qm_debug *debug = &qm->debug;
989 	void __iomem *io_base;
990 	u32 zip_core_info;
991 	u32 zip_core_num;
992 	int i, j, idx;
993 
994 	zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;
995 	zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) &
996 			zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask;
997 
998 	debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num,
999 				    sizeof(unsigned int), GFP_KERNEL);
1000 	if (!debug->last_words)
1001 		return -ENOMEM;
1002 
1003 	for (i = 0; i < com_dfx_regs_num; i++) {
1004 		io_base = qm->io_base + hzip_com_dfx_regs[i].offset;
1005 		debug->last_words[i] = readl_relaxed(io_base);
1006 	}
1007 
1008 	for (i = 0; i < zip_core_num; i++) {
1009 		io_base = get_zip_core_addr(qm, i);
1010 		for (j = 0; j < core_dfx_regs_num; j++) {
1011 			idx = com_dfx_regs_num + i * core_dfx_regs_num + j;
1012 			debug->last_words[idx] = readl_relaxed(
1013 				io_base + hzip_dump_dfx_regs[j].offset);
1014 		}
1015 	}
1016 
1017 	return 0;
1018 }
1019 
hisi_zip_show_last_regs_uninit(struct hisi_qm * qm)1020 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm)
1021 {
1022 	struct qm_debug *debug = &qm->debug;
1023 
1024 	if (qm->fun_type == QM_HW_VF || !debug->last_words)
1025 		return;
1026 
1027 	kfree(debug->last_words);
1028 	debug->last_words = NULL;
1029 }
1030 
hisi_zip_show_last_dfx_regs(struct hisi_qm * qm)1031 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)
1032 {
1033 	int core_dfx_regs_num =  ARRAY_SIZE(hzip_dump_dfx_regs);
1034 	int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs);
1035 	u32 zip_core_num, zip_comp_core_num;
1036 	struct qm_debug *debug = &qm->debug;
1037 	char buf[HZIP_BUF_SIZE];
1038 	u32 zip_core_info;
1039 	void __iomem *base;
1040 	int i, j, idx;
1041 	u32 val;
1042 
1043 	if (qm->fun_type == QM_HW_VF || !debug->last_words)
1044 		return;
1045 
1046 	for (i = 0; i < com_dfx_regs_num; i++) {
1047 		val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset);
1048 		if (debug->last_words[i] != val)
1049 			pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n",
1050 				 hzip_com_dfx_regs[i].name, debug->last_words[i], val);
1051 	}
1052 
1053 	zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;
1054 	zip_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CORE_NUM_CAP].shift) &
1055 			zip_basic_cap_info[ZIP_CORE_NUM_CAP].mask;
1056 	zip_comp_core_num = (zip_core_info >> zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].shift) &
1057 			zip_basic_cap_info[ZIP_CLUSTER_COMP_NUM_CAP].mask;
1058 
1059 	for (i = 0; i < zip_core_num; i++) {
1060 		if (i < zip_comp_core_num)
1061 			scnprintf(buf, sizeof(buf), "Comp_core-%d", i);
1062 		else
1063 			scnprintf(buf, sizeof(buf), "Decomp_core-%d",
1064 				  i - zip_comp_core_num);
1065 		base = get_zip_core_addr(qm, i);
1066 
1067 		pci_info(qm->pdev, "==>%s:\n", buf);
1068 		/* dump last word for dfx regs during control resetting */
1069 		for (j = 0; j < core_dfx_regs_num; j++) {
1070 			idx = com_dfx_regs_num + i * core_dfx_regs_num + j;
1071 			val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset);
1072 			if (debug->last_words[idx] != val)
1073 				pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n",
1074 					 hzip_dump_dfx_regs[j].name,
1075 					 debug->last_words[idx], val);
1076 		}
1077 	}
1078 }
1079 
hisi_zip_log_hw_error(struct hisi_qm * qm,u32 err_sts)1080 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
1081 {
1082 	const struct hisi_zip_hw_error *err = zip_hw_error;
1083 	struct device *dev = &qm->pdev->dev;
1084 	u32 err_val;
1085 
1086 	while (err->msg) {
1087 		if (err->int_msk & err_sts) {
1088 			dev_err(dev, "%s [error status=0x%x] found\n",
1089 				err->msg, err->int_msk);
1090 
1091 			if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) {
1092 				err_val = readl(qm->io_base +
1093 						HZIP_CORE_SRAM_ECC_ERR_INFO);
1094 				dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n",
1095 					((err_val >>
1096 					HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF));
1097 			}
1098 		}
1099 		err++;
1100 	}
1101 }
1102 
hisi_zip_get_hw_err_status(struct hisi_qm * qm)1103 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
1104 {
1105 	return readl(qm->io_base + HZIP_CORE_INT_STATUS);
1106 }
1107 
hisi_zip_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)1108 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1109 {
1110 	writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
1111 }
1112 
hisi_zip_disable_error_report(struct hisi_qm * qm,u32 err_type)1113 static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type)
1114 {
1115 	u32 nfe_mask;
1116 
1117 	nfe_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);
1118 	writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1119 }
1120 
hisi_zip_open_axi_master_ooo(struct hisi_qm * qm)1121 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
1122 {
1123 	u32 val;
1124 
1125 	val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1126 
1127 	writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE,
1128 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1129 
1130 	writel(val | HZIP_AXI_SHUTDOWN_ENABLE,
1131 	       qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
1132 }
1133 
hisi_zip_close_axi_master_ooo(struct hisi_qm * qm)1134 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
1135 {
1136 	u32 nfe_enb;
1137 
1138 	/* Disable ECC Mbit error report. */
1139 	nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1140 	writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC,
1141 	       qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
1142 
1143 	/* Inject zip ECC Mbit error to block master ooo. */
1144 	writel(HZIP_CORE_INT_STATUS_M_ECC,
1145 	       qm->io_base + HZIP_CORE_INT_SET);
1146 }
1147 
hisi_zip_get_err_result(struct hisi_qm * qm)1148 static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm)
1149 {
1150 	u32 err_status;
1151 
1152 	err_status = hisi_zip_get_hw_err_status(qm);
1153 	if (err_status) {
1154 		if (err_status & qm->err_info.ecc_2bits_mask)
1155 			qm->err_status.is_dev_ecc_mbit = true;
1156 		hisi_zip_log_hw_error(qm, err_status);
1157 
1158 		if (err_status & qm->err_info.dev_reset_mask) {
1159 			/* Disable the same error reporting until device is recovered. */
1160 			hisi_zip_disable_error_report(qm, err_status);
1161 			return ACC_ERR_NEED_RESET;
1162 		}
1163 		hisi_zip_clear_hw_err_status(qm, err_status);
1164 	}
1165 
1166 	return ACC_ERR_RECOVERED;
1167 }
1168 
hisi_zip_err_info_init(struct hisi_qm * qm)1169 static void hisi_zip_err_info_init(struct hisi_qm *qm)
1170 {
1171 	struct hisi_qm_err_info *err_info = &qm->err_info;
1172 
1173 	err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK;
1174 	err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver);
1175 	err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1176 					    ZIP_QM_NFE_MASK_CAP, qm->cap_ver);
1177 	err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC;
1178 	err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1179 							 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1180 	err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1181 							  ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1182 	err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1183 						      ZIP_QM_RESET_MASK_CAP, qm->cap_ver);
1184 	err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1185 						       ZIP_RESET_MASK_CAP, qm->cap_ver);
1186 	err_info->msi_wr_port = HZIP_WR_PORT;
1187 	err_info->acpi_rst = "ZRST";
1188 }
1189 
1190 static const struct hisi_qm_err_ini hisi_zip_err_ini = {
1191 	.hw_init		= hisi_zip_set_user_domain_and_cache,
1192 	.hw_err_enable		= hisi_zip_hw_error_enable,
1193 	.hw_err_disable		= hisi_zip_hw_error_disable,
1194 	.get_dev_hw_err_status	= hisi_zip_get_hw_err_status,
1195 	.clear_dev_hw_err_status = hisi_zip_clear_hw_err_status,
1196 	.open_axi_master_ooo	= hisi_zip_open_axi_master_ooo,
1197 	.close_axi_master_ooo	= hisi_zip_close_axi_master_ooo,
1198 	.open_sva_prefetch	= hisi_zip_open_sva_prefetch,
1199 	.close_sva_prefetch	= hisi_zip_close_sva_prefetch,
1200 	.show_last_dfx_regs	= hisi_zip_show_last_dfx_regs,
1201 	.err_info_init		= hisi_zip_err_info_init,
1202 	.get_err_result		= hisi_zip_get_err_result,
1203 };
1204 
hisi_zip_pf_probe_init(struct hisi_zip * hisi_zip)1205 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip)
1206 {
1207 	struct hisi_qm *qm = &hisi_zip->qm;
1208 	struct hisi_zip_ctrl *ctrl;
1209 	int ret;
1210 
1211 	ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
1212 	if (!ctrl)
1213 		return -ENOMEM;
1214 
1215 	hisi_zip->ctrl = ctrl;
1216 	ctrl->hisi_zip = hisi_zip;
1217 
1218 	ret = hisi_zip_set_user_domain_and_cache(qm);
1219 	if (ret)
1220 		return ret;
1221 
1222 	ret = hisi_zip_set_high_perf(qm);
1223 	if (ret)
1224 		return ret;
1225 
1226 	hisi_zip_open_sva_prefetch(qm);
1227 	hisi_qm_dev_err_init(qm);
1228 	hisi_zip_debug_regs_clear(qm);
1229 
1230 	ret = hisi_zip_show_last_regs_init(qm);
1231 	if (ret)
1232 		pci_err(qm->pdev, "Failed to init last word regs!\n");
1233 
1234 	return ret;
1235 }
1236 
zip_pre_store_cap_reg(struct hisi_qm * qm)1237 static int zip_pre_store_cap_reg(struct hisi_qm *qm)
1238 {
1239 	struct hisi_qm_cap_record *zip_cap;
1240 	struct pci_dev *pdev = qm->pdev;
1241 	size_t i, size;
1242 
1243 	size = ARRAY_SIZE(zip_cap_query_info);
1244 	zip_cap = devm_kzalloc(&pdev->dev, sizeof(*zip_cap) * size, GFP_KERNEL);
1245 	if (!zip_cap)
1246 		return -ENOMEM;
1247 
1248 	for (i = 0; i < size; i++) {
1249 		zip_cap[i].type = zip_cap_query_info[i].type;
1250 		zip_cap[i].name = zip_cap_query_info[i].name;
1251 		zip_cap[i].cap_val = hisi_qm_get_cap_value(qm, zip_cap_query_info,
1252 				     i, qm->cap_ver);
1253 	}
1254 
1255 	qm->cap_tables.dev_cap_table = zip_cap;
1256 	qm->cap_tables.dev_cap_size = size;
1257 
1258 	return 0;
1259 }
1260 
hisi_zip_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)1261 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1262 {
1263 	u64 alg_msk;
1264 	int ret;
1265 
1266 	qm->pdev = pdev;
1267 	qm->ver = pdev->revision;
1268 	qm->mode = uacce_mode;
1269 	qm->sqe_size = HZIP_SQE_SIZE;
1270 	qm->dev_name = hisi_zip_name;
1271 
1272 	qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ?
1273 			QM_HW_PF : QM_HW_VF;
1274 	if (qm->fun_type == QM_HW_PF) {
1275 		qm->qp_base = HZIP_PF_DEF_Q_BASE;
1276 		qm->qp_num = pf_q_num;
1277 		qm->debug.curr_qm_qp_num = pf_q_num;
1278 		qm->qm_list = &zip_devices;
1279 		qm->err_ini = &hisi_zip_err_ini;
1280 		if (pf_q_num_flag)
1281 			set_bit(QM_MODULE_PARAM, &qm->misc_ctl);
1282 	} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
1283 		/*
1284 		 * have no way to get qm configure in VM in v1 hardware,
1285 		 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force
1286 		 * to trigger only one VF in v1 hardware.
1287 		 *
1288 		 * v2 hardware has no such problem.
1289 		 */
1290 		qm->qp_base = HZIP_PF_DEF_Q_NUM;
1291 		qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
1292 	}
1293 
1294 	ret = hisi_qm_init(qm);
1295 	if (ret) {
1296 		pci_err(qm->pdev, "Failed to init zip qm configures!\n");
1297 		return ret;
1298 	}
1299 
1300 	/* Fetch and save the value of capability registers */
1301 	ret = zip_pre_store_cap_reg(qm);
1302 	if (ret) {
1303 		pci_err(qm->pdev, "Failed to pre-store capability registers!\n");
1304 		hisi_qm_uninit(qm);
1305 		return ret;
1306 	}
1307 
1308 	alg_msk = qm->cap_tables.dev_cap_table[ZIP_ALG_BITMAP].cap_val;
1309 	ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));
1310 	if (ret) {
1311 		pci_err(qm->pdev, "Failed to set zip algs!\n");
1312 		hisi_qm_uninit(qm);
1313 	}
1314 
1315 	return ret;
1316 }
1317 
hisi_zip_qm_uninit(struct hisi_qm * qm)1318 static void hisi_zip_qm_uninit(struct hisi_qm *qm)
1319 {
1320 	hisi_qm_uninit(qm);
1321 }
1322 
hisi_zip_probe_init(struct hisi_zip * hisi_zip)1323 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip)
1324 {
1325 	u32 type_rate = HZIP_SHAPER_RATE_COMPRESS;
1326 	struct hisi_qm *qm = &hisi_zip->qm;
1327 	int ret;
1328 
1329 	if (qm->fun_type == QM_HW_PF) {
1330 		ret = hisi_zip_pf_probe_init(hisi_zip);
1331 		if (ret)
1332 			return ret;
1333 		/* enable shaper type 0 */
1334 		if (qm->ver >= QM_HW_V3) {
1335 			type_rate |= QM_SHAPER_ENABLE;
1336 
1337 			/* ZIP need to enable shaper type 1 */
1338 			type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET;
1339 			qm->type_rate = type_rate;
1340 		}
1341 	}
1342 
1343 	return 0;
1344 }
1345 
hisi_zip_probe_uninit(struct hisi_qm * qm)1346 static void hisi_zip_probe_uninit(struct hisi_qm *qm)
1347 {
1348 	if (qm->fun_type == QM_HW_VF)
1349 		return;
1350 
1351 	hisi_zip_show_last_regs_uninit(qm);
1352 	hisi_zip_close_sva_prefetch(qm);
1353 	hisi_qm_dev_err_uninit(qm);
1354 }
1355 
hisi_zip_probe(struct pci_dev * pdev,const struct pci_device_id * id)1356 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1357 {
1358 	struct hisi_zip *hisi_zip;
1359 	struct hisi_qm *qm;
1360 	int ret;
1361 
1362 	hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL);
1363 	if (!hisi_zip)
1364 		return -ENOMEM;
1365 
1366 	qm = &hisi_zip->qm;
1367 
1368 	ret = hisi_zip_qm_init(qm, pdev);
1369 	if (ret) {
1370 		pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret);
1371 		return ret;
1372 	}
1373 
1374 	ret = hisi_zip_probe_init(hisi_zip);
1375 	if (ret) {
1376 		pci_err(pdev, "Failed to probe (%d)!\n", ret);
1377 		goto err_qm_uninit;
1378 	}
1379 
1380 	ret = hisi_qm_start(qm);
1381 	if (ret)
1382 		goto err_probe_uninit;
1383 
1384 	ret = hisi_zip_debugfs_init(qm);
1385 	if (ret)
1386 		pci_err(pdev, "failed to init debugfs (%d)!\n", ret);
1387 
1388 	hisi_qm_add_list(qm, &zip_devices);
1389 	ret = hisi_qm_alg_register(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);
1390 	if (ret < 0) {
1391 		pci_err(pdev, "failed to register driver to crypto!\n");
1392 		goto err_qm_del_list;
1393 	}
1394 
1395 	if (qm->uacce) {
1396 		ret = uacce_register(qm->uacce);
1397 		if (ret) {
1398 			pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1399 			goto err_qm_alg_unregister;
1400 		}
1401 	}
1402 
1403 	if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
1404 		ret = hisi_qm_sriov_enable(pdev, vfs_num);
1405 		if (ret < 0)
1406 			goto err_qm_alg_unregister;
1407 	}
1408 
1409 	hisi_qm_pm_init(qm);
1410 
1411 	return 0;
1412 
1413 err_qm_alg_unregister:
1414 	hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);
1415 
1416 err_qm_del_list:
1417 	hisi_qm_del_list(qm, &zip_devices);
1418 	hisi_zip_debugfs_exit(qm);
1419 	hisi_qm_stop(qm, QM_NORMAL);
1420 
1421 err_probe_uninit:
1422 	hisi_zip_probe_uninit(qm);
1423 
1424 err_qm_uninit:
1425 	hisi_zip_qm_uninit(qm);
1426 
1427 	return ret;
1428 }
1429 
hisi_zip_remove(struct pci_dev * pdev)1430 static void hisi_zip_remove(struct pci_dev *pdev)
1431 {
1432 	struct hisi_qm *qm = pci_get_drvdata(pdev);
1433 
1434 	hisi_qm_pm_uninit(qm);
1435 	hisi_qm_wait_task_finish(qm, &zip_devices);
1436 	hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);
1437 	hisi_qm_del_list(qm, &zip_devices);
1438 
1439 	if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1440 		hisi_qm_sriov_disable(pdev, true);
1441 
1442 	hisi_zip_debugfs_exit(qm);
1443 	hisi_qm_stop(qm, QM_NORMAL);
1444 	hisi_zip_probe_uninit(qm);
1445 	hisi_zip_qm_uninit(qm);
1446 }
1447 
1448 static const struct dev_pm_ops hisi_zip_pm_ops = {
1449 	SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1450 };
1451 
1452 static const struct pci_error_handlers hisi_zip_err_handler = {
1453 	.error_detected	= hisi_qm_dev_err_detected,
1454 	.slot_reset	= hisi_qm_dev_slot_reset,
1455 	.reset_prepare	= hisi_qm_reset_prepare,
1456 	.reset_done	= hisi_qm_reset_done,
1457 };
1458 
1459 static struct pci_driver hisi_zip_pci_driver = {
1460 	.name			= "hisi_zip",
1461 	.id_table		= hisi_zip_dev_ids,
1462 	.probe			= hisi_zip_probe,
1463 	.remove			= hisi_zip_remove,
1464 	.sriov_configure	= IS_ENABLED(CONFIG_PCI_IOV) ?
1465 					hisi_qm_sriov_configure : NULL,
1466 	.err_handler		= &hisi_zip_err_handler,
1467 	.shutdown		= hisi_qm_dev_shutdown,
1468 	.driver.pm		= &hisi_zip_pm_ops,
1469 };
1470 
hisi_zip_get_pf_driver(void)1471 struct pci_driver *hisi_zip_get_pf_driver(void)
1472 {
1473 	return &hisi_zip_pci_driver;
1474 }
1475 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver);
1476 
hisi_zip_register_debugfs(void)1477 static void hisi_zip_register_debugfs(void)
1478 {
1479 	if (!debugfs_initialized())
1480 		return;
1481 
1482 	hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL);
1483 }
1484 
hisi_zip_unregister_debugfs(void)1485 static void hisi_zip_unregister_debugfs(void)
1486 {
1487 	debugfs_remove_recursive(hzip_debugfs_root);
1488 }
1489 
hisi_zip_init(void)1490 static int __init hisi_zip_init(void)
1491 {
1492 	int ret;
1493 
1494 	hisi_qm_init_list(&zip_devices);
1495 	hisi_zip_register_debugfs();
1496 
1497 	ret = pci_register_driver(&hisi_zip_pci_driver);
1498 	if (ret < 0) {
1499 		hisi_zip_unregister_debugfs();
1500 		pr_err("Failed to register pci driver.\n");
1501 	}
1502 
1503 	return ret;
1504 }
1505 
hisi_zip_exit(void)1506 static void __exit hisi_zip_exit(void)
1507 {
1508 	pci_unregister_driver(&hisi_zip_pci_driver);
1509 	hisi_zip_unregister_debugfs();
1510 }
1511 
1512 module_init(hisi_zip_init);
1513 module_exit(hisi_zip_exit);
1514 
1515 MODULE_LICENSE("GPL v2");
1516 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
1517 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator");
1518