1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020 Intel Corporation. */ 3 4 #ifndef __CXL_H__ 5 #define __CXL_H__ 6 7 #include <linux/libnvdimm.h> 8 #include <linux/bitfield.h> 9 #include <linux/notifier.h> 10 #include <linux/bitops.h> 11 #include <linux/log2.h> 12 #include <linux/node.h> 13 #include <linux/io.h> 14 #include <linux/range.h> 15 #include <cxl/cxl.h> 16 17 extern const struct nvdimm_security_ops *cxl_security_ops; 18 19 /** 20 * DOC: cxl objects 21 * 22 * The CXL core objects like ports, decoders, and regions are shared 23 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers 24 * (port-driver, region-driver, nvdimm object-drivers... etc). 25 */ 26 27 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */ 28 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K 29 30 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/ 31 #define CXL_CM_OFFSET 0x1000 32 #define CXL_CM_CAP_HDR_OFFSET 0x0 33 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0) 34 #define CM_CAP_HDR_CAP_ID 1 35 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16) 36 #define CM_CAP_HDR_CAP_VERSION 1 37 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20) 38 #define CM_CAP_HDR_CACHE_MEM_VERSION 1 39 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24) 40 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20) 41 42 #define CXL_CM_CAP_CAP_ID_RAS 0x2 43 #define CXL_CM_CAP_CAP_ID_HDM 0x5 44 #define CXL_CM_CAP_CAP_HDM_VERSION 1 45 46 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ 47 #define CXL_HDM_DECODER_CAP_OFFSET 0x0 48 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0) 49 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4) 50 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8) 51 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9) 52 #define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11) 53 #define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12) 54 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4 55 #define CXL_HDM_DECODER_ENABLE BIT(1) 56 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10) 57 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14) 58 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18) 59 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c) 60 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) 61 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0) 62 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4) 63 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) 64 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) 65 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) 66 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) 67 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12) 68 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24) 69 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28) 70 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i) 71 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i) 72 73 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */ 74 #define CXL_DECODER_MIN_GRANULARITY 256 75 #define CXL_DECODER_MAX_ENCODED_IG 6 76 77 static inline int cxl_hdm_decoder_count(u32 cap_hdr) 78 { 79 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); 80 81 switch (val) { 82 case 0: 83 return 1; 84 case 1 ... 8: 85 return val * 2; 86 case 9 ... 12: 87 return (val - 4) * 4; 88 default: 89 return -ENXIO; 90 } 91 } 92 93 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ 94 static inline int eig_to_granularity(u16 eig, unsigned int *granularity) 95 { 96 if (eig > CXL_DECODER_MAX_ENCODED_IG) 97 return -EINVAL; 98 *granularity = CXL_DECODER_MIN_GRANULARITY << eig; 99 return 0; 100 } 101 102 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ 103 static inline int eiw_to_ways(u8 eiw, unsigned int *ways) 104 { 105 switch (eiw) { 106 case 0 ... 4: 107 *ways = 1 << eiw; 108 break; 109 case 8 ... 10: 110 *ways = 3 << (eiw - 8); 111 break; 112 default: 113 return -EINVAL; 114 } 115 116 return 0; 117 } 118 119 static inline int granularity_to_eig(int granularity, u16 *eig) 120 { 121 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY || 122 !is_power_of_2(granularity)) 123 return -EINVAL; 124 *eig = ilog2(granularity) - 8; 125 return 0; 126 } 127 128 static inline int ways_to_eiw(unsigned int ways, u8 *eiw) 129 { 130 if (ways > 16) 131 return -EINVAL; 132 if (is_power_of_2(ways)) { 133 *eiw = ilog2(ways); 134 return 0; 135 } 136 if (ways % 3) 137 return -EINVAL; 138 ways /= 3; 139 if (!is_power_of_2(ways)) 140 return -EINVAL; 141 *eiw = ilog2(ways) + 8; 142 return 0; 143 } 144 145 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */ 146 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0 147 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 148 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4 149 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 150 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8) 151 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8 152 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0)) 153 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC 154 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0) 155 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10 156 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0) 157 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14 158 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0) 159 #define CXL_RAS_HEADER_LOG_OFFSET 0x18 160 #define CXL_RAS_CAPABILITY_LENGTH 0x58 161 #define CXL_HEADERLOG_SIZE SZ_512 162 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) 163 164 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ 165 #define CXLDEV_CAP_ARRAY_OFFSET 0x0 166 #define CXLDEV_CAP_ARRAY_CAP_ID 0 167 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0) 168 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32) 169 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */ 170 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0) 171 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */ 172 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1 173 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2 174 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3 175 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000 176 177 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 178 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00 179 #define CXLDEV_EVENT_STATUS_INFO BIT(0) 180 #define CXLDEV_EVENT_STATUS_WARN BIT(1) 181 #define CXLDEV_EVENT_STATUS_FAIL BIT(2) 182 #define CXLDEV_EVENT_STATUS_FATAL BIT(3) 183 184 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \ 185 CXLDEV_EVENT_STATUS_WARN | \ 186 CXLDEV_EVENT_STATUS_FAIL | \ 187 CXLDEV_EVENT_STATUS_FATAL) 188 189 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */ 190 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0) 191 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4) 192 193 /* CXL 2.0 8.2.8.4 Mailbox Registers */ 194 #define CXLDEV_MBOX_CAPS_OFFSET 0x00 195 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0) 196 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6) 197 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7) 198 #define CXLDEV_MBOX_CTRL_OFFSET 0x04 199 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0) 200 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2) 201 #define CXLDEV_MBOX_CMD_OFFSET 0x08 202 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 203 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16) 204 #define CXLDEV_MBOX_STATUS_OFFSET 0x10 205 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0) 206 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32) 207 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18 208 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0) 209 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16) 210 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32) 211 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48) 212 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20 213 214 void cxl_probe_component_regs(struct device *dev, void __iomem *base, 215 struct cxl_component_reg_map *map); 216 void cxl_probe_device_regs(struct device *dev, void __iomem *base, 217 struct cxl_device_reg_map *map); 218 int cxl_map_component_regs(const struct cxl_register_map *map, 219 struct cxl_component_regs *regs, 220 unsigned long map_mask); 221 int cxl_map_device_regs(const struct cxl_register_map *map, 222 struct cxl_device_regs *regs); 223 int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs); 224 225 #define CXL_INSTANCES_COUNT -1 226 enum cxl_regloc_type; 227 int cxl_count_regblock(struct pci_dev *pdev, enum cxl_regloc_type type); 228 int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, 229 struct cxl_register_map *map, unsigned int index); 230 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, 231 struct cxl_register_map *map); 232 int cxl_setup_regs(struct cxl_register_map *map); 233 struct cxl_dport; 234 int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); 235 236 #define CXL_RESOURCE_NONE ((resource_size_t) -1) 237 #define CXL_TARGET_STRLEN 20 238 239 /* 240 * cxl_decoder flags that define the type of memory / devices this 241 * decoder supports as well as configuration lock status See "CXL 2.0 242 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. 243 * Additionally indicate whether decoder settings were autodetected, 244 * user customized. 245 */ 246 #define CXL_DECODER_F_RAM BIT(0) 247 #define CXL_DECODER_F_PMEM BIT(1) 248 #define CXL_DECODER_F_TYPE2 BIT(2) 249 #define CXL_DECODER_F_TYPE3 BIT(3) 250 #define CXL_DECODER_F_LOCK BIT(4) 251 #define CXL_DECODER_F_ENABLE BIT(5) 252 #define CXL_DECODER_F_NORMALIZED_ADDRESSING BIT(6) 253 #define CXL_DECODER_F_RESET_MASK (CXL_DECODER_F_ENABLE | CXL_DECODER_F_LOCK) 254 255 enum cxl_decoder_type { 256 CXL_DECODER_DEVMEM = 2, 257 CXL_DECODER_HOSTONLYMEM = 3, 258 }; 259 260 /* 261 * Current specification goes up to 8, double that seems a reasonable 262 * software max for the foreseeable future 263 */ 264 #define CXL_DECODER_MAX_INTERLEAVE 16 265 266 #define CXL_QOS_CLASS_INVALID -1 267 268 /** 269 * struct cxl_decoder - Common CXL HDM Decoder Attributes 270 * @dev: this decoder's device 271 * @id: kernel device name id 272 * @hpa_range: Host physical address range mapped by this decoder 273 * @interleave_ways: number of cxl_dports in this decode 274 * @interleave_granularity: data stride per dport 275 * @target_type: accelerator vs expander (type2 vs type3) selector 276 * @region: currently assigned region for this decoder 277 * @flags: memory type capabilities and locking 278 * @target_map: cached copy of hardware port-id list, available at init 279 * before all @dport objects have been instantiated. While 280 * dport id is 8bit, CFMWS interleave targets are 32bits. 281 * @commit: device/decoder-type specific callback to commit settings to hw 282 * @reset: device/decoder-type specific callback to reset hw settings 283 */ 284 struct cxl_decoder { 285 struct device dev; 286 int id; 287 struct range hpa_range; 288 int interleave_ways; 289 int interleave_granularity; 290 enum cxl_decoder_type target_type; 291 struct cxl_region *region; 292 unsigned long flags; 293 u32 target_map[CXL_DECODER_MAX_INTERLEAVE]; 294 int (*commit)(struct cxl_decoder *cxld); 295 void (*reset)(struct cxl_decoder *cxld); 296 }; 297 298 /* 299 * Track whether this decoder is free for userspace provisioning, reserved for 300 * region autodiscovery, whether it is started connecting (awaiting other 301 * peers), or has completed auto assembly. 302 */ 303 enum cxl_decoder_state { 304 CXL_DECODER_STATE_MANUAL, 305 CXL_DECODER_STATE_AUTO, 306 CXL_DECODER_STATE_AUTO_STAGED, 307 }; 308 309 /** 310 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder 311 * @cxld: base cxl_decoder_object 312 * @dpa_res: actively claimed DPA span of this decoder 313 * @skip: offset into @dpa_res where @cxld.hpa_range maps 314 * @state: autodiscovery state 315 * @part: partition index this decoder maps 316 * @pos: interleave position in @cxld.region 317 */ 318 struct cxl_endpoint_decoder { 319 struct cxl_decoder cxld; 320 struct resource *dpa_res; 321 resource_size_t skip; 322 enum cxl_decoder_state state; 323 int part; 324 int pos; 325 }; 326 327 /** 328 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder 329 * @cxld: base cxl_decoder object 330 * @nr_targets: number of elements in @target 331 * @target: active ordered target list in current decoder configuration 332 * 333 * The 'switch' decoder type represents the decoder instances of cxl_port's that 334 * route from the root of a CXL memory decode topology to the endpoints. They 335 * come in two flavors, root-level decoders, statically defined by platform 336 * firmware, and mid-level decoders, where interleave-granularity, 337 * interleave-width, and the target list are mutable. 338 */ 339 struct cxl_switch_decoder { 340 struct cxl_decoder cxld; 341 int nr_targets; 342 struct cxl_dport *target[]; 343 }; 344 345 struct cxl_root_decoder; 346 /** 347 * struct cxl_rd_ops - CXL root decoder callback operations 348 * @hpa_to_spa: Convert host physical address to system physical address 349 * @spa_to_hpa: Convert system physical address to host physical address 350 */ 351 struct cxl_rd_ops { 352 u64 (*hpa_to_spa)(struct cxl_root_decoder *cxlrd, u64 hpa); 353 u64 (*spa_to_hpa)(struct cxl_root_decoder *cxlrd, u64 spa); 354 }; 355 356 /** 357 * struct cxl_root_decoder - Static platform CXL address decoder 358 * @res: host / parent resource for region allocations 359 * @cache_size: extended linear cache size if exists, otherwise zero. 360 * @region_id: region id for next region provisioning event 361 * @platform_data: platform specific configuration data 362 * @range_lock: sync region autodiscovery by address range 363 * @qos_class: QoS performance class cookie 364 * @ops: CXL root decoder operations 365 * @cxlsd: base cxl switch decoder 366 */ 367 struct cxl_root_decoder { 368 struct resource *res; 369 resource_size_t cache_size; 370 atomic_t region_id; 371 void *platform_data; 372 struct mutex range_lock; 373 int qos_class; 374 struct cxl_rd_ops ops; 375 struct cxl_switch_decoder cxlsd; 376 }; 377 378 /* 379 * enum cxl_config_state - State machine for region configuration 380 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely 381 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more 382 * changes to interleave_ways or interleave_granularity 383 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now 384 * active 385 * @CXL_CONFIG_RESET_PENDING: see commit_store() 386 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware 387 */ 388 enum cxl_config_state { 389 CXL_CONFIG_IDLE, 390 CXL_CONFIG_INTERLEAVE_ACTIVE, 391 CXL_CONFIG_ACTIVE, 392 CXL_CONFIG_RESET_PENDING, 393 CXL_CONFIG_COMMIT, 394 }; 395 396 /** 397 * struct cxl_region_params - region settings 398 * @state: allow the driver to lockdown further parameter changes 399 * @uuid: unique id for persistent regions 400 * @interleave_ways: number of endpoints in the region 401 * @interleave_granularity: capacity each endpoint contributes to a stripe 402 * @res: allocated iomem capacity for this region 403 * @targets: active ordered targets in current decoder configuration 404 * @nr_targets: number of targets 405 * @cache_size: extended linear cache size if exists, otherwise zero. 406 * 407 * State transitions are protected by cxl_rwsem.region 408 */ 409 struct cxl_region_params { 410 enum cxl_config_state state; 411 uuid_t uuid; 412 int interleave_ways; 413 int interleave_granularity; 414 struct resource *res; 415 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; 416 int nr_targets; 417 resource_size_t cache_size; 418 }; 419 420 /* 421 * Indicate whether this region has been assembled by autodetection or 422 * userspace assembly. Prevent endpoint decoders outside of automatic 423 * detection from being added to the region. 424 */ 425 #define CXL_REGION_F_AUTO 0 426 427 /* 428 * Require that a committed region successfully complete a teardown once 429 * any of its associated decoders have been torn down. This maintains 430 * the commit state for the region since there are committed decoders, 431 * but blocks cxl_region_probe(). 432 */ 433 #define CXL_REGION_F_NEEDS_RESET 1 434 435 /* 436 * Indicate whether this region is locked due to 1 or more decoders that have 437 * been locked. The approach of all or nothing is taken with regard to the 438 * locked attribute. CXL_REGION_F_NEEDS_RESET should not be set if this flag is 439 * set. 440 */ 441 #define CXL_REGION_F_LOCK 2 442 443 /* 444 * Indicate Normalized Addressing. Use it to disable SPA conversion if 445 * HPA != SPA and an address translation callback handler does not 446 * exist. Flag is needed by AMD Zen5 platforms. 447 */ 448 #define CXL_REGION_F_NORMALIZED_ADDRESSING 3 449 450 /** 451 * struct cxl_region - CXL region 452 * @dev: This region's device 453 * @id: This region's id. Id is globally unique across all regions 454 * @cxlrd: Region's root decoder 455 * @hpa_range: Address range occupied by the region 456 * @mode: Operational mode of the mapped capacity 457 * @type: Endpoint decoder target type 458 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown 459 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge 460 * @flags: Region state flags 461 * @params: active + config params for the region 462 * @coord: QoS access coordinates for the region 463 * @node_notifier: notifier for setting the access coordinates to node 464 * @adist_notifier: notifier for calculating the abstract distance of node 465 */ 466 struct cxl_region { 467 struct device dev; 468 int id; 469 struct cxl_root_decoder *cxlrd; 470 struct range hpa_range; 471 enum cxl_partition_mode mode; 472 enum cxl_decoder_type type; 473 struct cxl_nvdimm_bridge *cxl_nvb; 474 struct cxl_pmem_region *cxlr_pmem; 475 unsigned long flags; 476 struct cxl_region_params params; 477 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 478 struct notifier_block node_notifier; 479 struct notifier_block adist_notifier; 480 }; 481 482 struct cxl_nvdimm_bridge { 483 int id; 484 struct device dev; 485 struct cxl_port *port; 486 struct nvdimm_bus *nvdimm_bus; 487 struct nvdimm_bus_descriptor nd_desc; 488 }; 489 490 #define CXL_DEV_ID_LEN 19 491 492 enum { 493 CXL_NVD_F_INVALIDATED = 0, 494 }; 495 496 struct cxl_nvdimm { 497 struct device dev; 498 struct cxl_memdev *cxlmd; 499 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */ 500 u64 dirty_shutdowns; 501 unsigned long flags; 502 }; 503 504 struct cxl_pmem_region_mapping { 505 struct cxl_memdev *cxlmd; 506 struct cxl_nvdimm *cxl_nvd; 507 u64 start; 508 u64 size; 509 int position; 510 }; 511 512 struct cxl_pmem_region { 513 struct device dev; 514 struct cxl_region *cxlr; 515 struct nd_region *nd_region; 516 struct range hpa_range; 517 int nr_mappings; 518 struct cxl_pmem_region_mapping mapping[]; 519 }; 520 521 struct cxl_dax_region { 522 struct device dev; 523 struct cxl_region *cxlr; 524 struct range hpa_range; 525 }; 526 527 /** 528 * struct cxl_port - logical collection of upstream port devices and 529 * downstream port devices to construct a CXL memory 530 * decode hierarchy. 531 * @dev: this port's device 532 * @uport_dev: PCI or platform device implementing the upstream port capability 533 * @host_bridge: Shortcut to the platform attach point for this port 534 * @id: id for port device-name 535 * @dports: cxl_dport instances referenced by decoders 536 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port 537 * @regions: cxl_region_ref instances, regions mapped by this port 538 * @parent_dport: dport that points to this port in the parent 539 * @decoder_ida: allocator for decoder ids 540 * @reg_map: component and ras register mapping parameters 541 * @regs: mapped component registers 542 * @nr_dports: number of entries in @dports 543 * @hdm_end: track last allocated HDM decoder instance for allocation ordering 544 * @commit_end: cursor to track highest committed decoder for commit ordering 545 * @dead: last ep has been removed, force port re-creation 546 * @depth: How deep this port is relative to the root. depth 0 is the root. 547 * @cdat: Cached CDAT data 548 * @cdat_available: Should a CDAT attribute be available in sysfs 549 * @pci_latency: Upstream latency in picoseconds 550 * @component_reg_phys: Physical address of component register 551 */ 552 struct cxl_port { 553 struct device dev; 554 struct device *uport_dev; 555 struct device *host_bridge; 556 int id; 557 struct xarray dports; 558 struct xarray endpoints; 559 struct xarray regions; 560 struct cxl_dport *parent_dport; 561 struct ida decoder_ida; 562 struct cxl_register_map reg_map; 563 struct cxl_component_regs regs; 564 int nr_dports; 565 int hdm_end; 566 int commit_end; 567 bool dead; 568 unsigned int depth; 569 struct cxl_cdat { 570 void *table; 571 size_t length; 572 } cdat; 573 bool cdat_available; 574 long pci_latency; 575 resource_size_t component_reg_phys; 576 }; 577 578 struct cxl_root; 579 580 struct cxl_root_ops { 581 int (*qos_class)(struct cxl_root *cxl_root, 582 struct access_coordinate *coord, int entries, 583 int *qos_class); 584 int (*translation_setup_root)(struct cxl_root *cxl_root, void *data); 585 }; 586 587 /** 588 * struct cxl_root - logical collection of root cxl_port items 589 * 590 * @port: cxl_port member 591 * @ops: cxl root operations 592 */ 593 struct cxl_root { 594 struct cxl_port port; 595 struct cxl_root_ops ops; 596 }; 597 598 static inline struct cxl_root * 599 to_cxl_root(const struct cxl_port *port) 600 { 601 return container_of(port, struct cxl_root, port); 602 } 603 604 static inline struct cxl_dport * 605 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) 606 { 607 return xa_load(&port->dports, (unsigned long)dport_dev); 608 } 609 610 struct cxl_rcrb_info { 611 resource_size_t base; 612 u16 aer_cap; 613 }; 614 615 /** 616 * struct cxl_dport - CXL downstream port 617 * @dport_dev: PCI bridge or firmware device representing the downstream link 618 * @reg_map: component and ras register mapping parameters 619 * @port_id: unique hardware identifier for dport in decoder target list 620 * @rcrb: Data about the Root Complex Register Block layout 621 * @rch: Indicate whether this dport was enumerated in RCH or VH mode 622 * @port: reference to cxl_port that contains this downstream port 623 * @regs: Dport parsed register blocks 624 * @coord: access coordinates (bandwidth and latency performance attributes) 625 * @link_latency: calculated PCIe downstream latency 626 * @gpf_dvsec: Cached GPF port DVSEC 627 */ 628 struct cxl_dport { 629 struct device *dport_dev; 630 struct cxl_register_map reg_map; 631 int port_id; 632 struct cxl_rcrb_info rcrb; 633 bool rch; 634 struct cxl_port *port; 635 struct cxl_regs regs; 636 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 637 long link_latency; 638 int gpf_dvsec; 639 }; 640 641 /** 642 * struct cxl_ep - track an endpoint's interest in a port 643 * @ep: device that hosts a generic CXL endpoint (expander or accelerator) 644 * @dport: which dport routes to this endpoint on @port 645 * @next: cxl switch port across the link attached to @dport NULL if 646 * attached to an endpoint 647 */ 648 struct cxl_ep { 649 struct device *ep; 650 struct cxl_dport *dport; 651 struct cxl_port *next; 652 }; 653 654 /** 655 * struct cxl_region_ref - track a region's interest in a port 656 * @port: point in topology to install this reference 657 * @decoder: decoder assigned for @region in @port 658 * @region: region for this reference 659 * @endpoints: cxl_ep references for region members beneath @port 660 * @nr_targets_set: track how many targets have been programmed during setup 661 * @nr_eps: number of endpoints beneath @port 662 * @nr_targets: number of distinct targets needed to reach @nr_eps 663 */ 664 struct cxl_region_ref { 665 struct cxl_port *port; 666 struct cxl_decoder *decoder; 667 struct cxl_region *region; 668 struct xarray endpoints; 669 int nr_targets_set; 670 int nr_eps; 671 int nr_targets; 672 }; 673 674 /* 675 * The platform firmware device hosting the root is also the top of the 676 * CXL port topology. All other CXL ports have another CXL port as their 677 * parent and their ->uport_dev / host device is out-of-line of the port 678 * ancestry. 679 */ 680 static inline bool is_cxl_root(struct cxl_port *port) 681 { 682 return port->uport_dev == port->dev.parent; 683 } 684 685 /* Address translation functions exported to cxl_translate test module only */ 686 int cxl_validate_translation_params(u8 eiw, u16 eig, int pos); 687 u64 cxl_calculate_hpa_offset(u64 dpa_offset, int pos, u8 eiw, u16 eig); 688 u64 cxl_calculate_dpa_offset(u64 hpa_offset, u8 eiw, u16 eig); 689 int cxl_calculate_position(u64 hpa_offset, u8 eiw, u16 eig); 690 struct cxl_cxims_data { 691 int nr_maps; 692 u64 xormaps[] __counted_by(nr_maps); 693 }; 694 695 #if IS_ENABLED(CONFIG_CXL_ACPI) 696 u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw); 697 #else 698 static inline u64 cxl_do_xormap_calc(struct cxl_cxims_data *cximsd, u64 addr, int hbiw) 699 { 700 return ULLONG_MAX; 701 } 702 #endif 703 704 int cxl_num_decoders_committed(struct cxl_port *port); 705 bool is_cxl_port(const struct device *dev); 706 struct cxl_port *to_cxl_port(const struct device *dev); 707 struct cxl_port *parent_port_of(struct cxl_port *port); 708 void cxl_port_commit_reap(struct cxl_decoder *cxld); 709 struct pci_bus; 710 int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, 711 struct pci_bus *bus); 712 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); 713 struct cxl_port *devm_cxl_add_port(struct device *host, 714 struct device *uport_dev, 715 resource_size_t component_reg_phys, 716 struct cxl_dport *parent_dport); 717 struct cxl_root *devm_cxl_add_root(struct device *host); 718 int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, 719 struct cxl_dport *parent_dport); 720 struct cxl_root *find_cxl_root(struct cxl_port *port); 721 722 DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev)) 723 DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 724 DEFINE_FREE(put_cxl_root_decoder, struct cxl_root_decoder *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->cxlsd.cxld.dev)) 725 DEFINE_FREE(put_cxl_region, struct cxl_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 726 DEFINE_FREE(put_cxl_dax_region, struct cxl_dax_region *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev)) 727 728 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); 729 void cxl_bus_rescan(void); 730 void cxl_bus_drain(void); 731 struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, 732 struct cxl_dport **dport); 733 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, 734 struct cxl_dport **dport); 735 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); 736 737 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, 738 struct device *dport, int port_id, 739 resource_size_t component_reg_phys); 740 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, 741 struct device *dport_dev, int port_id, 742 resource_size_t rcrb); 743 744 #ifdef CONFIG_CXL_ATL 745 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root); 746 #else 747 static inline 748 void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) {} 749 #endif 750 751 struct cxl_decoder *to_cxl_decoder(struct device *dev); 752 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); 753 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); 754 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); 755 bool is_root_decoder(struct device *dev); 756 bool is_switch_decoder(struct device *dev); 757 bool is_endpoint_decoder(struct device *dev); 758 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, 759 unsigned int nr_targets); 760 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port, 761 unsigned int nr_targets); 762 int cxl_decoder_add(struct cxl_decoder *cxld); 763 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port); 764 int cxl_decoder_add_locked(struct cxl_decoder *cxld); 765 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld); 766 static inline int cxl_root_decoder_autoremove(struct device *host, 767 struct cxl_root_decoder *cxlrd) 768 { 769 return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); 770 } 771 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); 772 773 /** 774 * struct cxl_endpoint_dvsec_info - Cached DVSEC info 775 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time 776 * @ranges: Number of active HDM ranges this device uses. 777 * @port: endpoint port associated with this info instance 778 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE 779 */ 780 struct cxl_endpoint_dvsec_info { 781 bool mem_enabled; 782 int ranges; 783 struct cxl_port *port; 784 struct range dvsec_range[2]; 785 }; 786 787 int devm_cxl_switch_port_decoders_setup(struct cxl_port *port); 788 int devm_cxl_endpoint_decoders_setup(struct cxl_port *port); 789 void cxl_port_update_decoder_targets(struct cxl_port *port, 790 struct cxl_dport *dport); 791 int cxl_port_setup_regs(struct cxl_port *port, 792 resource_size_t component_reg_phys); 793 794 struct cxl_dev_state; 795 int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, 796 struct cxl_endpoint_dvsec_info *info); 797 798 bool is_cxl_region(struct device *dev); 799 800 extern const struct bus_type cxl_bus_type; 801 802 /* 803 * Note, add_dport() is expressly for the cxl_port driver. TODO: investigate a 804 * type-safe driver model where probe()/remove() take the type of object implied 805 * by @id and the add_dport() op only defined for the CXL_DEVICE_PORT driver 806 * template. 807 */ 808 struct cxl_driver { 809 const char *name; 810 int (*probe)(struct device *dev); 811 void (*remove)(struct device *dev); 812 struct cxl_dport *(*add_dport)(struct cxl_port *port, 813 struct device *dport_dev); 814 struct device_driver drv; 815 int id; 816 }; 817 818 #define to_cxl_drv(__drv) container_of_const(__drv, struct cxl_driver, drv) 819 820 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner, 821 const char *modname); 822 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME) 823 void cxl_driver_unregister(struct cxl_driver *cxl_drv); 824 825 #define module_cxl_driver(__cxl_driver) \ 826 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister) 827 828 #define CXL_DEVICE_NVDIMM_BRIDGE 1 829 #define CXL_DEVICE_NVDIMM 2 830 #define CXL_DEVICE_PORT 3 831 #define CXL_DEVICE_ROOT 4 832 #define CXL_DEVICE_MEMORY_EXPANDER 5 833 #define CXL_DEVICE_REGION 6 834 #define CXL_DEVICE_PMEM_REGION 7 835 #define CXL_DEVICE_DAX_REGION 8 836 #define CXL_DEVICE_PMU 9 837 838 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*") 839 #define CXL_MODALIAS_FMT "cxl:t%d" 840 841 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev); 842 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host, 843 struct cxl_port *port); 844 struct cxl_nvdimm_bridge *__devm_cxl_add_nvdimm_bridge(struct device *host, 845 struct cxl_port *port); 846 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); 847 bool is_cxl_nvdimm(struct device *dev); 848 int devm_cxl_add_nvdimm(struct device *host, struct cxl_port *port, 849 struct cxl_memdev *cxlmd); 850 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); 851 852 #ifdef CONFIG_CXL_REGION 853 bool is_cxl_pmem_region(struct device *dev); 854 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); 855 int cxl_add_to_region(struct cxl_endpoint_decoder *cxled); 856 struct cxl_dax_region *to_cxl_dax_region(struct device *dev); 857 u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa); 858 bool cxl_region_contains_resource(const struct resource *res); 859 #else 860 static inline bool is_cxl_pmem_region(struct device *dev) 861 { 862 return false; 863 } 864 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) 865 { 866 return NULL; 867 } 868 static inline int cxl_add_to_region(struct cxl_endpoint_decoder *cxled) 869 { 870 return 0; 871 } 872 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) 873 { 874 return NULL; 875 } 876 static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, 877 u64 spa) 878 { 879 return 0; 880 } 881 static inline bool cxl_region_contains_resource(const struct resource *res) 882 { 883 return false; 884 } 885 #endif 886 887 void cxl_endpoint_parse_cdat(struct cxl_port *port); 888 void cxl_switch_parse_cdat(struct cxl_dport *dport); 889 890 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, 891 struct access_coordinate *coord); 892 void cxl_region_perf_data_calculate(struct cxl_region *cxlr, 893 struct cxl_endpoint_decoder *cxled); 894 void cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr); 895 896 void cxl_memdev_update_perf(struct cxl_memdev *cxlmd); 897 898 void cxl_coordinates_combine(struct access_coordinate *out, 899 struct access_coordinate *c1, 900 struct access_coordinate *c2); 901 902 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); 903 struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port, 904 struct device *dport_dev); 905 906 /* 907 * Unit test builds overrides this to __weak, find the 'strong' version 908 * of these symbols in tools/testing/cxl/. 909 */ 910 #ifndef __mock 911 #define __mock static 912 #endif 913 914 u16 cxl_gpf_get_dvsec(struct device *dev); 915 916 #endif /* __CXL_H__ */ 917