1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 * Copyright (c) 2016 by Delphix. All rights reserved.
25 */
26
27 /*
28 * hci1394_ohci.c
29 * Provides access routines to the OpenHCI HW.
30 */
31
32 #include <sys/conf.h>
33 #include <sys/ddi.h>
34 #include <sys/modctl.h>
35 #include <sys/sunddi.h>
36 #include <sys/types.h>
37 #include <sys/mkdev.h>
38 #include <sys/kmem.h>
39 #include <sys/pci.h>
40
41 #include <sys/1394/adapters/hci1394.h>
42 #include <sys/1394/adapters/hci1394_extern.h>
43
44
45 /*
46 * Data swap macros used to swap config rom data that is going to be placed
47 * in OpenHCI registers. The config rom is treated like a byte stream. When
48 * the services layer calls into us to update the config rom, they pass us a
49 * byte stream of data. This works well except for the the fact that the
50 * hardware uses its internal registers for the first 5 quadlets. We have to
51 * copy the cfgrom header and bus options into their corresponding OpenHCI
52 * registers. On an x86 machine, this means we have to byte swap them first.
53 */
54 #ifdef _LITTLE_ENDIAN
55 #define OHCI_SWAP32(DATA) (ddi_swap32(DATA))
56 #else
57 #define OHCI_SWAP32(DATA) (DATA)
58 #endif
59
60
61 static int hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl);
62 static int hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl);
63 static int hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl);
64 static int hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl);
65 static int hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl);
66 static int hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl);
67 static int hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl,
68 uint_t address, uint_t *data);
69 static int hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl,
70 uint_t address, uint_t data);
71
72
73 /*
74 * hci1394_ohci_init()
75 * Initialize the OpenHCI hardware.
76 */
77 int
hci1394_ohci_init(hci1394_state_t * soft_state,hci1394_drvinfo_t * drvinfo,hci1394_ohci_handle_t * ohci_hdl)78 hci1394_ohci_init(hci1394_state_t *soft_state, hci1394_drvinfo_t *drvinfo,
79 hci1394_ohci_handle_t *ohci_hdl)
80 {
81 int status;
82 uint32_t version;
83 hci1394_ohci_t *ohci;
84 #if defined(__x86)
85 uint16_t cmdreg;
86 #endif
87
88
89 ASSERT(ohci_hdl != NULL);
90
91 /* alloc the space for ohci */
92 ohci = kmem_alloc(sizeof (hci1394_ohci_t), KM_SLEEP);
93 *ohci_hdl = ohci;
94
95 /*
96 * Start with the cycle timer rollover interrupt disabled. When it is
97 * enabled, we will get an interrupt every 64 seconds, even if we have
98 * nothing plugged into the bus. This interrupt is used to keep track
99 * of the bus time. We will enable the interrupt when the bus manager
100 * writes to the bus_time CSR register (Currently there are not known
101 * implementations that write to the bus_time register)
102 */
103 ohci->ohci_bustime_enabled = B_FALSE;
104 ohci->ohci_bustime_count = 0;
105
106 ohci->ohci_set_root_holdoff = B_FALSE;
107 ohci->ohci_set_gap_count = B_FALSE;
108 ohci->ohci_gap_count = 0;
109
110 mutex_init(&ohci->ohci_mutex, NULL, MUTEX_DRIVER,
111 drvinfo->di_iblock_cookie);
112
113 /* Map OpenHCI Registers */
114 status = ddi_regs_map_setup(drvinfo->di_dip, OHCI_REG_SET,
115 (caddr_t *)&ohci->ohci_regs, 0, 0, &drvinfo->di_reg_attr,
116 &ohci->ohci_reg_handle);
117 if (status != DDI_SUCCESS) {
118 mutex_destroy(&ohci->ohci_mutex);
119 kmem_free(ohci, sizeof (hci1394_ohci_t));
120 *ohci_hdl = NULL;
121 return (DDI_FAILURE);
122 }
123
124 ohci->soft_state = soft_state;
125 ohci->ohci_drvinfo = drvinfo;
126
127 /*
128 * make sure PCI Master and PCI Memory Access are enabled on x86
129 * platforms. This may not be the case if plug and play OS is
130 * set in the BIOS
131 */
132 #if defined(__x86)
133 cmdreg = pci_config_get16(soft_state->pci_config, PCI_CONF_COMM);
134 if ((cmdreg & (PCI_COMM_MAE | PCI_COMM_ME)) != (PCI_COMM_MAE |
135 PCI_COMM_ME)) {
136 cmdreg |= PCI_COMM_MAE | PCI_COMM_ME;
137 pci_config_put16(soft_state->pci_config, PCI_CONF_COMM, cmdreg);
138 }
139 #endif
140
141 /*
142 * Initialize the openHCI chip. This is broken out because we need to
143 * do this when resuming too.
144 */
145 status = hci1394_ohci_chip_init(ohci);
146 if (status != DDI_SUCCESS) {
147 ddi_regs_map_free(&ohci->ohci_reg_handle);
148 mutex_destroy(&ohci->ohci_mutex);
149 kmem_free(ohci, sizeof (hci1394_ohci_t));
150 *ohci_hdl = NULL;
151 return (DDI_FAILURE);
152 }
153
154 /* Init the 1394 PHY */
155 status = hci1394_ohci_phy_init(ohci);
156 if (status != DDI_SUCCESS) {
157 (void) hci1394_ohci_soft_reset(ohci);
158 ddi_regs_map_free(&ohci->ohci_reg_handle);
159 mutex_destroy(&ohci->ohci_mutex);
160 kmem_free(ohci, sizeof (hci1394_ohci_t));
161 *ohci_hdl = NULL;
162 return (DDI_FAILURE);
163 }
164
165 /* Init 1394a features if present */
166 if (ohci->ohci_phy == H1394_PHY_1394A) {
167 status = hci1394_ohci_1394a_init(ohci);
168 if (status != DDI_SUCCESS) {
169 (void) hci1394_ohci_soft_reset(ohci);
170 ddi_regs_map_free(&ohci->ohci_reg_handle);
171 mutex_destroy(&ohci->ohci_mutex);
172 kmem_free(ohci, sizeof (hci1394_ohci_t));
173 *ohci_hdl = NULL;
174 return (DDI_FAILURE);
175 }
176 }
177
178 /* save away guid, phy type, and vendor info */
179 soft_state->halinfo.guid = hci1394_ohci_guid(ohci);
180 soft_state->halinfo.phy = ohci->ohci_phy;
181 soft_state->vendor_info.ohci_vendor_id =
182 ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->vendor_id);
183 version = ddi_get32(ohci->ohci_reg_handle, &ohci->ohci_regs->version);
184 soft_state->vendor_info.ohci_version = version;
185
186 /* We do not support version < 1.0 */
187 if (OHCI_VERSION(version) == 0) {
188 cmn_err(CE_NOTE,
189 "hci1394(%d): OpenHCI version %x.%x is not supported",
190 drvinfo->di_instance, OHCI_VERSION(version),
191 OHCI_REVISION(version));
192 (void) hci1394_ohci_soft_reset(ohci);
193 ddi_regs_map_free(&ohci->ohci_reg_handle);
194 mutex_destroy(&ohci->ohci_mutex);
195 kmem_free(ohci, sizeof (hci1394_ohci_t));
196 *ohci_hdl = NULL;
197 return (DDI_FAILURE);
198 }
199
200 /* Initialize the selfid buffer */
201 status = hci1394_ohci_selfid_init(ohci);
202 if (status != DDI_SUCCESS) {
203 (void) hci1394_ohci_soft_reset(ohci);
204 ddi_regs_map_free(&ohci->ohci_reg_handle);
205 mutex_destroy(&ohci->ohci_mutex);
206 kmem_free(ohci, sizeof (hci1394_ohci_t));
207 *ohci_hdl = NULL;
208 return (DDI_FAILURE);
209 }
210
211 /* Initialize the config rom buffer */
212 status = hci1394_ohci_cfgrom_init(ohci);
213 if (status != DDI_SUCCESS) {
214 (void) hci1394_ohci_soft_reset(ohci);
215 hci1394_buf_free(&ohci->ohci_selfid_handle);
216 ddi_regs_map_free(&ohci->ohci_reg_handle);
217 mutex_destroy(&ohci->ohci_mutex);
218 kmem_free(ohci, sizeof (hci1394_ohci_t));
219 *ohci_hdl = NULL;
220 return (DDI_FAILURE);
221 }
222
223 return (DDI_SUCCESS);
224 }
225
226
227 /*
228 * hci1394_ohci_fini()
229 * Cleanup after OpenHCI init. This should be called during detach.
230 */
231 void
hci1394_ohci_fini(hci1394_ohci_handle_t * ohci_hdl)232 hci1394_ohci_fini(hci1394_ohci_handle_t *ohci_hdl)
233 {
234 hci1394_ohci_t *ohci;
235
236
237 ASSERT(ohci_hdl != NULL);
238
239 ohci = *ohci_hdl;
240
241 /* reset chip */
242 (void) hci1394_ohci_soft_reset(ohci);
243
244 /* Free config rom space */
245 hci1394_buf_free(&ohci->ohci_cfgrom_handle);
246
247 /* Free selfid buffer space */
248 hci1394_buf_free(&ohci->ohci_selfid_handle);
249
250 /* Free up the OpenHCI registers */
251 ddi_regs_map_free(&ohci->ohci_reg_handle);
252
253 mutex_destroy(&ohci->ohci_mutex);
254
255 /* Free the OpenHCI state space */
256 kmem_free(ohci, sizeof (hci1394_ohci_t));
257 *ohci_hdl = NULL;
258 }
259
260
261 /*
262 * hci1394_ohci_chip_init()
263 * Initialize the OpenHCI registers. This contains the bulk of the initial
264 * register setup.
265 */
266 static int
hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl)267 hci1394_ohci_chip_init(hci1394_ohci_handle_t ohci_hdl)
268 {
269 int status;
270
271
272 ASSERT(ohci_hdl != NULL);
273
274 /* Reset 1394 OHCI HW */
275 status = hci1394_ohci_soft_reset(ohci_hdl);
276 if (status != DDI_SUCCESS) {
277 return (DDI_FAILURE);
278 }
279
280 /*
281 * Setup Host Control Register. The software reset does not put all
282 * registers in a known state. The Host Control Register is one of these
283 * registers. First make sure noByteSwapData and postedWriteEnable and
284 * are cleared.
285 */
286 ddi_put32(ohci_hdl->ohci_reg_handle,
287 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_NO_BSWAP |
288 OHCI_HC_POSTWR_ENBL);
289
290 /*
291 * the determination if we should swap data is made during the PCI
292 * initialization.
293 */
294 if (ohci_hdl->soft_state->swap_data == B_FALSE) {
295 /*
296 * most hba's don't swap data. It will be swapped in the
297 * global swap for SPARC. Enable Link Power(LPS). Enable
298 * Posted Writes
299 */
300 ddi_put32(ohci_hdl->ohci_reg_handle,
301 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_NO_BSWAP |
302 OHCI_HC_LPS | OHCI_HC_POSTWR_ENBL);
303 } else {
304 /*
305 * Swap Data. Enable Link Power(LPS). Enable Posted Writes
306 */
307 ddi_put32(ohci_hdl->ohci_reg_handle,
308 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LPS |
309 OHCI_HC_POSTWR_ENBL);
310 }
311
312 /*
313 * Wait for PHY to come up. There does not seem to be standard time for
314 * how long wait for the PHY to come up. The problem is that the PHY
315 * provides a clock to the link layer and if that is not stable, we
316 * could get a PCI timeout error when reading/writing a phy register
317 * (and maybe an OpenHCI register?) This used to be set to 10mS which
318 * works for just about every adapter we tested on. We got a new TI
319 * adapter which would crash the system once in a while if nothing
320 * (1394 device) was pluged into the adapter. Changing this delay to
321 * 50mS made that problem go away. This value is set via a patchable
322 * variable located in hci1394_extern.c
323 */
324 delay(drv_usectohz(hci1394_phy_stabilization_delay_uS));
325
326 /* Clear Isochrounous receive multi-chan mode registers */
327 ddi_put32(ohci_hdl->ohci_reg_handle,
328 &ohci_hdl->ohci_regs->ir_multi_maskhi_clr, 0xFFFFFFFF);
329 ddi_put32(ohci_hdl->ohci_reg_handle,
330 &ohci_hdl->ohci_regs->ir_multi_masklo_clr, 0xFFFFFFFF);
331
332 /*
333 * Setup async retry on busy or ack_data_error
334 * secondlimit = 0 <= bits 31-29
335 * cycleLimit = 0 <= bits 28-16
336 * maxPhysRespRetries = 0 <= bits 11-8
337 * maxARRespRetries = 0 <= bits 7-4
338 * maxATReqRetries = 2 <= bits 3-0
339 */
340 ddi_put32(ohci_hdl->ohci_reg_handle,
341 &ohci_hdl->ohci_regs->at_retries, 0x00000002);
342
343 /*
344 * Setup Link Control
345 * Enable cycleMaster, cycleTimerEnable, and rcvPhyPkt.
346 */
347 ddi_put32(ohci_hdl->ohci_reg_handle,
348 &ohci_hdl->ohci_regs->link_ctrl_clr, 0xFFFFFFFF);
349 ddi_put32(ohci_hdl->ohci_reg_handle,
350 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST |
351 OHCI_LC_CTIME_ENBL | OHCI_LC_RCV_PHY);
352
353 /*
354 * Set the Physical address map boundary to 0x0000FFFFFFFF. The
355 * phys_upper_bound is the upper 32-bits of the 48-bit 1394 address. The
356 * lower 16 bits are assumed to be 0xFFFF.
357 */
358 ddi_put32(ohci_hdl->ohci_reg_handle,
359 &ohci_hdl->ohci_regs->phys_upper_bound, (uint32_t)0x0000FFFF);
360
361 /*
362 * Enable all async requests.
363 * The asyncReqResourceAll bit (0x80000000) does not get cleared during
364 * a bus reset. If this code is changed to selectively allow nodes to
365 * perform ARREQ's, the ARREQ filter bits will need to be updated after
366 * every bus reset.
367 */
368 ddi_put32(ohci_hdl->ohci_reg_handle,
369 &ohci_hdl->ohci_regs->ar_req_filterhi_set, (uint32_t)0x80000000);
370
371 /*
372 * clear isochronous interrupt event and mask registers clearing the
373 * mask registers disable all isoc tx & rx ints
374 */
375 ddi_put32(ohci_hdl->ohci_reg_handle,
376 &ohci_hdl->ohci_regs->it_intr_event_clr, (uint32_t)0xFFFFFFFF);
377 ddi_put32(ohci_hdl->ohci_reg_handle,
378 &ohci_hdl->ohci_regs->it_intr_mask_clr, (uint32_t)0xFFFFFFFF);
379 ddi_put32(ohci_hdl->ohci_reg_handle,
380 &ohci_hdl->ohci_regs->ir_intr_event_clr, (uint32_t)0xFFFFFFFF);
381 ddi_put32(ohci_hdl->ohci_reg_handle,
382 &ohci_hdl->ohci_regs->ir_intr_mask_clr, (uint32_t)0xFFFFFFFF);
383
384 /* Clear interrupt event/mask register */
385 ddi_put32(ohci_hdl->ohci_reg_handle,
386 &ohci_hdl->ohci_regs->intr_event_clr, (uint32_t)0xFFFFFFFF);
387 ddi_put32(ohci_hdl->ohci_reg_handle,
388 &ohci_hdl->ohci_regs->intr_mask_clr, (uint32_t)0xFFFFFFFF);
389
390 return (DDI_SUCCESS);
391 }
392
393
394 /*
395 * hci1394_ohci_soft_reset()
396 * Reset OpenHCI HW.
397 */
398 int
hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl)399 hci1394_ohci_soft_reset(hci1394_ohci_handle_t ohci_hdl)
400 {
401 uint32_t resetStatus;
402
403
404 ASSERT(ohci_hdl != NULL);
405
406 /* Reset 1394 HW - Reset is bit 16 in HCControl */
407 ddi_put32(ohci_hdl->ohci_reg_handle,
408 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_SOFT_RESET);
409
410 /* Wait for reset to complete */
411 drv_usecwait(OHCI_CHIP_RESET_TIME_IN_uSEC);
412
413 /* Verify reset is complete */
414 resetStatus = ddi_get32(ohci_hdl->ohci_reg_handle,
415 &ohci_hdl->ohci_regs->hc_ctrl_set);
416 resetStatus = resetStatus & OHCI_HC_SOFT_RESET;
417 if (resetStatus != 0) {
418 return (DDI_FAILURE);
419 }
420
421 return (DDI_SUCCESS);
422 }
423
424
425 /*
426 * hci1394_ohci_reg_read()
427 * Read OpenHCI register. This is called from the test ioctl interface
428 * through devctl.
429 */
430 void
hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t * data)431 hci1394_ohci_reg_read(hci1394_ohci_handle_t ohci_hdl,
432 uint_t offset, uint32_t *data)
433 {
434 uint32_t *addr;
435
436
437 ASSERT(ohci_hdl != NULL);
438 ASSERT(data != NULL);
439
440 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs +
441 (uintptr_t)(offset & OHCI_REG_ADDR_MASK));
442 *data = ddi_get32(ohci_hdl->ohci_reg_handle, addr);
443 }
444
445
446 /*
447 * hci1394_ohci_reg_write()
448 * Write OpenHCI register. This is called from the test ioctl interface
449 * through devctl.
450 */
451 void
hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t data)452 hci1394_ohci_reg_write(hci1394_ohci_handle_t ohci_hdl,
453 uint_t offset, uint32_t data)
454 {
455 uint32_t *addr;
456
457
458 ASSERT(ohci_hdl != NULL);
459
460 addr = (uint32_t *)((uintptr_t)ohci_hdl->ohci_regs +
461 (uintptr_t)(offset & OHCI_REG_ADDR_MASK));
462 ddi_put32(ohci_hdl->ohci_reg_handle, addr, data);
463 }
464
465
466 /*
467 * hci1394_ohci_intr_master_enable()
468 * Enable interrupts to be passed on from OpenHCI. This is a global mask.
469 * Individual interrupts still need to be enabled for interrupts to be
470 * generated.
471 */
472 void
hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl)473 hci1394_ohci_intr_master_enable(hci1394_ohci_handle_t ohci_hdl)
474 {
475 ASSERT(ohci_hdl != NULL);
476
477 ddi_put32(ohci_hdl->ohci_reg_handle,
478 &ohci_hdl->ohci_regs->intr_mask_set, OHCI_INTR_MASTER_INTR_ENBL);
479 }
480
481
482 /*
483 * hci1394_ohci_intr_master_disable()
484 * Disable all OpenHCI interrupts from being passed on. This does not affect
485 * the individual interrupt mask settings. When interrupts are enabled
486 * again, the same individual interrupts will still be enabled.
487 */
488 void
hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl)489 hci1394_ohci_intr_master_disable(hci1394_ohci_handle_t ohci_hdl)
490 {
491 ASSERT(ohci_hdl != NULL);
492
493 ddi_put32(ohci_hdl->ohci_reg_handle,
494 &ohci_hdl->ohci_regs->intr_mask_clr, OHCI_INTR_MASTER_INTR_ENBL);
495 }
496
497
498 /*
499 * hci1394_ohci_intr_asserted()
500 * Return which ENABLED interrupts are asserted. If an interrupt is disabled
501 * via its mask bit, it will not be returned from here.
502 *
503 * NOTE: we may want to make this a macro at some point.
504 */
505 uint32_t
hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl)506 hci1394_ohci_intr_asserted(hci1394_ohci_handle_t ohci_hdl)
507 {
508 uint32_t interrupts_asserted;
509
510 ASSERT(ohci_hdl != NULL);
511
512 /*
513 * Only look at interrupts which are enabled by reading the
514 * intr_event_clr register.
515 */
516 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle,
517 &ohci_hdl->ohci_regs->intr_event_clr);
518
519 return (interrupts_asserted);
520 }
521
522
523 /*
524 * hci1394_ohci_intr_enable()
525 * Enable an individual interrupt or set of interrupts. This does not affect
526 * the global interrupt mask.
527 */
528 void
hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)529 hci1394_ohci_intr_enable(hci1394_ohci_handle_t ohci_hdl,
530 uint32_t interrupt_mask)
531 {
532 ASSERT(ohci_hdl != NULL);
533
534 ddi_put32(ohci_hdl->ohci_reg_handle,
535 &ohci_hdl->ohci_regs->intr_mask_set, interrupt_mask);
536 }
537
538
539 /*
540 * hci1394_ohci_intr_disable()
541 * Disable an individual interrupt or set of interrupts. This does not affect
542 * the global interrupt mask.
543 */
544 void
hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)545 hci1394_ohci_intr_disable(hci1394_ohci_handle_t ohci_hdl,
546 uint32_t interrupt_mask)
547 {
548 ASSERT(ohci_hdl != NULL);
549
550 ddi_put32(ohci_hdl->ohci_reg_handle,
551 &ohci_hdl->ohci_regs->intr_mask_clr, interrupt_mask);
552 }
553
554
555 /*
556 * hci1394_ohci_intr_clear()
557 * Clear a set of interrupts so that they are not asserted anymore.
558 *
559 * NOTE: we may want to make this a macro at some point.
560 */
561 void
hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)562 hci1394_ohci_intr_clear(hci1394_ohci_handle_t ohci_hdl,
563 uint32_t interrupt_mask)
564 {
565 ASSERT(ohci_hdl != NULL);
566
567 ddi_put32(ohci_hdl->ohci_reg_handle,
568 &ohci_hdl->ohci_regs->intr_event_clr, interrupt_mask);
569 }
570
571
572 /*
573 * hci1394_ohci_it_intr_asserted()
574 * Return which ENABLED isoch TX interrupts are asserted. If an interrupt is
575 * disabled via its mask bit, it will not be returned from here.
576 *
577 * NOTE: we may want to make this a macro at some point.
578 */
579 uint32_t
hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl)580 hci1394_ohci_it_intr_asserted(hci1394_ohci_handle_t ohci_hdl)
581 {
582 uint32_t interrupts_asserted;
583
584 ASSERT(ohci_hdl != NULL);
585
586 /* Only look at interrupts which are enabled */
587 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle,
588 &ohci_hdl->ohci_regs->it_intr_event_clr);
589
590 return (interrupts_asserted);
591 }
592
593
594 /*
595 * hci1394_ohci_it_intr_enable()
596 * Enable an individual isoch TX interrupt. This does not affect the general
597 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/
598 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
599 */
600 void
hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)601 hci1394_ohci_it_intr_enable(hci1394_ohci_handle_t ohci_hdl,
602 uint32_t interrupt_mask)
603 {
604 ASSERT(ohci_hdl != NULL);
605
606 ddi_put32(ohci_hdl->ohci_reg_handle,
607 &ohci_hdl->ohci_regs->it_intr_mask_set, interrupt_mask);
608 }
609
610
611 /*
612 * hci1394_ohci_it_intr_disable()
613 * Disable an individual isoch TX interrupt. This does not affect the general
614 * isoch interrupt mask in the OpenHCI Mask register. That is enabled/
615 * disabled via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
616 */
617 void
hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)618 hci1394_ohci_it_intr_disable(hci1394_ohci_handle_t ohci_hdl,
619 uint32_t interrupt_mask)
620 {
621 ASSERT(ohci_hdl != NULL);
622
623 ddi_put32(ohci_hdl->ohci_reg_handle,
624 &ohci_hdl->ohci_regs->it_intr_mask_clr, interrupt_mask);
625 }
626
627
628 /*
629 * hci1394_ohci_it_intr_clear()
630 * Clear an individual isoch TX interrupt so that it is not asserted anymore.
631 *
632 * NOTE: we may want to make this a macro at some point.
633 */
634 void
hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)635 hci1394_ohci_it_intr_clear(hci1394_ohci_handle_t ohci_hdl,
636 uint32_t interrupt_mask)
637 {
638 ASSERT(ohci_hdl != NULL);
639
640 ddi_put32(ohci_hdl->ohci_reg_handle,
641 &ohci_hdl->ohci_regs->it_intr_event_clr, interrupt_mask);
642 }
643
644
645 /*
646 * hci1394_ohci_it_ctxt_count_get()
647 * Determine the number of supported isochronous transmit contexts.
648 */
649 int
hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)650 hci1394_ohci_it_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)
651 {
652 uint32_t channel_mask;
653 int count;
654
655 ASSERT(ohci_hdl != NULL);
656
657 /*
658 * hw is required to support contexts 0 to N, where N <= 31
659 * the interrupt mask bits are wired to ground for unsupported
660 * contexts. Write 1's to all it mask bits, then read the mask.
661 * Implemented contexts will read (sequentially) as 1
662 */
663 ddi_put32(ohci_hdl->ohci_reg_handle,
664 &ohci_hdl->ohci_regs->it_intr_mask_set, 0xFFFFFFFF);
665 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle,
666 &ohci_hdl->ohci_regs->it_intr_mask_set);
667 count = 0;
668 while (channel_mask != 0) {
669 channel_mask = channel_mask >> 1;
670 count++;
671 }
672
673 return (count);
674 }
675
676
677 /*
678 * hci1394_ohci_it_cmd_ptr_set()
679 * Set the context pointer for a given isoch TX context. This is the IO
680 * address for the HW to fetch the first descriptor. The context should
681 * not be running when this routine is called.
682 */
683 void
hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,uint_t context_number,uint32_t io_addr)684 hci1394_ohci_it_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,
685 uint_t context_number, uint32_t io_addr)
686 {
687 ASSERT(ohci_hdl != NULL);
688
689 ddi_put32(ohci_hdl->ohci_reg_handle,
690 &ohci_hdl->ohci_regs->it[context_number].cmd_ptrlo,
691 io_addr);
692 }
693
694
695 /*
696 * hci1394_ohci_ir_intr_asserted()
697 * Return which ENABLED isoch RX interrupts are asserted. If an interrupt is
698 * disabled via its mask bit, it will not be returned from here.
699 *
700 * NOTE: we may want to make this a macro at some point.
701 */
702 uint32_t
hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl)703 hci1394_ohci_ir_intr_asserted(hci1394_ohci_handle_t ohci_hdl)
704 {
705 uint32_t interrupts_asserted;
706
707 ASSERT(ohci_hdl != NULL);
708
709 /* Only look at interrupts which are enabled */
710 interrupts_asserted = ddi_get32(ohci_hdl->ohci_reg_handle,
711 &ohci_hdl->ohci_regs->ir_intr_event_clr);
712
713 return (interrupts_asserted);
714 }
715
716
717 /*
718 * hci1394_ohci_ir_intr_enable()
719 * Enable an individual isoch RX interrupt. This does not affect the isoch
720 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled
721 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
722 */
723 void
hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)724 hci1394_ohci_ir_intr_enable(hci1394_ohci_handle_t ohci_hdl,
725 uint32_t interrupt_mask)
726 {
727 ASSERT(ohci_hdl != NULL);
728
729 ddi_put32(ohci_hdl->ohci_reg_handle,
730 &ohci_hdl->ohci_regs->ir_intr_mask_set, interrupt_mask);
731 }
732
733
734 /*
735 * hci1394_ohci_ir_intr_disable()
736 * Disable an individual isoch RX interrupt. This does not affect the isoch
737 * interrupt mask in the OpenHCI Mask register. That is enabled/disabled
738 * via hci1394_ohci_intr_enable/hci1394_ohci_intr_disable.
739 */
740 void
hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)741 hci1394_ohci_ir_intr_disable(hci1394_ohci_handle_t ohci_hdl,
742 uint32_t interrupt_mask)
743 {
744 ASSERT(ohci_hdl != NULL);
745
746 ddi_put32(ohci_hdl->ohci_reg_handle,
747 &ohci_hdl->ohci_regs->ir_intr_mask_clr, interrupt_mask);
748 }
749
750
751 /*
752 * hci1394_ohci_ir_intr_clear()
753 * Clear an individual isoch RX interrupt so that it is not asserted anymore.
754 *
755 * NOTE: we may want to make this a macro at some point.
756 */
757 void
hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl,uint32_t interrupt_mask)758 hci1394_ohci_ir_intr_clear(hci1394_ohci_handle_t ohci_hdl,
759 uint32_t interrupt_mask)
760 {
761 ASSERT(ohci_hdl != NULL);
762
763 ddi_put32(ohci_hdl->ohci_reg_handle,
764 &ohci_hdl->ohci_regs->ir_intr_event_clr, interrupt_mask);
765 }
766
767
768 /*
769 * hci1394_ohci_ir_ctxt_count_get()
770 * Determine the number of supported isochronous receive contexts.
771 */
772 int
hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)773 hci1394_ohci_ir_ctxt_count_get(hci1394_ohci_handle_t ohci_hdl)
774 {
775 uint32_t channel_mask;
776 int count;
777
778 ASSERT(ohci_hdl != NULL);
779
780 /*
781 * hw is required to support contexts 0 to N, where N <= 31
782 * the interrupt mask bits are wired to ground for unsupported
783 * contexts. Write 1's to all ir mask bits, then read the mask.
784 * Implemented contexts will read (sequentially) as 1
785 */
786 ddi_put32(ohci_hdl->ohci_reg_handle,
787 &ohci_hdl->ohci_regs->ir_intr_mask_set, 0xFFFFFFFF);
788 channel_mask = ddi_get32(ohci_hdl->ohci_reg_handle,
789 &ohci_hdl->ohci_regs->ir_intr_mask_set);
790 count = 0;
791 while (channel_mask != 0) {
792 channel_mask = channel_mask >> 1;
793 count++;
794 }
795
796 return (count);
797 }
798
799
800 /*
801 * hci1394_ohci_ir_cmd_ptr_set()
802 * Set the context pointer for a given isoch RX context. This is the IO
803 * address for the HW to fetch the first descriptor. The context should
804 * not be running when this routine is called.
805 */
806 void
hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,uint_t context_number,uint32_t io_addr)807 hci1394_ohci_ir_cmd_ptr_set(hci1394_ohci_handle_t ohci_hdl,
808 uint_t context_number, uint32_t io_addr)
809 {
810 ASSERT(ohci_hdl != NULL);
811
812 ddi_put32(ohci_hdl->ohci_reg_handle,
813 &ohci_hdl->ohci_regs->ir[context_number].cmd_ptrlo,
814 io_addr);
815 }
816
817
818 /*
819 * hci1394_ohci_link_enable()
820 * Enable the 1394 link layer. When the link is enabled, the PHY will pass
821 * up any 1394 bus transactions which would normally come up to the link.
822 */
823 void
hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl)824 hci1394_ohci_link_enable(hci1394_ohci_handle_t ohci_hdl)
825 {
826 ASSERT(ohci_hdl != NULL);
827
828 ddi_put32(ohci_hdl->ohci_reg_handle,
829 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_LINK_ENBL);
830 }
831
832
833 /*
834 * hci1394_ohci_link_disable()
835 * Disable the 1394 link layer. When the link is disabled, the PHY will NOT
836 * pass up any 1394 bus transactions which would normally come up to the
837 * link. This "logically" disconnects us from the 1394 bus.
838 */
839 void
hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl)840 hci1394_ohci_link_disable(hci1394_ohci_handle_t ohci_hdl)
841 {
842 ASSERT(ohci_hdl != NULL);
843
844 ddi_put32(ohci_hdl->ohci_reg_handle,
845 &ohci_hdl->ohci_regs->hc_ctrl_clr, OHCI_HC_LINK_ENBL);
846 }
847
848
849 /*
850 * hci1394_ohci_bus_reset()
851 * Reset the 1394 bus. This performs a "long" bus reset and can be called
852 * when the adapter has either a 1394-1995 or 1394A PHY.
853 */
854 int
hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl)855 hci1394_ohci_bus_reset(hci1394_ohci_handle_t ohci_hdl)
856 {
857 int status;
858 uint_t reg;
859
860
861 ASSERT(ohci_hdl != NULL);
862
863 /*
864 * We want to reset the bus. We also handle the root_holdoff and gap
865 * count cacheing explained at the top of this file.
866 */
867 reg = OHCI_PHY_IBR;
868 if (ohci_hdl->ohci_set_root_holdoff == B_TRUE) {
869 reg = reg | OHCI_PHY_RHB;
870 }
871 if (ohci_hdl->ohci_set_gap_count == B_TRUE) {
872 reg = reg | ohci_hdl->ohci_gap_count;
873 } else {
874 reg = reg | OHCI_PHY_MAX_GAP;
875 }
876
877 /*
878 * Reset the bus. We intentionally do NOT do a PHY read here. A PHY
879 * read could introduce race conditions and would be more likely to fail
880 * due to a timeout.
881 */
882 status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg);
883 if (status != DDI_SUCCESS) {
884 return (DDI_FAILURE);
885 }
886
887 /* clear the root holdoff and gap count state bits */
888 ohci_hdl->ohci_set_root_holdoff = B_FALSE;
889 ohci_hdl->ohci_set_gap_count = B_FALSE;
890
891 return (DDI_SUCCESS);
892 }
893
894 /*
895 *
896 * hci1394_ohci_bus_reset_nroot()
897 * Reset the 1394 bus. This performs a "long" bus reset with out a root.
898 */
899 int
hci1394_ohci_bus_reset_nroot(hci1394_ohci_handle_t ohci_hdl)900 hci1394_ohci_bus_reset_nroot(hci1394_ohci_handle_t ohci_hdl)
901 {
902 int status;
903 uint_t reg;
904
905 ASSERT(ohci_hdl != NULL);
906
907 /*
908 * We want to reset the bus. We don't care about any holdoff
909 * we are suspending need no root...
910 */
911 (void) hci1394_ohci_phy_read(ohci_hdl, 0x1, ®);
912 reg = reg | OHCI_PHY_IBR;
913 reg = reg & ~OHCI_PHY_RHB;
914
915 /*
916 * Reset the bus. We intentionally do NOT do a PHY read here. A PHY
917 * read could introduce race conditions and would be more likely to fail
918 * due to a timeout.
919 */
920 status = hci1394_ohci_phy_write(ohci_hdl, 0x1, reg);
921 if (status != DDI_SUCCESS) {
922 return (DDI_FAILURE);
923 }
924
925 return (DDI_SUCCESS);
926 }
927
928 /*
929 * hci1394_ohci_phy_init()
930 * Setup the PHY. This should be called during attach and performs any PHY
931 * initialization required including figuring out what kind of PHY we have.
932 */
933 int
hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl)934 hci1394_ohci_phy_init(hci1394_ohci_handle_t ohci_hdl)
935 {
936 int status;
937 uint_t phy_reg;
938
939
940 ASSERT(ohci_hdl != NULL);
941
942 /*
943 * if the phy has extended set to 7, the phy is a not a 1394-1995 PHY.
944 * It could be a 1394a phy or beyond. The PHY type can be found in PHY
945 * register page 1 in the compliance_level register.
946 *
947 * Since there are not any current standards beyond 1394A, we are going
948 * to consider the PHY to be a 1394A phy if the extended bit is set.
949 *
950 * phy registers are byte wide registers and are addressed as 0, 1, 2,
951 * 3, ... Phy register 0 may not be read or written.
952 *
953 * Phy register 0x2 (bit 0 MSB, 7 LSB)
954 * Extended - bits 0 - 2
955 * Total Ports - bits 4 - 7
956 */
957 status = hci1394_ohci_phy_read(ohci_hdl, 2, &phy_reg);
958 if (status != DDI_SUCCESS) {
959 return (DDI_FAILURE);
960 }
961
962 if ((phy_reg & OHCI_PHY_EXTND_MASK) != OHCI_PHY_EXTND) {
963 /*
964 * if the extended bit is not set, we have to be a 1394-1995
965 * PHY
966 */
967 ohci_hdl->ohci_phy = H1394_PHY_1995;
968 } else {
969 /* Treat all other PHY's as a 1394A PHY */
970 ohci_hdl->ohci_phy = H1394_PHY_1394A;
971 }
972
973 return (DDI_SUCCESS);
974 }
975
976
977 /*
978 * hci1394_ohci_phy_resume()
979 * re-initialize the PHY. This routine should be called during a resume after
980 * a successful suspend has been done.
981 */
982 /* ARGSUSED */
983 static int
hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl)984 hci1394_ohci_phy_resume(hci1394_ohci_handle_t ohci_hdl)
985 {
986 ASSERT(ohci_hdl != NULL);
987
988 /* There is currently nothing to re-initialize here */
989 return (DDI_SUCCESS);
990 }
991
992
993 /*
994 * hci1394_ohci_phy_set()
995 * Perform bitset operation on PHY register.
996 */
997 int
hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t bits)998 hci1394_ohci_phy_set(hci1394_ohci_handle_t ohci_hdl, uint_t address,
999 uint_t bits)
1000 {
1001 int status;
1002 uint_t reg;
1003
1004
1005 ASSERT(ohci_hdl != NULL);
1006
1007 mutex_enter(&ohci_hdl->ohci_mutex);
1008
1009 /* read the PHY register */
1010 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®);
1011 if (status != DDI_SUCCESS) {
1012 mutex_exit(&ohci_hdl->ohci_mutex);
1013 return (DDI_FAILURE);
1014 }
1015
1016 /* Set the bits and write the result back */
1017 reg = reg | bits;
1018 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg);
1019 if (status != DDI_SUCCESS) {
1020 mutex_exit(&ohci_hdl->ohci_mutex);
1021 return (DDI_FAILURE);
1022 }
1023
1024 mutex_exit(&ohci_hdl->ohci_mutex);
1025
1026 return (DDI_SUCCESS);
1027 }
1028
1029
1030 /*
1031 * hci1394_ohci_phy_clr()
1032 * Perform bitclr operation on PHY register.
1033 */
1034 int
hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t bits)1035 hci1394_ohci_phy_clr(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1036 uint_t bits)
1037 {
1038 int status;
1039 uint_t reg;
1040
1041
1042 ASSERT(ohci_hdl != NULL);
1043
1044 mutex_enter(&ohci_hdl->ohci_mutex);
1045
1046 /* read the PHY register */
1047 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, ®);
1048 if (status != DDI_SUCCESS) {
1049 mutex_exit(&ohci_hdl->ohci_mutex);
1050 return (DDI_FAILURE);
1051 }
1052
1053 /* Set the bits and write the result back */
1054 reg = reg & ~bits;
1055 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, reg);
1056 if (status != DDI_SUCCESS) {
1057 mutex_exit(&ohci_hdl->ohci_mutex);
1058 return (DDI_FAILURE);
1059 }
1060
1061 mutex_exit(&ohci_hdl->ohci_mutex);
1062 return (DDI_SUCCESS);
1063 }
1064
1065
1066 /*
1067 * hci1394_ohci_phy_read()
1068 * Atomic PHY register read
1069 */
1070 int
hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t * data)1071 hci1394_ohci_phy_read(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1072 uint_t *data)
1073 {
1074 int status;
1075
1076 ASSERT(ohci_hdl != NULL);
1077 mutex_enter(&ohci_hdl->ohci_mutex);
1078 status = hci1394_ohci_phy_read_no_lock(ohci_hdl, address, data);
1079 mutex_exit(&ohci_hdl->ohci_mutex);
1080
1081 return (status);
1082 }
1083
1084
1085 /*
1086 * hci1394_ohci_phy_write()
1087 * Atomic PHY register write
1088 */
1089 int
hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t data)1090 hci1394_ohci_phy_write(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1091 uint_t data)
1092 {
1093 int status;
1094
1095 ASSERT(ohci_hdl != NULL);
1096 mutex_enter(&ohci_hdl->ohci_mutex);
1097 status = hci1394_ohci_phy_write_no_lock(ohci_hdl, address, data);
1098 mutex_exit(&ohci_hdl->ohci_mutex);
1099
1100 return (status);
1101 }
1102
1103
1104 /*
1105 * hci1394_ohci_phy_read_no_lock()
1106 * This routine actually performs the PHY register read. It is seperated
1107 * out from phy_read so set & clr lock can perform an atomic PHY register
1108 * operation. It assumes the OpenHCI mutex is held.
1109 */
1110 static int
hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t * data)1111 hci1394_ohci_phy_read_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1112 uint_t *data)
1113 {
1114 uint32_t ohci_reg;
1115 int count;
1116
1117
1118 ASSERT(ohci_hdl != NULL);
1119 ASSERT(data != NULL);
1120 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex));
1121
1122 /* You can't read or write PHY register #0 */
1123 if (address == 0) {
1124 return (DDI_FAILURE);
1125 }
1126
1127 /* Verify phy access not in progress */
1128 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1129 &ohci_hdl->ohci_regs->phy_ctrl);
1130 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) {
1131 return (DDI_FAILURE);
1132 }
1133
1134 /* Start the PHY register read */
1135 ohci_reg = OHCI_PHYC_RDREG | ((address & 0xF) <<
1136 OHCI_PHYC_REGADDR_SHIFT);
1137 ddi_put32(ohci_hdl->ohci_reg_handle, &ohci_hdl->ohci_regs->phy_ctrl,
1138 ohci_reg);
1139
1140 /*
1141 * The PHY read usually takes less than 1uS. It is not worth having
1142 * this be interrupt driven. Having this be interrupt driven would also
1143 * make the bus reset and self id processing much more complex for
1144 * 1995 PHY's. We will wait up to hci1394_phy_delay_uS for the read
1145 * to complete (this was initially set to 10). I have yet to see
1146 * count > 1. The delay is a patchable variable.
1147 */
1148 count = 0;
1149 while (count < hci1394_phy_delay_uS) {
1150 /* See if the read is done yet */
1151 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1152 &ohci_hdl->ohci_regs->phy_ctrl);
1153 if ((ohci_reg & OHCI_PHYC_RDDONE) != 0) {
1154 /*
1155 * The read is done. clear the phyRegRecv interrupt. We
1156 * do not have this interrupt enabled but this keeps
1157 * things clean in case someone in the future does.
1158 * Break out of the loop, we are done.
1159 */
1160 ddi_put32(ohci_hdl->ohci_reg_handle,
1161 &ohci_hdl->ohci_regs->intr_event_clr,
1162 OHCI_INTR_PHY_REG_RCVD);
1163 break;
1164 }
1165
1166 /*
1167 * the phy read did not yet complete, wait 1uS, increment the
1168 * count and try again.
1169 */
1170 drv_usecwait(1);
1171 count++;
1172 }
1173
1174 /* Check to see if we timed out */
1175 if (count >= hci1394_phy_delay_uS) {
1176 /* we timed out, return failure */
1177 *data = 0;
1178 return (DDI_FAILURE);
1179 }
1180
1181 /* setup the PHY read data to be returned */
1182 *data = (ddi_get32(ohci_hdl->ohci_reg_handle,
1183 &ohci_hdl->ohci_regs->phy_ctrl) & OHCI_PHYC_RDDATA_MASK) >>
1184 OHCI_PHYC_RDDATA_SHIFT;
1185
1186 return (DDI_SUCCESS);
1187 }
1188
1189
1190 /*
1191 * hci1394_ohci_phy_write_no_lock()
1192 * This routine actually performs the PHY register write. It is separated
1193 * out from phy_write so set & clr lock can perform an atomic PHY register
1194 * operation. It assumes the OpenHCI mutex is held.
1195 */
1196 static int
hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl,uint_t address,uint_t data)1197 hci1394_ohci_phy_write_no_lock(hci1394_ohci_handle_t ohci_hdl, uint_t address,
1198 uint_t data)
1199 {
1200 uint32_t ohci_reg;
1201 int count;
1202
1203
1204 ASSERT(ohci_hdl != NULL);
1205 ASSERT(MUTEX_HELD(&ohci_hdl->ohci_mutex));
1206
1207 /* You can't read or write PHY register #0 */
1208 if (address == 0) {
1209 return (DDI_FAILURE);
1210 }
1211
1212 /* Verify phy access not in progress */
1213 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1214 &ohci_hdl->ohci_regs->phy_ctrl);
1215 if ((ohci_reg & (OHCI_PHYC_RDREG | OHCI_PHYC_WRREG)) != 0) {
1216 return (DDI_FAILURE);
1217 }
1218
1219 /* Start the PHY register write */
1220 ohci_reg = OHCI_PHYC_WRREG | ((address & 0xF) <<
1221 OHCI_PHYC_REGADDR_SHIFT) | (data & OHCI_PHYC_WRDATA_MASK);
1222 ddi_put32(ohci_hdl->ohci_reg_handle,
1223 &ohci_hdl->ohci_regs->phy_ctrl, ohci_reg);
1224
1225 /*
1226 * The PHY write usually takes less than 1uS. It is not worth having
1227 * this be interrupt driven. Having this be interrupt driven would also
1228 * make the bus reset and self id processing much more complex. We will
1229 * wait up to hci1394_phy_delay_uS for the write to complete (this was
1230 * initially set to 10). I have yet to see count > 0. The delay is a
1231 * patchable variable.
1232 */
1233 count = 0;
1234 while (count < hci1394_phy_delay_uS) {
1235 /* See if the write is done yet */
1236 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1237 &ohci_hdl->ohci_regs->phy_ctrl);
1238 if ((ohci_reg & OHCI_PHYC_WRREG) == 0) {
1239 /*
1240 * The write completed. Break out of the loop, we are
1241 * done.
1242 */
1243 break;
1244 }
1245
1246 /*
1247 * the phy write did not yet complete, wait 1uS, increment the
1248 * count and try again.
1249 */
1250 drv_usecwait(1);
1251 count++;
1252 }
1253
1254 /* Check to see if we timed out */
1255 if (count >= hci1394_phy_delay_uS) {
1256 /* we timed out, return failure */
1257 return (DDI_FAILURE);
1258 }
1259
1260 return (DDI_SUCCESS);
1261 }
1262
1263
1264 /*
1265 * hci1394_ohci_phy_info()
1266 * Return selfid word for our PHY. This routine should ONLY be called for
1267 * adapters with a 1394-1995 PHY. These PHY's do not embed their own selfid
1268 * information in the selfid buffer so we need to do it for them in the
1269 * selfid complete interrupt handler. This routine only supports building
1270 * selfid info for a 3 port PHY. Since we will probably not ever see a
1271 * 1394-1995 PHY in any production system, and if we do it will have 3 ports
1272 * or less, this is a pretty safe assumption.
1273 */
1274 int
hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl,uint32_t * info)1275 hci1394_ohci_phy_info(hci1394_ohci_handle_t ohci_hdl, uint32_t *info)
1276 {
1277 int status;
1278 uint32_t phy_info;
1279 uint32_t reg;
1280 int index;
1281 int num_ports;
1282 int count;
1283 uint32_t port_status;
1284
1285
1286 ASSERT(ohci_hdl != NULL);
1287 ASSERT(info != NULL);
1288 ASSERT(ohci_hdl->ohci_phy == H1394_PHY_1995);
1289
1290 /*
1291 * Set Link on. We are using power class 0 since we have no idea what
1292 * our real power class is.
1293 */
1294 phy_info = 0x80400000;
1295
1296 /* Add in Physical ID */
1297 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1298 &ohci_hdl->ohci_regs->node_id);
1299 phy_info = phy_info | ((reg << IEEE1394_SELFID_PHYID_SHIFT) &
1300 IEEE1394_SELFID_PHYID_MASK);
1301
1302 /* Add in Gap Count */
1303 status = hci1394_ohci_phy_read(ohci_hdl, 1, ®);
1304 if (status != DDI_SUCCESS) {
1305 return (DDI_FAILURE);
1306 }
1307 phy_info = phy_info | ((reg << IEEE1394_SELFID_GAP_CNT_SHIFT) &
1308 IEEE1394_SELFID_GAP_CNT_MASK);
1309
1310 /* Add in speed & ports */
1311 status = hci1394_ohci_phy_read(ohci_hdl, 2, ®);
1312 if (status != DDI_SUCCESS) {
1313 return (DDI_FAILURE);
1314 }
1315 phy_info = phy_info | ((reg & 0xC0) << 8);
1316 num_ports = reg & 0x1F;
1317
1318 /* PHY reports that it has 0 ports?? */
1319 if (num_ports == 0) {
1320 return (DDI_FAILURE);
1321 }
1322
1323 /* Build up the port information for each port in the PHY */
1324 count = 0;
1325 for (index = 0; index < 3; index++) {
1326 if (num_ports > 0) {
1327 status = hci1394_ohci_phy_read(ohci_hdl,
1328 count + 3, ®);
1329 if (status != DDI_SUCCESS) {
1330 return (DDI_FAILURE);
1331 }
1332 /* if port is not connected */
1333 if ((reg & 0x04) == 0) {
1334 port_status =
1335 IEEE1394_SELFID_PORT_NOT_CONNECTED;
1336
1337 /* else if port is connected to parent */
1338 } else if ((reg & 0x08) == 0) {
1339 port_status = IEEE1394_SELFID_PORT_TO_PARENT;
1340
1341 /* else port is connected to child */
1342 } else {
1343 port_status = IEEE1394_SELFID_PORT_TO_CHILD;
1344 }
1345
1346 num_ports--;
1347 } else {
1348 port_status = IEEE1394_SELFID_PORT_NO_PORT;
1349 }
1350
1351 /* add in the port information */
1352 phy_info = phy_info | (port_status << (6 - (index * 2)));
1353 count++;
1354 }
1355
1356 /* Copy the PHY selfid info to the return parameter */
1357 *info = phy_info;
1358
1359 return (DDI_SUCCESS);
1360 }
1361
1362
1363 /*
1364 * hci1394_ohci_current_busgen()
1365 * return the current bus generation.
1366 */
1367 uint_t
hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl)1368 hci1394_ohci_current_busgen(hci1394_ohci_handle_t ohci_hdl)
1369 {
1370 uint32_t reg;
1371 uint_t generation_count;
1372
1373
1374 ASSERT(ohci_hdl != NULL);
1375
1376 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1377 &ohci_hdl->ohci_regs->self_id_count);
1378 generation_count = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT;
1379
1380 return (generation_count);
1381 }
1382
1383
1384 /*
1385 * hci1394_ohci_startup()
1386 * Startup the 1394 nexus driver. This is called after all of the HW has
1387 * been initialized (in both attach and resume) and we are ready to
1388 * participate on the bus.
1389 */
1390 int
hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl)1391 hci1394_ohci_startup(hci1394_ohci_handle_t ohci_hdl)
1392 {
1393 int status;
1394
1395
1396 ASSERT(ohci_hdl != NULL);
1397
1398 /*
1399 * Turn on 1394 link. This allows us to receive 1394 traffic off the
1400 * bus
1401 */
1402 hci1394_ohci_link_enable(ohci_hdl);
1403
1404 /*
1405 * Reset the 1394 Bus.
1406 * Need to do this so that the link layer can collect all of the self-id
1407 * packets. The Interrupt routine will cause further initialization
1408 * after the bus reset has completed
1409 */
1410 status = hci1394_ohci_bus_reset(ohci_hdl);
1411 if (status != DDI_SUCCESS) {
1412 return (DDI_FAILURE);
1413 }
1414
1415 /* setup out initial interrupt mask and enable interrupts */
1416 hci1394_isr_mask_setup(ohci_hdl->soft_state);
1417 hci1394_ohci_intr_master_enable(ohci_hdl);
1418
1419 return (DDI_SUCCESS);
1420 }
1421
1422
1423 /*
1424 * hci1394_ohci_postwr_addr()
1425 * Read the Posted Write Address registers. This should be read when a
1426 * posted write error is detected to find out what transaction had an error.
1427 */
1428 void
hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl,uint64_t * addr)1429 hci1394_ohci_postwr_addr(hci1394_ohci_handle_t ohci_hdl, uint64_t *addr)
1430 {
1431 uint32_t reg;
1432
1433
1434 ASSERT(ohci_hdl != NULL);
1435 ASSERT(addr != NULL);
1436
1437 /* read in the errored address */
1438 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1439 &ohci_hdl->ohci_regs->posted_write_addrhi);
1440 *addr = ((uint64_t)reg) << 32;
1441 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1442 &ohci_hdl->ohci_regs->posted_write_addrlo);
1443 *addr = *addr | (uint64_t)reg;
1444
1445 /*
1446 * Interrupt should be cleared after reading the posted write address.
1447 * See 13.2.8.1 in OpenHCI spec v1.0.
1448 */
1449 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_POST_WR_ERR);
1450 }
1451
1452
1453 /*
1454 * hci1394_ohci_guid()
1455 * Return the adapter's GUID
1456 */
1457 uint64_t
hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl)1458 hci1394_ohci_guid(hci1394_ohci_handle_t ohci_hdl)
1459 {
1460 uint32_t reg;
1461 uint64_t guid;
1462
1463
1464 ASSERT(ohci_hdl != NULL);
1465
1466 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1467 &ohci_hdl->ohci_regs->guid_hi);
1468 guid = ((uint64_t)reg) << 32;
1469 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1470 &ohci_hdl->ohci_regs->guid_lo);
1471 guid = guid | (uint64_t)reg;
1472
1473 return (guid);
1474 }
1475
1476
1477 /*
1478 * hci1394_ohci_csr_read()
1479 * Read one of the HW implemented CSR registers. These include
1480 * bus_manager_id, bandwidth_available, channels_available_hi, and
1481 * channels_available_lo. Offset should be set to
1482 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL
1483 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO.
1484 */
1485 int
hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t * data)1486 hci1394_ohci_csr_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset,
1487 uint32_t *data)
1488 {
1489 uint_t generation;
1490 int status;
1491
1492
1493 ASSERT(ohci_hdl != NULL);
1494 ASSERT(data != NULL);
1495
1496 /*
1497 * read the CSR register by doing a cswap with the same compare and
1498 * swap value.
1499 */
1500 generation = hci1394_ohci_current_busgen(ohci_hdl);
1501 status = hci1394_ohci_csr_cswap(ohci_hdl, generation, offset, 0, 0,
1502 data);
1503 if (status != DDI_SUCCESS) {
1504 return (DDI_FAILURE);
1505 }
1506
1507 return (DDI_SUCCESS);
1508 }
1509
1510
1511 /*
1512 * hci1394_ohci_csr_cswap()
1513 * Perform a compare/swap on one of the HW implemented CSR registers. These
1514 * include bus_manager_id, bandwidth_available, channels_available_hi, and
1515 * channels_available_lo. Offset should be set to
1516 * OHCI_CSR_SEL_BUS_MGR_ID, OHCI_CSR_SEL_BANDWIDTH_AVAIL
1517 * OHCI_CSR_SEL_CHANS_AVAIL_HI, or OHCI_CSR_SEL_CHANS_AVAIL_LO.
1518 */
1519 int
hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl,uint_t generation,uint_t offset,uint32_t compare,uint32_t swap,uint32_t * old)1520 hci1394_ohci_csr_cswap(hci1394_ohci_handle_t ohci_hdl, uint_t generation,
1521 uint_t offset, uint32_t compare, uint32_t swap, uint32_t *old)
1522 {
1523 int count;
1524 uint32_t ohci_reg;
1525
1526
1527 ASSERT(ohci_hdl != NULL);
1528 ASSERT(old != NULL);
1529
1530 /*
1531 * Make sure we have not gotten a bus reset since this action was
1532 * started.
1533 */
1534 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
1535 return (DDI_FAILURE);
1536 }
1537
1538 mutex_enter(&ohci_hdl->ohci_mutex);
1539
1540 /* init csrData and csrCompare */
1541 ddi_put32(ohci_hdl->ohci_reg_handle,
1542 &ohci_hdl->ohci_regs->csr_data, swap);
1543 ddi_put32(ohci_hdl->ohci_reg_handle,
1544 &ohci_hdl->ohci_regs->csr_compare_data, compare);
1545
1546 /* start the compare swap */
1547 ddi_put32(ohci_hdl->ohci_reg_handle,
1548 &ohci_hdl->ohci_regs->csr_ctrl, offset & OHCI_CSR_SELECT);
1549
1550 /*
1551 * The CSR access should be immediate. There in nothing that officially
1552 * states this so we will wait up to 2uS just in case before we timeout.
1553 * We actually perform a compare swap with both compare and swap set
1554 * to the same value. This will return the old value which is in
1555 * essence, a read.
1556 */
1557 count = 0;
1558 while (count < 2) {
1559 /* See if the compare swap is done */
1560 ohci_reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1561 &ohci_hdl->ohci_regs->csr_ctrl);
1562 if ((ohci_reg & OHCI_CSR_DONE) != 0) {
1563 /* The compare swap is done, break out of the loop */
1564 break;
1565 }
1566 /*
1567 * The compare swap has not completed yet, wait 1uS, increment
1568 * the count and try again
1569 */
1570 drv_usecwait(1);
1571 count++;
1572 }
1573
1574 /* If we timed out, return an error */
1575 if (count >= 2) {
1576 *old = 0;
1577 mutex_exit(&ohci_hdl->ohci_mutex);
1578 return (DDI_FAILURE);
1579 }
1580
1581 /* Copy the old data into the return parameter */
1582 *old = ddi_get32(ohci_hdl->ohci_reg_handle,
1583 &ohci_hdl->ohci_regs->csr_data);
1584
1585 mutex_exit(&ohci_hdl->ohci_mutex);
1586
1587 /*
1588 * There is a race condition in the OpenHCI design here. After checking
1589 * the generation and before performing the cswap, we could get a bus
1590 * reset and incorrectly set something like the bus manager. This would
1591 * put us into a condition where we would not have a bus manager and
1592 * we would think there was one. If it is possible that this race
1593 * condition occured, we will reset the bus to clean things up. We only
1594 * care about this if the compare swap was successful.
1595 */
1596 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
1597 if (*old == compare) {
1598 (void) hci1394_ohci_bus_reset(ohci_hdl);
1599 return (DDI_FAILURE);
1600 }
1601 }
1602
1603 return (DDI_SUCCESS);
1604 }
1605
1606
1607 /*
1608 * hci1394_ohci_contender_enable()
1609 * Set the contender bit in the PHY. This routine should only be called
1610 * if our PHY is 1394A compliant. (i.e. this routine should not be called
1611 * for a 1394-1995 PHY).
1612 */
1613 int
hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl)1614 hci1394_ohci_contender_enable(hci1394_ohci_handle_t ohci_hdl)
1615 {
1616 int status;
1617
1618
1619 ASSERT(ohci_hdl != NULL);
1620
1621 /*
1622 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a
1623 * contender bit to set.
1624 */
1625 if (ohci_hdl->ohci_phy == H1394_PHY_1995) {
1626 return (DDI_FAILURE);
1627 }
1628
1629 /* Set the Contender Bit */
1630 status = hci1394_ohci_phy_set(ohci_hdl, 0x4, OHCI_PHY_CNTDR);
1631 if (status != DDI_SUCCESS) {
1632 return (DDI_FAILURE);
1633 }
1634
1635 return (DDI_SUCCESS);
1636 }
1637
1638
1639 /*
1640 * hci1394_ohci_root_holdoff_enable()
1641 * Set the root holdoff bit in the PHY. Since there are race conditions when
1642 * writing to PHY register 1 (which can get updated from a PHY packet off the
1643 * bus), we cache this state until a "long" bus reset is issued.
1644 */
1645 int
hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl)1646 hci1394_ohci_root_holdoff_enable(hci1394_ohci_handle_t ohci_hdl)
1647 {
1648 ASSERT(ohci_hdl != NULL);
1649
1650 ohci_hdl->ohci_set_root_holdoff = B_TRUE;
1651
1652 return (DDI_SUCCESS);
1653 }
1654
1655
1656 /*
1657 * hci1394_ohci_gap_count_set()
1658 * Set the gap count in the PHY. Since there are race conditions when writing
1659 * to PHY register 1 (which can get updated from a PHY packet off the bus),
1660 * we cache this gap count until a "long" bus reset is issued.
1661 */
1662 int
hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl,uint_t gap_count)1663 hci1394_ohci_gap_count_set(hci1394_ohci_handle_t ohci_hdl, uint_t gap_count)
1664 {
1665 ASSERT(ohci_hdl != NULL);
1666
1667 ohci_hdl->ohci_set_gap_count = B_TRUE;
1668 ohci_hdl->ohci_gap_count = gap_count & OHCI_PHY_MAX_GAP;
1669
1670 return (DDI_SUCCESS);
1671 }
1672
1673
1674 /*
1675 * hci1394_ohci_phy_filter_set()
1676 * Enable a node (or nodes) to perform transactions to our physical
1677 * memory. OpenHCI allows you to disable/enable physical requests on a node
1678 * per node basis. A physical request is basically a read/write to 1394
1679 * address space 0x0 - 0xFFFFFFFF. This address goes out to the IO MMU (in
1680 * the case of a SPARC machine). The HAL starts with all nodes unable to
1681 * read/write physical memory. The Services Layer will call down and enable
1682 * nodes via setting a physical filter bit for that given node. Since node
1683 * numbers change every bus reset, the services layer has to call down after
1684 * every bus reset to re-enable physical accesses. (NOTE: the hardware
1685 * automatically clears these bits.
1686 */
1687 int
hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl,uint64_t mask,uint_t generation)1688 hci1394_ohci_phy_filter_set(hci1394_ohci_handle_t ohci_hdl, uint64_t mask,
1689 uint_t generation)
1690 {
1691 uint32_t data;
1692
1693
1694 ASSERT(ohci_hdl != NULL);
1695
1696 /*
1697 * Make sure we have not gotten a bus reset since this action was
1698 * started.
1699 */
1700 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
1701 return (DDI_FAILURE);
1702 }
1703
1704 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF);
1705 ddi_put32(ohci_hdl->ohci_reg_handle,
1706 &ohci_hdl->ohci_regs->phys_req_filterhi_set, data);
1707 data = (uint32_t)(mask & 0xFFFFFFFF);
1708 ddi_put32(ohci_hdl->ohci_reg_handle,
1709 &ohci_hdl->ohci_regs->phys_req_filterlo_set, data);
1710
1711 /*
1712 * There is a race condition in the OpenHCI design here. After checking
1713 * the generation and before setting the physical filter bits, we could
1714 * get a bus reset and incorrectly set the physical filter bits. If it
1715 * is possible that this race condition occured, we will reset the bus
1716 * to clean things up.
1717 */
1718 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
1719 (void) hci1394_ohci_bus_reset(ohci_hdl);
1720 return (DDI_SUCCESS);
1721 }
1722
1723 return (DDI_SUCCESS);
1724 }
1725
1726
1727 /*
1728 * hci1394_ohci_phy_filter_clr()
1729 * Disable a node (or nodes) from performing transactions to our physical
1730 * memory. See hci1394_ohci_phy_filter_set() above for more info.
1731 */
1732 int
hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl,uint64_t mask,uint_t generation)1733 hci1394_ohci_phy_filter_clr(hci1394_ohci_handle_t ohci_hdl,
1734 uint64_t mask, uint_t generation)
1735 {
1736 uint32_t data;
1737
1738
1739 ASSERT(ohci_hdl != NULL);
1740
1741 /*
1742 * Make sure we have not gotten a bus reset since this action was
1743 * started.
1744 */
1745 if (generation != hci1394_ohci_current_busgen(ohci_hdl)) {
1746 return (DDI_FAILURE);
1747 }
1748
1749 data = (uint32_t)((mask >> 32) & 0xFFFFFFFF);
1750 ddi_put32(ohci_hdl->ohci_reg_handle,
1751 &ohci_hdl->ohci_regs->phys_req_filterhi_clr, data);
1752 data = (uint32_t)(mask & 0xFFFFFFFF);
1753 ddi_put32(ohci_hdl->ohci_reg_handle,
1754 &ohci_hdl->ohci_regs->phys_req_filterlo_clr, data);
1755
1756 return (DDI_SUCCESS);
1757 }
1758
1759
1760 /*
1761 * hci1394_ohci_bus_reset_short()
1762 * Perform a 1394A short bus reset. This function should only be called
1763 * on an adapter with a 1394A PHY (or later).
1764 */
1765 int
hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl)1766 hci1394_ohci_bus_reset_short(hci1394_ohci_handle_t ohci_hdl)
1767 {
1768 int status;
1769
1770 ASSERT(ohci_hdl != NULL);
1771
1772 /*
1773 * Make sure that phy is not a 1394-1995 phy. Those phy's do not have a
1774 * contender bit to set.
1775 */
1776 if (ohci_hdl->ohci_phy == H1394_PHY_1995) {
1777 return (DDI_FAILURE);
1778 }
1779
1780 /* Initiate the short bus reset */
1781 status = hci1394_ohci_phy_set(ohci_hdl, 0x5, OHCI_PHY_ISBR);
1782 if (status != DDI_SUCCESS) {
1783 return (DDI_FAILURE);
1784 }
1785
1786 return (status);
1787 }
1788
1789
1790 /*
1791 * hci1394_ohci_cfgrom_update()
1792 * Update the config rom with the provided contents. The config rom is
1793 * provided as a byte stream which is multiple of 4 bytes large. The
1794 * size is passed as a quadlet (4 bytes) count. The entire contents
1795 * of the config rom is updated at once. We do not provide a partial
1796 * update interface.
1797 */
1798 void
hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl,void * local_buf,uint_t quadlet_count)1799 hci1394_ohci_cfgrom_update(hci1394_ohci_handle_t ohci_hdl, void *local_buf,
1800 uint_t quadlet_count)
1801 {
1802 uint32_t *data;
1803
1804
1805 ASSERT(ohci_hdl != NULL);
1806 ASSERT(local_buf != NULL);
1807
1808 data = (uint32_t *)local_buf;
1809
1810 /* zero out the config ROM header to start */
1811 ddi_put32(ohci_hdl->ohci_reg_handle,
1812 &ohci_hdl->ohci_regs->config_rom_hdr, 0);
1813
1814 /* copy Services Layer buffer into config rom buffer */
1815 ddi_rep_put8(ohci_hdl->ohci_cfgrom.bi_handle, local_buf,
1816 (uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr, quadlet_count << 2,
1817 DDI_DEV_AUTOINCR);
1818
1819 (void) ddi_dma_sync(ohci_hdl->ohci_cfgrom.bi_dma_handle, 0,
1820 quadlet_count << 2, DDI_DMA_SYNC_FORDEV);
1821
1822 /*
1823 * setup OHCI bus options and config rom hdr registers. We need to swap
1824 * the config rom header and bus options on an X86 machine since the
1825 * data is provided to us as a byte stream and the OHCI registers expect
1826 * a big endian 32-bit number.
1827 */
1828 ddi_put32(ohci_hdl->ohci_reg_handle,
1829 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(data[2]));
1830 ddi_put32(ohci_hdl->ohci_reg_handle,
1831 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(data[0]));
1832 }
1833
1834
1835 /*
1836 * hci1394_ohci_nodeid_get()
1837 * Return our current nodeid (bus #/Node #)
1838 */
1839 void
hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl,uint_t * nodeid)1840 hci1394_ohci_nodeid_get(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid)
1841 {
1842 uint32_t reg;
1843
1844 ASSERT(ohci_hdl != NULL);
1845 ASSERT(nodeid != NULL);
1846 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1847 &ohci_hdl->ohci_regs->node_id);
1848 *nodeid = (reg & 0xFFFF) << 16;
1849 }
1850
1851
1852 /*
1853 * hci1394_ohci_nodeid_set()
1854 * Set our current nodeid (bus #/Node #). This actually sets our bus number.
1855 * Our node number cannot be set by software. This is usually trigered via
1856 * a write to the CSR NODEIDS register.
1857 */
1858 void
hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl,uint_t nodeid)1859 hci1394_ohci_nodeid_set(hci1394_ohci_handle_t ohci_hdl, uint_t nodeid)
1860 {
1861 uint32_t reg;
1862
1863 ASSERT(ohci_hdl != NULL);
1864
1865 reg = ((nodeid & 0xFFC00000) >> 16);
1866 ddi_put32(ohci_hdl->ohci_reg_handle,
1867 &ohci_hdl->ohci_regs->node_id, reg);
1868 }
1869
1870
1871 /*
1872 * hci1394_ohci_nodeid_info()
1873 * Return our current nodeid (bus #/Node #). This also returns whether or
1874 * not our nodeid error bit is set. This is useful in determining if the
1875 * bus reset completed without errors in the selfid complete interrupt
1876 * processing.
1877 */
1878 void
hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl,uint_t * nodeid,boolean_t * error)1879 hci1394_ohci_nodeid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *nodeid,
1880 boolean_t *error)
1881 {
1882 uint32_t reg;
1883
1884 ASSERT(ohci_hdl != NULL);
1885 ASSERT(nodeid != NULL);
1886
1887 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1888 &ohci_hdl->ohci_regs->node_id);
1889 *nodeid = reg & 0xFFFF;
1890 if ((reg & OHCI_NDID_IDVALID) == 0) {
1891 *error = B_TRUE;
1892 } else {
1893 *error = B_FALSE;
1894 }
1895 }
1896
1897
1898 /*
1899 * hci1394_ohci_cycletime_get()
1900 * Return the current cycle time
1901 */
1902 void
hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl,uint32_t * cycle_time)1903 hci1394_ohci_cycletime_get(hci1394_ohci_handle_t ohci_hdl,
1904 uint32_t *cycle_time)
1905 {
1906 ASSERT(ohci_hdl != NULL);
1907 ASSERT(cycle_time != NULL);
1908 *cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle,
1909 &ohci_hdl->ohci_regs->isoch_cycle_timer);
1910 }
1911
1912
1913 /*
1914 * hci1394_ohci_cycletime_get()
1915 * Set the cycle time
1916 */
1917 void
hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl,uint32_t cycle_time)1918 hci1394_ohci_cycletime_set(hci1394_ohci_handle_t ohci_hdl,
1919 uint32_t cycle_time)
1920 {
1921 ASSERT(ohci_hdl != NULL);
1922 ddi_put32(ohci_hdl->ohci_reg_handle,
1923 &ohci_hdl->ohci_regs->isoch_cycle_timer, cycle_time);
1924 }
1925
1926
1927 /*
1928 * hci1394_ohci_bustime_get()
1929 * Return the current bus time.
1930 */
1931 void
hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl,uint32_t * bus_time)1932 hci1394_ohci_bustime_get(hci1394_ohci_handle_t ohci_hdl, uint32_t *bus_time)
1933 {
1934 uint32_t bus_time1;
1935 uint32_t bus_time2;
1936 uint32_t cycle_time;
1937
1938
1939 ASSERT(ohci_hdl != NULL);
1940 ASSERT(bus_time != NULL);
1941
1942 /*
1943 * The bus time is composed of a portion of the cycle time and the
1944 * cycle time rollover count (ohci_bustime_count). There is a race
1945 * condition where we read the rollover count and then the cycle
1946 * timer rolls over. This is the reason for the double read of the
1947 * rollover count.
1948 */
1949 do {
1950 bus_time1 = ohci_hdl->ohci_bustime_count;
1951 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle,
1952 &ohci_hdl->ohci_regs->isoch_cycle_timer);
1953 bus_time2 = ohci_hdl->ohci_bustime_count;
1954 } while (bus_time1 != bus_time2);
1955
1956 *bus_time = (bus_time2 << 7) | (cycle_time >> 25);
1957 }
1958
1959
1960 /*
1961 * hci1394_ohci_bustime_set()
1962 * Set the cycle timer rollover portion of the bus time.
1963 */
1964 void
hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl,uint32_t bus_time)1965 hci1394_ohci_bustime_set(hci1394_ohci_handle_t ohci_hdl, uint32_t bus_time)
1966 {
1967 ASSERT(ohci_hdl != NULL);
1968
1969 /*
1970 * we will start with the cycle 64 seconds interrupt disabled. If this
1971 * is the first write to bus time, enable the interrupt.
1972 */
1973 if (ohci_hdl->ohci_bustime_enabled == B_FALSE) {
1974 ohci_hdl->ohci_bustime_enabled = B_TRUE;
1975 /* Clear the cycle64Seconds interrupt then enable it */
1976 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS);
1977 hci1394_ohci_intr_enable(ohci_hdl, OHCI_INTR_CYC_64_SECS);
1978 }
1979 ohci_hdl->ohci_bustime_count = (bus_time >> 7);
1980 }
1981
1982
1983 /*
1984 * hci1394_ohci_atreq_retries_get()
1985 * Get the number of atreq retries we will perform.
1986 */
1987 void
hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl,uint_t * atreq_retries)1988 hci1394_ohci_atreq_retries_get(hci1394_ohci_handle_t ohci_hdl,
1989 uint_t *atreq_retries)
1990 {
1991 uint32_t reg;
1992
1993 ASSERT(ohci_hdl != NULL);
1994 ASSERT(atreq_retries != NULL);
1995 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
1996 &ohci_hdl->ohci_regs->at_retries);
1997 *atreq_retries = reg & OHCI_RET_MAX_ATREQ_MASK;
1998 }
1999
2000
2001 /*
2002 * hci1394_ohci_atreq_retries_get()
2003 * Set the number of atreq retries we will perform.
2004 */
2005 void
hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl,uint_t atreq_retries)2006 hci1394_ohci_atreq_retries_set(hci1394_ohci_handle_t ohci_hdl,
2007 uint_t atreq_retries)
2008 {
2009 uint32_t reg;
2010
2011
2012 ASSERT(ohci_hdl != NULL);
2013
2014 mutex_enter(&ohci_hdl->ohci_mutex);
2015 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2016 &ohci_hdl->ohci_regs->at_retries);
2017 reg = reg & ~OHCI_RET_MAX_ATREQ_MASK;
2018 reg = reg | (atreq_retries & OHCI_RET_MAX_ATREQ_MASK);
2019 ddi_put32(ohci_hdl->ohci_reg_handle,
2020 &ohci_hdl->ohci_regs->at_retries, reg);
2021 mutex_exit(&ohci_hdl->ohci_mutex);
2022 }
2023
2024
2025 /*
2026 * hci1394_ohci_isr_cycle64seconds()
2027 * Interrupt handler for the cycle64seconds interrupt.
2028 */
2029 void
hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl)2030 hci1394_ohci_isr_cycle64seconds(hci1394_ohci_handle_t ohci_hdl)
2031 {
2032 uint32_t cycle_time;
2033
2034 ASSERT(ohci_hdl != NULL);
2035
2036 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_CYC_64_SECS);
2037 cycle_time = ddi_get32(ohci_hdl->ohci_reg_handle,
2038 &ohci_hdl->ohci_regs->isoch_cycle_timer);
2039
2040 /*
2041 * cycle64second interrupts when the MSBit in the cycle timer changes
2042 * state. We only care about rollover so we will increment only when
2043 * the MSBit is set to 0.
2044 */
2045 if ((cycle_time & 0x80000000) == 0) {
2046 ohci_hdl->ohci_bustime_count++;
2047 }
2048 }
2049
2050
2051 /*
2052 * hci1394_ohci_isr_phy()
2053 * Interrupt handler for a PHY event
2054 */
2055 void
hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl)2056 hci1394_ohci_isr_phy(hci1394_ohci_handle_t ohci_hdl)
2057 {
2058 uint_t phy_status;
2059 int status;
2060
2061
2062 ASSERT(ohci_hdl != NULL);
2063
2064 /* clear the interrupt */
2065 hci1394_ohci_intr_clear(ohci_hdl, OHCI_INTR_PHY);
2066
2067 /* increment the statistics count */
2068 ohci_hdl->ohci_drvinfo->di_stats.st_phy_isr++;
2069
2070 /*
2071 * If the PHY is a 1995 phy, just return since there are no status bits
2072 * to read.
2073 */
2074 if (ohci_hdl->ohci_phy == H1394_PHY_1995) {
2075 return;
2076 }
2077
2078 /* See why we got this interrupt */
2079 status = hci1394_ohci_phy_read(ohci_hdl, 5, &phy_status);
2080 if (status != DDI_SUCCESS) {
2081 return;
2082 }
2083
2084 if (phy_status & OHCI_PHY_LOOP_ERR) {
2085 ohci_hdl->ohci_drvinfo->di_stats.st_phy_loop_err++;
2086 cmn_err(CE_NOTE, "hci1394(%d): ERROR - bus loop detected",
2087 ohci_hdl->ohci_drvinfo->di_instance);
2088 }
2089 if (phy_status & OHCI_PHY_PWRFAIL_ERR) {
2090 ohci_hdl->ohci_drvinfo->di_stats.st_phy_pwrfail_err++;
2091 }
2092 if (phy_status & OHCI_PHY_TIMEOUT_ERR) {
2093 ohci_hdl->ohci_drvinfo->di_stats.st_phy_timeout_err++;
2094 }
2095 if (phy_status & OHCI_PHY_PORTEVT_ERR) {
2096 ohci_hdl->ohci_drvinfo->di_stats.st_phy_portevt_err++;
2097 }
2098
2099 /* clear any set status bits */
2100 status = hci1394_ohci_phy_write(ohci_hdl, 5, phy_status);
2101 if (status != DDI_SUCCESS) {
2102 return;
2103 }
2104
2105 /*
2106 * Disable the PHY interrupt. We are getting stuck in this ISR in
2107 * certain PHY implementations so we will disable the interrupt until
2108 * we see a selfid complete.
2109 */
2110 hci1394_ohci_intr_disable(ohci_hdl, OHCI_INTR_PHY);
2111 }
2112
2113
2114 /*
2115 * hci1394_ohci_root_check
2116 * Returns status about if we are currently the root node on the 1394 bus.
2117 * returns B_TRUE if we are the root, B_FALSE if we are not the root.
2118 */
2119 boolean_t
hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl)2120 hci1394_ohci_root_check(hci1394_ohci_handle_t ohci_hdl)
2121 {
2122 uint32_t reg;
2123 int status;
2124
2125 ASSERT(ohci_hdl != NULL);
2126 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2127 &ohci_hdl->ohci_regs->node_id);
2128 if ((reg & OHCI_REG_NODEID_ROOT) && (reg & OHCI_NDID_IDVALID)) {
2129 status = B_TRUE;
2130 } else {
2131 status = B_FALSE;
2132 }
2133
2134 return (status);
2135 }
2136
2137
2138 /*
2139 * hci1394_ohci_cmc_check()
2140 * Returns status about if we are cycle master capable. Returns
2141 * B_TRUE if we are the cycle master capable, B_FALSE if we are not the cycle
2142 * master capable.
2143 */
2144 boolean_t
hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl)2145 hci1394_ohci_cmc_check(hci1394_ohci_handle_t ohci_hdl)
2146 {
2147 uint32_t reg;
2148 int status;
2149
2150 ASSERT(ohci_hdl != NULL);
2151 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2152 &ohci_hdl->ohci_regs->bus_options);
2153 if (reg & OHCI_REG_BUSOPTIONS_CMC) {
2154 status = B_TRUE;
2155 } else {
2156 status = B_FALSE;
2157 }
2158
2159 return (status);
2160 }
2161
2162
2163 /*
2164 * hci1394_ohci_cycle_master_enable()
2165 * Enables us to be cycle master. If we are root, we will start generating
2166 * cycle start packets.
2167 */
2168 void
hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl)2169 hci1394_ohci_cycle_master_enable(hci1394_ohci_handle_t ohci_hdl)
2170 {
2171 ASSERT(ohci_hdl != NULL);
2172
2173 /* First make sure that cycleTooLong is clear */
2174 ddi_put32(ohci_hdl->ohci_reg_handle,
2175 &ohci_hdl->ohci_regs->intr_event_clr, OHCI_INTR_CYC_TOO_LONG);
2176
2177 /* Enable Cycle Master */
2178 ddi_put32(ohci_hdl->ohci_reg_handle,
2179 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_CYC_MAST);
2180 }
2181
2182
2183 /*
2184 * hci1394_ohci_cycle_master_disable()
2185 * Disabled us from being cycle master. If we are root, we will stop
2186 * generating cycle start packets.
2187 */
2188 void
hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl)2189 hci1394_ohci_cycle_master_disable(hci1394_ohci_handle_t ohci_hdl)
2190 {
2191 ASSERT(ohci_hdl != NULL);
2192
2193 /* disable cycle master */
2194 ddi_put32(ohci_hdl->ohci_reg_handle,
2195 &ohci_hdl->ohci_regs->link_ctrl_clr, OHCI_LC_CYC_MAST);
2196 }
2197
2198
2199 /*
2200 * hci1394_ohci_resume()
2201 * Re-initialize the openHCI HW during a resume. (after a power suspend)
2202 */
2203 int
hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl)2204 hci1394_ohci_resume(hci1394_ohci_handle_t ohci_hdl)
2205 {
2206 uint32_t quadlet;
2207 int status;
2208
2209
2210 ASSERT(ohci_hdl != NULL);
2211
2212 /* Re-initialize the OpenHCI chip */
2213 status = hci1394_ohci_chip_init(ohci_hdl);
2214 if (status != DDI_SUCCESS) {
2215 return (DDI_FAILURE);
2216 }
2217
2218 /* Re-initialize the PHY */
2219 status = hci1394_ohci_phy_resume(ohci_hdl);
2220 if (status != DDI_SUCCESS) {
2221 return (DDI_FAILURE);
2222 }
2223
2224 /* Re-initialize any 1394A features we are using */
2225 status = hci1394_ohci_1394a_resume(ohci_hdl);
2226 if (status != DDI_SUCCESS) {
2227 return (DDI_FAILURE);
2228 }
2229
2230 /* Tell OpenHCI where the Config ROM buffer is */
2231 ddi_put32(ohci_hdl->ohci_reg_handle,
2232 &ohci_hdl->ohci_regs->config_rom_maplo,
2233 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address);
2234
2235 /* Tell OpenHCI where the SelfId buffer is */
2236 ddi_put32(ohci_hdl->ohci_reg_handle,
2237 &ohci_hdl->ohci_regs->self_id_buflo,
2238 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address);
2239
2240 /* Enable selfid DMA engine */
2241 hci1394_ohci_selfid_enable(ohci_hdl);
2242
2243 /*
2244 * re-setup OHCI bus options and config rom hdr registers. We need to
2245 * read from the config rom using ddi_rep_get8 since it is stored as
2246 * a byte stream. We need to swap the config rom header and bus options
2247 * on an X86 machine since the data is a byte stream and the OHCI
2248 * registers expect a big endian 32-bit number.
2249 */
2250 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet,
2251 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[8], 4,
2252 DDI_DEV_AUTOINCR);
2253 ddi_put32(ohci_hdl->ohci_reg_handle,
2254 &ohci_hdl->ohci_regs->bus_options, OHCI_SWAP32(quadlet));
2255 ddi_rep_get8(ohci_hdl->ohci_cfgrom.bi_handle, (uint8_t *)&quadlet,
2256 &((uint8_t *)ohci_hdl->ohci_cfgrom.bi_kaddr)[0], 4,
2257 DDI_DEV_AUTOINCR);
2258 ddi_put32(ohci_hdl->ohci_reg_handle,
2259 &ohci_hdl->ohci_regs->config_rom_hdr, OHCI_SWAP32(quadlet));
2260
2261 return (DDI_SUCCESS);
2262 }
2263
2264
2265 /*
2266 * hci1394_ohci_selfid_init()
2267 * Initialize the selfid buffer
2268 */
2269 static int
hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl)2270 hci1394_ohci_selfid_init(hci1394_ohci_handle_t ohci_hdl)
2271 {
2272 hci1394_buf_parms_t parms;
2273 int status;
2274
2275
2276 ASSERT(ohci_hdl != NULL);
2277
2278 /*
2279 * Setup for 2K buffer, aligned on a 2Kbyte address boundary. Make sure
2280 * that the buffer is not broken up into multiple cookies. OpenHCI can
2281 * only handle one address for the selfid buffer location.
2282 */
2283 parms.bp_length = 2048;
2284 parms.bp_max_cookies = 1;
2285 parms.bp_alignment = 2048;
2286 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms,
2287 &ohci_hdl->ohci_selfid, &ohci_hdl->ohci_selfid_handle);
2288 if (status != DDI_SUCCESS) {
2289 return (DDI_FAILURE);
2290 }
2291
2292 /* Tell OpenHCI where the buffer is */
2293 ddi_put32(ohci_hdl->ohci_reg_handle,
2294 &ohci_hdl->ohci_regs->self_id_buflo,
2295 (uint32_t)ohci_hdl->ohci_selfid.bi_cookie.dmac_address);
2296
2297 /* Enable selfid DMA engine */
2298 hci1394_ohci_selfid_enable(ohci_hdl);
2299
2300 return (DDI_SUCCESS);
2301 }
2302
2303
2304 /*
2305 * hci1394_ohci_selfid_enable()
2306 * Allow selfid packets to be placed into the selfid buffer. This should be
2307 * called after the selfid buffer address has been setup in the HW.
2308 */
2309 void
hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl)2310 hci1394_ohci_selfid_enable(hci1394_ohci_handle_t ohci_hdl)
2311 {
2312 ASSERT(ohci_hdl != NULL);
2313
2314 /*
2315 * Allow selfid packets to be received. This should be called during
2316 * driver attach after the selfid buffer address has been initialized.
2317 *
2318 * Link Control Register
2319 * rscSelfId = 1 <= bit 9
2320 */
2321 ddi_put32(ohci_hdl->ohci_reg_handle,
2322 &ohci_hdl->ohci_regs->link_ctrl_set, OHCI_LC_RCV_SELF);
2323 }
2324
2325
2326 /*
2327 * hci1394_ohci_selfid_read()
2328 * Read a word out of the selfid buffer.
2329 */
2330 void
hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl,uint_t offset,uint32_t * data)2331 hci1394_ohci_selfid_read(hci1394_ohci_handle_t ohci_hdl, uint_t offset,
2332 uint32_t *data)
2333 {
2334 ASSERT(ohci_hdl != NULL);
2335 ASSERT(data != NULL);
2336 *data = ddi_get32(ohci_hdl->ohci_selfid.bi_handle,
2337 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[offset]);
2338 }
2339
2340
2341 /*
2342 * hci1394_ohci_selfid_info()
2343 * Return the current bus generation, the number of bytes currently in the
2344 * selfid buffer, and if we have seen any selfid errors.
2345 */
2346 void
hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl,uint_t * busgen,uint_t * size,boolean_t * error)2347 hci1394_ohci_selfid_info(hci1394_ohci_handle_t ohci_hdl, uint_t *busgen,
2348 uint_t *size, boolean_t *error)
2349 {
2350 uint32_t reg;
2351
2352
2353 ASSERT(ohci_hdl != NULL);
2354 ASSERT(busgen != NULL);
2355 ASSERT(size != NULL);
2356 ASSERT(error != NULL);
2357
2358 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2359 &ohci_hdl->ohci_regs->self_id_count);
2360 *busgen = (reg & OHCI_SLFC_GEN_MASK) >> OHCI_SLFC_GEN_SHIFT;
2361 *size = reg & OHCI_SLFC_NUM_QUADS_MASK;
2362 if ((reg & OHCI_SLFC_ERROR) == 0) {
2363 *error = B_FALSE;
2364 } else {
2365 *error = B_TRUE;
2366 }
2367 }
2368
2369
2370 /*
2371 * hci1394_ohci_selfid_buf_current()
2372 * Test if the selfid buffer is current. Return B_TRUE if it is current and
2373 * B_FALSE if it is not current.
2374 */
2375 boolean_t
hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl)2376 hci1394_ohci_selfid_buf_current(hci1394_ohci_handle_t ohci_hdl)
2377 {
2378 uint32_t reg;
2379 int status;
2380
2381 ASSERT(ohci_hdl != NULL);
2382
2383 /*
2384 * if the generation stored in the selfid buffer is not equal to the
2385 * generation we have previously stored, the selfid buffer is not
2386 * current. (It maybe older or it maybe newer)
2387 */
2388 reg = ddi_get32(ohci_hdl->ohci_selfid.bi_handle,
2389 &((uint32_t *)ohci_hdl->ohci_selfid.bi_kaddr)[0]);
2390 if (ohci_hdl->ohci_drvinfo->di_gencnt != ((reg & OHCI_SLFC_GEN_MASK) >>
2391 OHCI_SLFC_GEN_SHIFT)) {
2392 status = B_FALSE;
2393 } else {
2394 status = B_TRUE;
2395 }
2396
2397 return (status);
2398 }
2399
2400
2401 /*
2402 * hci1394_ohci_selfid_sync()
2403 * Perform a ddi_dma_sync on the selfid buffer
2404 */
2405 void
hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl)2406 hci1394_ohci_selfid_sync(hci1394_ohci_handle_t ohci_hdl)
2407 {
2408 ASSERT(ohci_hdl != NULL);
2409 (void) ddi_dma_sync(ohci_hdl->ohci_selfid.bi_dma_handle, 0,
2410 ohci_hdl->ohci_selfid.bi_length, DDI_DMA_SYNC_FORKERNEL);
2411 }
2412
2413
2414 /*
2415 * hci1394_ohci_cfgrom_init()
2416 * Initialize the configuration ROM buffer
2417 */
2418 static int
hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl)2419 hci1394_ohci_cfgrom_init(hci1394_ohci_handle_t ohci_hdl)
2420 {
2421 hci1394_buf_parms_t parms;
2422 int status;
2423
2424
2425 ASSERT(ohci_hdl != NULL);
2426
2427 /*
2428 * Setup for 1K buffer, aligned at 1K address boundary, and allow no
2429 * less than 4 byte data transfers. Create the Buffer. Make sure that
2430 * the buffer is not broken up into multiple cookies. OpenHCI can only
2431 * handle one address for the config ROM buffer location.
2432 */
2433 parms.bp_length = 1024;
2434 parms.bp_max_cookies = 1;
2435 parms.bp_alignment = 1024;
2436 status = hci1394_buf_alloc(ohci_hdl->ohci_drvinfo, &parms,
2437 &ohci_hdl->ohci_cfgrom, &ohci_hdl->ohci_cfgrom_handle);
2438 if (status != DDI_SUCCESS) {
2439 return (DDI_FAILURE);
2440 }
2441
2442 /* Tell OpenHCI where the buffer is */
2443 ddi_put32(ohci_hdl->ohci_reg_handle,
2444 &ohci_hdl->ohci_regs->config_rom_maplo,
2445 (uint32_t)ohci_hdl->ohci_cfgrom.bi_cookie.dmac_address);
2446
2447 return (DDI_SUCCESS);
2448 }
2449
2450
2451 /*
2452 * hci1394_ohci_bus_capabilities()
2453 * Return our current bus capabilities
2454 */
2455 void
hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl,uint32_t * bus_capabilities)2456 hci1394_ohci_bus_capabilities(hci1394_ohci_handle_t ohci_hdl,
2457 uint32_t *bus_capabilities)
2458 {
2459 ASSERT(ohci_hdl != NULL);
2460
2461 /*
2462 * read in the bus options register. Set bits saying that we are isoch
2463 * resource manager capable, Cycle master capable, and Isoch capable
2464 */
2465 *bus_capabilities = ddi_get32(ohci_hdl->ohci_reg_handle,
2466 &ohci_hdl->ohci_regs->bus_options) | (OHCI_BOPT_IRMC |
2467 OHCI_BOPT_CMC | OHCI_BOPT_ISC);
2468 }
2469
2470
2471 /*
2472 * hci1394_ohci_at_active()
2473 * Returns status one if either of the AT engines are active. If either AT
2474 * engine is active, we return B_TRUE. If both AT engines are not active, we
2475 * return B_FALSE.
2476 */
2477 boolean_t
hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl)2478 hci1394_ohci_at_active(hci1394_ohci_handle_t ohci_hdl)
2479 {
2480 uint32_t reg;
2481
2482
2483 ASSERT(ohci_hdl != NULL);
2484
2485 /* see if atreq active bit set */
2486 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2487 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set);
2488 if (reg & OHCI_CC_ACTIVE_MASK) {
2489 /* atreq engine is still active */
2490 return (B_TRUE);
2491 }
2492
2493 /* see if atresp active bit set */
2494 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2495 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set);
2496 if (reg & OHCI_CC_ACTIVE_MASK) {
2497 /* atresp engine is still active */
2498 return (B_TRUE);
2499 }
2500
2501 /* both atreq and atresp active bits are cleared */
2502 return (B_FALSE);
2503 }
2504
2505
2506 /*
2507 * hci1394_ohci_atreq_start()
2508 * Start the atreq dma engine. Set the address of the first descriptor
2509 * to read in equal to cmdptr.
2510 */
2511 void
hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)2512 hci1394_ohci_atreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
2513 {
2514 ASSERT(ohci_hdl != NULL);
2515
2516 ddi_put32(ohci_hdl->ohci_reg_handle,
2517 &ohci_hdl->ohci_regs->at_req.cmd_ptrlo, cmdptr);
2518 ddi_put32(ohci_hdl->ohci_reg_handle,
2519 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
2520 }
2521
2522
2523 /*
2524 * hci1394_ohci_atreq_wake()
2525 * Wake up the atreq dma engine. This should be called when a new descriptor
2526 * is added to the Q and the dma engine has already be started. It it OK to
2527 * call this when the DMA engine is active.
2528 */
2529 void
hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl)2530 hci1394_ohci_atreq_wake(hci1394_ohci_handle_t ohci_hdl)
2531 {
2532 ASSERT(ohci_hdl != NULL);
2533
2534 ddi_put32(ohci_hdl->ohci_reg_handle,
2535 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
2536 }
2537
2538
2539 /*
2540 * hci1394_ohci_atreq_stop()
2541 * Stop the atreq dma engine. No further descriptors will be read until
2542 * it dma engine is started again.
2543 */
2544 void
hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl)2545 hci1394_ohci_atreq_stop(hci1394_ohci_handle_t ohci_hdl)
2546 {
2547 ASSERT(ohci_hdl != NULL);
2548
2549 ddi_put32(ohci_hdl->ohci_reg_handle,
2550 &ohci_hdl->ohci_regs->at_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
2551 }
2552
2553
2554 /*
2555 * hci1394_ohci_arresp_start()
2556 * Start the arresp dma engine. Set the address of the first descriptor
2557 * to read in equal to cmdptr.
2558 */
2559 void
hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)2560 hci1394_ohci_arresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
2561 {
2562 ASSERT(ohci_hdl != NULL);
2563
2564 ddi_put32(ohci_hdl->ohci_reg_handle,
2565 &ohci_hdl->ohci_regs->ar_resp.cmd_ptrlo, cmdptr);
2566 ddi_put32(ohci_hdl->ohci_reg_handle,
2567 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
2568 }
2569
2570
2571 /*
2572 * hci1394_ohci_arresp_wake()
2573 * Wake up the arresp dma engine. This should be called when a new
2574 * descriptor is added to the Q and the dma engine has already be started.
2575 * It is OK to call this when the DMA engine is active.
2576 */
2577 void
hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl)2578 hci1394_ohci_arresp_wake(hci1394_ohci_handle_t ohci_hdl)
2579 {
2580 ASSERT(ohci_hdl != NULL);
2581
2582 ddi_put32(ohci_hdl->ohci_reg_handle,
2583 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
2584 }
2585
2586
2587 /*
2588 * hci1394_ohci_atreq_stop()
2589 * Stop the arresp dma engine. No further data will be received after any
2590 * current packets being received have finished.
2591 */
2592 void
hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl)2593 hci1394_ohci_arresp_stop(hci1394_ohci_handle_t ohci_hdl)
2594 {
2595 ASSERT(ohci_hdl != NULL);
2596
2597 ddi_put32(ohci_hdl->ohci_reg_handle,
2598 &ohci_hdl->ohci_regs->ar_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
2599 }
2600
2601
2602 /*
2603 * hci1394_ohci_arreq_start()
2604 * Start the arreq dma engine. Set the address of the first descriptor
2605 * to read in equal to cmdptr.
2606 */
2607 void
hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)2608 hci1394_ohci_arreq_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
2609 {
2610 ASSERT(ohci_hdl != NULL);
2611
2612 ddi_put32(ohci_hdl->ohci_reg_handle,
2613 &ohci_hdl->ohci_regs->ar_req.cmd_ptrlo, cmdptr);
2614 ddi_put32(ohci_hdl->ohci_reg_handle,
2615 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
2616 }
2617
2618
2619 /*
2620 * hci1394_ohci_arreq_wake()
2621 * Wake up the arreq dma engine. This should be called when a new descriptor
2622 * is added to the Q and the dma engine has already be started. It is OK to
2623 * call this when the DMA engine is active.
2624 */
2625 void
hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl)2626 hci1394_ohci_arreq_wake(hci1394_ohci_handle_t ohci_hdl)
2627 {
2628 ASSERT(ohci_hdl != NULL);
2629
2630 ddi_put32(ohci_hdl->ohci_reg_handle,
2631 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
2632 }
2633
2634
2635 /*
2636 * hci1394_ohci_arreq_stop()
2637 * Stop the arreq dma engine. No further data will be received after any
2638 * current packets being received have finished.
2639 */
2640 void
hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl)2641 hci1394_ohci_arreq_stop(hci1394_ohci_handle_t ohci_hdl)
2642 {
2643 ASSERT(ohci_hdl != NULL);
2644
2645 ddi_put32(ohci_hdl->ohci_reg_handle,
2646 &ohci_hdl->ohci_regs->ar_req.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
2647 }
2648
2649
2650 /*
2651 * hci1394_ohci_atresp_start()
2652 * Start the atresp dma engine. Set the address of the first descriptor
2653 * to read in equal to cmdptr.
2654 */
2655 void
hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl,uint32_t cmdptr)2656 hci1394_ohci_atresp_start(hci1394_ohci_handle_t ohci_hdl, uint32_t cmdptr)
2657 {
2658 ASSERT(ohci_hdl != NULL);
2659
2660 ddi_put32(ohci_hdl->ohci_reg_handle,
2661 &ohci_hdl->ohci_regs->at_resp.cmd_ptrlo, cmdptr);
2662 ddi_put32(ohci_hdl->ohci_reg_handle,
2663 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_RUN_MASK);
2664 }
2665
2666
2667 /*
2668 * hci1394_ohci_atresp_wake()
2669 * Wake up the atresp dma engine. This should be called when a new
2670 * descriptor is added to the Q and the dma engine has already be started.
2671 * It is OK to call this when the DMA engine is active.
2672 */
2673 void
hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl)2674 hci1394_ohci_atresp_wake(hci1394_ohci_handle_t ohci_hdl)
2675 {
2676 ASSERT(ohci_hdl != NULL);
2677
2678 ddi_put32(ohci_hdl->ohci_reg_handle,
2679 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_set, OHCI_CC_WAKE_MASK);
2680 }
2681
2682
2683 /*
2684 * hci1394_ohci_atresp_stop()
2685 * Stop the atresp dma engine. No further descriptors will be read until
2686 * it dma engine is started again.
2687 */
2688 void
hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl)2689 hci1394_ohci_atresp_stop(hci1394_ohci_handle_t ohci_hdl)
2690 {
2691 ASSERT(ohci_hdl != NULL);
2692
2693 ddi_put32(ohci_hdl->ohci_reg_handle,
2694 &ohci_hdl->ohci_regs->at_resp.ctxt_ctrl_clr, OHCI_CC_RUN_MASK);
2695 }
2696
2697
2698 /*
2699 * hci1394_ohci_1394a_init()
2700 * Initialize any 1394a features that we are using.
2701 */
2702 /* ARGSUSED */
2703 int
hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl)2704 hci1394_ohci_1394a_init(hci1394_ohci_handle_t ohci_hdl)
2705 {
2706 uint32_t reg;
2707 int status;
2708
2709 ASSERT(ohci_hdl != NULL);
2710
2711 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2712 &ohci_hdl->ohci_regs->hc_ctrl_set);
2713 if (reg & OHCI_HC_PROG_PHY_ENBL) {
2714 ddi_put32(ohci_hdl->ohci_reg_handle,
2715 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL);
2716 status = hci1394_ohci_phy_set(ohci_hdl, 5,
2717 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI));
2718 if (status != DDI_SUCCESS) {
2719 return (DDI_FAILURE);
2720 }
2721 }
2722
2723 return (DDI_SUCCESS);
2724 }
2725
2726
2727 /*
2728 * hci1394_ohci_1394a_init()
2729 * Re-initialize any 1394a features that we are using.
2730 */
2731 /* ARGSUSED */
2732 int
hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl)2733 hci1394_ohci_1394a_resume(hci1394_ohci_handle_t ohci_hdl)
2734 {
2735 uint32_t reg;
2736 int status;
2737
2738 ASSERT(ohci_hdl != NULL);
2739
2740 reg = ddi_get32(ohci_hdl->ohci_reg_handle,
2741 &ohci_hdl->ohci_regs->hc_ctrl_set);
2742 if (reg & OHCI_HC_PROG_PHY_ENBL) {
2743 ddi_put32(ohci_hdl->ohci_reg_handle,
2744 &ohci_hdl->ohci_regs->hc_ctrl_set, OHCI_HC_APHY_ENBL);
2745 status = hci1394_ohci_phy_set(ohci_hdl, 5,
2746 (OHCI_PHY_ENBL_ACCEL | OHCI_PHY_ENBL_MULTI));
2747 if (status != DDI_SUCCESS) {
2748 return (DDI_FAILURE);
2749 }
2750 }
2751
2752 return (DDI_SUCCESS);
2753 }
2754