xref: /titanic_41/usr/src/uts/common/io/1394/adapters/hci1394_csr.c (revision 7c478bd95313f5f23a4c958a745db2134aa03244)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 /*
30  * hci1394_csr.c
31  *    This code contains the code for the CSR registers handled by the HAL in
32  *    SW.  The HW implemented CSR registers are in hci1394_ohci.c
33  *
34  *   For more information on CSR registers, see
35  *	IEEE 1212
36  *	IEEE 1394-1995
37  *		section 8.3.2
38  *	IEEE P1394A Draft 3.0
39  *		sections 10.32,10.33
40  *
41  * NOTE: A read/write to a CSR SW based register will first go to the Services
42  *    Layer which will do some filtering and then come through the s1394if. Look
43  *    in hci1394_s1394if.c to see which registers are implemented in HW and
44  *    which are implemented in SW.
45  */
46 
47 #include <sys/conf.h>
48 #include <sys/ddi.h>
49 #include <sys/modctl.h>
50 #include <sys/stat.h>
51 #include <sys/sunddi.h>
52 #include <sys/cmn_err.h>
53 #include <sys/kmem.h>
54 #include <sys/types.h>
55 
56 #include <sys/1394/adapters/hci1394.h>
57 #include <sys/1394/adapters/hci1394_extern.h>
58 
59 
60 /*
61  * The split_timeout_lo register cannot be set below 800 and above 7999.  The
62  * split_timeout_hi register cannot be set above 7.
63  */
64 #define	CSR_MIN_SPLIT_TIMEOUT_LO	800
65 #define	CSR_MAX_SPLIT_TIMEOUT_LO	7999
66 #define	CSR_MAX_SPLIT_TIMEOUT_HI	7
67 
68 /*
69  * We will convert the split_timeout_lo to return the data in most significant
70  * 13 bits on the fly.
71  */
72 #define	CSR_SPLIT_TIMEOUT_LO_SHIFT	19
73 
74 /*
75  * This is what we report to the services layer as our node capabilities.
76  * See IEEE 1212_1994, section 8.4.11
77  *
78  * Split Timeout Registers are implemented (bit 15)
79  * This node uses 64-bit addressing (bit 9)
80  * This node uses fixed addressing scheme (bit 8)
81  * STATE_BITS.lost is implemented
82  * STATE_BITS.dreq is implemented
83  */
84 #define	CSR_INITIAL_NODE_CAPABILITIES	0x000083C0
85 
86 /*
87  * macro to calculate split_timeout based on split_timeout_lo and
88  * split_timeout_hi
89  */
90 #define	CSR_SPLIT_TIMEOUT(split_hi, split_lo) \
91 	((split_hi * IEEE1394_BUS_CYCLES_PER_SEC) + split_lo)
92 
93 
94 static void hci1394_csr_state_init(hci1394_csr_t *csr);
95 
96 
97 /*
98  * hci1394_csr_init()
99  *    Initialize CSR state and CSR SW based registers.
100  */
101 void
hci1394_csr_init(hci1394_drvinfo_t * drvinfo,hci1394_ohci_handle_t ohci,hci1394_csr_handle_t * csr_handle)102 hci1394_csr_init(hci1394_drvinfo_t *drvinfo, hci1394_ohci_handle_t ohci,
103     hci1394_csr_handle_t *csr_handle)
104 {
105 	hci1394_csr_t *csr;
106 
107 
108 	ASSERT(drvinfo != NULL);
109 	ASSERT(ohci != NULL);
110 	ASSERT(csr_handle != NULL);
111 	TNF_PROBE_0_DEBUG(hci1394_csr_init_enter, HCI1394_TNF_HAL_STACK, "");
112 
113 	/* alloc the space to keep track of the csr registers */
114 	csr = kmem_alloc(sizeof (hci1394_csr_t), KM_SLEEP);
115 
116 	/* setup the return parameter */
117 	*csr_handle = csr;
118 
119 	/* Initialize the csr structure */
120 	csr->csr_drvinfo = drvinfo;
121 	csr->csr_ohci = ohci;
122 	mutex_init(&csr->csr_mutex, NULL, MUTEX_DRIVER,
123 	    drvinfo->di_iblock_cookie);
124 	hci1394_csr_state_init(csr);
125 
126 	TNF_PROBE_0_DEBUG(hci1394_csr_init_exit, HCI1394_TNF_HAL_STACK, "");
127 }
128 
129 
130 /*
131  * hci1394_csr_fini()
132  *    Free up any space allocated and any mutexes used.
133  */
134 void
hci1394_csr_fini(hci1394_csr_handle_t * csr_handle)135 hci1394_csr_fini(hci1394_csr_handle_t *csr_handle)
136 {
137 	hci1394_csr_t *csr;
138 
139 
140 	ASSERT(csr_handle != NULL);
141 	TNF_PROBE_0_DEBUG(hci1394_csr_fini_enter, HCI1394_TNF_HAL_STACK, "");
142 
143 	csr = (hci1394_csr_t *)*csr_handle;
144 	mutex_destroy(&csr->csr_mutex);
145 	kmem_free(csr, sizeof (hci1394_csr_t));
146 	*csr_handle = NULL;
147 
148 	TNF_PROBE_0_DEBUG(hci1394_csr_fini_exit, HCI1394_TNF_HAL_STACK, "");
149 }
150 
151 
152 /*
153  * hci1394_csr_resume()
154  *    When resuming power on a workstation, re-setup our CSR registers.
155  */
156 void
hci1394_csr_resume(hci1394_csr_handle_t csr_handle)157 hci1394_csr_resume(hci1394_csr_handle_t csr_handle)
158 {
159 	ASSERT(csr_handle != NULL);
160 	TNF_PROBE_0_DEBUG(hci1394_csr_resume_enter, HCI1394_TNF_HAL_STACK, "");
161 	hci1394_csr_state_init(csr_handle);
162 	TNF_PROBE_0_DEBUG(hci1394_csr_resume_exit, HCI1394_TNF_HAL_STACK, "");
163 }
164 
165 
166 /*
167  * hci1394_csr_node_capabilities()
168  *    Return the CSR node capabilities.
169  */
170 void
hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle,uint32_t * capabilities)171 hci1394_csr_node_capabilities(hci1394_csr_handle_t csr_handle,
172     uint32_t *capabilities)
173 {
174 	ASSERT(csr_handle != NULL);
175 	ASSERT(capabilities != NULL);
176 	TNF_PROBE_0_DEBUG(hci1394_csr_node_capabilities_enter,
177 	    HCI1394_TNF_HAL_STACK, "");
178 
179 	mutex_enter(&csr_handle->csr_mutex);
180 	*capabilities = csr_handle->csr_capabilities;
181 	mutex_exit(&csr_handle->csr_mutex);
182 
183 	TNF_PROBE_0_DEBUG(hci1394_csr_node_capabilities_exit,
184 	    HCI1394_TNF_HAL_STACK, "");
185 }
186 
187 
188 /*
189  * hci1394_csr_state_get()
190  *    Read the CSR state register. Currently we only support the dreq, cmstr,
191  *    and abdicate bits in the CSR state register.  See the specs mentioned
192  *    above for the behavior of these bits.
193  */
194 void
hci1394_csr_state_get(hci1394_csr_handle_t csr_handle,uint32_t * state)195 hci1394_csr_state_get(hci1394_csr_handle_t csr_handle, uint32_t *state)
196 {
197 	ASSERT(csr_handle != NULL);
198 	ASSERT(state != NULL);
199 	TNF_PROBE_0_DEBUG(hci1394_csr_state_get_enter, HCI1394_TNF_HAL_STACK,
200 	    "");
201 
202 	mutex_enter(&csr_handle->csr_mutex);
203 	*state = csr_handle->csr_state;
204 	mutex_exit(&csr_handle->csr_mutex);
205 
206 	TNF_PROBE_0_DEBUG(hci1394_csr_state_get_exit, HCI1394_TNF_HAL_STACK,
207 	    "");
208 }
209 
210 
211 /*
212  * hci1394_csr_state_bset()
213  *    Perform a bit set on the CSR state register.  The value of state will be
214  *    or'd with the CSR state register. Currently we only support the dreq,
215  *    cmstr, and abdicate bits in the CSR state register.  See the specs
216  *    mentioned above for the behavior of these bits.
217  */
218 void
hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle,uint32_t state)219 hci1394_csr_state_bset(hci1394_csr_handle_t csr_handle, uint32_t state)
220 {
221 	uint32_t supported_state;
222 
223 
224 	ASSERT(csr_handle != NULL);
225 	TNF_PROBE_0_DEBUG(hci1394_csr_state_bset_enter, HCI1394_TNF_HAL_STACK,
226 	    "");
227 
228 	mutex_enter(&csr_handle->csr_mutex);
229 
230 	/* only support dreq, cmstr, and abdicate bits */
231 	supported_state = state & (IEEE1394_CSR_STATE_ABDICATE |
232 	    IEEE1394_CSR_STATE_CMSTR | IEEE1394_CSR_STATE_DREQ);
233 
234 	/*
235 	 * If we are setting the Cycle Master bit and we are the root node,
236 	 * enable Cycle Start Packets.
237 	 */
238 	if ((supported_state & IEEE1394_CSR_STATE_CMSTR) &&
239 	    (hci1394_ohci_root_check(csr_handle->csr_ohci))) {
240 		hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci);
241 	}
242 
243 	/* set the supported bits in csr_state */
244 	csr_handle->csr_state |= supported_state;
245 
246 	mutex_exit(&csr_handle->csr_mutex);
247 
248 	TNF_PROBE_0_DEBUG(hci1394_csr_state_bset_exit, HCI1394_TNF_HAL_STACK,
249 	    "");
250 }
251 
252 
253 /*
254  * hci1394_csr_state_bclr()
255  *     Perform a bit clear on the CSR state register. The inverted value of
256  *     state will be and'd with CSR state register. Currently we only support
257  *     the dreq, cmstr, and abdicate bits in the CSR state register.  See the
258  *     specs mentioned above for the behavior of these bits.
259  */
260 void
hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle,uint32_t state)261 hci1394_csr_state_bclr(hci1394_csr_handle_t csr_handle, uint32_t state)
262 {
263 	uint32_t supported_state;
264 
265 
266 	ASSERT(csr_handle != NULL);
267 	TNF_PROBE_0_DEBUG(hci1394_csr_state_bclr_enter, HCI1394_TNF_HAL_STACK,
268 	    "");
269 
270 	mutex_enter(&csr_handle->csr_mutex);
271 
272 	/* only support dreq, cmstr, and abdicate bits */
273 	supported_state = state & (IEEE1394_CSR_STATE_ABDICATE |
274 	    IEEE1394_CSR_STATE_CMSTR | IEEE1394_CSR_STATE_DREQ);
275 
276 	/*
277 	 * If we are clearing the Cycle Master bit and we are the root node,
278 	 * disable Cycle Start Packets.
279 	 */
280 	if ((supported_state & IEEE1394_CSR_STATE_CMSTR) &&
281 	    (hci1394_ohci_root_check(csr_handle->csr_ohci))) {
282 		hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci);
283 	}
284 
285 	/* Clear the supported bits in csr_state */
286 	csr_handle->csr_state &= ~state;
287 
288 	mutex_exit(&csr_handle->csr_mutex);
289 
290 	TNF_PROBE_0_DEBUG(hci1394_csr_state_bclr_exit, HCI1394_TNF_HAL_STACK,
291 	    "");
292 }
293 
294 
295 /*
296  * hci1394_csr_split_timeout_hi_get()
297  *    Read the CSR split_timeout_hi register.
298  */
299 void
hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle,uint32_t * split_timeout_hi)300 hci1394_csr_split_timeout_hi_get(hci1394_csr_handle_t csr_handle,
301     uint32_t *split_timeout_hi)
302 {
303 	ASSERT(csr_handle != NULL);
304 	ASSERT(split_timeout_hi != NULL);
305 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_hi_get_enter,
306 	    HCI1394_TNF_HAL_STACK, "");
307 
308 	mutex_enter(&csr_handle->csr_mutex);
309 	*split_timeout_hi = csr_handle->csr_split_timeout_hi;
310 	mutex_exit(&csr_handle->csr_mutex);
311 
312 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_hi_get_exit,
313 	    HCI1394_TNF_HAL_STACK, "");
314 
315 }
316 
317 
318 /*
319  * hci1394_csr_split_timeout_lo_get()
320  *    Read the CSR split_timeout_lo register.
321  */
322 void
hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle,uint32_t * split_timeout_lo)323 hci1394_csr_split_timeout_lo_get(hci1394_csr_handle_t csr_handle,
324     uint32_t *split_timeout_lo)
325 {
326 	ASSERT(csr_handle != NULL);
327 	ASSERT(split_timeout_lo != NULL);
328 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_lo_get_enter,
329 	    HCI1394_TNF_HAL_STACK, "");
330 
331 	mutex_enter(&csr_handle->csr_mutex);
332 
333 	/*
334 	 * Read the split_timeout_lo CSR register. Convert split_timeout_lo to
335 	 * use the data in most significant 13 bits on the fly.
336 	 */
337 	*split_timeout_lo = csr_handle->csr_split_timeout_lo <<
338 	    CSR_SPLIT_TIMEOUT_LO_SHIFT;
339 
340 	mutex_exit(&csr_handle->csr_mutex);
341 
342 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_lo_get_exit,
343 	    HCI1394_TNF_HAL_STACK, "");
344 
345 }
346 
347 
348 /*
349  * hci1394_csr_split_timeout_hi_set()
350  *    Write the CSR split_timeout_hi register. This routine will also
351  *    re-calculate the "split_timeout" which is used internally in the HAL
352  *    driver. The only accesses to split_timeout_hi and split_timeout_lo
353  *    should be over the 1394 bus. Only the least significant 3 bits are
354  *    relevant in the split_timeout_hi register.
355  */
356 void
hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle,uint32_t split_timeout_hi)357 hci1394_csr_split_timeout_hi_set(hci1394_csr_handle_t csr_handle,
358     uint32_t split_timeout_hi)
359 {
360 	ASSERT(csr_handle != NULL);
361 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_hi_set_enter,
362 	    HCI1394_TNF_HAL_STACK, "");
363 
364 	mutex_enter(&csr_handle->csr_mutex);
365 
366 	/*
367 	 * update the split_timeout_hi CSR register. Only look at the 3 LSBits.
368 	 * Update our internal split_timeout value.
369 	 */
370 	csr_handle->csr_split_timeout_hi = split_timeout_hi &
371 	    CSR_MAX_SPLIT_TIMEOUT_HI;
372 	csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT(
373 	    csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo);
374 
375 	mutex_exit(&csr_handle->csr_mutex);
376 
377 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_hi_set_exit,
378 	    HCI1394_TNF_HAL_STACK, "");
379 }
380 
381 
382 /*
383  * hci1394_csr_split_timeout_lo_set()
384  *    Write the CSR split_timeout_lo register. This routine will also
385  *    re-calculate the "split_timeout" which is used internally in the HAL
386  *    driver. The only accesses to split_timeout_hi and split_timeout_lo
387  *    should be over the 1394 bus. Only the most significant 13 bits are
388  *    relevant in the split_timeout_lo register.
389  */
390 void
hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle,uint32_t split_timeout_lo)391 hci1394_csr_split_timeout_lo_set(hci1394_csr_handle_t csr_handle,
392     uint32_t split_timeout_lo)
393 {
394 	ASSERT(csr_handle != NULL);
395 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_lo_set_enter,
396 	    HCI1394_TNF_HAL_STACK, "");
397 
398 	mutex_enter(&csr_handle->csr_mutex);
399 
400 	/*
401 	 * Update the split_timeout_lo CSR register.  Only look at the 3 LSBits.
402 	 * Convert the split_timeout_lo to use the data in most significant 13
403 	 * bits on the fly.
404 	 */
405 	csr_handle->csr_split_timeout_lo = split_timeout_lo >>
406 	    CSR_SPLIT_TIMEOUT_LO_SHIFT;
407 
408 	/* threshold the split_timeout_lo value */
409 	if (csr_handle->csr_split_timeout_lo < CSR_MIN_SPLIT_TIMEOUT_LO) {
410 		csr_handle->csr_split_timeout_lo = CSR_MIN_SPLIT_TIMEOUT_LO;
411 	} else if (csr_handle->csr_split_timeout_lo >
412 	    CSR_MAX_SPLIT_TIMEOUT_LO) {
413 		csr_handle->csr_split_timeout_lo = CSR_MAX_SPLIT_TIMEOUT_LO;
414 	}
415 
416 	/* Update our internal split_timeout value */
417 	csr_handle->csr_split_timeout = CSR_SPLIT_TIMEOUT(
418 	    csr_handle->csr_split_timeout_hi, csr_handle->csr_split_timeout_lo);
419 
420 	mutex_exit(&csr_handle->csr_mutex);
421 
422 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_lo_set_exit,
423 	    HCI1394_TNF_HAL_STACK, "");
424 }
425 
426 
427 /*
428  * hci1394_csr_split_timeout_get()
429  *    Return the current value of split_timeout.  This is the  only routine
430  *    which should be used to get the split timeout for use in a calculation
431  *    (e.g. for calculating ACK pending timeout).
432  */
433 uint_t
hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle)434 hci1394_csr_split_timeout_get(hci1394_csr_handle_t csr_handle)
435 {
436 	uint_t split_timeout;
437 
438 
439 	ASSERT(csr_handle != NULL);
440 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_get_enter,
441 	    HCI1394_TNF_HAL_STACK, "");
442 
443 	mutex_enter(&csr_handle->csr_mutex);
444 
445 	/* read our internal split_timeout value */
446 	split_timeout = csr_handle->csr_split_timeout;
447 
448 	mutex_exit(&csr_handle->csr_mutex);
449 
450 	TNF_PROBE_0_DEBUG(hci1394_csr_split_timeout_get_exit,
451 	    HCI1394_TNF_HAL_STACK, "");
452 
453 	return (split_timeout);
454 }
455 
456 
457 /*
458  * hci1394_csr_bus_reset()
459  *    Perform required bus reset processing on CSR registers. This includes
460  *    clearing the abdicate bit, and setting/clearing the Cycle Master bit.
461  *    See sections 10.32 and 10.33 in the IEEE P1394A Draft 3.0 spec.  See
462  *    section 8.3.2.2.1 in the IEEE 1394-1995 spec. This routine should be
463  *    called every bus reset.
464  */
465 void
hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle)466 hci1394_csr_bus_reset(hci1394_csr_handle_t csr_handle)
467 {
468 	ASSERT(csr_handle != NULL);
469 	TNF_PROBE_0_DEBUG(hci1394_csr_bus_reset_enter, HCI1394_TNF_HAL_STACK,
470 	    "");
471 
472 	mutex_enter(&csr_handle->csr_mutex);
473 
474 	/* Clear the abdicate bit.  Always do this. */
475 	csr_handle->csr_state &= ~IEEE1394_CSR_STATE_ABDICATE;
476 
477 	/* if we are NOT currently the root node on the bus */
478 	if (hci1394_ohci_root_check(csr_handle->csr_ohci) == B_FALSE) {
479 		/*
480 		 * Set the was_root state.  This is needed for the Cycle Master
481 		 * state machine below.
482 		 */
483 		csr_handle->csr_was_root = B_FALSE;
484 
485 		/*
486 		 * Clear the Cycle Master bit.  We do not have to shut off cycle
487 		 * master in OpenHCI.  The HW will automatically stop generating
488 		 * Cycle Start packets when it is not the root node.
489 		 */
490 		csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR;
491 
492 	/*
493 	 * if we are currently the root node on the bus and we were NOT
494 	 * the root before the reset.
495 	 */
496 	} else if (csr_handle->csr_was_root == B_FALSE) {
497 
498 		/* set the was_root state to TRUE */
499 		csr_handle->csr_was_root = B_TRUE;
500 
501 		/*
502 		 * if we are cycle master capable, set the Cycle Master bit and
503 		 * start Cycle Start packets. We should always be Cycle Master
504 		 * capable.
505 		 */
506 		if (hci1394_ohci_cmc_check(csr_handle->csr_ohci)) {
507 			csr_handle->csr_state |= IEEE1394_CSR_STATE_CMSTR;
508 			hci1394_ohci_cycle_master_enable(csr_handle->csr_ohci);
509 
510 		/*
511 		 * if we are NOT cycle master capable, clear the Cycle Master
512 		 * bit and stop Cycle Start packets. We should never see this
513 		 * in OpenHCI. I think? :-)
514 		 */
515 		} else {
516 			csr_handle->csr_state &= ~IEEE1394_CSR_STATE_CMSTR;
517 			hci1394_ohci_cycle_master_disable(csr_handle->csr_ohci);
518 		}
519 	}
520 	/*
521 	 * else {}
522 	 * else we are root now. We were root before, keep cmstr the same.
523 	 * Nothing to do.
524 	 */
525 
526 	mutex_exit(&csr_handle->csr_mutex);
527 
528 	TNF_PROBE_0_DEBUG(hci1394_csr_bus_reset_exit, HCI1394_TNF_HAL_STACK,
529 	    "");
530 }
531 
532 
533 /*
534  * hci1394_csr_state_init()
535  *    set the CSR SW registers and state variables to their initial settings.
536  */
hci1394_csr_state_init(hci1394_csr_t * csr)537 static void hci1394_csr_state_init(hci1394_csr_t *csr)
538 {
539 	ASSERT(csr != NULL);
540 	TNF_PROBE_0_DEBUG(hci1394_csr_state_init_enter, HCI1394_TNF_HAL_STACK,
541 	    "");
542 
543 	mutex_enter(&csr->csr_mutex);
544 
545 	/*
546 	 * Initialize the split timeout to be 0 seconds (split_timeout_hi) and
547 	 * use a patchable variable for the initial split_timeout_lo. This
548 	 * variable must be patched before the driver attaches.  It is never
549 	 * looked at again after this code is run.
550 	 *
551 	 * Calculate the split_timeout which we will use in the driver based on
552 	 * split_timeout_lo and split_timeout_hi.
553 	 */
554 	csr->csr_split_timeout_hi = 0;
555 	csr->csr_split_timeout_lo = hci1394_split_timeout;
556 	csr->csr_split_timeout = CSR_SPLIT_TIMEOUT(
557 	    csr->csr_split_timeout_hi, csr->csr_split_timeout_lo);
558 
559 	/* Set the initial CSR State register to 0 */
560 	csr->csr_state = 0;
561 
562 	/*
563 	 * was_root is an internal state variable which tracks if we were root
564 	 * last bus reset.  This is needed for the required state register bus
565 	 * reset processing.
566 	 */
567 	csr->csr_was_root = B_FALSE;
568 
569 	/* setup our initial capabilities setting */
570 	csr->csr_capabilities = CSR_INITIAL_NODE_CAPABILITIES;
571 
572 	mutex_exit(&csr->csr_mutex);
573 
574 	TNF_PROBE_0_DEBUG(hci1394_csr_state_init_exit, HCI1394_TNF_HAL_STACK,
575 	    "");
576 }
577