1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_DEVICE_TYPES_H_ 7 #define _XE_DEVICE_TYPES_H_ 8 9 #include <linux/pci.h> 10 11 #include <drm/drm_device.h> 12 #include <drm/drm_file.h> 13 #include <drm/ttm/ttm_device.h> 14 15 #include "xe_devcoredump_types.h" 16 #include "xe_drm_ras_types.h" 17 #include "xe_heci_gsc.h" 18 #include "xe_late_bind_fw_types.h" 19 #include "xe_oa_types.h" 20 #include "xe_pagefault_types.h" 21 #include "xe_platform_types.h" 22 #include "xe_pmu_types.h" 23 #include "xe_pt_types.h" 24 #include "xe_sriov_pf_types.h" 25 #include "xe_sriov_types.h" 26 #include "xe_sriov_vf_types.h" 27 #include "xe_sriov_vf_ccs_types.h" 28 #include "xe_step_types.h" 29 #include "xe_survivability_mode_types.h" 30 #include "xe_sysctrl_types.h" 31 #include "xe_tile_types.h" 32 #include "xe_validation.h" 33 34 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 35 #define TEST_VM_OPS_ERROR 36 #endif 37 38 struct drm_pagemap_shrinker; 39 struct intel_display; 40 struct intel_dg_nvm_dev; 41 struct xe_ggtt; 42 struct xe_i2c; 43 struct xe_pat_ops; 44 struct xe_pxp; 45 struct xe_ttm_stolen_mgr; 46 struct xe_vram_region; 47 48 /** 49 * enum xe_wedged_mode - possible wedged modes 50 * @XE_WEDGED_MODE_NEVER: Device will never be declared wedged. 51 * @XE_WEDGED_MODE_UPON_CRITICAL_ERROR: Device will be declared wedged only 52 * when critical error occurs like GT reset failure or firmware failure. 53 * This is the default mode. 54 * @XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET: Device will be declared wedged on 55 * any hang. In this mode, engine resets are disabled to avoid automatic 56 * recovery attempts. This mode is primarily intended for debugging hangs. 57 */ 58 enum xe_wedged_mode { 59 XE_WEDGED_MODE_NEVER = 0, 60 XE_WEDGED_MODE_UPON_CRITICAL_ERROR = 1, 61 XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET = 2, 62 }; 63 64 #define XE_BO_INVALID_OFFSET LONG_MAX 65 66 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100) 67 #define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100) 68 #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100) 69 #define MEDIA_VERx100(xe) ((xe)->info.media_verx100) 70 #define IS_DGFX(xe) ((xe)->info.is_dgfx) 71 72 #define XE_VRAM_FLAGS_NEED64K BIT(0) 73 74 #define XE_GT0 0 75 #define XE_GT1 1 76 #define XE_MAX_TILES_PER_DEVICE (XE_GT1 + 1) 77 78 /* 79 * Highest GT/tile count for any platform. Used only for memory allocation 80 * sizing. Any logic looping over GTs or mapping userspace GT IDs into GT 81 * structures should use the per-platform xe->info.max_gt_per_tile instead. 82 */ 83 #define XE_MAX_GT_PER_TILE 2 84 85 #define XE_MAX_ASID (BIT(20)) 86 87 /** 88 * struct xe_device - Top level struct of Xe device 89 */ 90 struct xe_device { 91 /** @drm: drm device */ 92 struct drm_device drm; 93 94 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 95 /** @display: display device data, must be placed after drm device member */ 96 struct intel_display *display; 97 #endif 98 99 /** @devcoredump: device coredump */ 100 struct xe_devcoredump devcoredump; 101 102 /** @info: device info */ 103 struct intel_device_info { 104 /** @info.platform_name: platform name */ 105 const char *platform_name; 106 /** @info.graphics_name: graphics IP name */ 107 const char *graphics_name; 108 /** @info.media_name: media IP name */ 109 const char *media_name; 110 /** @info.graphics_verx100: graphics IP version */ 111 u32 graphics_verx100; 112 /** @info.media_verx100: media IP version */ 113 u32 media_verx100; 114 /** @info.mem_region_mask: mask of valid memory regions */ 115 u32 mem_region_mask; 116 /** @info.platform: Xe platform enum */ 117 enum xe_platform platform; 118 /** @info.subplatform: Xe subplatform enum */ 119 enum xe_subplatform subplatform; 120 /** @info.devid: device ID */ 121 u16 devid; 122 /** @info.revid: device revision */ 123 u8 revid; 124 /** @info.step: stepping information for each IP */ 125 struct xe_step_info step; 126 /** @info.dma_mask_size: DMA address bits */ 127 u8 dma_mask_size; 128 /** @info.vram_flags: Vram flags */ 129 u8 vram_flags; 130 /** @info.tile_count: Number of tiles */ 131 u8 tile_count; 132 /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */ 133 u8 max_gt_per_tile; 134 /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */ 135 u8 multi_lrc_mask; 136 /** @info.gt_count: Total number of GTs for entire device */ 137 u8 gt_count; 138 /** @info.vm_max_level: Max VM level */ 139 u8 vm_max_level; 140 /** @info.va_bits: Maximum bits of a virtual address */ 141 u8 va_bits; 142 143 /* 144 * Keep all flags below alphabetically sorted 145 */ 146 147 /** @info.force_execlist: Forced execlist submission */ 148 u8 force_execlist:1; 149 /** @info.has_access_counter: Device supports access counter */ 150 u8 has_access_counter:1; 151 /** @info.has_asid: Has address space ID */ 152 u8 has_asid:1; 153 /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ 154 u8 has_atomic_enable_pte_bit:1; 155 /** @info.has_cached_pt: Supports caching pagetable */ 156 u8 has_cached_pt:1; 157 /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ 158 u8 has_device_atomics_on_smem:1; 159 /** @info.has_fan_control: Device supports fan control */ 160 u8 has_fan_control:1; 161 /** @info.has_flat_ccs: Whether flat CCS metadata is used */ 162 u8 has_flat_ccs:1; 163 /** @info.has_gsc_nvm: Device has gsc non-volatile memory */ 164 u8 has_gsc_nvm:1; 165 /** @info.has_heci_cscfi: device has heci cscfi */ 166 u8 has_heci_cscfi:1; 167 /** @info.has_heci_gscfi: device has heci gscfi */ 168 u8 has_heci_gscfi:1; 169 /** @info.has_i2c: Device has I2C controller */ 170 u8 has_i2c:1; 171 /** @info.has_late_bind: Device has firmware late binding support */ 172 u8 has_late_bind:1; 173 /** @info.has_llc: Device has a shared CPU+GPU last level cache */ 174 u8 has_llc:1; 175 /** @info.has_mbx_power_limits: Device has support to manage power limits using 176 * pcode mailbox commands. 177 */ 178 u8 has_mbx_power_limits:1; 179 /** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */ 180 u8 has_mbx_thermal_info:1; 181 /** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */ 182 u8 has_mem_copy_instr:1; 183 /** @info.has_mert: Device has standalone MERT */ 184 u8 has_mert:1; 185 /** @info.has_page_reclaim_hw_assist: Device supports page reclamation feature */ 186 u8 has_page_reclaim_hw_assist:1; 187 /** @info.has_pre_prod_wa: Pre-production workarounds still present in driver */ 188 u8 has_pre_prod_wa:1; 189 /** @info.has_pxp: Device has PXP support */ 190 u8 has_pxp:1; 191 /** @info.has_ctx_tlb_inval: Has context based TLB invalidations */ 192 u8 has_ctx_tlb_inval:1; 193 /** @info.has_range_tlb_inval: Has range based TLB invalidations */ 194 u8 has_range_tlb_inval:1; 195 /** @info.has_soc_remapper_sysctrl: Has SoC remapper system controller */ 196 u8 has_soc_remapper_sysctrl:1; 197 /** @info.has_soc_remapper_telem: Has SoC remapper telemetry support */ 198 u8 has_soc_remapper_telem:1; 199 /** @info.has_sriov: Supports SR-IOV */ 200 u8 has_sriov:1; 201 /** @info.has_sysctrl: Supports System Controller */ 202 u8 has_sysctrl:1; 203 /** @info.has_usm: Device has unified shared memory support */ 204 u8 has_usm:1; 205 /** @info.has_64bit_timestamp: Device supports 64-bit timestamps */ 206 u8 has_64bit_timestamp:1; 207 /** @info.is_dgfx: is discrete device */ 208 u8 is_dgfx:1; 209 /** @info.needs_scratch: needs scratch page for oob prefetch to work */ 210 u8 needs_scratch:1; 211 /** 212 * @info.probe_display: Probe display hardware. If set to 213 * false, the driver will behave as if there is no display 214 * hardware present and will not try to read/write to it in any 215 * way. The display hardware, if it exists, will not be 216 * exposed to userspace and will be left untouched in whatever 217 * state the firmware or bootloader left it in. 218 */ 219 u8 probe_display:1; 220 /** @info.skip_guc_pc: Skip GuC based PM feature init */ 221 u8 skip_guc_pc:1; 222 /** @info.skip_pcode: skip access to PCODE uC */ 223 u8 skip_pcode:1; 224 /** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */ 225 u8 needs_shared_vf_gt_wq:1; 226 } info; 227 228 /** @wa_active: keep track of active workarounds */ 229 struct { 230 /** @wa_active.oob: bitmap with active OOB workarounds */ 231 unsigned long *oob; 232 233 /** 234 * @wa_active.oob_initialized: Mark oob as initialized to help detecting misuse 235 * of XE_DEVICE_WA() - it can only be called on initialization after 236 * Device OOB WAs have been processed. 237 */ 238 bool oob_initialized; 239 } wa_active; 240 241 /** @survivability: survivability information for device */ 242 struct xe_survivability survivability; 243 244 /** @irq: device interrupt state */ 245 struct { 246 /** @irq.lock: lock for processing irq's on this device */ 247 spinlock_t lock; 248 249 /** @irq.enabled: interrupts enabled on this device */ 250 atomic_t enabled; 251 252 /** @irq.msix: irq info for platforms that support MSI-X */ 253 struct { 254 /** @irq.msix.nvec: number of MSI-X interrupts */ 255 u16 nvec; 256 /** @irq.msix.indexes: used to allocate MSI-X indexes */ 257 struct xarray indexes; 258 } msix; 259 } irq; 260 261 /** @ttm: ttm device */ 262 struct ttm_device ttm; 263 264 /** @mmio: mmio info for device */ 265 struct { 266 /** @mmio.size: size of MMIO space for device */ 267 size_t size; 268 /** @mmio.regs: pointer to MMIO space for device */ 269 void __iomem *regs; 270 } mmio; 271 272 /** @mem: memory info for device */ 273 struct { 274 /** @mem.vram: VRAM info for device */ 275 struct xe_vram_region *vram; 276 /** @mem.sys_mgr: system TTM manager */ 277 struct ttm_resource_manager sys_mgr; 278 /** @mem.shrinker: system memory shrinker. */ 279 struct xe_shrinker *shrinker; 280 /** @mem.stolen_mgr: stolen memory manager. */ 281 struct xe_ttm_stolen_mgr *stolen_mgr; 282 } mem; 283 284 /** @sriov: device level virtualization data */ 285 struct { 286 /** @sriov.__mode: SR-IOV mode (Don't access directly!) */ 287 enum xe_sriov_mode __mode; 288 289 union { 290 /** @sriov.pf: PF specific data */ 291 struct xe_device_pf pf; 292 /** @sriov.vf: VF specific data */ 293 struct xe_device_vf vf; 294 }; 295 296 /** @sriov.wq: workqueue used by the virtualization workers */ 297 struct workqueue_struct *wq; 298 } sriov; 299 300 /** @usm: unified memory state */ 301 struct { 302 /** @usm.asid_to_vm: convert an ASID to VM */ 303 struct xarray asid_to_vm; 304 /** @usm.next_asid: next ASID, used to cyclical alloc asids */ 305 u32 next_asid; 306 /** @usm.lock: protects UM state */ 307 struct rw_semaphore lock; 308 /** @usm.pf_wq: page fault work queue, unbound, high priority */ 309 struct workqueue_struct *pf_wq; 310 /* 311 * We pick 4 here because, in the current implementation, it 312 * yields the best bandwidth utilization of the kernel paging 313 * engine. 314 */ 315 #define XE_PAGEFAULT_QUEUE_COUNT 4 316 /** @usm.pf_queue: Page fault queues */ 317 struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT]; 318 #if IS_ENABLED(CONFIG_DRM_XE_PAGEMAP) 319 /** @usm.dpagemap_shrinker: Shrinker for unused pagemaps */ 320 struct drm_pagemap_shrinker *dpagemap_shrinker; 321 #endif 322 } usm; 323 324 /** @pinned: pinned BO state */ 325 struct { 326 /** @pinned.lock: protected pinned BO list state */ 327 spinlock_t lock; 328 /** @pinned.early: early pinned lists */ 329 struct { 330 /** @pinned.early.kernel_bo_present: pinned kernel BO that are present */ 331 struct list_head kernel_bo_present; 332 /** @pinned.early.evicted: pinned BO that have been evicted */ 333 struct list_head evicted; 334 } early; 335 /** @pinned.late: late pinned lists */ 336 struct { 337 /** @pinned.late.kernel_bo_present: pinned kernel BO that are present */ 338 struct list_head kernel_bo_present; 339 /** @pinned.late.evicted: pinned BO that have been evicted */ 340 struct list_head evicted; 341 /** @pinned.late.external: pinned external and dma-buf. */ 342 struct list_head external; 343 } late; 344 } pinned; 345 346 /** @ufence_wq: user fence wait queue */ 347 wait_queue_head_t ufence_wq; 348 349 /** @preempt_fence_wq: used to serialize preempt fences */ 350 struct workqueue_struct *preempt_fence_wq; 351 352 /** @ordered_wq: used to serialize compute mode resume */ 353 struct workqueue_struct *ordered_wq; 354 355 /** @unordered_wq: used to serialize unordered work */ 356 struct workqueue_struct *unordered_wq; 357 358 /** @destroy_wq: used to serialize SVM pagemap destroy work */ 359 struct workqueue_struct *destroy_wq; 360 361 /** @tiles: device tiles */ 362 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; 363 364 /** 365 * @mem_access: keep track of memory access in the device, possibly 366 * triggering additional actions when they occur. 367 */ 368 struct { 369 /** 370 * @mem_access.vram_userfault: Encapsulate vram_userfault 371 * related stuff 372 */ 373 struct { 374 /** 375 * @mem_access.vram_userfault.lock: Protects access to 376 * @mem_access.vram_userfault.list Using mutex instead of spinlock 377 * as lock is applied to entire list operation which 378 * may sleep 379 */ 380 struct mutex lock; 381 382 /** 383 * @mem_access.vram_userfault.list: Keep list of userfaulted 384 * vram bo, which require to release their mmap mappings 385 * at runtime suspend path 386 */ 387 struct list_head list; 388 } vram_userfault; 389 } mem_access; 390 391 /** 392 * @pat: Encapsulate PAT related stuff 393 */ 394 struct { 395 /** @pat.ops: Internal operations to abstract platforms */ 396 const struct xe_pat_ops *ops; 397 /** @pat.table: PAT table to program in the HW */ 398 const struct xe_pat_table_entry *table; 399 /** @pat.n_entries: Number of PAT entries */ 400 int n_entries; 401 /** @pat.pat_ats: PAT entry for PCIe ATS responses */ 402 const struct xe_pat_table_entry *pat_ats; 403 /** @pat.pat_primary_pta: primary GT PAT entry for page table accesses */ 404 const struct xe_pat_table_entry *pat_primary_pta; 405 /** @pat.pat_media_pta: media GT PAT entry for page table accesses */ 406 const struct xe_pat_table_entry *pat_media_pta; 407 u16 idx[__XE_CACHE_LEVEL_COUNT]; 408 } pat; 409 410 /** @d3cold: Encapsulate d3cold related stuff */ 411 struct { 412 /** @d3cold.capable: Indicates if root port is d3cold capable */ 413 bool capable; 414 415 /** @d3cold.allowed: Indicates if d3cold is a valid device state */ 416 bool allowed; 417 418 /** 419 * @d3cold.vram_threshold: 420 * 421 * This represents the permissible threshold(in megabytes) 422 * for vram save/restore. d3cold will be disallowed, 423 * when vram_usages is above or equals the threshold value 424 * to avoid the vram save/restore latency. 425 * Default threshold value is 300mb. 426 */ 427 u32 vram_threshold; 428 /** @d3cold.lock: protect vram_threshold */ 429 struct mutex lock; 430 } d3cold; 431 432 /** @pm_notifier: Our PM notifier to perform actions in response to various PM events. */ 433 struct notifier_block pm_notifier; 434 /** @pm_block: Completion to block validating tasks on suspend / hibernate prepare */ 435 struct completion pm_block; 436 /** @rebind_resume_list: List of wq items to kick on resume. */ 437 struct list_head rebind_resume_list; 438 /** @rebind_resume_lock: Lock to protect the rebind_resume_list */ 439 struct mutex rebind_resume_lock; 440 441 /** @pmt: Support the PMT driver callback interface */ 442 struct { 443 /** @pmt.lock: protect access for telemetry data */ 444 struct mutex lock; 445 } pmt; 446 447 /** @soc_remapper: SoC remapper object */ 448 struct { 449 /** @soc_remapper.lock: Serialize access to SoC Remapper's index registers */ 450 spinlock_t lock; 451 452 /** @soc_remapper.set_telem_region: Set telemetry index */ 453 void (*set_telem_region)(struct xe_device *xe, u32 index); 454 455 /** @soc_remapper.set_sysctrl_region: Set system controller index */ 456 void (*set_sysctrl_region)(struct xe_device *xe, u32 index); 457 } soc_remapper; 458 459 /** 460 * @pm_callback_task: Track the active task that is running in either 461 * the runtime_suspend or runtime_resume callbacks. 462 */ 463 struct task_struct *pm_callback_task; 464 465 /** @hwmon: hwmon subsystem integration */ 466 struct xe_hwmon *hwmon; 467 468 /** @heci_gsc: graphics security controller */ 469 struct xe_heci_gsc heci_gsc; 470 471 /** @nvm: discrete graphics non-volatile memory */ 472 struct intel_dg_nvm_dev *nvm; 473 474 /** @late_bind: xe mei late bind interface */ 475 struct xe_late_bind late_bind; 476 477 /** @oa: oa observation subsystem */ 478 struct xe_oa oa; 479 480 /** @pxp: Encapsulate Protected Xe Path support */ 481 struct xe_pxp *pxp; 482 483 /** @needs_flr_on_fini: requests function-reset on fini */ 484 bool needs_flr_on_fini; 485 486 /** @wedged: Struct to control Wedged States and mode */ 487 struct { 488 /** @wedged.flag: Xe device faced a critical error and is now blocked. */ 489 atomic_t flag; 490 /** @wedged.mode: Mode controlled by kernel parameter and debugfs */ 491 enum xe_wedged_mode mode; 492 /** @wedged.method: Recovery method to be sent in the drm device wedged uevent */ 493 unsigned long method; 494 /** @wedged.inconsistent_reset: Inconsistent reset policy state between GTs */ 495 bool inconsistent_reset; 496 } wedged; 497 498 /** @bo_device: Struct to control async free of BOs */ 499 struct xe_bo_dev { 500 /** @bo_device.async_free: Free worker */ 501 struct work_struct async_free; 502 /** @bo_device.async_list: List of BOs to be freed */ 503 struct llist_head async_list; 504 } bo_device; 505 506 /** @pmu: performance monitoring unit */ 507 struct xe_pmu pmu; 508 509 /** @ras: RAS structure for device */ 510 struct xe_drm_ras ras; 511 512 /** @i2c: I2C host controller */ 513 struct xe_i2c *i2c; 514 515 /** @sc: System Controller */ 516 struct xe_sysctrl sc; 517 518 /** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */ 519 u32 atomic_svm_timeslice_ms; 520 521 /** @min_run_period_lr_ms: LR VM (preempt fence mode) timeslice */ 522 u32 min_run_period_lr_ms; 523 524 /** @min_run_period_pf_ms: LR VM (page fault mode) timeslice */ 525 u32 min_run_period_pf_ms; 526 527 #ifdef TEST_VM_OPS_ERROR 528 /** 529 * @vm_inject_error_position: inject errors at different places in VM 530 * bind IOCTL based on this value 531 */ 532 u8 vm_inject_error_position; 533 #endif 534 535 #if IS_ENABLED(CONFIG_TRACE_GPU_MEM) 536 /** 537 * @global_total_pages: global GPU page usage tracked for gpu_mem 538 * tracepoints 539 */ 540 atomic64_t global_total_pages; 541 #endif 542 /** @val: The domain for exhaustive eviction, which is currently per device. */ 543 struct xe_validation_device val; 544 545 /** @psmi: GPU debugging via additional validation HW */ 546 struct { 547 /** @psmi.capture_obj: PSMI buffer for VRAM */ 548 struct xe_bo *capture_obj[XE_MAX_TILES_PER_DEVICE + 1]; 549 /** @psmi.region_mask: Mask of valid memory regions */ 550 u8 region_mask; 551 } psmi; 552 553 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 554 /** @g2g_test_array: for testing G2G communications */ 555 u32 *g2g_test_array; 556 /** @g2g_test_count: for testing G2G communications */ 557 atomic_t g2g_test_count; 558 #endif 559 560 /* private: */ 561 562 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 563 /* 564 * Any fields below this point are the ones used by display. 565 * They are temporarily added here so xe_device can be desguised as 566 * drm_i915_private during build. After cleanup these should go away, 567 * migrating to the right sub-structs 568 */ 569 570 struct intel_uncore { 571 spinlock_t lock; 572 } uncore; 573 #endif 574 }; 575 576 /** 577 * struct xe_file - file handle for Xe driver 578 */ 579 struct xe_file { 580 /** @xe: xe DEVICE **/ 581 struct xe_device *xe; 582 583 /** @drm: base DRM file */ 584 struct drm_file *drm; 585 586 /** @vm: VM state for file */ 587 struct { 588 /** @vm.xa: xarray to store VMs */ 589 struct xarray xa; 590 /** 591 * @vm.lock: Protects VM lookup + reference and removal from 592 * file xarray. Not an intended to be an outer lock which does 593 * thing while being held. 594 */ 595 struct mutex lock; 596 } vm; 597 598 /** @exec_queue: Submission exec queue state for file */ 599 struct { 600 /** @exec_queue.xa: xarray to store exece queues */ 601 struct xarray xa; 602 /** 603 * @exec_queue.lock: Protects exec queue lookup + reference and 604 * removal from file xarray. Not intended to be an outer lock 605 * which does things while being held. 606 */ 607 struct mutex lock; 608 /** 609 * @exec_queue.pending_removal: items pending to be removed to 610 * synchronize GPU state update with ongoing query. 611 */ 612 atomic_t pending_removal; 613 } exec_queue; 614 615 /** @run_ticks: hw engine class run time in ticks for this drm client */ 616 u64 run_ticks[XE_ENGINE_CLASS_MAX]; 617 618 /** @client: drm client */ 619 struct xe_drm_client *client; 620 621 /** 622 * @process_name: process name for file handle, used to safely output 623 * during error situations where xe file can outlive process 624 */ 625 char *process_name; 626 627 /** 628 * @pid: pid for file handle, used to safely output uring error 629 * situations where xe file can outlive process 630 */ 631 pid_t pid; 632 633 /** @refcount: ref count of this xe file */ 634 struct kref refcount; 635 }; 636 637 #endif 638