1 //===--- AMDGPU.h - Declare AMDGPU target feature support -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares AMDGPU TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H 15 16 #include "clang/Basic/TargetID.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/StringSet.h" 20 #include "llvm/Support/AMDGPUAddrSpace.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/TargetParser/TargetParser.h" 23 #include "llvm/TargetParser/Triple.h" 24 #include <optional> 25 26 namespace clang { 27 namespace targets { 28 29 class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo { 30 31 static const char *const GCCRegNames[]; 32 33 static const LangASMap AMDGPUDefIsGenMap; 34 static const LangASMap AMDGPUDefIsPrivMap; 35 36 llvm::AMDGPU::GPUKind GPUKind; 37 unsigned GPUFeatures; 38 unsigned WavefrontSize; 39 40 /// Whether to use cumode or WGP mode. True for cumode. False for WGP mode. 41 bool CUMode; 42 43 /// Whether having image instructions. 44 bool HasImage = false; 45 46 /// Target ID is device name followed by optional feature name postfixed 47 /// by plus or minus sign delimitted by colon, e.g. gfx908:xnack+:sramecc-. 48 /// If the target ID contains feature+, map it to true. 49 /// If the target ID contains feature-, map it to false. 50 /// If the target ID does not contain a feature (default), do not map it. 51 llvm::StringMap<bool> OffloadArchFeatures; 52 std::string TargetID; 53 hasFP64()54 bool hasFP64() const { 55 return getTriple().isAMDGCN() || 56 !!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64); 57 } 58 59 /// Has fast fma f32 hasFastFMAF()60 bool hasFastFMAF() const { 61 return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_FMA_F32); 62 } 63 64 /// Has fast fma f64 hasFastFMA()65 bool hasFastFMA() const { return getTriple().isAMDGCN(); } 66 hasFMAF()67 bool hasFMAF() const { 68 return getTriple().isAMDGCN() || 69 !!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA); 70 } 71 hasFullRateDenormalsF32()72 bool hasFullRateDenormalsF32() const { 73 return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_DENORMAL_F32); 74 } 75 hasLDEXPF()76 bool hasLDEXPF() const { 77 return getTriple().isAMDGCN() || 78 !!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP); 79 } 80 isAMDGCN(const llvm::Triple & TT)81 static bool isAMDGCN(const llvm::Triple &TT) { return TT.isAMDGCN(); } 82 isR600(const llvm::Triple & TT)83 static bool isR600(const llvm::Triple &TT) { 84 return TT.getArch() == llvm::Triple::r600; 85 } 86 87 public: 88 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts); 89 90 void setAddressSpaceMap(bool DefaultIsPrivate); 91 92 void adjust(DiagnosticsEngine &Diags, LangOptions &Opts, 93 const TargetInfo *Aux) override; 94 getPointerWidthV(LangAS AS)95 uint64_t getPointerWidthV(LangAS AS) const override { 96 if (isR600(getTriple())) 97 return 32; 98 unsigned TargetAS = getTargetAddressSpace(AS); 99 100 if (TargetAS == llvm::AMDGPUAS::PRIVATE_ADDRESS || 101 TargetAS == llvm::AMDGPUAS::LOCAL_ADDRESS) 102 return 32; 103 104 return 64; 105 } 106 getPointerAlignV(LangAS AddrSpace)107 uint64_t getPointerAlignV(LangAS AddrSpace) const override { 108 return getPointerWidthV(AddrSpace); 109 } 110 isAddressSpaceSupersetOf(LangAS A,LangAS B)111 virtual bool isAddressSpaceSupersetOf(LangAS A, LangAS B) const override { 112 // The flat address space AS(0) is a superset of all the other address 113 // spaces used by the backend target. 114 return A == B || 115 ((A == LangAS::Default || 116 (isTargetAddressSpace(A) && 117 toTargetAddressSpace(A) == llvm::AMDGPUAS::FLAT_ADDRESS)) && 118 isTargetAddressSpace(B) && 119 toTargetAddressSpace(B) >= llvm::AMDGPUAS::FLAT_ADDRESS && 120 toTargetAddressSpace(B) <= llvm::AMDGPUAS::PRIVATE_ADDRESS && 121 toTargetAddressSpace(B) != llvm::AMDGPUAS::REGION_ADDRESS); 122 } 123 getMaxPointerWidth()124 uint64_t getMaxPointerWidth() const override { 125 return getTriple().isAMDGCN() ? 64 : 32; 126 } 127 hasBFloat16Type()128 bool hasBFloat16Type() const override { return isAMDGCN(getTriple()); } 129 getClobbers()130 std::string_view getClobbers() const override { return ""; } 131 132 ArrayRef<const char *> getGCCRegNames() const override; 133 getGCCRegAliases()134 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 135 return {}; 136 } 137 138 /// Accepted register names: (n, m is unsigned integer, n < m) 139 /// v 140 /// s 141 /// a 142 /// {vn}, {v[n]} 143 /// {sn}, {s[n]} 144 /// {an}, {a[n]} 145 /// {S} , where S is a special register name 146 ////{v[n:m]} 147 /// {s[n:m]} 148 /// {a[n:m]} validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info)149 bool validateAsmConstraint(const char *&Name, 150 TargetInfo::ConstraintInfo &Info) const override { 151 static const ::llvm::StringSet<> SpecialRegs({ 152 "exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma", 153 "flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo", 154 "exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi", 155 }); 156 157 switch (*Name) { 158 case 'I': 159 Info.setRequiresImmediate(-16, 64); 160 return true; 161 case 'J': 162 Info.setRequiresImmediate(-32768, 32767); 163 return true; 164 case 'A': 165 case 'B': 166 case 'C': 167 Info.setRequiresImmediate(); 168 return true; 169 default: 170 break; 171 } 172 173 StringRef S(Name); 174 175 if (S == "DA" || S == "DB") { 176 Name++; 177 Info.setRequiresImmediate(); 178 return true; 179 } 180 181 bool HasLeftParen = S.consume_front("{"); 182 if (S.empty()) 183 return false; 184 if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') { 185 if (!HasLeftParen) 186 return false; 187 auto E = S.find('}'); 188 if (!SpecialRegs.count(S.substr(0, E))) 189 return false; 190 S = S.drop_front(E + 1); 191 if (!S.empty()) 192 return false; 193 // Found {S} where S is a special register. 194 Info.setAllowsRegister(); 195 Name = S.data() - 1; 196 return true; 197 } 198 S = S.drop_front(); 199 if (!HasLeftParen) { 200 if (!S.empty()) 201 return false; 202 // Found s, v or a. 203 Info.setAllowsRegister(); 204 Name = S.data() - 1; 205 return true; 206 } 207 bool HasLeftBracket = S.consume_front("["); 208 unsigned long long N; 209 if (S.empty() || consumeUnsignedInteger(S, 10, N)) 210 return false; 211 if (S.consume_front(":")) { 212 if (!HasLeftBracket) 213 return false; 214 unsigned long long M; 215 if (consumeUnsignedInteger(S, 10, M) || N >= M) 216 return false; 217 } 218 if (HasLeftBracket) { 219 if (!S.consume_front("]")) 220 return false; 221 } 222 if (!S.consume_front("}")) 223 return false; 224 if (!S.empty()) 225 return false; 226 // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]} 227 // or {a[n:m]}. 228 Info.setAllowsRegister(); 229 Name = S.data() - 1; 230 return true; 231 } 232 233 // \p Constraint will be left pointing at the last character of 234 // the constraint. In practice, it won't be changed unless the 235 // constraint is longer than one character. convertConstraint(const char * & Constraint)236 std::string convertConstraint(const char *&Constraint) const override { 237 238 StringRef S(Constraint); 239 if (S == "DA" || S == "DB") { 240 return std::string("^") + std::string(Constraint++, 2); 241 } 242 243 const char *Begin = Constraint; 244 TargetInfo::ConstraintInfo Info("", ""); 245 if (validateAsmConstraint(Constraint, Info)) 246 return std::string(Begin).substr(0, Constraint - Begin + 1); 247 248 Constraint = Begin; 249 return std::string(1, *Constraint); 250 } 251 252 bool 253 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 254 StringRef CPU, 255 const std::vector<std::string> &FeatureVec) const override; 256 257 llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override; 258 useFP16ConversionIntrinsics()259 bool useFP16ConversionIntrinsics() const override { return false; } 260 261 void getTargetDefines(const LangOptions &Opts, 262 MacroBuilder &Builder) const override; 263 getBuiltinVaListKind()264 BuiltinVaListKind getBuiltinVaListKind() const override { 265 return TargetInfo::CharPtrBuiltinVaList; 266 } 267 isValidCPUName(StringRef Name)268 bool isValidCPUName(StringRef Name) const override { 269 if (getTriple().isAMDGCN()) 270 return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE; 271 return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE; 272 } 273 274 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 275 setCPU(const std::string & Name)276 bool setCPU(const std::string &Name) override { 277 if (getTriple().isAMDGCN()) { 278 GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name); 279 GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind); 280 } else { 281 GPUKind = llvm::AMDGPU::parseArchR600(Name); 282 GPUFeatures = llvm::AMDGPU::getArchAttrR600(GPUKind); 283 } 284 285 return GPUKind != llvm::AMDGPU::GK_NONE; 286 } 287 setSupportedOpenCLOpts()288 void setSupportedOpenCLOpts() override { 289 auto &Opts = getSupportedOpenCLOpts(); 290 Opts["cl_clang_storage_class_specifiers"] = true; 291 Opts["__cl_clang_variadic_functions"] = true; 292 Opts["__cl_clang_function_pointers"] = true; 293 Opts["__cl_clang_non_portable_kernel_param_types"] = true; 294 Opts["__cl_clang_bitfields"] = true; 295 296 bool IsAMDGCN = isAMDGCN(getTriple()); 297 298 Opts["cl_khr_fp64"] = hasFP64(); 299 Opts["__opencl_c_fp64"] = hasFP64(); 300 301 if (IsAMDGCN || GPUKind >= llvm::AMDGPU::GK_CEDAR) { 302 Opts["cl_khr_byte_addressable_store"] = true; 303 Opts["cl_khr_global_int32_base_atomics"] = true; 304 Opts["cl_khr_global_int32_extended_atomics"] = true; 305 Opts["cl_khr_local_int32_base_atomics"] = true; 306 Opts["cl_khr_local_int32_extended_atomics"] = true; 307 } 308 309 if (IsAMDGCN) { 310 Opts["cl_khr_fp16"] = true; 311 Opts["cl_khr_int64_base_atomics"] = true; 312 Opts["cl_khr_int64_extended_atomics"] = true; 313 Opts["cl_khr_mipmap_image"] = true; 314 Opts["cl_khr_mipmap_image_writes"] = true; 315 Opts["cl_khr_subgroups"] = true; 316 Opts["cl_amd_media_ops"] = true; 317 Opts["cl_amd_media_ops2"] = true; 318 319 Opts["__opencl_c_images"] = true; 320 Opts["__opencl_c_3d_image_writes"] = true; 321 Opts["cl_khr_3d_image_writes"] = true; 322 323 Opts["__opencl_c_generic_address_space"] = 324 GPUKind >= llvm::AMDGPU::GK_GFX700; 325 } 326 } 327 getOpenCLTypeAddrSpace(OpenCLTypeKind TK)328 LangAS getOpenCLTypeAddrSpace(OpenCLTypeKind TK) const override { 329 switch (TK) { 330 case OCLTK_Image: 331 return LangAS::opencl_constant; 332 333 case OCLTK_ClkEvent: 334 case OCLTK_Queue: 335 case OCLTK_ReserveID: 336 return LangAS::opencl_global; 337 338 default: 339 return TargetInfo::getOpenCLTypeAddrSpace(TK); 340 } 341 } 342 getOpenCLBuiltinAddressSpace(unsigned AS)343 LangAS getOpenCLBuiltinAddressSpace(unsigned AS) const override { 344 switch (AS) { 345 case 0: 346 return LangAS::opencl_generic; 347 case 1: 348 return LangAS::opencl_global; 349 case 3: 350 return LangAS::opencl_local; 351 case 4: 352 return LangAS::opencl_constant; 353 case 5: 354 return LangAS::opencl_private; 355 default: 356 return getLangASFromTargetAS(AS); 357 } 358 } 359 getCUDABuiltinAddressSpace(unsigned AS)360 LangAS getCUDABuiltinAddressSpace(unsigned AS) const override { 361 switch (AS) { 362 case 0: 363 return LangAS::Default; 364 case 1: 365 return LangAS::cuda_device; 366 case 3: 367 return LangAS::cuda_shared; 368 case 4: 369 return LangAS::cuda_constant; 370 default: 371 return getLangASFromTargetAS(AS); 372 } 373 } 374 getConstantAddressSpace()375 std::optional<LangAS> getConstantAddressSpace() const override { 376 return getLangASFromTargetAS(llvm::AMDGPUAS::CONSTANT_ADDRESS); 377 } 378 getGridValue()379 const llvm::omp::GV &getGridValue() const override { 380 switch (WavefrontSize) { 381 case 32: 382 return llvm::omp::getAMDGPUGridValues<32>(); 383 case 64: 384 return llvm::omp::getAMDGPUGridValues<64>(); 385 default: 386 llvm_unreachable("getGridValue not implemented for this wavesize"); 387 } 388 } 389 390 /// \returns Target specific vtbl ptr address space. getVtblPtrAddressSpace()391 unsigned getVtblPtrAddressSpace() const override { 392 return static_cast<unsigned>(llvm::AMDGPUAS::CONSTANT_ADDRESS); 393 } 394 395 /// \returns If a target requires an address within a target specific address 396 /// space \p AddressSpace to be converted in order to be used, then return the 397 /// corresponding target specific DWARF address space. 398 /// 399 /// \returns Otherwise return std::nullopt and no conversion will be emitted 400 /// in the DWARF. 401 std::optional<unsigned> getDWARFAddressSpace(unsigned AddressSpace)402 getDWARFAddressSpace(unsigned AddressSpace) const override { 403 const unsigned DWARF_Private = 1; 404 const unsigned DWARF_Local = 2; 405 if (AddressSpace == llvm::AMDGPUAS::PRIVATE_ADDRESS) { 406 return DWARF_Private; 407 } else if (AddressSpace == llvm::AMDGPUAS::LOCAL_ADDRESS) { 408 return DWARF_Local; 409 } else { 410 return std::nullopt; 411 } 412 } 413 checkCallingConvention(CallingConv CC)414 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 415 switch (CC) { 416 default: 417 return CCCR_Warning; 418 case CC_C: 419 case CC_DeviceKernel: 420 return CCCR_OK; 421 } 422 } 423 424 // In amdgcn target the null pointer in global, constant, and generic 425 // address space has value 0 but in private and local address space has 426 // value ~0. getNullPointerValue(LangAS AS)427 uint64_t getNullPointerValue(LangAS AS) const override { 428 // FIXME: Also should handle region. 429 return (AS == LangAS::opencl_local || AS == LangAS::opencl_private || 430 AS == LangAS::sycl_local || AS == LangAS::sycl_private) 431 ? ~0 432 : 0; 433 } 434 435 void setAuxTarget(const TargetInfo *Aux) override; 436 hasBitIntType()437 bool hasBitIntType() const override { return true; } 438 439 // Record offload arch features since they are needed for defining the 440 // pre-defined macros. handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)441 bool handleTargetFeatures(std::vector<std::string> &Features, 442 DiagnosticsEngine &Diags) override { 443 HasFullBFloat16 = true; 444 auto TargetIDFeatures = 445 getAllPossibleTargetIDFeatures(getTriple(), getArchNameAMDGCN(GPUKind)); 446 for (const auto &F : Features) { 447 assert(F.front() == '+' || F.front() == '-'); 448 if (F == "+wavefrontsize64") 449 WavefrontSize = 64; 450 else if (F == "+cumode") 451 CUMode = true; 452 else if (F == "-cumode") 453 CUMode = false; 454 else if (F == "+image-insts") 455 HasImage = true; 456 bool IsOn = F.front() == '+'; 457 StringRef Name = StringRef(F).drop_front(); 458 if (!llvm::is_contained(TargetIDFeatures, Name)) 459 continue; 460 assert(!OffloadArchFeatures.contains(Name)); 461 OffloadArchFeatures[Name] = IsOn; 462 } 463 return true; 464 } 465 getTargetID()466 std::optional<std::string> getTargetID() const override { 467 if (!isAMDGCN(getTriple())) 468 return std::nullopt; 469 // When -target-cpu is not set, we assume generic code that it is valid 470 // for all GPU and use an empty string as target ID to represent that. 471 if (GPUKind == llvm::AMDGPU::GK_NONE) 472 return std::string(""); 473 return getCanonicalTargetID(getArchNameAMDGCN(GPUKind), 474 OffloadArchFeatures); 475 } 476 hasHIPImageSupport()477 bool hasHIPImageSupport() const override { return HasImage; } 478 hardwareInterferenceSizes()479 std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { 480 // This is imprecise as the value can vary between 64, 128 (even 256!) bytes 481 // depending on the level of cache and the target architecture. We select 482 // the size that corresponds to the largest L1 cache line for all 483 // architectures. 484 return std::make_pair(128, 128); 485 } 486 }; 487 488 } // namespace targets 489 } // namespace clang 490 491 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H 492