1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/notifier.h>
49 #include <linux/refcount.h>
50 #include <linux/auxiliary_bus.h>
51 #include <linux/mutex.h>
52
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <net/devlink.h>
58
59 #define MLX5_ADEV_NAME "mlx5_core"
60
61 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
62
63 enum {
64 MLX5_BOARD_ID_LEN = 64,
65 };
66
67 enum {
68 MLX5_CMD_WQ_MAX_NAME = 32,
69 };
70
71 enum {
72 CMD_OWNER_SW = 0x0,
73 CMD_OWNER_HW = 0x1,
74 CMD_STATUS_SUCCESS = 0,
75 };
76
77 enum mlx5_sqp_t {
78 MLX5_SQP_SMI = 0,
79 MLX5_SQP_GSI = 1,
80 MLX5_SQP_IEEE_1588 = 2,
81 MLX5_SQP_SNIFFER = 3,
82 MLX5_SQP_SYNC_UMR = 4,
83 };
84
85 enum {
86 MLX5_MAX_PORTS = 8,
87 };
88
89 enum {
90 MLX5_ATOMIC_MODE_OFFSET = 16,
91 MLX5_ATOMIC_MODE_IB_COMP = 1,
92 MLX5_ATOMIC_MODE_CX = 2,
93 MLX5_ATOMIC_MODE_8B = 3,
94 MLX5_ATOMIC_MODE_16B = 4,
95 MLX5_ATOMIC_MODE_32B = 5,
96 MLX5_ATOMIC_MODE_64B = 6,
97 MLX5_ATOMIC_MODE_128B = 7,
98 MLX5_ATOMIC_MODE_256B = 8,
99 };
100
101 enum {
102 MLX5_REG_SBPR = 0xb001,
103 MLX5_REG_SBCM = 0xb002,
104 MLX5_REG_QPTS = 0x4002,
105 MLX5_REG_QETCR = 0x4005,
106 MLX5_REG_QTCT = 0x400a,
107 MLX5_REG_QPDPM = 0x4013,
108 MLX5_REG_QCAM = 0x4019,
109 MLX5_REG_DCBX_PARAM = 0x4020,
110 MLX5_REG_DCBX_APP = 0x4021,
111 MLX5_REG_FPGA_CAP = 0x4022,
112 MLX5_REG_FPGA_CTRL = 0x4023,
113 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
114 MLX5_REG_CORE_DUMP = 0x402e,
115 MLX5_REG_PCAP = 0x5001,
116 MLX5_REG_PMTU = 0x5003,
117 MLX5_REG_PTYS = 0x5004,
118 MLX5_REG_PAOS = 0x5006,
119 MLX5_REG_PFCC = 0x5007,
120 MLX5_REG_PPCNT = 0x5008,
121 MLX5_REG_PPTB = 0x500b,
122 MLX5_REG_PBMC = 0x500c,
123 MLX5_REG_PMAOS = 0x5012,
124 MLX5_REG_PUDE = 0x5009,
125 MLX5_REG_PMPE = 0x5010,
126 MLX5_REG_PELC = 0x500e,
127 MLX5_REG_PVLC = 0x500f,
128 MLX5_REG_PCMR = 0x5041,
129 MLX5_REG_PDDR = 0x5031,
130 MLX5_REG_PMLP = 0x5002,
131 MLX5_REG_PPLM = 0x5023,
132 MLX5_REG_PCAM = 0x507f,
133 MLX5_REG_NODE_DESC = 0x6001,
134 MLX5_REG_HOST_ENDIANNESS = 0x7004,
135 MLX5_REG_MTCAP = 0x9009,
136 MLX5_REG_MTMP = 0x900A,
137 MLX5_REG_MCIA = 0x9014,
138 MLX5_REG_MFRL = 0x9028,
139 MLX5_REG_MLCR = 0x902b,
140 MLX5_REG_MRTC = 0x902d,
141 MLX5_REG_MTRC_CAP = 0x9040,
142 MLX5_REG_MTRC_CONF = 0x9041,
143 MLX5_REG_MTRC_STDB = 0x9042,
144 MLX5_REG_MTRC_CTRL = 0x9043,
145 MLX5_REG_MPEIN = 0x9050,
146 MLX5_REG_MPCNT = 0x9051,
147 MLX5_REG_MTPPS = 0x9053,
148 MLX5_REG_MTPPSE = 0x9054,
149 MLX5_REG_MTUTC = 0x9055,
150 MLX5_REG_MPEGC = 0x9056,
151 MLX5_REG_MPIR = 0x9059,
152 MLX5_REG_MCQS = 0x9060,
153 MLX5_REG_MCQI = 0x9061,
154 MLX5_REG_MCC = 0x9062,
155 MLX5_REG_MCDA = 0x9063,
156 MLX5_REG_MCAM = 0x907f,
157 MLX5_REG_MSECQ = 0x9155,
158 MLX5_REG_MSEES = 0x9156,
159 MLX5_REG_MIRC = 0x9162,
160 MLX5_REG_MTPTM = 0x9180,
161 MLX5_REG_MTCTR = 0x9181,
162 MLX5_REG_MRTCQ = 0x9182,
163 MLX5_REG_SBCAM = 0xB01F,
164 MLX5_REG_RESOURCE_DUMP = 0xC000,
165 MLX5_REG_NIC_CAP = 0xC00D,
166 MLX5_REG_DTOR = 0xC00E,
167 MLX5_REG_VHCA_ICM_CTRL = 0xC010,
168 };
169
170 enum mlx5_qpts_trust_state {
171 MLX5_QPTS_TRUST_PCP = 1,
172 MLX5_QPTS_TRUST_DSCP = 2,
173 };
174
175 enum mlx5_dcbx_oper_mode {
176 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
177 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
178 };
179
180 enum {
181 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
182 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
183 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
184 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
185 };
186
187 enum mlx5_page_fault_resume_flags {
188 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
189 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
190 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
191 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
192 };
193
194 enum dbg_rsc_type {
195 MLX5_DBG_RSC_QP,
196 MLX5_DBG_RSC_EQ,
197 MLX5_DBG_RSC_CQ,
198 };
199
200 enum port_state_policy {
201 MLX5_POLICY_DOWN = 0,
202 MLX5_POLICY_UP = 1,
203 MLX5_POLICY_FOLLOW = 2,
204 MLX5_POLICY_INVALID = 0xffffffff
205 };
206
207 enum mlx5_coredev_type {
208 MLX5_COREDEV_PF,
209 MLX5_COREDEV_VF,
210 MLX5_COREDEV_SF,
211 };
212
213 struct mlx5_field_desc {
214 int i;
215 };
216
217 struct mlx5_rsc_debug {
218 struct mlx5_core_dev *dev;
219 void *object;
220 enum dbg_rsc_type type;
221 struct dentry *root;
222 struct mlx5_field_desc fields[];
223 };
224
225 enum mlx5_dev_event {
226 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
227 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
228 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
229 };
230
231 enum mlx5_port_status {
232 MLX5_PORT_UP = 1,
233 MLX5_PORT_DOWN = 2,
234 };
235
236 enum mlx5_cmdif_state {
237 MLX5_CMDIF_STATE_UNINITIALIZED,
238 MLX5_CMDIF_STATE_UP,
239 MLX5_CMDIF_STATE_DOWN,
240 };
241
242 struct mlx5_cmd_first {
243 __be32 data[4];
244 };
245
246 struct mlx5_cmd_msg {
247 struct list_head list;
248 struct cmd_msg_cache *parent;
249 u32 len;
250 struct mlx5_cmd_first first;
251 struct mlx5_cmd_mailbox *next;
252 };
253
254 struct mlx5_cmd_debug {
255 struct dentry *dbg_root;
256 void *in_msg;
257 void *out_msg;
258 u8 status;
259 u16 inlen;
260 u16 outlen;
261 };
262
263 struct cmd_msg_cache {
264 /* protect block chain allocations
265 */
266 spinlock_t lock;
267 struct list_head head;
268 unsigned int max_inbox_size;
269 unsigned int num_ent;
270 };
271
272 enum {
273 MLX5_NUM_COMMAND_CACHES = 5,
274 };
275
276 struct mlx5_cmd_stats {
277 u64 sum;
278 u64 n;
279 /* number of times command failed */
280 u64 failed;
281 /* number of times command failed on bad status returned by FW */
282 u64 failed_mbox_status;
283 /* last command failed returned errno */
284 u32 last_failed_errno;
285 /* last bad status returned by FW */
286 u8 last_failed_mbox_status;
287 /* last command failed syndrome returned by FW */
288 u32 last_failed_syndrome;
289 struct dentry *root;
290 /* protect command average calculations */
291 spinlock_t lock;
292 };
293
294 struct mlx5_cmd {
295 struct mlx5_nb nb;
296
297 /* members which needs to be queried or reinitialized each reload */
298 struct {
299 u16 cmdif_rev;
300 u8 log_sz;
301 u8 log_stride;
302 int max_reg_cmds;
303 unsigned long bitmask;
304 struct semaphore sem;
305 struct semaphore pages_sem;
306 struct semaphore throttle_sem;
307 struct semaphore unprivileged_sem;
308 struct xarray privileged_uids;
309 } vars;
310 enum mlx5_cmdif_state state;
311 void *cmd_alloc_buf;
312 dma_addr_t alloc_dma;
313 int alloc_size;
314 void *cmd_buf;
315 dma_addr_t dma;
316
317 /* protect command queue allocations
318 */
319 spinlock_t alloc_lock;
320
321 /* protect token allocations
322 */
323 spinlock_t token_lock;
324 u8 token;
325 char wq_name[MLX5_CMD_WQ_MAX_NAME];
326 struct workqueue_struct *wq;
327 int mode;
328 u16 allowed_opcode;
329 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
330 struct dma_pool *pool;
331 struct mlx5_cmd_debug dbg;
332 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
333 int checksum_disabled;
334 struct xarray stats;
335 };
336
337 struct mlx5_cmd_mailbox {
338 void *buf;
339 dma_addr_t dma;
340 struct mlx5_cmd_mailbox *next;
341 };
342
343 struct mlx5_buf_list {
344 void *buf;
345 dma_addr_t map;
346 };
347
348 struct mlx5_frag_buf {
349 struct mlx5_buf_list *frags;
350 int npages;
351 int size;
352 u8 page_shift;
353 };
354
355 struct mlx5_frag_buf_ctrl {
356 struct mlx5_buf_list *frags;
357 u32 sz_m1;
358 u16 frag_sz_m1;
359 u16 strides_offset;
360 u8 log_sz;
361 u8 log_stride;
362 u8 log_frag_strides;
363 };
364
365 struct mlx5_core_psv {
366 u32 psv_idx;
367 struct psv_layout {
368 u32 pd;
369 u16 syndrome;
370 u16 reserved;
371 u16 bg;
372 u16 app_tag;
373 u32 ref_tag;
374 } psv;
375 };
376
377 struct mlx5_core_sig_ctx {
378 struct mlx5_core_psv psv_memory;
379 struct mlx5_core_psv psv_wire;
380 struct ib_sig_err err_item;
381 bool sig_status_checked;
382 bool sig_err_exists;
383 u32 sigerr_count;
384 };
385
386 #define MLX5_24BIT_MASK ((1 << 24) - 1)
387
388 enum mlx5_res_type {
389 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
390 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
391 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
392 MLX5_RES_SRQ = 3,
393 MLX5_RES_XSRQ = 4,
394 MLX5_RES_XRQ = 5,
395 };
396
397 struct mlx5_core_rsc_common {
398 enum mlx5_res_type res;
399 refcount_t refcount;
400 struct completion free;
401 };
402
403 struct mlx5_uars_page {
404 void __iomem *map;
405 bool wc;
406 u32 index;
407 struct list_head list;
408 unsigned int bfregs;
409 unsigned long *reg_bitmap; /* for non fast path bf regs */
410 unsigned long *fp_bitmap;
411 unsigned int reg_avail;
412 unsigned int fp_avail;
413 struct kref ref_count;
414 struct mlx5_core_dev *mdev;
415 };
416
417 struct mlx5_bfreg_head {
418 /* protect blue flame registers allocations */
419 struct mutex lock;
420 struct list_head list;
421 };
422
423 struct mlx5_bfreg_data {
424 struct mlx5_bfreg_head reg_head;
425 struct mlx5_bfreg_head wc_head;
426 };
427
428 struct mlx5_sq_bfreg {
429 void __iomem *map;
430 struct mlx5_uars_page *up;
431 bool wc;
432 u32 index;
433 unsigned int offset;
434 };
435
436 struct mlx5_core_health {
437 struct health_buffer __iomem *health;
438 __be32 __iomem *health_counter;
439 struct timer_list timer;
440 u32 prev;
441 int miss_counter;
442 u8 synd;
443 u32 fatal_error;
444 u32 crdump_size;
445 struct workqueue_struct *wq;
446 unsigned long flags;
447 struct work_struct fatal_report_work;
448 struct work_struct report_work;
449 struct devlink_health_reporter *fw_reporter;
450 struct devlink_health_reporter *fw_fatal_reporter;
451 struct devlink_health_reporter *vnic_reporter;
452 struct delayed_work update_fw_log_ts_work;
453 };
454
455 enum {
456 MLX5_PF_NOTIFY_DISABLE_VF,
457 MLX5_PF_NOTIFY_ENABLE_VF,
458 };
459
460 struct mlx5_vf_context {
461 int enabled;
462 u64 port_guid;
463 u64 node_guid;
464 /* Valid bits are used to validate administrative guid only.
465 * Enabled after ndo_set_vf_guid
466 */
467 u8 port_guid_valid:1;
468 u8 node_guid_valid:1;
469 enum port_state_policy policy;
470 struct blocking_notifier_head notifier;
471 };
472
473 struct mlx5_core_sriov {
474 struct mlx5_vf_context *vfs_ctx;
475 int num_vfs;
476 u16 max_vfs;
477 u16 max_ec_vfs;
478 };
479
480 struct mlx5_events;
481 struct mlx5_mpfs;
482 struct mlx5_eswitch;
483 struct mlx5_lag;
484 struct mlx5_devcom_dev;
485 struct mlx5_fw_reset;
486 struct mlx5_eq_table;
487 struct mlx5_irq_table;
488 struct mlx5_vhca_state_notifier;
489 struct mlx5_sf_dev_table;
490 struct mlx5_sf_hw_table;
491 struct mlx5_sf_table;
492 struct mlx5_crypto_dek_priv;
493
494 struct mlx5_rate_limit {
495 u32 rate;
496 u32 max_burst_sz;
497 u16 typical_pkt_sz;
498 };
499
500 struct mlx5_rl_entry {
501 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
502 u64 refcount;
503 u16 index;
504 u16 uid;
505 u8 dedicated : 1;
506 };
507
508 struct mlx5_rl_table {
509 /* protect rate limit table */
510 struct mutex rl_lock;
511 u16 max_size;
512 u32 max_rate;
513 u32 min_rate;
514 struct mlx5_rl_entry *rl_entry;
515 u64 refcount;
516 };
517
518 struct mlx5_core_roce {
519 struct mlx5_flow_table *ft;
520 struct mlx5_flow_group *fg;
521 struct mlx5_flow_handle *allow_rule;
522 };
523
524 enum {
525 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
526 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
527 /* Set during device detach to block any further devices
528 * creation/deletion on drivers rescan. Unset during device attach.
529 */
530 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
531 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
532 };
533
534 struct mlx5_adev {
535 struct auxiliary_device adev;
536 struct mlx5_core_dev *mdev;
537 int idx;
538 };
539
540 struct mlx5_debugfs_entries {
541 struct dentry *dbg_root;
542 struct dentry *qp_debugfs;
543 struct dentry *eq_debugfs;
544 struct dentry *cq_debugfs;
545 struct dentry *cmdif_debugfs;
546 struct dentry *pages_debugfs;
547 struct dentry *lag_debugfs;
548 };
549
550 enum mlx5_func_type {
551 MLX5_PF,
552 MLX5_VF,
553 MLX5_SF,
554 MLX5_HOST_PF,
555 MLX5_EC_VF,
556 MLX5_FUNC_TYPE_NUM,
557 };
558
559 struct mlx5_ft_pool;
560 struct mlx5_priv {
561 /* IRQ table valid only for real pci devices PF or VF */
562 struct mlx5_irq_table *irq_table;
563 struct mlx5_eq_table *eq_table;
564
565 /* pages stuff */
566 struct mlx5_nb pg_nb;
567 struct workqueue_struct *pg_wq;
568 struct xarray page_root_xa;
569 atomic_t reg_pages;
570 struct list_head free_list;
571 u32 fw_pages;
572 u32 page_counters[MLX5_FUNC_TYPE_NUM];
573 u32 fw_pages_alloc_failed;
574 u32 give_pages_dropped;
575 u32 reclaim_pages_discard;
576
577 struct mlx5_core_health health;
578 struct list_head traps;
579
580 struct mlx5_debugfs_entries dbg;
581
582 /* start: alloc staff */
583 /* protect buffer allocation according to numa node */
584 struct mutex alloc_mutex;
585 int numa_node;
586
587 struct mutex pgdir_mutex;
588 struct list_head pgdir_list;
589 /* end: alloc staff */
590
591 struct mlx5_adev **adev;
592 int adev_idx;
593 int sw_vhca_id;
594 struct mlx5_events *events;
595 struct mlx5_vhca_events *vhca_events;
596
597 struct mlx5_flow_steering *steering;
598 struct mlx5_mpfs *mpfs;
599 struct mlx5_eswitch *eswitch;
600 struct mlx5_core_sriov sriov;
601 struct mlx5_lag *lag;
602 u32 flags;
603 struct mlx5_devcom_dev *devc;
604 struct mlx5_devcom_comp_dev *hca_devcom_comp;
605 struct mlx5_fw_reset *fw_reset;
606 struct mlx5_core_roce roce;
607 struct mlx5_fc_stats *fc_stats;
608 struct mlx5_rl_table rl_table;
609 struct mlx5_ft_pool *ft_pool;
610
611 struct mlx5_bfreg_data bfregs;
612 struct mlx5_uars_page *uar;
613 #ifdef CONFIG_MLX5_SF
614 struct mlx5_vhca_state_notifier *vhca_state_notifier;
615 struct mlx5_sf_dev_table *sf_dev_table;
616 struct mlx5_core_dev *parent_mdev;
617 #endif
618 #ifdef CONFIG_MLX5_SF_MANAGER
619 struct mlx5_sf_hw_table *sf_hw_table;
620 struct mlx5_sf_table *sf_table;
621 #endif
622 struct blocking_notifier_head lag_nh;
623 };
624
625 enum mlx5_device_state {
626 MLX5_DEVICE_STATE_UP = 1,
627 MLX5_DEVICE_STATE_INTERNAL_ERROR,
628 };
629
630 enum mlx5_interface_state {
631 MLX5_INTERFACE_STATE_UP = BIT(0),
632 MLX5_BREAK_FW_WAIT = BIT(1),
633 };
634
635 enum mlx5_pci_status {
636 MLX5_PCI_STATUS_DISABLED,
637 MLX5_PCI_STATUS_ENABLED,
638 };
639
640 enum mlx5_pagefault_type_flags {
641 MLX5_PFAULT_REQUESTOR = 1 << 0,
642 MLX5_PFAULT_WRITE = 1 << 1,
643 MLX5_PFAULT_RDMA = 1 << 2,
644 };
645
646 struct mlx5_td {
647 /* protects tirs list changes while tirs refresh */
648 struct mutex list_lock;
649 struct list_head tirs_list;
650 u32 tdn;
651 };
652
653 struct mlx5e_resources {
654 struct mlx5e_hw_objs {
655 u32 pdn;
656 struct mlx5_td td;
657 u32 mkey;
658 struct mlx5_sq_bfreg bfreg;
659 #define MLX5_MAX_NUM_TC 8
660 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
661 bool tisn_valid;
662 } hw_objs;
663 struct net_device *uplink_netdev;
664 struct mutex uplink_netdev_lock;
665 struct mlx5_crypto_dek_priv *dek_priv;
666 };
667
668 enum mlx5_sw_icm_type {
669 MLX5_SW_ICM_TYPE_STEERING,
670 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
671 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
672 MLX5_SW_ICM_TYPE_SW_ENCAP,
673 };
674
675 #define MLX5_MAX_RESERVED_GIDS 8
676
677 struct mlx5_rsvd_gids {
678 unsigned int start;
679 unsigned int count;
680 struct ida ida;
681 };
682
683 struct mlx5_clock;
684 struct mlx5_clock_dev_state;
685 struct mlx5_dm;
686 struct mlx5_fw_tracer;
687 struct mlx5_vxlan;
688 struct mlx5_geneve;
689 struct mlx5_hv_vhca;
690
691 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
692 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
693
694 enum {
695 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
696 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
697 };
698
699 enum {
700 MKEY_CACHE_LAST_STD_ENTRY = 20,
701 MLX5_IMR_KSM_CACHE_ENTRY,
702 MAX_MKEY_CACHE_ENTRIES
703 };
704
705 struct mlx5_profile {
706 u64 mask;
707 u8 log_max_qp;
708 u8 num_cmd_caches;
709 struct {
710 int size;
711 int limit;
712 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
713 };
714
715 struct mlx5_hca_cap {
716 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
717 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
718 };
719
720 enum mlx5_wc_state {
721 MLX5_WC_STATE_UNINITIALIZED,
722 MLX5_WC_STATE_UNSUPPORTED,
723 MLX5_WC_STATE_SUPPORTED,
724 };
725
726 struct mlx5_core_dev {
727 struct device *device;
728 enum mlx5_coredev_type coredev_type;
729 struct pci_dev *pdev;
730 /* sync pci state */
731 struct mutex pci_status_mutex;
732 enum mlx5_pci_status pci_status;
733 u8 rev_id;
734 char board_id[MLX5_BOARD_ID_LEN];
735 struct mlx5_cmd cmd;
736 struct {
737 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
738 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
739 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
740 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
741 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
742 u8 embedded_cpu;
743 } caps;
744 struct mlx5_timeouts *timeouts;
745 u64 sys_image_guid;
746 phys_addr_t iseg_base;
747 struct mlx5_init_seg __iomem *iseg;
748 phys_addr_t bar_addr;
749 enum mlx5_device_state state;
750 /* sync interface state */
751 struct mutex intf_state_mutex;
752 struct lock_class_key lock_key;
753 unsigned long intf_state;
754 struct mlx5_priv priv;
755 struct mlx5_profile profile;
756 u32 issi;
757 struct mlx5e_resources mlx5e_res;
758 struct mlx5_dm *dm;
759 struct mlx5_vxlan *vxlan;
760 struct mlx5_geneve *geneve;
761 struct {
762 struct mlx5_rsvd_gids reserved_gids;
763 u32 roce_en;
764 } roce;
765 #ifdef CONFIG_MLX5_FPGA
766 struct mlx5_fpga_device *fpga;
767 #endif
768 struct mlx5_clock *clock;
769 struct mlx5_clock_dev_state *clock_state;
770 struct mlx5_ib_clock_info *clock_info;
771 struct mlx5_fw_tracer *tracer;
772 struct mlx5_rsc_dump *rsc_dump;
773 u32 vsc_addr;
774 struct mlx5_hv_vhca *hv_vhca;
775 struct mlx5_hwmon *hwmon;
776 u64 num_block_tc;
777 u64 num_block_ipsec;
778 #ifdef CONFIG_MLX5_MACSEC
779 struct mlx5_macsec_fs *macsec_fs;
780 /* MACsec notifier chain to sync MACsec core and IB database */
781 struct blocking_notifier_head macsec_nh;
782 #endif
783 u64 num_ipsec_offloads;
784 struct mlx5_sd *sd;
785 enum mlx5_wc_state wc_state;
786 /* sync write combining state */
787 struct mutex wc_state_lock;
788 };
789
790 struct mlx5_db {
791 __be32 *db;
792 union {
793 struct mlx5_db_pgdir *pgdir;
794 struct mlx5_ib_user_db_page *user_page;
795 } u;
796 dma_addr_t dma;
797 int index;
798 };
799
800 enum {
801 MLX5_COMP_EQ_SIZE = 1024,
802 };
803
804 enum {
805 MLX5_PTYS_IB = 1 << 0,
806 MLX5_PTYS_EN = 1 << 2,
807 };
808
809 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
810
811 enum {
812 MLX5_CMD_ENT_STATE_PENDING_COMP,
813 };
814
815 struct mlx5_cmd_work_ent {
816 unsigned long state;
817 struct mlx5_cmd_msg *in;
818 struct mlx5_cmd_msg *out;
819 void *uout;
820 int uout_size;
821 mlx5_cmd_cbk_t callback;
822 struct delayed_work cb_timeout_work;
823 void *context;
824 int idx;
825 struct completion handling;
826 struct completion slotted;
827 struct completion done;
828 struct mlx5_cmd *cmd;
829 struct work_struct work;
830 struct mlx5_cmd_layout *lay;
831 int ret;
832 int page_queue;
833 u8 status;
834 u8 token;
835 u64 ts1;
836 u64 ts2;
837 u16 op;
838 bool polling;
839 /* Track the max comp handlers */
840 refcount_t refcnt;
841 };
842
843 enum phy_port_state {
844 MLX5_AAA_111
845 };
846
847 struct mlx5_hca_vport_context {
848 u32 field_select;
849 bool sm_virt_aware;
850 bool has_smi;
851 bool has_raw;
852 enum port_state_policy policy;
853 enum phy_port_state phys_state;
854 enum ib_port_state vport_state;
855 u8 port_physical_state;
856 u64 sys_image_guid;
857 u64 port_guid;
858 u64 node_guid;
859 u32 cap_mask1;
860 u32 cap_mask1_perm;
861 u16 cap_mask2;
862 u16 cap_mask2_perm;
863 u16 lid;
864 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
865 u8 lmc;
866 u8 subnet_timeout;
867 u16 sm_lid;
868 u8 sm_sl;
869 u16 qkey_violation_counter;
870 u16 pkey_violation_counter;
871 bool grh_required;
872 u8 num_plane;
873 };
874
875 #define STRUCT_FIELD(header, field) \
876 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
877 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
878
879 extern struct dentry *mlx5_debugfs_root;
880
fw_rev_maj(struct mlx5_core_dev * dev)881 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
882 {
883 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
884 }
885
fw_rev_min(struct mlx5_core_dev * dev)886 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
887 {
888 return ioread32be(&dev->iseg->fw_rev) >> 16;
889 }
890
fw_rev_sub(struct mlx5_core_dev * dev)891 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
892 {
893 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
894 }
895
mlx5_base_mkey(const u32 key)896 static inline u32 mlx5_base_mkey(const u32 key)
897 {
898 return key & 0xffffff00u;
899 }
900
wq_get_byte_sz(u8 log_sz,u8 log_stride)901 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
902 {
903 return ((u32)1 << log_sz) << log_stride;
904 }
905
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)906 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
907 u8 log_stride, u8 log_sz,
908 u16 strides_offset,
909 struct mlx5_frag_buf_ctrl *fbc)
910 {
911 fbc->frags = frags;
912 fbc->log_stride = log_stride;
913 fbc->log_sz = log_sz;
914 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
915 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
916 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
917 fbc->strides_offset = strides_offset;
918 }
919
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)920 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
921 u8 log_stride, u8 log_sz,
922 struct mlx5_frag_buf_ctrl *fbc)
923 {
924 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
925 }
926
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)927 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
928 u32 ix)
929 {
930 unsigned int frag;
931
932 ix += fbc->strides_offset;
933 frag = ix >> fbc->log_frag_strides;
934
935 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
936 }
937
938 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)939 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
940 {
941 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
942
943 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
944 }
945
946 enum {
947 CMD_ALLOWED_OPCODE_ALL,
948 };
949
950 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
951 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
952 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
953
954 struct mlx5_async_ctx {
955 struct mlx5_core_dev *dev;
956 atomic_t num_inflight;
957 struct completion inflight_done;
958 };
959
960 struct mlx5_async_work;
961
962 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
963
964 struct mlx5_async_work {
965 struct mlx5_async_ctx *ctx;
966 mlx5_async_cbk_t user_callback;
967 u16 opcode; /* cmd opcode */
968 u16 op_mod; /* cmd op_mod */
969 u8 throttle_locked:1;
970 u8 unpriv_locked:1;
971 void *out; /* pointer to the cmd output buffer */
972 };
973
974 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
975 struct mlx5_async_ctx *ctx);
976 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
977 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
978 void *out, int out_size, mlx5_async_cbk_t callback,
979 struct mlx5_async_work *work);
980 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
981 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
982 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
983 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
984 int out_size);
985
986 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
987 ({ \
988 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
989 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
990 })
991
992 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
993 ({ \
994 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
995 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
996 })
997
998 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
999 void *out, int out_size);
1000 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1001 int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1002 void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1003
1004 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1005 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1006
1007 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1008
1009 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1010 int mlx5_health_init(struct mlx5_core_dev *dev);
1011 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1012 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1013 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1014 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1015 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1016 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1017 struct mlx5_frag_buf *buf, int node);
1018 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1019 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1020 int inlen);
1021 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1022 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1023 int outlen);
1024 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1025 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1026 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1027 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1028 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1029 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1030 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1031 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1032 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1033 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1034 void mlx5_register_debugfs(void);
1035 void mlx5_unregister_debugfs(void);
1036
1037 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1038 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1039 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1040 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1041 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1042
1043 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1044 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1045 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1046 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1047 void *data_out, int size_out, u16 reg_id, int arg,
1048 int write, bool verbose);
1049 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1050 int size_in, void *data_out, int size_out,
1051 u16 reg_num, int arg, int write);
1052
1053 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1054 int node);
1055
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1056 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1057 {
1058 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1059 }
1060
1061 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1062
1063 const char *mlx5_command_str(int command);
1064 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1065 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1066 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1067 int npsvs, u32 *sig_index);
1068 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1069 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1070 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1071
1072 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1073 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1074 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1075 struct mlx5_rate_limit *rl);
1076 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1077 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1078 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1079 bool dedicated_entry, u16 *index);
1080 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1081 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1082 struct mlx5_rate_limit *rl_1);
1083 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1084 bool map_wc, bool fast_path);
1085 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1086
1087 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1088 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1089 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1090 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1091 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1092 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1093
mlx5_mkey_to_idx(u32 mkey)1094 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1095 {
1096 return mkey >> 8;
1097 }
1098
mlx5_idx_to_mkey(u32 mkey_idx)1099 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1100 {
1101 return mkey_idx << 8;
1102 }
1103
mlx5_mkey_variant(u32 mkey)1104 static inline u8 mlx5_mkey_variant(u32 mkey)
1105 {
1106 return mkey & 0xff;
1107 }
1108
1109 /* Async-atomic event notifier used by mlx5 core to forward FW
1110 * evetns received from event queue to mlx5 consumers.
1111 * Optimise event queue dipatching.
1112 */
1113 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1114 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1115
1116 /* Async-atomic event notifier used for forwarding
1117 * evetns from the event queue into the to mlx5 events dispatcher,
1118 * eswitch, clock and others.
1119 */
1120 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1121 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1122
1123 /* Blocking event notifier used to forward SW events, used for slow path */
1124 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1125 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1126 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1127 void *data);
1128
1129 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1130
1131 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1132 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1133 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1134 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1135 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1136 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1137 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1138 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1139 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1140 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1141 struct net_device *slave);
1142 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1143 u64 *values,
1144 int num_counters,
1145 size_t *offsets);
1146 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1147
1148 #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1149 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1150 peer; \
1151 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1152
1153 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1154 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1155 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1156 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1157 u64 length, u32 log_alignment, u16 uid,
1158 phys_addr_t *addr, u32 *obj_id);
1159 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1160 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1161
1162 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1163 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1164
1165 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1166 int vf_id,
1167 struct notifier_block *nb);
1168 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1169 int vf_id,
1170 struct notifier_block *nb);
1171 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1172 struct ib_device *device,
1173 struct rdma_netdev_alloc_params *params);
1174
1175 enum {
1176 MLX5_PCI_DEV_IS_VF = 1 << 0,
1177 };
1178
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1179 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1180 {
1181 return dev->coredev_type == MLX5_COREDEV_PF;
1182 }
1183
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1184 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1185 {
1186 return dev->coredev_type == MLX5_COREDEV_VF;
1187 }
1188
mlx5_core_same_coredev_type(const struct mlx5_core_dev * dev1,const struct mlx5_core_dev * dev2)1189 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1190 const struct mlx5_core_dev *dev2)
1191 {
1192 return dev1->coredev_type == dev2->coredev_type;
1193 }
1194
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1195 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1196 {
1197 return dev->caps.embedded_cpu;
1198 }
1199
1200 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1201 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1202 {
1203 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1204 }
1205
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1206 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1207 {
1208 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1209 }
1210
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1211 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1212 {
1213 return dev->priv.sriov.max_vfs;
1214 }
1215
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1216 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1217 {
1218 /* LACP owner conditions:
1219 * 1) Function is physical.
1220 * 2) LAG is supported by FW.
1221 * 3) LAG is managed by driver (currently the only option).
1222 */
1223 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1224 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1225 MLX5_CAP_GEN(dev, lag_master);
1226 }
1227
mlx5_core_max_ec_vfs(const struct mlx5_core_dev * dev)1228 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1229 {
1230 return dev->priv.sriov.max_ec_vfs;
1231 }
1232
mlx5_get_gid_table_len(u16 param)1233 static inline int mlx5_get_gid_table_len(u16 param)
1234 {
1235 if (param > 4) {
1236 pr_warn("gid table length is zero\n");
1237 return 0;
1238 }
1239
1240 return 8 * (1 << param);
1241 }
1242
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1243 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1244 {
1245 return !!(dev->priv.rl_table.max_size);
1246 }
1247
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1248 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1249 {
1250 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1251 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1252 }
1253
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1254 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1255 {
1256 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1257 }
1258
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1259 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1260 {
1261 return mlx5_core_is_mp_slave(dev) ||
1262 mlx5_core_is_mp_master(dev);
1263 }
1264
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1265 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1266 {
1267 if (!mlx5_core_mp_enabled(dev))
1268 return 1;
1269
1270 return MLX5_CAP_GEN(dev, native_port_num);
1271 }
1272
mlx5_get_dev_index(struct mlx5_core_dev * dev)1273 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1274 {
1275 int idx = MLX5_CAP_GEN(dev, native_port_num);
1276
1277 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1278 return idx - 1;
1279 else
1280 return PCI_FUNC(dev->pdev->devfn);
1281 }
1282
1283 enum {
1284 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1285 };
1286
1287 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1288
mlx5_get_roce_state(struct mlx5_core_dev * dev)1289 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1290 {
1291 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1292 return MLX5_CAP_GEN(dev, roce);
1293
1294 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1295 * in order to support RoCE enable/disable feature
1296 */
1297 return mlx5_is_roce_on(dev);
1298 }
1299
1300 #ifdef CONFIG_MLX5_MACSEC
mlx5e_is_macsec_device(const struct mlx5_core_dev * mdev)1301 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1302 {
1303 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1304 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1305 return false;
1306
1307 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1308 return false;
1309
1310 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1311 return false;
1312
1313 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1314 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1315 return false;
1316
1317 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1318 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1319 return false;
1320
1321 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1322 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1323 return false;
1324
1325 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1326 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1327 return false;
1328
1329 return true;
1330 }
1331
1332 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1333
mlx5_is_macsec_roce_supported(struct mlx5_core_dev * mdev)1334 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1335 {
1336 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1337 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1338 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1339 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1340 return false;
1341
1342 return true;
1343 }
1344 #endif
1345
1346 enum {
1347 MLX5_OCTWORD = 16,
1348 };
1349
1350 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1351 #endif /* MLX5_DRIVER_H */
1352