1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef __ICP_QAT_FW_LOADER_HANDLE_H__ 4 #define __ICP_QAT_FW_LOADER_HANDLE_H__ 5 #include "icp_qat_uclo.h" 6 7 struct icp_qat_fw_loader_ae_data { 8 unsigned int state; 9 unsigned int ustore_size; 10 unsigned int free_addr; 11 unsigned int free_size; 12 unsigned int live_ctx_mask; 13 }; 14 15 struct icp_qat_fw_loader_hal_handle { 16 struct icp_qat_fw_loader_ae_data aes[ICP_QAT_UCLO_MAX_AE]; 17 unsigned int ae_mask; 18 unsigned int admin_ae_mask; 19 unsigned int slice_mask; 20 unsigned int revision_id; 21 unsigned int ae_max_num; 22 unsigned int upc_mask; 23 unsigned int max_ustore; 24 }; 25 26 struct icp_qat_fw_loader_handle { 27 struct icp_qat_fw_loader_hal_handle *hal_handle; 28 struct adf_accel_dev *accel_dev; 29 device_t pci_dev; 30 void *obj_handle; 31 void *sobj_handle; 32 void *mobj_handle; 33 bool fw_auth; 34 unsigned int cfg_ae_mask; 35 rman_res_t hal_sram_size; 36 struct resource *hal_sram_addr_v; 37 unsigned int hal_sram_offset; 38 struct resource *hal_misc_addr_v; 39 uintptr_t hal_cap_g_ctl_csr_addr_v; 40 uintptr_t hal_cap_ae_xfer_csr_addr_v; 41 uintptr_t hal_cap_ae_local_csr_addr_v; 42 uintptr_t hal_ep_csr_addr_v; 43 }; 44 45 struct icp_firml_dram_desc { 46 struct bus_dmamem dram_mem; 47 48 struct resource *dram_base_addr; 49 void *dram_base_addr_v; 50 bus_addr_t dram_bus_addr; 51 u64 dram_size; 52 }; 53 #endif 54