1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_fb_helper.h> 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "atom.h" 36 37 #include <linux/vga_switcheroo.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pci.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 #include "amdgpu_gem.h" 44 #include "amdgpu_display.h" 45 #include "amdgpu_ras.h" 46 #include "amdgpu_reset.h" 47 #include "amd_pcie.h" 48 #include "amdgpu_userq.h" 49 50 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 51 { 52 struct amdgpu_gpu_instance *gpu_instance; 53 int i; 54 55 mutex_lock(&mgpu_info.mutex); 56 57 for (i = 0; i < mgpu_info.num_gpu; i++) { 58 gpu_instance = &(mgpu_info.gpu_ins[i]); 59 if (gpu_instance->adev == adev) { 60 mgpu_info.gpu_ins[i] = 61 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 62 mgpu_info.num_gpu--; 63 if (adev->flags & AMD_IS_APU) 64 mgpu_info.num_apu--; 65 else 66 mgpu_info.num_dgpu--; 67 break; 68 } 69 } 70 71 mutex_unlock(&mgpu_info.mutex); 72 } 73 74 /** 75 * amdgpu_driver_unload_kms - Main unload function for KMS. 76 * 77 * @dev: drm dev pointer 78 * 79 * This is the main unload function for KMS (all asics). 80 * Returns 0 on success. 81 */ 82 void amdgpu_driver_unload_kms(struct drm_device *dev) 83 { 84 struct amdgpu_device *adev = drm_to_adev(dev); 85 86 if (adev == NULL) 87 return; 88 89 amdgpu_unregister_gpu_instance(adev); 90 91 if (adev->rmmio == NULL) 92 return; 93 94 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) 95 drm_warn(dev, "smart shift update failed\n"); 96 97 amdgpu_acpi_fini(adev); 98 amdgpu_device_fini_hw(adev); 99 } 100 101 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 102 { 103 struct amdgpu_gpu_instance *gpu_instance; 104 105 mutex_lock(&mgpu_info.mutex); 106 107 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 108 drm_err(adev_to_drm(adev), "Cannot register more gpu instance\n"); 109 mutex_unlock(&mgpu_info.mutex); 110 return; 111 } 112 113 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 114 gpu_instance->adev = adev; 115 gpu_instance->mgpu_fan_enabled = 0; 116 117 mgpu_info.num_gpu++; 118 if (adev->flags & AMD_IS_APU) 119 mgpu_info.num_apu++; 120 else 121 mgpu_info.num_dgpu++; 122 123 mutex_unlock(&mgpu_info.mutex); 124 } 125 126 /** 127 * amdgpu_driver_load_kms - Main load function for KMS. 128 * 129 * @adev: pointer to struct amdgpu_device 130 * @flags: device flags 131 * 132 * This is the main load function for KMS (all asics). 133 * Returns 0 on success, error on failure. 134 */ 135 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 136 { 137 struct drm_device *dev; 138 int r, acpi_status; 139 140 dev = adev_to_drm(adev); 141 142 /* amdgpu_device_init should report only fatal error 143 * like memory allocation failure or iomapping failure, 144 * or memory manager initialization failure, it must 145 * properly initialize the GPU MC controller and permit 146 * VRAM allocation 147 */ 148 r = amdgpu_device_init(adev, flags); 149 if (r) { 150 dev_err(dev->dev, "Fatal error during GPU init\n"); 151 goto out; 152 } 153 154 amdgpu_device_detect_runtime_pm_mode(adev); 155 156 /* Call ACPI methods: require modeset init 157 * but failure is not fatal 158 */ 159 160 acpi_status = amdgpu_acpi_init(adev); 161 if (acpi_status) 162 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 163 164 if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) 165 drm_warn(dev, "smart shift update failed\n"); 166 167 out: 168 if (r) 169 amdgpu_driver_unload_kms(dev); 170 171 return r; 172 } 173 174 static enum amd_ip_block_type 175 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) 176 { 177 enum amd_ip_block_type type; 178 179 switch (ip) { 180 case AMDGPU_HW_IP_GFX: 181 type = AMD_IP_BLOCK_TYPE_GFX; 182 break; 183 case AMDGPU_HW_IP_COMPUTE: 184 type = AMD_IP_BLOCK_TYPE_GFX; 185 break; 186 case AMDGPU_HW_IP_DMA: 187 type = AMD_IP_BLOCK_TYPE_SDMA; 188 break; 189 case AMDGPU_HW_IP_UVD: 190 case AMDGPU_HW_IP_UVD_ENC: 191 type = AMD_IP_BLOCK_TYPE_UVD; 192 break; 193 case AMDGPU_HW_IP_VCE: 194 type = AMD_IP_BLOCK_TYPE_VCE; 195 break; 196 case AMDGPU_HW_IP_VCN_DEC: 197 case AMDGPU_HW_IP_VCN_ENC: 198 type = AMD_IP_BLOCK_TYPE_VCN; 199 break; 200 case AMDGPU_HW_IP_VCN_JPEG: 201 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 202 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 203 break; 204 case AMDGPU_HW_IP_VPE: 205 type = AMD_IP_BLOCK_TYPE_VPE; 206 break; 207 default: 208 type = AMD_IP_BLOCK_TYPE_NUM; 209 break; 210 } 211 212 return type; 213 } 214 215 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 216 struct drm_amdgpu_query_fw *query_fw, 217 struct amdgpu_device *adev) 218 { 219 switch (query_fw->fw_type) { 220 case AMDGPU_INFO_FW_VCE: 221 fw_info->ver = adev->vce.fw_version; 222 fw_info->feature = adev->vce.fb_version; 223 break; 224 case AMDGPU_INFO_FW_UVD: 225 fw_info->ver = adev->uvd.fw_version; 226 fw_info->feature = 0; 227 break; 228 case AMDGPU_INFO_FW_VCN: 229 fw_info->ver = adev->vcn.fw_version; 230 fw_info->feature = 0; 231 break; 232 case AMDGPU_INFO_FW_GMC: 233 fw_info->ver = adev->gmc.fw_version; 234 fw_info->feature = 0; 235 break; 236 case AMDGPU_INFO_FW_GFX_ME: 237 fw_info->ver = adev->gfx.me_fw_version; 238 fw_info->feature = adev->gfx.me_feature_version; 239 break; 240 case AMDGPU_INFO_FW_GFX_PFP: 241 fw_info->ver = adev->gfx.pfp_fw_version; 242 fw_info->feature = adev->gfx.pfp_feature_version; 243 break; 244 case AMDGPU_INFO_FW_GFX_CE: 245 fw_info->ver = adev->gfx.ce_fw_version; 246 fw_info->feature = adev->gfx.ce_feature_version; 247 break; 248 case AMDGPU_INFO_FW_GFX_RLC: 249 fw_info->ver = adev->gfx.rlc_fw_version; 250 fw_info->feature = adev->gfx.rlc_feature_version; 251 break; 252 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 253 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 254 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 255 break; 256 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 257 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 258 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 259 break; 260 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 261 fw_info->ver = adev->gfx.rlc_srls_fw_version; 262 fw_info->feature = adev->gfx.rlc_srls_feature_version; 263 break; 264 case AMDGPU_INFO_FW_GFX_RLCP: 265 fw_info->ver = adev->gfx.rlcp_ucode_version; 266 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 267 break; 268 case AMDGPU_INFO_FW_GFX_RLCV: 269 fw_info->ver = adev->gfx.rlcv_ucode_version; 270 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 271 break; 272 case AMDGPU_INFO_FW_GFX_MEC: 273 if (query_fw->index == 0) { 274 fw_info->ver = adev->gfx.mec_fw_version; 275 fw_info->feature = adev->gfx.mec_feature_version; 276 } else if (query_fw->index == 1) { 277 fw_info->ver = adev->gfx.mec2_fw_version; 278 fw_info->feature = adev->gfx.mec2_feature_version; 279 } else 280 return -EINVAL; 281 break; 282 case AMDGPU_INFO_FW_SMC: 283 fw_info->ver = adev->pm.fw_version; 284 fw_info->feature = 0; 285 break; 286 case AMDGPU_INFO_FW_TA: 287 switch (query_fw->index) { 288 case TA_FW_TYPE_PSP_XGMI: 289 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 290 fw_info->feature = adev->psp.xgmi_context.context 291 .bin_desc.feature_version; 292 break; 293 case TA_FW_TYPE_PSP_RAS: 294 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 295 fw_info->feature = adev->psp.ras_context.context 296 .bin_desc.feature_version; 297 break; 298 case TA_FW_TYPE_PSP_HDCP: 299 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 300 fw_info->feature = adev->psp.hdcp_context.context 301 .bin_desc.feature_version; 302 break; 303 case TA_FW_TYPE_PSP_DTM: 304 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 305 fw_info->feature = adev->psp.dtm_context.context 306 .bin_desc.feature_version; 307 break; 308 case TA_FW_TYPE_PSP_RAP: 309 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 310 fw_info->feature = adev->psp.rap_context.context 311 .bin_desc.feature_version; 312 break; 313 case TA_FW_TYPE_PSP_SECUREDISPLAY: 314 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 315 fw_info->feature = 316 adev->psp.securedisplay_context.context.bin_desc 317 .feature_version; 318 break; 319 default: 320 return -EINVAL; 321 } 322 break; 323 case AMDGPU_INFO_FW_SDMA: 324 if (query_fw->index >= adev->sdma.num_instances) 325 return -EINVAL; 326 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 327 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 328 break; 329 case AMDGPU_INFO_FW_SOS: 330 fw_info->ver = adev->psp.sos.fw_version; 331 fw_info->feature = adev->psp.sos.feature_version; 332 break; 333 case AMDGPU_INFO_FW_ASD: 334 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 335 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 336 break; 337 case AMDGPU_INFO_FW_DMCU: 338 fw_info->ver = adev->dm.dmcu_fw_version; 339 fw_info->feature = 0; 340 break; 341 case AMDGPU_INFO_FW_DMCUB: 342 fw_info->ver = adev->dm.dmcub_fw_version; 343 fw_info->feature = 0; 344 break; 345 case AMDGPU_INFO_FW_TOC: 346 fw_info->ver = adev->psp.toc.fw_version; 347 fw_info->feature = adev->psp.toc.feature_version; 348 break; 349 case AMDGPU_INFO_FW_CAP: 350 fw_info->ver = adev->psp.cap_fw_version; 351 fw_info->feature = adev->psp.cap_feature_version; 352 break; 353 case AMDGPU_INFO_FW_MES_KIQ: 354 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 355 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 356 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 357 break; 358 case AMDGPU_INFO_FW_MES: 359 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 360 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 361 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 362 break; 363 case AMDGPU_INFO_FW_IMU: 364 fw_info->ver = adev->gfx.imu_fw_version; 365 fw_info->feature = 0; 366 break; 367 case AMDGPU_INFO_FW_VPE: 368 fw_info->ver = adev->vpe.fw_version; 369 fw_info->feature = adev->vpe.feature_version; 370 break; 371 default: 372 return -EINVAL; 373 } 374 return 0; 375 } 376 377 static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, 378 struct drm_amdgpu_info *info, 379 struct drm_amdgpu_info_uq_metadata_gfx *meta) 380 { 381 int ret = -EOPNOTSUPP; 382 383 if (adev->gfx.funcs->get_gfx_shadow_info) { 384 struct amdgpu_gfx_shadow_info shadow = {}; 385 386 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 387 meta->shadow_size = shadow.shadow_size; 388 meta->shadow_alignment = shadow.shadow_alignment; 389 meta->csa_size = shadow.csa_size; 390 meta->csa_alignment = shadow.csa_alignment; 391 ret = 0; 392 } 393 394 return ret; 395 } 396 397 static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, 398 struct drm_amdgpu_info *info, 399 struct drm_amdgpu_info_uq_metadata_compute *meta) 400 { 401 int ret = -EOPNOTSUPP; 402 403 if (adev->gfx.funcs->get_gfx_shadow_info) { 404 struct amdgpu_gfx_shadow_info shadow = {}; 405 406 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); 407 meta->eop_size = shadow.eop_size; 408 meta->eop_alignment = shadow.eop_alignment; 409 ret = 0; 410 } 411 412 return ret; 413 } 414 415 static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, 416 struct drm_amdgpu_info *info, 417 struct drm_amdgpu_info_uq_metadata_sdma *meta) 418 { 419 int ret = -EOPNOTSUPP; 420 421 if (adev->sdma.get_csa_info) { 422 struct amdgpu_sdma_csa_info csa = {}; 423 424 adev->sdma.get_csa_info(adev, &csa); 425 meta->csa_size = csa.size; 426 meta->csa_alignment = csa.alignment; 427 ret = 0; 428 } 429 430 return ret; 431 } 432 433 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 434 struct drm_amdgpu_info *info, 435 struct drm_amdgpu_info_hw_ip *result) 436 { 437 uint32_t ib_start_alignment = 0; 438 uint32_t ib_size_alignment = 0; 439 enum amd_ip_block_type type; 440 unsigned int num_rings = 0; 441 uint32_t num_slots = 0; 442 unsigned int i, j; 443 444 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 445 return -EINVAL; 446 447 switch (info->query_hw_ip.type) { 448 case AMDGPU_HW_IP_GFX: 449 type = AMD_IP_BLOCK_TYPE_GFX; 450 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 451 if (adev->gfx.gfx_ring[i].sched.ready && 452 !adev->gfx.gfx_ring[i].no_user_submission) 453 ++num_rings; 454 455 if (!adev->gfx.disable_uq) { 456 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) 457 num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); 458 } 459 460 ib_start_alignment = 32; 461 ib_size_alignment = 32; 462 break; 463 case AMDGPU_HW_IP_COMPUTE: 464 type = AMD_IP_BLOCK_TYPE_GFX; 465 for (i = 0; i < adev->gfx.num_compute_rings; i++) 466 if (adev->gfx.compute_ring[i].sched.ready && 467 !adev->gfx.compute_ring[i].no_user_submission) 468 ++num_rings; 469 470 if (!adev->sdma.disable_uq) { 471 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) 472 num_slots += hweight32(adev->mes.compute_hqd_mask[i]); 473 } 474 475 ib_start_alignment = 32; 476 ib_size_alignment = 32; 477 break; 478 case AMDGPU_HW_IP_DMA: 479 type = AMD_IP_BLOCK_TYPE_SDMA; 480 for (i = 0; i < adev->sdma.num_instances; i++) 481 if (adev->sdma.instance[i].ring.sched.ready && 482 !adev->sdma.instance[i].ring.no_user_submission) 483 ++num_rings; 484 485 if (!adev->gfx.disable_uq) { 486 for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) 487 num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); 488 } 489 490 ib_start_alignment = 256; 491 ib_size_alignment = 4; 492 break; 493 case AMDGPU_HW_IP_UVD: 494 type = AMD_IP_BLOCK_TYPE_UVD; 495 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 496 if (adev->uvd.harvest_config & (1 << i)) 497 continue; 498 499 if (adev->uvd.inst[i].ring.sched.ready && 500 !adev->uvd.inst[i].ring.no_user_submission) 501 ++num_rings; 502 } 503 ib_start_alignment = 256; 504 ib_size_alignment = 64; 505 break; 506 case AMDGPU_HW_IP_VCE: 507 type = AMD_IP_BLOCK_TYPE_VCE; 508 for (i = 0; i < adev->vce.num_rings; i++) 509 if (adev->vce.ring[i].sched.ready && 510 !adev->vce.ring[i].no_user_submission) 511 ++num_rings; 512 ib_start_alignment = 256; 513 ib_size_alignment = 4; 514 break; 515 case AMDGPU_HW_IP_UVD_ENC: 516 type = AMD_IP_BLOCK_TYPE_UVD; 517 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 518 if (adev->uvd.harvest_config & (1 << i)) 519 continue; 520 521 for (j = 0; j < adev->uvd.num_enc_rings; j++) 522 if (adev->uvd.inst[i].ring_enc[j].sched.ready && 523 !adev->uvd.inst[i].ring_enc[j].no_user_submission) 524 ++num_rings; 525 } 526 ib_start_alignment = 256; 527 ib_size_alignment = 4; 528 break; 529 case AMDGPU_HW_IP_VCN_DEC: 530 type = AMD_IP_BLOCK_TYPE_VCN; 531 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 532 if (adev->vcn.harvest_config & (1 << i)) 533 continue; 534 535 if (adev->vcn.inst[i].ring_dec.sched.ready && 536 !adev->vcn.inst[i].ring_dec.no_user_submission) 537 ++num_rings; 538 } 539 ib_start_alignment = 256; 540 ib_size_alignment = 64; 541 break; 542 case AMDGPU_HW_IP_VCN_ENC: 543 type = AMD_IP_BLOCK_TYPE_VCN; 544 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 545 if (adev->vcn.harvest_config & (1 << i)) 546 continue; 547 548 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; j++) 549 if (adev->vcn.inst[i].ring_enc[j].sched.ready && 550 !adev->vcn.inst[i].ring_enc[j].no_user_submission) 551 ++num_rings; 552 } 553 ib_start_alignment = 256; 554 ib_size_alignment = 4; 555 break; 556 case AMDGPU_HW_IP_VCN_JPEG: 557 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 558 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 559 560 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 561 if (adev->jpeg.harvest_config & (1 << i)) 562 continue; 563 564 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) 565 if (adev->jpeg.inst[i].ring_dec[j].sched.ready && 566 !adev->jpeg.inst[i].ring_dec[j].no_user_submission) 567 ++num_rings; 568 } 569 ib_start_alignment = 256; 570 ib_size_alignment = 64; 571 break; 572 case AMDGPU_HW_IP_VPE: 573 type = AMD_IP_BLOCK_TYPE_VPE; 574 if (adev->vpe.ring.sched.ready && 575 !adev->vpe.ring.no_user_submission) 576 ++num_rings; 577 ib_start_alignment = 256; 578 ib_size_alignment = 4; 579 break; 580 default: 581 return -EINVAL; 582 } 583 584 for (i = 0; i < adev->num_ip_blocks; i++) 585 if (adev->ip_blocks[i].version->type == type && 586 adev->ip_blocks[i].status.valid) 587 break; 588 589 if (i == adev->num_ip_blocks) 590 return 0; 591 592 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 593 num_rings); 594 595 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 596 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 597 598 if (adev->asic_type >= CHIP_VEGA10) { 599 switch (type) { 600 case AMD_IP_BLOCK_TYPE_GFX: 601 result->ip_discovery_version = 602 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0)); 603 break; 604 case AMD_IP_BLOCK_TYPE_SDMA: 605 result->ip_discovery_version = 606 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 607 break; 608 case AMD_IP_BLOCK_TYPE_UVD: 609 case AMD_IP_BLOCK_TYPE_VCN: 610 case AMD_IP_BLOCK_TYPE_JPEG: 611 result->ip_discovery_version = 612 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0)); 613 break; 614 case AMD_IP_BLOCK_TYPE_VCE: 615 result->ip_discovery_version = 616 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0)); 617 break; 618 case AMD_IP_BLOCK_TYPE_VPE: 619 result->ip_discovery_version = 620 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0)); 621 break; 622 default: 623 result->ip_discovery_version = 0; 624 break; 625 } 626 } else { 627 result->ip_discovery_version = 0; 628 } 629 result->capabilities_flags = 0; 630 result->available_rings = (1 << num_rings) - 1; 631 result->userq_num_slots = num_slots; 632 result->ib_start_alignment = ib_start_alignment; 633 result->ib_size_alignment = ib_size_alignment; 634 return 0; 635 } 636 637 /* 638 * Userspace get information ioctl 639 */ 640 /** 641 * amdgpu_info_ioctl - answer a device specific request. 642 * 643 * @dev: drm device pointer 644 * @data: request object 645 * @filp: drm filp 646 * 647 * This function is used to pass device specific parameters to the userspace 648 * drivers. Examples include: pci device id, pipeline parms, tiling params, 649 * etc. (all asics). 650 * Returns 0 on success, -EINVAL on failure. 651 */ 652 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 653 { 654 struct amdgpu_device *adev = drm_to_adev(dev); 655 struct drm_amdgpu_info *info = data; 656 struct amdgpu_mode_info *minfo = &adev->mode_info; 657 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 658 struct amdgpu_fpriv *fpriv; 659 struct amdgpu_ip_block *ip_block; 660 enum amd_ip_block_type type; 661 struct amdgpu_xcp *xcp; 662 u32 count, inst_mask; 663 uint32_t size = info->return_size; 664 struct drm_crtc *crtc; 665 uint32_t ui32 = 0; 666 uint64_t ui64 = 0; 667 int i, found, ret; 668 int ui32_size = sizeof(ui32); 669 670 if (!info->return_size || !info->return_pointer) 671 return -EINVAL; 672 673 switch (info->query) { 674 case AMDGPU_INFO_ACCEL_WORKING: 675 ui32 = adev->accel_working; 676 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 677 case AMDGPU_INFO_CRTC_FROM_ID: 678 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 679 crtc = (struct drm_crtc *)minfo->crtcs[i]; 680 if (crtc && crtc->base.id == info->mode_crtc.id) { 681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 682 683 ui32 = amdgpu_crtc->crtc_id; 684 found = 1; 685 break; 686 } 687 } 688 if (!found) { 689 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 690 return -EINVAL; 691 } 692 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 693 case AMDGPU_INFO_HW_IP_INFO: { 694 struct drm_amdgpu_info_hw_ip ip = {}; 695 696 ret = amdgpu_hw_ip_info(adev, info, &ip); 697 if (ret) 698 return ret; 699 700 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 701 return ret ? -EFAULT : 0; 702 } 703 case AMDGPU_INFO_HW_IP_COUNT: { 704 fpriv = (struct amdgpu_fpriv *)filp->driver_priv; 705 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type); 706 ip_block = amdgpu_device_ip_get_ip_block(adev, type); 707 708 if (!ip_block || !ip_block->status.valid) 709 return -EINVAL; 710 711 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 && 712 fpriv->xcp_id < adev->xcp_mgr->num_xcps) { 713 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id]; 714 switch (type) { 715 case AMD_IP_BLOCK_TYPE_GFX: 716 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); 717 if (ret) 718 return ret; 719 count = hweight32(inst_mask); 720 break; 721 case AMD_IP_BLOCK_TYPE_SDMA: 722 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask); 723 if (ret) 724 return ret; 725 count = hweight32(inst_mask); 726 break; 727 case AMD_IP_BLOCK_TYPE_JPEG: 728 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 729 if (ret) 730 return ret; 731 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings; 732 break; 733 case AMD_IP_BLOCK_TYPE_VCN: 734 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); 735 if (ret) 736 return ret; 737 count = hweight32(inst_mask); 738 break; 739 default: 740 return -EINVAL; 741 } 742 743 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 744 } 745 746 switch (type) { 747 case AMD_IP_BLOCK_TYPE_GFX: 748 case AMD_IP_BLOCK_TYPE_VCE: 749 count = 1; 750 break; 751 case AMD_IP_BLOCK_TYPE_SDMA: 752 count = adev->sdma.num_instances; 753 break; 754 case AMD_IP_BLOCK_TYPE_JPEG: 755 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings; 756 break; 757 case AMD_IP_BLOCK_TYPE_VCN: 758 count = adev->vcn.num_vcn_inst; 759 break; 760 case AMD_IP_BLOCK_TYPE_UVD: 761 count = adev->uvd.num_uvd_inst; 762 break; 763 case AMD_IP_BLOCK_TYPE_VPE: 764 count = adev->vpe.num_instances; 765 break; 766 /* For all other IP block types not listed in the switch statement 767 * the ip status is valid here and the instance count is one. 768 */ 769 default: 770 count = 1; 771 break; 772 } 773 774 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 775 } 776 case AMDGPU_INFO_TIMESTAMP: 777 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 778 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 779 case AMDGPU_INFO_FW_VERSION: { 780 struct drm_amdgpu_info_firmware fw_info; 781 782 /* We only support one instance of each IP block right now. */ 783 if (info->query_fw.ip_instance != 0) 784 return -EINVAL; 785 786 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 787 if (ret) 788 return ret; 789 790 return copy_to_user(out, &fw_info, 791 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 792 } 793 case AMDGPU_INFO_NUM_BYTES_MOVED: 794 ui64 = atomic64_read(&adev->num_bytes_moved); 795 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 796 case AMDGPU_INFO_NUM_EVICTIONS: 797 ui64 = atomic64_read(&adev->num_evictions); 798 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 799 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 800 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 801 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 802 case AMDGPU_INFO_VRAM_USAGE: 803 ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 804 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; 805 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 806 case AMDGPU_INFO_VIS_VRAM_USAGE: 807 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 808 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 809 case AMDGPU_INFO_GTT_USAGE: 810 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 811 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 812 case AMDGPU_INFO_GDS_CONFIG: { 813 struct drm_amdgpu_info_gds gds_info; 814 815 memset(&gds_info, 0, sizeof(gds_info)); 816 gds_info.compute_partition_size = adev->gds.gds_size; 817 gds_info.gds_total_size = adev->gds.gds_size; 818 gds_info.gws_per_compute_partition = adev->gds.gws_size; 819 gds_info.oa_per_compute_partition = adev->gds.oa_size; 820 return copy_to_user(out, &gds_info, 821 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 822 } 823 case AMDGPU_INFO_VRAM_GTT: { 824 struct drm_amdgpu_info_vram_gtt vram_gtt; 825 826 vram_gtt.vram_size = adev->gmc.real_vram_size - 827 atomic64_read(&adev->vram_pin_size) - 828 AMDGPU_VM_RESERVED_VRAM; 829 vram_gtt.vram_cpu_accessible_size = 830 min(adev->gmc.visible_vram_size - 831 atomic64_read(&adev->visible_pin_size), 832 vram_gtt.vram_size); 833 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 834 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 835 return copy_to_user(out, &vram_gtt, 836 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 837 } 838 case AMDGPU_INFO_MEMORY: { 839 struct drm_amdgpu_memory_info mem; 840 struct ttm_resource_manager *gtt_man = 841 &adev->mman.gtt_mgr.manager; 842 struct ttm_resource_manager *vram_man = 843 &adev->mman.vram_mgr.manager; 844 845 memset(&mem, 0, sizeof(mem)); 846 mem.vram.total_heap_size = adev->gmc.real_vram_size; 847 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 848 atomic64_read(&adev->vram_pin_size) - 849 AMDGPU_VM_RESERVED_VRAM; 850 mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? 851 ttm_resource_manager_usage(vram_man) : 0; 852 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 853 854 mem.cpu_accessible_vram.total_heap_size = 855 adev->gmc.visible_vram_size; 856 mem.cpu_accessible_vram.usable_heap_size = 857 min(adev->gmc.visible_vram_size - 858 atomic64_read(&adev->visible_pin_size), 859 mem.vram.usable_heap_size); 860 mem.cpu_accessible_vram.heap_usage = 861 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 862 mem.cpu_accessible_vram.max_allocation = 863 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 864 865 mem.gtt.total_heap_size = gtt_man->size; 866 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 867 atomic64_read(&adev->gart_pin_size); 868 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 869 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 870 871 return copy_to_user(out, &mem, 872 min((size_t)size, sizeof(mem))) 873 ? -EFAULT : 0; 874 } 875 case AMDGPU_INFO_READ_MMR_REG: { 876 int ret = 0; 877 unsigned int n, alloc_size; 878 uint32_t *regs; 879 unsigned int se_num = (info->read_mmr_reg.instance >> 880 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 881 AMDGPU_INFO_MMR_SE_INDEX_MASK; 882 unsigned int sh_num = (info->read_mmr_reg.instance >> 883 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 884 AMDGPU_INFO_MMR_SH_INDEX_MASK; 885 886 if (!down_read_trylock(&adev->reset_domain->sem)) 887 return -ENOENT; 888 889 /* set full masks if the userspace set all bits 890 * in the bitfields 891 */ 892 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) { 893 se_num = 0xffffffff; 894 } else if (se_num >= AMDGPU_GFX_MAX_SE) { 895 ret = -EINVAL; 896 goto out; 897 } 898 899 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) { 900 sh_num = 0xffffffff; 901 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) { 902 ret = -EINVAL; 903 goto out; 904 } 905 906 if (info->read_mmr_reg.count > 128) { 907 ret = -EINVAL; 908 goto out; 909 } 910 911 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 912 if (!regs) { 913 ret = -ENOMEM; 914 goto out; 915 } 916 917 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 918 919 amdgpu_gfx_off_ctrl(adev, false); 920 for (i = 0; i < info->read_mmr_reg.count; i++) { 921 if (amdgpu_asic_read_register(adev, se_num, sh_num, 922 info->read_mmr_reg.dword_offset + i, 923 ®s[i])) { 924 DRM_DEBUG_KMS("unallowed offset %#x\n", 925 info->read_mmr_reg.dword_offset + i); 926 kfree(regs); 927 amdgpu_gfx_off_ctrl(adev, true); 928 ret = -EFAULT; 929 goto out; 930 } 931 } 932 amdgpu_gfx_off_ctrl(adev, true); 933 n = copy_to_user(out, regs, min(size, alloc_size)); 934 kfree(regs); 935 ret = (n ? -EFAULT : 0); 936 out: 937 up_read(&adev->reset_domain->sem); 938 return ret; 939 } 940 case AMDGPU_INFO_DEV_INFO: { 941 struct drm_amdgpu_info_device *dev_info; 942 uint64_t vm_size; 943 uint32_t pcie_gen_mask, pcie_width_mask; 944 945 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 946 if (!dev_info) 947 return -ENOMEM; 948 949 dev_info->device_id = adev->pdev->device; 950 dev_info->chip_rev = adev->rev_id; 951 dev_info->external_rev = adev->external_rev_id; 952 dev_info->pci_rev = adev->pdev->revision; 953 dev_info->family = adev->family; 954 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 955 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 956 /* return all clocks in KHz */ 957 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 958 if (adev->pm.dpm_enabled) { 959 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 960 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 961 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; 962 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; 963 } else { 964 dev_info->max_engine_clock = 965 dev_info->min_engine_clock = 966 adev->clock.default_sclk * 10; 967 dev_info->max_memory_clock = 968 dev_info->min_memory_clock = 969 adev->clock.default_mclk * 10; 970 } 971 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 972 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 973 adev->gfx.config.max_shader_engines; 974 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 975 dev_info->ids_flags = 0; 976 if (adev->flags & AMD_IS_APU) 977 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 978 if (adev->gfx.mcbp) 979 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 980 if (amdgpu_is_tmz(adev)) 981 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 982 if (adev->gfx.config.ta_cntl2_truncate_coord_mode) 983 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; 984 985 /* Gang submit is not supported under SRIOV currently */ 986 if (!amdgpu_sriov_vf(adev)) 987 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; 988 989 if (amdgpu_passthrough(adev)) 990 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << 991 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 992 AMDGPU_IDS_FLAGS_MODE_MASK; 993 else if (amdgpu_sriov_vf(adev)) 994 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << 995 AMDGPU_IDS_FLAGS_MODE_SHIFT) & 996 AMDGPU_IDS_FLAGS_MODE_MASK; 997 998 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 999 vm_size -= AMDGPU_VA_RESERVED_TOP; 1000 1001 /* Older VCE FW versions are buggy and can handle only 40bits */ 1002 if (adev->vce.fw_version && 1003 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 1004 vm_size = min(vm_size, 1ULL << 40); 1005 1006 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; 1007 dev_info->virtual_address_max = 1008 min(vm_size, AMDGPU_GMC_HOLE_START); 1009 1010 if (vm_size > AMDGPU_GMC_HOLE_START) { 1011 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 1012 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 1013 } 1014 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1015 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 1016 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 1017 dev_info->cu_active_number = adev->gfx.cu_info.number; 1018 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 1019 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 1020 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 1021 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 1022 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 1023 sizeof(dev_info->cu_bitmap)); 1024 dev_info->vram_type = adev->gmc.vram_type; 1025 dev_info->vram_bit_width = adev->gmc.vram_width; 1026 dev_info->vce_harvest_config = adev->vce.harvest_config; 1027 dev_info->gc_double_offchip_lds_buf = 1028 adev->gfx.config.double_offchip_lds_buf; 1029 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 1030 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 1031 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 1032 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 1033 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 1034 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 1035 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 1036 1037 if (adev->family >= AMDGPU_FAMILY_NV) 1038 dev_info->pa_sc_tile_steering_override = 1039 adev->gfx.config.pa_sc_tile_steering_override; 1040 1041 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 1042 1043 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ 1044 pcie_gen_mask = adev->pm.pcie_gen_mask & 1045 (adev->pm.pcie_gen_mask >> CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT); 1046 pcie_width_mask = adev->pm.pcie_mlw_mask & 1047 (adev->pm.pcie_mlw_mask >> CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT); 1048 dev_info->pcie_gen = fls(pcie_gen_mask); 1049 dev_info->pcie_num_lanes = 1050 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : 1051 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : 1052 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : 1053 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : 1054 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : 1055 pcie_width_mask & CAIL_ASIC_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; 1056 1057 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; 1058 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; 1059 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; 1060 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; 1061 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * 1062 adev->gfx.config.gc_gl1c_per_sa; 1063 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; 1064 dev_info->mall_size = adev->gmc.mall_size; 1065 1066 1067 if (adev->gfx.funcs->get_gfx_shadow_info) { 1068 struct amdgpu_gfx_shadow_info shadow_info; 1069 1070 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); 1071 if (!ret) { 1072 dev_info->shadow_size = shadow_info.shadow_size; 1073 dev_info->shadow_alignment = shadow_info.shadow_alignment; 1074 dev_info->csa_size = shadow_info.csa_size; 1075 dev_info->csa_alignment = shadow_info.csa_alignment; 1076 } 1077 } 1078 1079 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev); 1080 1081 ret = copy_to_user(out, dev_info, 1082 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 1083 kfree(dev_info); 1084 return ret; 1085 } 1086 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 1087 unsigned int i; 1088 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 1089 struct amd_vce_state *vce_state; 1090 1091 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 1092 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 1093 if (vce_state) { 1094 vce_clk_table.entries[i].sclk = vce_state->sclk; 1095 vce_clk_table.entries[i].mclk = vce_state->mclk; 1096 vce_clk_table.entries[i].eclk = vce_state->evclk; 1097 vce_clk_table.num_valid_entries++; 1098 } 1099 } 1100 1101 return copy_to_user(out, &vce_clk_table, 1102 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 1103 } 1104 case AMDGPU_INFO_VBIOS: { 1105 uint32_t bios_size = adev->bios_size; 1106 1107 switch (info->vbios_info.type) { 1108 case AMDGPU_INFO_VBIOS_SIZE: 1109 return copy_to_user(out, &bios_size, 1110 min((size_t)size, sizeof(bios_size))) 1111 ? -EFAULT : 0; 1112 case AMDGPU_INFO_VBIOS_IMAGE: { 1113 uint8_t *bios; 1114 uint32_t bios_offset = info->vbios_info.offset; 1115 1116 if (bios_offset >= bios_size) 1117 return -EINVAL; 1118 1119 bios = adev->bios + bios_offset; 1120 return copy_to_user(out, bios, 1121 min((size_t)size, (size_t)(bios_size - bios_offset))) 1122 ? -EFAULT : 0; 1123 } 1124 case AMDGPU_INFO_VBIOS_INFO: { 1125 struct drm_amdgpu_info_vbios vbios_info = {}; 1126 struct atom_context *atom_context; 1127 1128 atom_context = adev->mode_info.atom_context; 1129 if (atom_context) { 1130 memcpy(vbios_info.name, atom_context->name, 1131 sizeof(atom_context->name)); 1132 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 1133 sizeof(atom_context->vbios_pn)); 1134 vbios_info.version = atom_context->version; 1135 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 1136 sizeof(atom_context->vbios_ver_str)); 1137 memcpy(vbios_info.date, atom_context->date, 1138 sizeof(atom_context->date)); 1139 } 1140 1141 return copy_to_user(out, &vbios_info, 1142 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 1143 } 1144 default: 1145 DRM_DEBUG_KMS("Invalid request %d\n", 1146 info->vbios_info.type); 1147 return -EINVAL; 1148 } 1149 } 1150 case AMDGPU_INFO_NUM_HANDLES: { 1151 struct drm_amdgpu_info_num_handles handle; 1152 1153 switch (info->query_hw_ip.type) { 1154 case AMDGPU_HW_IP_UVD: 1155 /* Starting Polaris, we support unlimited UVD handles */ 1156 if (adev->asic_type < CHIP_POLARIS10) { 1157 handle.uvd_max_handles = adev->uvd.max_handles; 1158 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 1159 1160 return copy_to_user(out, &handle, 1161 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 1162 } else { 1163 return -ENODATA; 1164 } 1165 1166 break; 1167 default: 1168 return -EINVAL; 1169 } 1170 } 1171 case AMDGPU_INFO_SENSOR: { 1172 if (!adev->pm.dpm_enabled) 1173 return -ENOENT; 1174 1175 switch (info->sensor_info.type) { 1176 case AMDGPU_INFO_SENSOR_GFX_SCLK: 1177 /* get sclk in Mhz */ 1178 if (amdgpu_dpm_read_sensor(adev, 1179 AMDGPU_PP_SENSOR_GFX_SCLK, 1180 (void *)&ui32, &ui32_size)) { 1181 return -EINVAL; 1182 } 1183 ui32 /= 100; 1184 break; 1185 case AMDGPU_INFO_SENSOR_GFX_MCLK: 1186 /* get mclk in Mhz */ 1187 if (amdgpu_dpm_read_sensor(adev, 1188 AMDGPU_PP_SENSOR_GFX_MCLK, 1189 (void *)&ui32, &ui32_size)) { 1190 return -EINVAL; 1191 } 1192 ui32 /= 100; 1193 break; 1194 case AMDGPU_INFO_SENSOR_GPU_TEMP: 1195 /* get temperature in millidegrees C */ 1196 if (amdgpu_dpm_read_sensor(adev, 1197 AMDGPU_PP_SENSOR_GPU_TEMP, 1198 (void *)&ui32, &ui32_size)) { 1199 return -EINVAL; 1200 } 1201 break; 1202 case AMDGPU_INFO_SENSOR_GPU_LOAD: 1203 /* get GPU load */ 1204 if (amdgpu_dpm_read_sensor(adev, 1205 AMDGPU_PP_SENSOR_GPU_LOAD, 1206 (void *)&ui32, &ui32_size)) { 1207 return -EINVAL; 1208 } 1209 break; 1210 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 1211 /* get average GPU power */ 1212 if (amdgpu_dpm_read_sensor(adev, 1213 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 1214 (void *)&ui32, &ui32_size)) { 1215 /* fall back to input power for backwards compat */ 1216 if (amdgpu_dpm_read_sensor(adev, 1217 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1218 (void *)&ui32, &ui32_size)) { 1219 return -EINVAL; 1220 } 1221 } 1222 ui32 >>= 8; 1223 break; 1224 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER: 1225 /* get input GPU power */ 1226 if (amdgpu_dpm_read_sensor(adev, 1227 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 1228 (void *)&ui32, &ui32_size)) { 1229 return -EINVAL; 1230 } 1231 ui32 >>= 8; 1232 break; 1233 case AMDGPU_INFO_SENSOR_VDDNB: 1234 /* get VDDNB in millivolts */ 1235 if (amdgpu_dpm_read_sensor(adev, 1236 AMDGPU_PP_SENSOR_VDDNB, 1237 (void *)&ui32, &ui32_size)) { 1238 return -EINVAL; 1239 } 1240 break; 1241 case AMDGPU_INFO_SENSOR_VDDGFX: 1242 /* get VDDGFX in millivolts */ 1243 if (amdgpu_dpm_read_sensor(adev, 1244 AMDGPU_PP_SENSOR_VDDGFX, 1245 (void *)&ui32, &ui32_size)) { 1246 return -EINVAL; 1247 } 1248 break; 1249 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1250 /* get stable pstate sclk in Mhz */ 1251 if (amdgpu_dpm_read_sensor(adev, 1252 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1253 (void *)&ui32, &ui32_size)) { 1254 return -EINVAL; 1255 } 1256 ui32 /= 100; 1257 break; 1258 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1259 /* get stable pstate mclk in Mhz */ 1260 if (amdgpu_dpm_read_sensor(adev, 1261 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1262 (void *)&ui32, &ui32_size)) { 1263 return -EINVAL; 1264 } 1265 ui32 /= 100; 1266 break; 1267 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: 1268 /* get peak pstate sclk in Mhz */ 1269 if (amdgpu_dpm_read_sensor(adev, 1270 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 1271 (void *)&ui32, &ui32_size)) { 1272 return -EINVAL; 1273 } 1274 ui32 /= 100; 1275 break; 1276 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: 1277 /* get peak pstate mclk in Mhz */ 1278 if (amdgpu_dpm_read_sensor(adev, 1279 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 1280 (void *)&ui32, &ui32_size)) { 1281 return -EINVAL; 1282 } 1283 ui32 /= 100; 1284 break; 1285 default: 1286 DRM_DEBUG_KMS("Invalid request %d\n", 1287 info->sensor_info.type); 1288 return -EINVAL; 1289 } 1290 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1291 } 1292 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1293 ui32 = atomic_read(&adev->vram_lost_counter); 1294 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1295 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1296 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1297 uint64_t ras_mask; 1298 1299 if (!ras) 1300 return -EINVAL; 1301 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1302 1303 return copy_to_user(out, &ras_mask, 1304 min_t(u64, size, sizeof(ras_mask))) ? 1305 -EFAULT : 0; 1306 } 1307 case AMDGPU_INFO_VIDEO_CAPS: { 1308 const struct amdgpu_video_codecs *codecs; 1309 struct drm_amdgpu_info_video_caps *caps; 1310 int r; 1311 1312 if (!adev->asic_funcs->query_video_codecs) 1313 return -EINVAL; 1314 1315 switch (info->video_cap.type) { 1316 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1317 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1318 if (r) 1319 return -EINVAL; 1320 break; 1321 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1322 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1323 if (r) 1324 return -EINVAL; 1325 break; 1326 default: 1327 DRM_DEBUG_KMS("Invalid request %d\n", 1328 info->video_cap.type); 1329 return -EINVAL; 1330 } 1331 1332 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1333 if (!caps) 1334 return -ENOMEM; 1335 1336 for (i = 0; i < codecs->codec_count; i++) { 1337 int idx = codecs->codec_array[i].codec_type; 1338 1339 switch (idx) { 1340 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1341 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1342 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1343 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1344 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1345 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1346 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1347 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1348 caps->codec_info[idx].valid = 1; 1349 caps->codec_info[idx].max_width = 1350 codecs->codec_array[i].max_width; 1351 caps->codec_info[idx].max_height = 1352 codecs->codec_array[i].max_height; 1353 caps->codec_info[idx].max_pixels_per_frame = 1354 codecs->codec_array[i].max_pixels_per_frame; 1355 caps->codec_info[idx].max_level = 1356 codecs->codec_array[i].max_level; 1357 break; 1358 default: 1359 break; 1360 } 1361 } 1362 r = copy_to_user(out, caps, 1363 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1364 kfree(caps); 1365 return r; 1366 } 1367 case AMDGPU_INFO_MAX_IBS: { 1368 uint32_t max_ibs[AMDGPU_HW_IP_NUM]; 1369 1370 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 1371 max_ibs[i] = amdgpu_ring_max_ibs(i); 1372 1373 return copy_to_user(out, max_ibs, 1374 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; 1375 } 1376 case AMDGPU_INFO_GPUVM_FAULT: { 1377 struct amdgpu_fpriv *fpriv = filp->driver_priv; 1378 struct amdgpu_vm *vm = &fpriv->vm; 1379 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault; 1380 unsigned long flags; 1381 1382 if (!vm) 1383 return -EINVAL; 1384 1385 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); 1386 1387 xa_lock_irqsave(&adev->vm_manager.pasids, flags); 1388 gpuvm_fault.addr = vm->fault_info.addr; 1389 gpuvm_fault.status = vm->fault_info.status; 1390 gpuvm_fault.vmhub = vm->fault_info.vmhub; 1391 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); 1392 1393 return copy_to_user(out, &gpuvm_fault, 1394 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; 1395 } 1396 case AMDGPU_INFO_UQ_FW_AREAS: { 1397 struct drm_amdgpu_info_uq_metadata meta_info = {}; 1398 1399 switch (info->query_hw_ip.type) { 1400 case AMDGPU_HW_IP_GFX: 1401 ret = amdgpu_userq_metadata_info_gfx(adev, info, &meta_info.gfx); 1402 if (ret) 1403 return ret; 1404 1405 ret = copy_to_user(out, &meta_info, 1406 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1407 return 0; 1408 case AMDGPU_HW_IP_COMPUTE: 1409 ret = amdgpu_userq_metadata_info_compute(adev, info, &meta_info.compute); 1410 if (ret) 1411 return ret; 1412 1413 ret = copy_to_user(out, &meta_info, 1414 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1415 return 0; 1416 case AMDGPU_HW_IP_DMA: 1417 ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma); 1418 if (ret) 1419 return ret; 1420 1421 ret = copy_to_user(out, &meta_info, 1422 min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; 1423 return 0; 1424 default: 1425 return -EINVAL; 1426 } 1427 } 1428 default: 1429 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1430 return -EINVAL; 1431 } 1432 return 0; 1433 } 1434 1435 /** 1436 * amdgpu_driver_open_kms - drm callback for open 1437 * 1438 * @dev: drm dev pointer 1439 * @file_priv: drm file 1440 * 1441 * On device open, init vm on cayman+ (all asics). 1442 * Returns 0 on success, error on failure. 1443 */ 1444 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1445 { 1446 struct amdgpu_device *adev = drm_to_adev(dev); 1447 struct amdgpu_fpriv *fpriv; 1448 int r, pasid; 1449 1450 /* Ensure IB tests are run on ring */ 1451 flush_delayed_work(&adev->delayed_init_work); 1452 1453 1454 if (amdgpu_ras_intr_triggered()) { 1455 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1456 return -EHWPOISON; 1457 } 1458 1459 file_priv->driver_priv = NULL; 1460 1461 r = pm_runtime_get_sync(dev->dev); 1462 if (r < 0) 1463 goto pm_put; 1464 1465 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1466 if (unlikely(!fpriv)) { 1467 r = -ENOMEM; 1468 goto out_suspend; 1469 } 1470 1471 pasid = amdgpu_pasid_alloc(16); 1472 if (pasid < 0) { 1473 dev_warn(adev->dev, "No more PASIDs available!"); 1474 pasid = 0; 1475 } 1476 1477 r = amdgpu_xcp_open_device(adev, fpriv, file_priv); 1478 if (r) 1479 goto error_pasid; 1480 1481 amdgpu_debugfs_vm_init(file_priv); 1482 1483 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id, pasid); 1484 if (r) 1485 goto error_pasid; 1486 1487 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1488 if (!fpriv->prt_va) { 1489 r = -ENOMEM; 1490 goto error_vm; 1491 } 1492 1493 if (adev->gfx.mcbp) { 1494 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1495 1496 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1497 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1498 if (r) 1499 goto error_vm; 1500 } 1501 1502 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va); 1503 if (r) 1504 goto error_vm; 1505 1506 mutex_init(&fpriv->bo_list_lock); 1507 idr_init_base(&fpriv->bo_list_handles, 1); 1508 1509 r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); 1510 if (r) 1511 drm_warn(adev_to_drm(adev), 1512 "Failed to init usermode queue manager (%d), use legacy workload submission only\n", 1513 r); 1514 1515 r = amdgpu_eviction_fence_init(&fpriv->evf_mgr); 1516 if (r) 1517 goto error_vm; 1518 1519 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1520 1521 file_priv->driver_priv = fpriv; 1522 goto out_suspend; 1523 1524 error_vm: 1525 amdgpu_vm_fini(adev, &fpriv->vm); 1526 1527 error_pasid: 1528 if (pasid) 1529 amdgpu_pasid_free(pasid); 1530 1531 kfree(fpriv); 1532 1533 out_suspend: 1534 pm_put: 1535 pm_runtime_put_autosuspend(dev->dev); 1536 1537 return r; 1538 } 1539 1540 /** 1541 * amdgpu_driver_postclose_kms - drm callback for post close 1542 * 1543 * @dev: drm dev pointer 1544 * @file_priv: drm file 1545 * 1546 * On device post close, tear down vm on cayman+ (all asics). 1547 */ 1548 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1549 struct drm_file *file_priv) 1550 { 1551 struct amdgpu_device *adev = drm_to_adev(dev); 1552 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1553 struct amdgpu_bo_list *list; 1554 struct amdgpu_bo *pd; 1555 u32 pasid; 1556 int handle; 1557 1558 if (!fpriv) 1559 return; 1560 1561 pm_runtime_get_sync(dev->dev); 1562 1563 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1564 amdgpu_uvd_free_handles(adev, file_priv); 1565 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1566 amdgpu_vce_free_handles(adev, file_priv); 1567 1568 if (fpriv->csa_va) { 1569 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1570 1571 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1572 fpriv->csa_va, csa_addr)); 1573 fpriv->csa_va = NULL; 1574 } 1575 1576 amdgpu_seq64_unmap(adev, fpriv); 1577 1578 pasid = fpriv->vm.pasid; 1579 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1580 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1581 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1582 amdgpu_bo_unreserve(pd); 1583 } 1584 1585 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1586 amdgpu_vm_fini(adev, &fpriv->vm); 1587 1588 if (pasid) 1589 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1590 amdgpu_bo_unref(&pd); 1591 1592 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1593 amdgpu_bo_list_put(list); 1594 1595 idr_destroy(&fpriv->bo_list_handles); 1596 mutex_destroy(&fpriv->bo_list_lock); 1597 1598 kfree(fpriv); 1599 file_priv->driver_priv = NULL; 1600 1601 pm_runtime_put_autosuspend(dev->dev); 1602 } 1603 1604 1605 void amdgpu_driver_release_kms(struct drm_device *dev) 1606 { 1607 struct amdgpu_device *adev = drm_to_adev(dev); 1608 1609 amdgpu_device_fini_sw(adev); 1610 pci_set_drvdata(adev->pdev, NULL); 1611 } 1612 1613 /* 1614 * VBlank related functions. 1615 */ 1616 /** 1617 * amdgpu_get_vblank_counter_kms - get frame count 1618 * 1619 * @crtc: crtc to get the frame count from 1620 * 1621 * Gets the frame count on the requested crtc (all asics). 1622 * Returns frame count on success, -EINVAL on failure. 1623 */ 1624 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1625 { 1626 struct drm_device *dev = crtc->dev; 1627 unsigned int pipe = crtc->index; 1628 struct amdgpu_device *adev = drm_to_adev(dev); 1629 int vpos, hpos, stat; 1630 u32 count; 1631 1632 if (pipe >= adev->mode_info.num_crtc) { 1633 DRM_ERROR("Invalid crtc %u\n", pipe); 1634 return -EINVAL; 1635 } 1636 1637 /* The hw increments its frame counter at start of vsync, not at start 1638 * of vblank, as is required by DRM core vblank counter handling. 1639 * Cook the hw count here to make it appear to the caller as if it 1640 * incremented at start of vblank. We measure distance to start of 1641 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1642 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1643 * result by 1 to give the proper appearance to caller. 1644 */ 1645 if (adev->mode_info.crtcs[pipe]) { 1646 /* Repeat readout if needed to provide stable result if 1647 * we cross start of vsync during the queries. 1648 */ 1649 do { 1650 count = amdgpu_display_vblank_get_counter(adev, pipe); 1651 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1652 * vpos as distance to start of vblank, instead of 1653 * regular vertical scanout pos. 1654 */ 1655 stat = amdgpu_display_get_crtc_scanoutpos( 1656 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1657 &vpos, &hpos, NULL, NULL, 1658 &adev->mode_info.crtcs[pipe]->base.hwmode); 1659 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1660 1661 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1662 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1663 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1664 } else { 1665 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1666 pipe, vpos); 1667 1668 /* Bump counter if we are at >= leading edge of vblank, 1669 * but before vsync where vpos would turn negative and 1670 * the hw counter really increments. 1671 */ 1672 if (vpos >= 0) 1673 count++; 1674 } 1675 } else { 1676 /* Fallback to use value as is. */ 1677 count = amdgpu_display_vblank_get_counter(adev, pipe); 1678 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1679 } 1680 1681 return count; 1682 } 1683 1684 /** 1685 * amdgpu_enable_vblank_kms - enable vblank interrupt 1686 * 1687 * @crtc: crtc to enable vblank interrupt for 1688 * 1689 * Enable the interrupt on the requested crtc (all asics). 1690 * Returns 0 on success, -EINVAL on failure. 1691 */ 1692 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1693 { 1694 struct drm_device *dev = crtc->dev; 1695 unsigned int pipe = crtc->index; 1696 struct amdgpu_device *adev = drm_to_adev(dev); 1697 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1698 1699 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1700 } 1701 1702 /** 1703 * amdgpu_disable_vblank_kms - disable vblank interrupt 1704 * 1705 * @crtc: crtc to disable vblank interrupt for 1706 * 1707 * Disable the interrupt on the requested crtc (all asics). 1708 */ 1709 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1710 { 1711 struct drm_device *dev = crtc->dev; 1712 unsigned int pipe = crtc->index; 1713 struct amdgpu_device *adev = drm_to_adev(dev); 1714 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1715 1716 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1717 } 1718 1719 /* 1720 * Debugfs info 1721 */ 1722 #if defined(CONFIG_DEBUG_FS) 1723 1724 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1725 { 1726 struct amdgpu_device *adev = m->private; 1727 struct drm_amdgpu_info_firmware fw_info; 1728 struct drm_amdgpu_query_fw query_fw; 1729 struct atom_context *ctx = adev->mode_info.atom_context; 1730 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1731 int ret, i; 1732 1733 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1734 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type 1735 TA_FW_NAME(XGMI), 1736 TA_FW_NAME(RAS), 1737 TA_FW_NAME(HDCP), 1738 TA_FW_NAME(DTM), 1739 TA_FW_NAME(RAP), 1740 TA_FW_NAME(SECUREDISPLAY), 1741 #undef TA_FW_NAME 1742 }; 1743 1744 /* VCE */ 1745 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1746 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1747 if (ret) 1748 return ret; 1749 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1750 fw_info.feature, fw_info.ver); 1751 1752 /* UVD */ 1753 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1754 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1755 if (ret) 1756 return ret; 1757 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1758 fw_info.feature, fw_info.ver); 1759 1760 /* GMC */ 1761 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1762 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1763 if (ret) 1764 return ret; 1765 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1766 fw_info.feature, fw_info.ver); 1767 1768 /* ME */ 1769 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1770 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1771 if (ret) 1772 return ret; 1773 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1774 fw_info.feature, fw_info.ver); 1775 1776 /* PFP */ 1777 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1778 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1779 if (ret) 1780 return ret; 1781 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1782 fw_info.feature, fw_info.ver); 1783 1784 /* CE */ 1785 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1786 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1787 if (ret) 1788 return ret; 1789 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1790 fw_info.feature, fw_info.ver); 1791 1792 /* RLC */ 1793 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1794 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1795 if (ret) 1796 return ret; 1797 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1798 fw_info.feature, fw_info.ver); 1799 1800 /* RLC SAVE RESTORE LIST CNTL */ 1801 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1802 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1803 if (ret) 1804 return ret; 1805 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1806 fw_info.feature, fw_info.ver); 1807 1808 /* RLC SAVE RESTORE LIST GPM MEM */ 1809 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1810 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1811 if (ret) 1812 return ret; 1813 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1814 fw_info.feature, fw_info.ver); 1815 1816 /* RLC SAVE RESTORE LIST SRM MEM */ 1817 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1818 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1819 if (ret) 1820 return ret; 1821 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1822 fw_info.feature, fw_info.ver); 1823 1824 /* RLCP */ 1825 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1826 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1827 if (ret) 1828 return ret; 1829 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1830 fw_info.feature, fw_info.ver); 1831 1832 /* RLCV */ 1833 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1834 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1835 if (ret) 1836 return ret; 1837 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1838 fw_info.feature, fw_info.ver); 1839 1840 /* MEC */ 1841 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1842 query_fw.index = 0; 1843 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1844 if (ret) 1845 return ret; 1846 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1847 fw_info.feature, fw_info.ver); 1848 1849 /* MEC2 */ 1850 if (adev->gfx.mec2_fw) { 1851 query_fw.index = 1; 1852 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1853 if (ret) 1854 return ret; 1855 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1856 fw_info.feature, fw_info.ver); 1857 } 1858 1859 /* IMU */ 1860 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1861 query_fw.index = 0; 1862 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1863 if (ret) 1864 return ret; 1865 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1866 fw_info.feature, fw_info.ver); 1867 1868 /* PSP SOS */ 1869 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1870 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1871 if (ret) 1872 return ret; 1873 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1874 fw_info.feature, fw_info.ver); 1875 1876 1877 /* PSP ASD */ 1878 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1879 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1880 if (ret) 1881 return ret; 1882 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1883 fw_info.feature, fw_info.ver); 1884 1885 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1886 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1887 query_fw.index = i; 1888 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1889 if (ret) 1890 continue; 1891 1892 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1893 ta_fw_name[i], fw_info.feature, fw_info.ver); 1894 } 1895 1896 /* SMC */ 1897 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1898 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1899 if (ret) 1900 return ret; 1901 smu_program = (fw_info.ver >> 24) & 0xff; 1902 smu_major = (fw_info.ver >> 16) & 0xff; 1903 smu_minor = (fw_info.ver >> 8) & 0xff; 1904 smu_debug = (fw_info.ver >> 0) & 0xff; 1905 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1906 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1907 1908 /* SDMA */ 1909 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1910 for (i = 0; i < adev->sdma.num_instances; i++) { 1911 query_fw.index = i; 1912 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1913 if (ret) 1914 return ret; 1915 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1916 i, fw_info.feature, fw_info.ver); 1917 } 1918 1919 /* VCN */ 1920 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1921 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1922 if (ret) 1923 return ret; 1924 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1925 fw_info.feature, fw_info.ver); 1926 1927 /* DMCU */ 1928 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1929 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1930 if (ret) 1931 return ret; 1932 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1933 fw_info.feature, fw_info.ver); 1934 1935 /* DMCUB */ 1936 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1937 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1938 if (ret) 1939 return ret; 1940 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1941 fw_info.feature, fw_info.ver); 1942 1943 /* TOC */ 1944 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1945 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1946 if (ret) 1947 return ret; 1948 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1949 fw_info.feature, fw_info.ver); 1950 1951 /* CAP */ 1952 if (adev->psp.cap_fw) { 1953 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1954 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1955 if (ret) 1956 return ret; 1957 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1958 fw_info.feature, fw_info.ver); 1959 } 1960 1961 /* MES_KIQ */ 1962 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1963 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1964 if (ret) 1965 return ret; 1966 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1967 fw_info.feature, fw_info.ver); 1968 1969 /* MES */ 1970 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1971 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1972 if (ret) 1973 return ret; 1974 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1975 fw_info.feature, fw_info.ver); 1976 1977 /* VPE */ 1978 query_fw.fw_type = AMDGPU_INFO_FW_VPE; 1979 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1980 if (ret) 1981 return ret; 1982 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", 1983 fw_info.feature, fw_info.ver); 1984 1985 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); 1986 1987 return 0; 1988 } 1989 1990 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1991 1992 #endif 1993 1994 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1995 { 1996 #if defined(CONFIG_DEBUG_FS) 1997 struct drm_minor *minor = adev_to_drm(adev)->primary; 1998 struct dentry *root = minor->debugfs_root; 1999 2000 debugfs_create_file("amdgpu_firmware_info", 0444, root, 2001 adev, &amdgpu_debugfs_firmware_info_fops); 2002 2003 #endif 2004 } 2005