1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef KFD_PRIV_H_INCLUDED
25 #define KFD_PRIV_H_INCLUDED
26
27 #include <linux/hashtable.h>
28 #include <linux/mmu_notifier.h>
29 #include <linux/memremap.h>
30 #include <linux/mutex.h>
31 #include <linux/types.h>
32 #include <linux/atomic.h>
33 #include <linux/workqueue.h>
34 #include <linux/spinlock.h>
35 #include <uapi/linux/kfd_ioctl.h>
36 #include <linux/idr.h>
37 #include <linux/kfifo.h>
38 #include <linux/seq_file.h>
39 #include <linux/kref.h>
40 #include <linux/sysfs.h>
41 #include <linux/device_cgroup.h>
42 #include <drm/drm_file.h>
43 #include <drm/drm_drv.h>
44 #include <drm/drm_device.h>
45 #include <drm/drm_ioctl.h>
46 #include <kgd_kfd_interface.h>
47 #include <linux/swap.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu.h"
51
52 #define KFD_MAX_RING_ENTRY_SIZE 8
53
54 #define KFD_SYSFS_FILE_MODE 0444
55
56 /* GPU ID hash width in bits */
57 #define KFD_GPU_ID_HASH_WIDTH 16
58
59 /* Use upper bits of mmap offset to store KFD driver specific information.
60 * BITS[63:62] - Encode MMAP type
61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
62 * BITS[45:0] - MMAP offset value
63 *
64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
65 * defines are w.r.t to PAGE_SIZE
66 */
67 #define KFD_MMAP_TYPE_SHIFT 62
68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT)
69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT)
70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT)
71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT)
72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT)
73
74 #define KFD_MMAP_GPU_ID_SHIFT 46
75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \
76 << KFD_MMAP_GPU_ID_SHIFT)
77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\
78 & KFD_MMAP_GPU_ID_MASK)
79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \
80 >> KFD_MMAP_GPU_ID_SHIFT)
81
82 /*
83 * When working with cp scheduler we should assign the HIQ manually or via
84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot
85 * definitions for Kaveri. In Kaveri only the first ME queues participates
86 * in the cp scheduling taking that in mind we set the HIQ slot in the
87 * second ME.
88 */
89 #define KFD_CIK_HIQ_PIPE 4
90 #define KFD_CIK_HIQ_QUEUE 0
91
92 /* Macro for allocating structures */
93 #define kfd_alloc_struct(ptr_to_struct) \
94 ((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL))
95
96 #define KFD_MAX_NUM_OF_PROCESSES 512
97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
98
99 /*
100 * Size of the per-process TBA+TMA buffer: 2 pages
101 *
102 * The first chunk is the TBA used for the CWSR ISA code. The second
103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode.
104 */
105 #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2)
106 #define KFD_CWSR_TMA_OFFSET (PAGE_SIZE + 2048)
107
108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \
109 (KFD_MAX_NUM_OF_PROCESSES * \
110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
111
112 #define KFD_KERNEL_QUEUE_SIZE 2048
113
114 #define KFD_UNMAP_LATENCY_MS (4000)
115
116 #define KFD_MAX_SDMA_QUEUES 128
117
118 /*
119 * 512 = 0x200
120 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the
121 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA.
122 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC
123 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in
124 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE.
125 */
126 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
127
128 /**
129 * enum kfd_ioctl_flags - KFD ioctl flags
130 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how
131 * userspace can use a given ioctl.
132 */
133 enum kfd_ioctl_flags {
134 /*
135 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE:
136 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially
137 * perform privileged operations and load arbitrary data into MQDs and
138 * eventually HQD registers when the queue is mapped by HWS. In order to
139 * prevent this we should perform additional security checks.
140 *
141 * This is equivalent to callers with the CHECKPOINT_RESTORE capability.
142 *
143 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE,
144 * we also allow ioctls with SYS_ADMIN capability.
145 */
146 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0),
147 };
148 /*
149 * Kernel module parameter to specify maximum number of supported queues per
150 * device
151 */
152 extern int max_num_of_queues_per_device;
153
154
155 /* Kernel module parameter to specify the scheduling policy */
156 extern int sched_policy;
157
158 /*
159 * Kernel module parameter to specify the maximum process
160 * number per HW scheduler
161 */
162 extern int hws_max_conc_proc;
163
164 extern int cwsr_enable;
165
166 /*
167 * Kernel module parameter to specify whether to send sigterm to HSA process on
168 * unhandled exception
169 */
170 extern int send_sigterm;
171
172 /*
173 * This kernel module is used to simulate large bar machine on non-large bar
174 * enabled machines.
175 */
176 extern int debug_largebar;
177
178 /* Set sh_mem_config.retry_disable on GFX v9 */
179 extern int amdgpu_noretry;
180
181 /* Halt if HWS hang is detected */
182 extern int halt_if_hws_hang;
183
184 /* Whether MEC FW support GWS barriers */
185 extern bool hws_gws_support;
186
187 /* Queue preemption timeout in ms */
188 extern int queue_preemption_timeout_ms;
189
190 /*
191 * Don't evict process queues on vm fault
192 */
193 extern int amdgpu_no_queue_eviction_on_vm_fault;
194
195 /* Enable eviction debug messages */
196 extern bool debug_evictions;
197
198 extern struct mutex kfd_processes_mutex;
199
200 enum cache_policy {
201 cache_policy_coherent,
202 cache_policy_noncoherent
203 };
204
205 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0))
206 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1)))
207 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\
208 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \
209 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \
210 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \
211 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)))
212
213 struct kfd_node;
214
215 struct kfd_event_interrupt_class {
216 bool (*interrupt_isr)(struct kfd_node *dev,
217 const uint32_t *ih_ring_entry, uint32_t *patched_ihre,
218 bool *patched_flag);
219 void (*interrupt_wq)(struct kfd_node *dev,
220 const uint32_t *ih_ring_entry);
221 };
222
223 struct kfd_device_info {
224 uint32_t gfx_target_version;
225 const struct kfd_event_interrupt_class *event_interrupt_class;
226 unsigned int max_pasid_bits;
227 unsigned int max_no_of_hqd;
228 unsigned int doorbell_size;
229 size_t ih_ring_entry_size;
230 uint8_t num_of_watch_points;
231 uint16_t mqd_size_aligned;
232 bool supports_cwsr;
233 bool needs_pci_atomics;
234 uint32_t no_atomic_fw_version;
235 unsigned int num_sdma_queues_per_engine;
236 unsigned int num_reserved_sdma_queues_per_engine;
237 DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
238 };
239
240 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev);
241 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev);
242
243 struct kfd_mem_obj {
244 uint32_t range_start;
245 uint32_t range_end;
246 uint64_t gpu_addr;
247 uint32_t *cpu_ptr;
248 void *gtt_mem;
249 };
250
251 struct kfd_vmid_info {
252 uint32_t first_vmid_kfd;
253 uint32_t last_vmid_kfd;
254 uint32_t vmid_num_kfd;
255 };
256
257 #define MAX_KFD_NODES 8
258
259 struct kfd_dev;
260
261 struct kfd_node {
262 unsigned int node_id;
263 struct amdgpu_device *adev; /* Duplicated here along with keeping
264 * a copy in kfd_dev to save a hop
265 */
266 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with
267 * keeping a copy in kfd_dev to
268 * save a hop
269 */
270 struct kfd_vmid_info vm_info;
271 unsigned int id; /* topology stub index */
272 uint32_t xcc_mask; /* Instance mask of XCCs present */
273 struct amdgpu_xcp *xcp;
274
275 /* Interrupts */
276 struct kfifo ih_fifo;
277 struct work_struct interrupt_work;
278 spinlock_t interrupt_lock;
279
280 /*
281 * Interrupts of interest to KFD are copied
282 * from the HW ring into a SW ring.
283 */
284 bool interrupts_active;
285 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */
286
287 /* QCM Device instance */
288 struct device_queue_manager *dqm;
289
290 /* Global GWS resource shared between processes */
291 void *gws;
292 bool gws_debug_workaround;
293
294 /* Clients watching SMI events */
295 struct list_head smi_clients;
296 spinlock_t smi_lock;
297 uint32_t reset_seq_num;
298
299 /* SRAM ECC flag */
300 atomic_t sram_ecc_flag;
301
302 /*spm process id */
303 unsigned int spm_pasid;
304
305 /* Maximum process number mapped to HW scheduler */
306 unsigned int max_proc_per_quantum;
307
308 unsigned int compute_vmid_bitmap;
309
310 struct kfd_local_mem_info local_mem_info;
311
312 struct kfd_dev *kfd;
313
314 /* Track per device allocated watch points */
315 uint32_t alloc_watch_ids;
316 spinlock_t watch_points_lock;
317 };
318
319 struct kfd_dev {
320 struct amdgpu_device *adev;
321
322 struct kfd_device_info device_info;
323
324 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
325 * page used by kernel queue
326 */
327
328 struct kgd2kfd_shared_resources shared_resources;
329
330 const struct kfd2kgd_calls *kfd2kgd;
331 struct mutex doorbell_mutex;
332
333 void *gtt_mem;
334 uint64_t gtt_start_gpu_addr;
335 void *gtt_start_cpu_ptr;
336 void *gtt_sa_bitmap;
337 struct mutex gtt_sa_lock;
338 unsigned int gtt_sa_chunk_size;
339 unsigned int gtt_sa_num_of_chunks;
340
341 bool init_complete;
342
343 /* Firmware versions */
344 uint16_t mec_fw_version;
345 uint16_t mec2_fw_version;
346 uint16_t sdma_fw_version;
347
348 /* CWSR */
349 bool cwsr_enabled;
350 const void *cwsr_isa;
351 unsigned int cwsr_isa_size;
352
353 /* xGMI */
354 uint64_t hive_id;
355
356 bool pci_atomic_requested;
357
358 /* Compute Profile ref. count */
359 atomic_t compute_profile;
360
361 struct ida doorbell_ida;
362 unsigned int max_doorbell_slices;
363
364 int noretry;
365
366 struct kfd_node *nodes[MAX_KFD_NODES];
367 unsigned int num_nodes;
368
369 struct workqueue_struct *ih_wq;
370
371 /* Kernel doorbells for KFD device */
372 struct amdgpu_bo *doorbells;
373
374 /* bitmap for dynamic doorbell allocation from doorbell object */
375 unsigned long *doorbell_bitmap;
376 };
377
378 enum kfd_mempool {
379 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1,
380 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2,
381 KFD_MEMPOOL_FRAMEBUFFER = 3,
382 };
383
384 /* Character device interface */
385 int kfd_chardev_init(void);
386 void kfd_chardev_exit(void);
387
388 /**
389 * enum kfd_unmap_queues_filter - Enum for queue filters.
390 *
391 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the
392 * running queues list.
393 *
394 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues
395 * in the run list.
396 *
397 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to
398 * specific process.
399 *
400 */
401 enum kfd_unmap_queues_filter {
402 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1,
403 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2,
404 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3
405 };
406
407 /**
408 * enum kfd_queue_type - Enum for various queue types.
409 *
410 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type.
411 *
412 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type.
413 *
414 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type.
415 *
416 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type.
417 *
418 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface.
419 *
420 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID.
421 */
422 enum kfd_queue_type {
423 KFD_QUEUE_TYPE_COMPUTE,
424 KFD_QUEUE_TYPE_SDMA,
425 KFD_QUEUE_TYPE_HIQ,
426 KFD_QUEUE_TYPE_DIQ,
427 KFD_QUEUE_TYPE_SDMA_XGMI,
428 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID
429 };
430
431 enum kfd_queue_format {
432 KFD_QUEUE_FORMAT_PM4,
433 KFD_QUEUE_FORMAT_AQL
434 };
435
436 enum KFD_QUEUE_PRIORITY {
437 KFD_QUEUE_PRIORITY_MINIMUM = 0,
438 KFD_QUEUE_PRIORITY_MAXIMUM = 15
439 };
440
441 /**
442 * struct queue_properties
443 *
444 * @type: The queue type.
445 *
446 * @queue_id: Queue identifier.
447 *
448 * @queue_address: Queue ring buffer address.
449 *
450 * @queue_size: Queue ring buffer size.
451 *
452 * @priority: Defines the queue priority relative to other queues in the
453 * process.
454 * This is just an indication and HW scheduling may override the priority as
455 * necessary while keeping the relative prioritization.
456 * the priority granularity is from 0 to f which f is the highest priority.
457 * currently all queues are initialized with the highest priority.
458 *
459 * @queue_percent: This field is partially implemented and currently a zero in
460 * this field defines that the queue is non active.
461 *
462 * @read_ptr: User space address which points to the number of dwords the
463 * cp read from the ring buffer. This field updates automatically by the H/W.
464 *
465 * @write_ptr: Defines the number of dwords written to the ring buffer.
466 *
467 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring
468 * buffer. This field should be similar to write_ptr and the user should
469 * update this field after updating the write_ptr.
470 *
471 * @doorbell_off: The doorbell offset in the doorbell pci-bar.
472 *
473 * @is_interop: Defines if this is a interop queue. Interop queue means that
474 * the queue can access both graphics and compute resources.
475 *
476 * @is_evicted: Defines if the queue is evicted. Only active queues
477 * are evicted, rendering them inactive.
478 *
479 * @is_active: Defines if the queue is active or not. @is_active and
480 * @is_evicted are protected by the DQM lock.
481 *
482 * @is_gws: Defines if the queue has been updated to be GWS-capable or not.
483 * @is_gws should be protected by the DQM lock, since changing it can yield the
484 * possibility of updating DQM state on number of GWS queues.
485 *
486 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid
487 * of the queue.
488 *
489 * This structure represents the queue properties for each queue no matter if
490 * it's user mode or kernel mode queue.
491 *
492 */
493
494 struct queue_properties {
495 enum kfd_queue_type type;
496 enum kfd_queue_format format;
497 unsigned int queue_id;
498 uint64_t queue_address;
499 uint64_t queue_size;
500 uint32_t priority;
501 uint32_t queue_percent;
502 void __user *read_ptr;
503 void __user *write_ptr;
504 void __iomem *doorbell_ptr;
505 uint32_t doorbell_off;
506 bool is_interop;
507 bool is_evicted;
508 bool is_suspended;
509 bool is_being_destroyed;
510 bool is_active;
511 bool is_gws;
512 uint32_t pm4_target_xcc;
513 bool is_dbg_wa;
514 bool is_user_cu_masked;
515 /* Not relevant for user mode queues in cp scheduling */
516 unsigned int vmid;
517 /* Relevant only for sdma queues*/
518 uint32_t sdma_engine_id;
519 uint32_t sdma_queue_id;
520 uint32_t sdma_vm_addr;
521 /* Relevant only for VI */
522 uint64_t eop_ring_buffer_address;
523 uint32_t eop_ring_buffer_size;
524 uint64_t ctx_save_restore_area_address;
525 uint32_t ctx_save_restore_area_size;
526 uint32_t ctl_stack_size;
527 uint64_t tba_addr;
528 uint64_t tma_addr;
529 uint64_t exception_status;
530
531 struct amdgpu_bo *wptr_bo;
532 struct amdgpu_bo *rptr_bo;
533 struct amdgpu_bo *ring_bo;
534 struct amdgpu_bo *eop_buf_bo;
535 struct amdgpu_bo *cwsr_bo;
536 };
537
538 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \
539 (q).queue_address != 0 && \
540 (q).queue_percent > 0 && \
541 !(q).is_evicted && \
542 !(q).is_suspended)
543
544 enum mqd_update_flag {
545 UPDATE_FLAG_DBG_WA_ENABLE = 1,
546 UPDATE_FLAG_DBG_WA_DISABLE = 2,
547 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */
548 };
549
550 struct mqd_update_info {
551 union {
552 struct {
553 uint32_t count; /* Must be a multiple of 32 */
554 uint32_t *ptr;
555 } cu_mask;
556 };
557 enum mqd_update_flag update_flag;
558 };
559
560 /**
561 * struct queue
562 *
563 * @list: Queue linked list.
564 *
565 * @mqd: The queue MQD (memory queue descriptor).
566 *
567 * @mqd_mem_obj: The MQD local gpu memory object.
568 *
569 * @gart_mqd_addr: The MQD gart mc address.
570 *
571 * @properties: The queue properties.
572 *
573 * @mec: Used only in no cp scheduling mode and identifies to micro engine id
574 * that the queue should be executed on.
575 *
576 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe
577 * id.
578 *
579 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot.
580 *
581 * @process: The kfd process that created this queue.
582 *
583 * @device: The kfd device that created this queue.
584 *
585 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL
586 * otherwise.
587 *
588 * This structure represents user mode compute queues.
589 * It contains all the necessary data to handle such queues.
590 *
591 */
592
593 struct queue {
594 struct list_head list;
595 void *mqd;
596 struct kfd_mem_obj *mqd_mem_obj;
597 uint64_t gart_mqd_addr;
598 struct queue_properties properties;
599
600 uint32_t mec;
601 uint32_t pipe;
602 uint32_t queue;
603
604 unsigned int sdma_id;
605 unsigned int doorbell_id;
606
607 struct kfd_process *process;
608 struct kfd_node *device;
609 void *gws;
610
611 /* procfs */
612 struct kobject kobj;
613
614 void *gang_ctx_bo;
615 uint64_t gang_ctx_gpu_addr;
616 void *gang_ctx_cpu_ptr;
617
618 struct amdgpu_bo *wptr_bo_gart;
619 };
620
621 enum KFD_MQD_TYPE {
622 KFD_MQD_TYPE_HIQ = 0, /* for hiq */
623 KFD_MQD_TYPE_CP, /* for cp queues and diq */
624 KFD_MQD_TYPE_SDMA, /* for sdma queues */
625 KFD_MQD_TYPE_DIQ, /* for diq */
626 KFD_MQD_TYPE_MAX
627 };
628
629 enum KFD_PIPE_PRIORITY {
630 KFD_PIPE_PRIORITY_CS_LOW = 0,
631 KFD_PIPE_PRIORITY_CS_MEDIUM,
632 KFD_PIPE_PRIORITY_CS_HIGH
633 };
634
635 struct scheduling_resources {
636 unsigned int vmid_mask;
637 enum kfd_queue_type type;
638 uint64_t queue_mask;
639 uint64_t gws_mask;
640 uint32_t oac_mask;
641 uint32_t gds_heap_base;
642 uint32_t gds_heap_size;
643 };
644
645 struct process_queue_manager {
646 /* data */
647 struct kfd_process *process;
648 struct list_head queues;
649 unsigned long *queue_slot_bitmap;
650 };
651
652 struct qcm_process_device {
653 /* The Device Queue Manager that owns this data */
654 struct device_queue_manager *dqm;
655 struct process_queue_manager *pqm;
656 /* Queues list */
657 struct list_head queues_list;
658 struct list_head priv_queue_list;
659
660 unsigned int queue_count;
661 unsigned int vmid;
662 bool is_debug;
663 unsigned int evicted; /* eviction counter, 0=active */
664
665 /* This flag tells if we should reset all wavefronts on
666 * process termination
667 */
668 bool reset_wavefronts;
669
670 /* This flag tells us if this process has a GWS-capable
671 * queue that will be mapped into the runlist. It's
672 * possible to request a GWS BO, but not have the queue
673 * currently mapped, and this changes how the MAP_PROCESS
674 * PM4 packet is configured.
675 */
676 bool mapped_gws_queue;
677
678 /* All the memory management data should be here too */
679 uint64_t gds_context_area;
680 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */
681 uint64_t page_table_base;
682 uint32_t sh_mem_config;
683 uint32_t sh_mem_bases;
684 uint32_t sh_mem_ape1_base;
685 uint32_t sh_mem_ape1_limit;
686 uint32_t gds_size;
687 uint32_t num_gws;
688 uint32_t num_oac;
689 uint32_t sh_hidden_private_base;
690
691 /* CWSR memory */
692 struct kgd_mem *cwsr_mem;
693 void *cwsr_kaddr;
694 uint64_t cwsr_base;
695 uint64_t tba_addr;
696 uint64_t tma_addr;
697
698 /* IB memory */
699 struct kgd_mem *ib_mem;
700 uint64_t ib_base;
701 void *ib_kaddr;
702
703 /* doorbells for kfd process */
704 struct amdgpu_bo *proc_doorbells;
705
706 /* bitmap for dynamic doorbell allocation from the bo */
707 unsigned long *doorbell_bitmap;
708 };
709
710 /* KFD Memory Eviction */
711
712 /* Approx. wait time before attempting to restore evicted BOs */
713 #define PROCESS_RESTORE_TIME_MS 100
714 /* Approx. back off time if restore fails due to lack of memory */
715 #define PROCESS_BACK_OFF_TIME_MS 100
716 /* Approx. time before evicting the process again */
717 #define PROCESS_ACTIVE_TIME_MS 10
718
719 /* 8 byte handle containing GPU ID in the most significant 4 bytes and
720 * idr_handle in the least significant 4 bytes
721 */
722 #define MAKE_HANDLE(gpu_id, idr_handle) \
723 (((uint64_t)(gpu_id) << 32) + idr_handle)
724 #define GET_GPU_ID(handle) (handle >> 32)
725 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF)
726
727 enum kfd_pdd_bound {
728 PDD_UNBOUND = 0,
729 PDD_BOUND,
730 PDD_BOUND_SUSPENDED,
731 };
732
733 #define MAX_SYSFS_FILENAME_LEN 15
734
735 /*
736 * SDMA counter runs at 100MHz frequency.
737 * We display SDMA activity in microsecond granularity in sysfs.
738 * As a result, the divisor is 100.
739 */
740 #define SDMA_ACTIVITY_DIVISOR 100
741
742 /* Data that is per-process-per device. */
743 struct kfd_process_device {
744 /* The device that owns this data. */
745 struct kfd_node *dev;
746
747 /* The process that owns this kfd_process_device. */
748 struct kfd_process *process;
749
750 /* per-process-per device QCM data structure */
751 struct qcm_process_device qpd;
752
753 /*Apertures*/
754 uint64_t lds_base;
755 uint64_t lds_limit;
756 uint64_t gpuvm_base;
757 uint64_t gpuvm_limit;
758 uint64_t scratch_base;
759 uint64_t scratch_limit;
760
761 /* VM context for GPUVM allocations */
762 struct file *drm_file;
763 void *drm_priv;
764
765 /* GPUVM allocations storage */
766 struct idr alloc_idr;
767
768 /* Flag used to tell the pdd has dequeued from the dqm.
769 * This is used to prevent dev->dqm->ops.process_termination() from
770 * being called twice when it is already called in IOMMU callback
771 * function.
772 */
773 bool already_dequeued;
774 bool runtime_inuse;
775
776 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */
777 enum kfd_pdd_bound bound;
778
779 /* VRAM usage */
780 atomic64_t vram_usage;
781 struct attribute attr_vram;
782 char vram_filename[MAX_SYSFS_FILENAME_LEN];
783
784 /* SDMA activity tracking */
785 uint64_t sdma_past_activity_counter;
786 struct attribute attr_sdma;
787 char sdma_filename[MAX_SYSFS_FILENAME_LEN];
788
789 /* Eviction activity tracking */
790 uint64_t last_evict_timestamp;
791 atomic64_t evict_duration_counter;
792 struct attribute attr_evict;
793
794 struct kobject *kobj_stats;
795
796 /*
797 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process
798 * that is associated with device encoded by "this" struct instance. The
799 * value reflects CU usage by all of the waves launched by this process
800 * on this device. A very important property of occupancy parameter is
801 * that its value is a snapshot of current use.
802 *
803 * Following is to be noted regarding how this parameter is reported:
804 *
805 * The number of waves that a CU can launch is limited by couple of
806 * parameters. These are encoded by struct amdgpu_cu_info instance
807 * that is part of every device definition. For GFX9 devices this
808 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves
809 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu)
810 * when they do use scratch memory. This could change for future
811 * devices and therefore this example should be considered as a guide.
812 *
813 * All CU's of a device are available for the process. This may not be true
814 * under certain conditions - e.g. CU masking.
815 *
816 * Finally number of CU's that are occupied by a process is affected by both
817 * number of CU's a device has along with number of other competing processes
818 */
819 struct attribute attr_cu_occupancy;
820
821 /* sysfs counters for GPU retry fault and page migration tracking */
822 struct kobject *kobj_counters;
823 struct attribute attr_faults;
824 struct attribute attr_page_in;
825 struct attribute attr_page_out;
826 uint64_t faults;
827 uint64_t page_in;
828 uint64_t page_out;
829
830 /* Exception code status*/
831 uint64_t exception_status;
832 void *vm_fault_exc_data;
833 size_t vm_fault_exc_data_size;
834
835 /* Tracks debug per-vmid request settings */
836 uint32_t spi_dbg_override;
837 uint32_t spi_dbg_launch_mode;
838 uint32_t watch_points[4];
839 uint32_t alloc_watch_ids;
840
841 /*
842 * If this process has been checkpointed before, then the user
843 * application will use the original gpu_id on the
844 * checkpointed node to refer to this device.
845 */
846 uint32_t user_gpu_id;
847
848 void *proc_ctx_bo;
849 uint64_t proc_ctx_gpu_addr;
850 void *proc_ctx_cpu_ptr;
851
852 /* Tracks queue reset status */
853 bool has_reset_queue;
854 };
855
856 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
857
858 struct svm_range_list {
859 struct mutex lock;
860 struct rb_root_cached objects;
861 struct list_head list;
862 struct work_struct deferred_list_work;
863 struct list_head deferred_range_list;
864 struct list_head criu_svm_metadata_list;
865 spinlock_t deferred_list_lock;
866 atomic_t evicted_ranges;
867 atomic_t drain_pagefaults;
868 struct delayed_work restore_work;
869 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
870 struct task_struct *faulting_task;
871 /* check point ts decides if page fault recovery need be dropped */
872 uint64_t checkpoint_ts[MAX_GPU_INSTANCE];
873
874 /* Default granularity to use in buffer migration
875 * and restoration of backing memory while handling
876 * recoverable page faults
877 */
878 uint8_t default_granularity;
879 };
880
881 /* Process data */
882 struct kfd_process {
883 /*
884 * kfd_process are stored in an mm_struct*->kfd_process*
885 * hash table (kfd_processes in kfd_process.c)
886 */
887 struct hlist_node kfd_processes;
888
889 /*
890 * Opaque pointer to mm_struct. We don't hold a reference to
891 * it so it should never be dereferenced from here. This is
892 * only used for looking up processes by their mm.
893 */
894 void *mm;
895
896 struct kref ref;
897 struct work_struct release_work;
898
899 struct mutex mutex;
900
901 /*
902 * In any process, the thread that started main() is the lead
903 * thread and outlives the rest.
904 * It is here because amd_iommu_bind_pasid wants a task_struct.
905 * It can also be used for safely getting a reference to the
906 * mm_struct of the process.
907 */
908 struct task_struct *lead_thread;
909
910 /* We want to receive a notification when the mm_struct is destroyed */
911 struct mmu_notifier mmu_notifier;
912
913 u32 pasid;
914
915 /*
916 * Array of kfd_process_device pointers,
917 * one for each device the process is using.
918 */
919 struct kfd_process_device *pdds[MAX_GPU_INSTANCE];
920 uint32_t n_pdds;
921
922 struct process_queue_manager pqm;
923
924 /*Is the user space process 32 bit?*/
925 bool is_32bit_user_mode;
926
927 /* Event-related data */
928 struct mutex event_mutex;
929 /* Event ID allocator and lookup */
930 struct idr event_idr;
931 /* Event page */
932 u64 signal_handle;
933 struct kfd_signal_page *signal_page;
934 size_t signal_mapped_size;
935 size_t signal_event_count;
936 bool signal_event_limit_reached;
937
938 /* Information used for memory eviction */
939 void *kgd_process_info;
940 /* Eviction fence that is attached to all the BOs of this process. The
941 * fence will be triggered during eviction and new one will be created
942 * during restore
943 */
944 struct dma_fence __rcu *ef;
945
946 /* Work items for evicting and restoring BOs */
947 struct delayed_work eviction_work;
948 struct delayed_work restore_work;
949 /* seqno of the last scheduled eviction */
950 unsigned int last_eviction_seqno;
951 /* Approx. the last timestamp (in jiffies) when the process was
952 * restored after an eviction
953 */
954 unsigned long last_restore_timestamp;
955
956 /* Indicates device process is debug attached with reserved vmid. */
957 bool debug_trap_enabled;
958
959 /* per-process-per device debug event fd file */
960 struct file *dbg_ev_file;
961
962 /* If the process is a kfd debugger, we need to know so we can clean
963 * up at exit time. If a process enables debugging on itself, it does
964 * its own clean-up, so we don't set the flag here. We track this by
965 * counting the number of processes this process is debugging.
966 */
967 atomic_t debugged_process_count;
968
969 /* If the process is a debugged, this is the debugger process */
970 struct kfd_process *debugger_process;
971
972 /* Kobj for our procfs */
973 struct kobject *kobj;
974 struct kobject *kobj_queues;
975 struct attribute attr_pasid;
976
977 /* Keep track cwsr init */
978 bool has_cwsr;
979
980 /* Exception code enable mask and status */
981 uint64_t exception_enable_mask;
982 uint64_t exception_status;
983
984 /* Used to drain stale interrupts */
985 wait_queue_head_t wait_irq_drain;
986 bool irq_drain_is_open;
987
988 /* shared virtual memory registered by this process */
989 struct svm_range_list svms;
990
991 bool xnack_enabled;
992
993 /* Work area for debugger event writer worker. */
994 struct work_struct debug_event_workarea;
995
996 /* Tracks debug per-vmid request for debug flags */
997 u32 dbg_flags;
998
999 atomic_t poison;
1000 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */
1001 bool queues_paused;
1002
1003 /* Tracks runtime enable status */
1004 struct semaphore runtime_enable_sema;
1005 bool is_runtime_retry;
1006 struct kfd_runtime_info runtime_info;
1007
1008 /* if gpu page fault sent to KFD */
1009 bool gpu_page_fault;
1010 };
1011
1012 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */
1013 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE);
1014 extern struct srcu_struct kfd_processes_srcu;
1015
1016 /**
1017 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer.
1018 *
1019 * @filep: pointer to file structure.
1020 * @p: amdkfd process pointer.
1021 * @data: pointer to arg that was copied from user.
1022 *
1023 * Return: returns ioctl completion code.
1024 */
1025 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p,
1026 void *data);
1027
1028 struct amdkfd_ioctl_desc {
1029 unsigned int cmd;
1030 int flags;
1031 amdkfd_ioctl_t *func;
1032 unsigned int cmd_drv;
1033 const char *name;
1034 };
1035 bool kfd_dev_is_large_bar(struct kfd_node *dev);
1036
1037 int kfd_process_create_wq(void);
1038 void kfd_process_destroy_wq(void);
1039 void kfd_cleanup_processes(void);
1040 struct kfd_process *kfd_create_process(struct task_struct *thread);
1041 struct kfd_process *kfd_get_process(const struct task_struct *task);
1042 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid);
1043 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);
1044
1045 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id);
1046 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node,
1047 uint32_t *gpuid, uint32_t *gpuidx);
kfd_process_gpuid_from_gpuidx(struct kfd_process * p,uint32_t gpuidx,uint32_t * gpuid)1048 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p,
1049 uint32_t gpuidx, uint32_t *gpuid) {
1050 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL;
1051 }
kfd_process_device_from_gpuidx(struct kfd_process * p,uint32_t gpuidx)1052 static inline struct kfd_process_device *kfd_process_device_from_gpuidx(
1053 struct kfd_process *p, uint32_t gpuidx) {
1054 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL;
1055 }
1056
1057 void kfd_unref_process(struct kfd_process *p);
1058 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger);
1059 int kfd_process_restore_queues(struct kfd_process *p);
1060 void kfd_suspend_all_processes(void);
1061 int kfd_resume_all_processes(void);
1062
1063 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process,
1064 uint32_t gpu_id);
1065
1066 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id);
1067
1068 int kfd_process_device_init_vm(struct kfd_process_device *pdd,
1069 struct file *drm_file);
1070 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev,
1071 struct kfd_process *p);
1072 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev,
1073 struct kfd_process *p);
1074 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev,
1075 struct kfd_process *p);
1076
1077 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported);
1078
1079 int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process,
1080 struct vm_area_struct *vma);
1081
1082 /* KFD process API for creating and translating handles */
1083 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd,
1084 void *mem);
1085 void *kfd_process_device_translate_handle(struct kfd_process_device *p,
1086 int handle);
1087 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd,
1088 int handle);
1089 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid);
1090
1091 /* PASIDs */
1092 int kfd_pasid_init(void);
1093 void kfd_pasid_exit(void);
1094 bool kfd_set_pasid_limit(unsigned int new_limit);
1095 unsigned int kfd_get_pasid_limit(void);
1096 u32 kfd_pasid_alloc(void);
1097 void kfd_pasid_free(u32 pasid);
1098
1099 /* Doorbells */
1100 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd);
1101 int kfd_doorbell_init(struct kfd_dev *kfd);
1102 void kfd_doorbell_fini(struct kfd_dev *kfd);
1103 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process,
1104 struct vm_area_struct *vma);
1105 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
1106 unsigned int *doorbell_off);
1107 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr);
1108 u32 read_kernel_doorbell(u32 __iomem *db);
1109 void write_kernel_doorbell(void __iomem *db, u32 value);
1110 void write_kernel_doorbell64(void __iomem *db, u64 value);
1111 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
1112 struct kfd_process_device *pdd,
1113 unsigned int doorbell_id);
1114 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd);
1115 int kfd_alloc_process_doorbells(struct kfd_dev *kfd,
1116 struct kfd_process_device *pdd);
1117 void kfd_free_process_doorbells(struct kfd_dev *kfd,
1118 struct kfd_process_device *pdd);
1119 /* GTT Sub-Allocator */
1120
1121 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1122 struct kfd_mem_obj **mem_obj);
1123
1124 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj);
1125
1126 extern struct device *kfd_device;
1127
1128 /* KFD's procfs */
1129 void kfd_procfs_init(void);
1130 void kfd_procfs_shutdown(void);
1131 int kfd_procfs_add_queue(struct queue *q);
1132 void kfd_procfs_del_queue(struct queue *q);
1133
1134 /* Topology */
1135 int kfd_topology_init(void);
1136 void kfd_topology_shutdown(void);
1137 int kfd_topology_add_device(struct kfd_node *gpu);
1138 int kfd_topology_remove_device(struct kfd_node *gpu);
1139 struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
1140 uint32_t proximity_domain);
1141 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(
1142 uint32_t proximity_domain);
1143 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);
1144 struct kfd_node *kfd_device_by_id(uint32_t gpu_id);
1145 struct kfd_node *kfd_device_by_pci_dev(const struct pci_dev *pdev);
kfd_irq_is_from_node(struct kfd_node * node,uint32_t node_id,uint32_t vmid)1146 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id,
1147 uint32_t vmid)
1148 {
1149 return (node->interrupt_bitmap & (1 << node_id)) != 0 &&
1150 (node->compute_vmid_bitmap & (1 << vmid)) != 0;
1151 }
kfd_node_by_irq_ids(struct amdgpu_device * adev,uint32_t node_id,uint32_t vmid)1152 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev,
1153 uint32_t node_id, uint32_t vmid) {
1154 struct kfd_dev *dev = adev->kfd.dev;
1155 uint32_t i;
1156
1157 if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) &&
1158 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) &&
1159 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0))
1160 return dev->nodes[0];
1161
1162 for (i = 0; i < dev->num_nodes; i++)
1163 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid))
1164 return dev->nodes[i];
1165
1166 return NULL;
1167 }
1168 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev);
1169 int kfd_numa_node_to_apic_id(int numa_node_id);
1170
1171 /* Interrupts */
1172 #define KFD_IRQ_FENCE_CLIENTID 0xff
1173 #define KFD_IRQ_FENCE_SOURCEID 0xff
1174 #define KFD_IRQ_IS_FENCE(client, source) \
1175 ((client) == KFD_IRQ_FENCE_CLIENTID && \
1176 (source) == KFD_IRQ_FENCE_SOURCEID)
1177 int kfd_interrupt_init(struct kfd_node *dev);
1178 void kfd_interrupt_exit(struct kfd_node *dev);
1179 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry);
1180 bool interrupt_is_wanted(struct kfd_node *dev,
1181 const uint32_t *ih_ring_entry,
1182 uint32_t *patched_ihre, bool *flag);
1183 int kfd_process_drain_interrupts(struct kfd_process_device *pdd);
1184 void kfd_process_close_interrupt_drain(unsigned int pasid);
1185
1186 /* amdkfd Apertures */
1187 int kfd_init_apertures(struct kfd_process *process);
1188
1189 void kfd_process_set_trap_handler(struct qcm_process_device *qpd,
1190 uint64_t tba_addr,
1191 uint64_t tma_addr);
1192 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd,
1193 bool enabled);
1194
1195 /* CWSR initialization */
1196 int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep);
1197
1198 /* CRIU */
1199 /*
1200 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private
1201 * structures:
1202 * kfd_criu_process_priv_data
1203 * kfd_criu_device_priv_data
1204 * kfd_criu_bo_priv_data
1205 * kfd_criu_queue_priv_data
1206 * kfd_criu_event_priv_data
1207 * kfd_criu_svm_range_priv_data
1208 */
1209
1210 #define KFD_CRIU_PRIV_VERSION 1
1211
1212 struct kfd_criu_process_priv_data {
1213 uint32_t version;
1214 uint32_t xnack_mode;
1215 };
1216
1217 struct kfd_criu_device_priv_data {
1218 /* For future use */
1219 uint64_t reserved;
1220 };
1221
1222 struct kfd_criu_bo_priv_data {
1223 uint64_t user_addr;
1224 uint32_t idr_handle;
1225 uint32_t mapped_gpuids[MAX_GPU_INSTANCE];
1226 };
1227
1228 /*
1229 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data,
1230 * kfd_criu_svm_range_priv_data is the object type
1231 */
1232 enum kfd_criu_object_type {
1233 KFD_CRIU_OBJECT_TYPE_QUEUE,
1234 KFD_CRIU_OBJECT_TYPE_EVENT,
1235 KFD_CRIU_OBJECT_TYPE_SVM_RANGE,
1236 };
1237
1238 struct kfd_criu_svm_range_priv_data {
1239 uint32_t object_type;
1240 uint64_t start_addr;
1241 uint64_t size;
1242 /* Variable length array of attributes */
1243 struct kfd_ioctl_svm_attribute attrs[];
1244 };
1245
1246 struct kfd_criu_queue_priv_data {
1247 uint32_t object_type;
1248 uint64_t q_address;
1249 uint64_t q_size;
1250 uint64_t read_ptr_addr;
1251 uint64_t write_ptr_addr;
1252 uint64_t doorbell_off;
1253 uint64_t eop_ring_buffer_address;
1254 uint64_t ctx_save_restore_area_address;
1255 uint32_t gpu_id;
1256 uint32_t type;
1257 uint32_t format;
1258 uint32_t q_id;
1259 uint32_t priority;
1260 uint32_t q_percent;
1261 uint32_t doorbell_id;
1262 uint32_t gws;
1263 uint32_t sdma_id;
1264 uint32_t eop_ring_buffer_size;
1265 uint32_t ctx_save_restore_area_size;
1266 uint32_t ctl_stack_size;
1267 uint32_t mqd_size;
1268 };
1269
1270 struct kfd_criu_event_priv_data {
1271 uint32_t object_type;
1272 uint64_t user_handle;
1273 uint32_t event_id;
1274 uint32_t auto_reset;
1275 uint32_t type;
1276 uint32_t signaled;
1277
1278 union {
1279 struct kfd_hsa_memory_exception_data memory_exception_data;
1280 struct kfd_hsa_hw_exception_data hw_exception_data;
1281 };
1282 };
1283
1284 int kfd_process_get_queue_info(struct kfd_process *p,
1285 uint32_t *num_queues,
1286 uint64_t *priv_data_sizes);
1287
1288 int kfd_criu_checkpoint_queues(struct kfd_process *p,
1289 uint8_t __user *user_priv_data,
1290 uint64_t *priv_data_offset);
1291
1292 int kfd_criu_restore_queue(struct kfd_process *p,
1293 uint8_t __user *user_priv_data,
1294 uint64_t *priv_data_offset,
1295 uint64_t max_priv_data_size);
1296
1297 int kfd_criu_checkpoint_events(struct kfd_process *p,
1298 uint8_t __user *user_priv_data,
1299 uint64_t *priv_data_offset);
1300
1301 int kfd_criu_restore_event(struct file *devkfd,
1302 struct kfd_process *p,
1303 uint8_t __user *user_priv_data,
1304 uint64_t *priv_data_offset,
1305 uint64_t max_priv_data_size);
1306 /* CRIU - End */
1307
1308 /* Queue Context Management */
1309 int init_queue(struct queue **q, const struct queue_properties *properties);
1310 void uninit_queue(struct queue *q);
1311 void print_queue_properties(struct queue_properties *q);
1312 void print_queue(struct queue *q);
1313 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo,
1314 u64 expected_size);
1315 void kfd_queue_buffer_put(struct amdgpu_bo **bo);
1316 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);
1317 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);
1318 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo);
1319 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd,
1320 struct queue_properties *properties);
1321 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev);
1322
1323 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
1324 struct kfd_node *dev);
1325 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
1326 struct kfd_node *dev);
1327 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
1328 struct kfd_node *dev);
1329 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
1330 struct kfd_node *dev);
1331 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,
1332 struct kfd_node *dev);
1333 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type,
1334 struct kfd_node *dev);
1335 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev);
1336 void device_queue_manager_uninit(struct device_queue_manager *dqm);
1337 struct kernel_queue *kernel_queue_init(struct kfd_node *dev,
1338 enum kfd_queue_type type);
1339 void kernel_queue_uninit(struct kernel_queue *kq);
1340 int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid);
1341 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id);
1342
1343 /* Process Queue Manager */
1344 struct process_queue_node {
1345 struct queue *q;
1346 struct kernel_queue *kq;
1347 struct list_head process_queue_list;
1348 };
1349
1350 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd);
1351 void kfd_process_dequeue_from_all_devices(struct kfd_process *p);
1352 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p);
1353 void pqm_uninit(struct process_queue_manager *pqm);
1354 int pqm_create_queue(struct process_queue_manager *pqm,
1355 struct kfd_node *dev,
1356 struct queue_properties *properties,
1357 unsigned int *qid,
1358 const struct kfd_criu_queue_priv_data *q_data,
1359 const void *restore_mqd,
1360 const void *restore_ctl_stack,
1361 uint32_t *p_doorbell_offset_in_process);
1362 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
1363 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid,
1364 struct queue_properties *p);
1365 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid,
1366 struct mqd_update_info *minfo);
1367 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
1368 void *gws);
1369 struct kernel_queue *pqm_get_kernel_queue(struct process_queue_manager *pqm,
1370 unsigned int qid);
1371 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
1372 unsigned int qid);
1373 int pqm_get_wave_state(struct process_queue_manager *pqm,
1374 unsigned int qid,
1375 void __user *ctl_stack,
1376 u32 *ctl_stack_used_size,
1377 u32 *save_area_used_size);
1378 int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
1379 uint64_t exception_clear_mask,
1380 void __user *buf,
1381 int *num_qss_entries,
1382 uint32_t *entry_size);
1383
1384 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm,
1385 uint64_t fence_value,
1386 unsigned int timeout_ms);
1387
1388 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
1389 unsigned int qid,
1390 u32 *mqd_size,
1391 u32 *ctl_stack_size);
1392 /* Packet Manager */
1393
1394 #define KFD_FENCE_COMPLETED (100)
1395 #define KFD_FENCE_INIT (10)
1396
1397 struct packet_manager {
1398 struct device_queue_manager *dqm;
1399 struct kernel_queue *priv_queue;
1400 struct mutex lock;
1401 bool allocated;
1402 struct kfd_mem_obj *ib_buffer_obj;
1403 unsigned int ib_size_bytes;
1404 bool is_over_subscription;
1405
1406 const struct packet_manager_funcs *pmf;
1407 };
1408
1409 struct packet_manager_funcs {
1410 /* Support ASIC-specific packet formats for PM4 packets */
1411 int (*map_process)(struct packet_manager *pm, uint32_t *buffer,
1412 struct qcm_process_device *qpd);
1413 int (*runlist)(struct packet_manager *pm, uint32_t *buffer,
1414 uint64_t ib, size_t ib_size_in_dwords, bool chain);
1415 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer,
1416 struct scheduling_resources *res);
1417 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer,
1418 struct queue *q, bool is_static);
1419 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer,
1420 enum kfd_unmap_queues_filter mode,
1421 uint32_t filter_param, bool reset);
1422 int (*set_grace_period)(struct packet_manager *pm, uint32_t *buffer,
1423 uint32_t grace_period);
1424 int (*query_status)(struct packet_manager *pm, uint32_t *buffer,
1425 uint64_t fence_address, uint64_t fence_value);
1426 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);
1427
1428 /* Packet sizes */
1429 int map_process_size;
1430 int runlist_size;
1431 int set_resources_size;
1432 int map_queues_size;
1433 int unmap_queues_size;
1434 int set_grace_period_size;
1435 int query_status_size;
1436 int release_mem_size;
1437 };
1438
1439 extern const struct packet_manager_funcs kfd_vi_pm_funcs;
1440 extern const struct packet_manager_funcs kfd_v9_pm_funcs;
1441 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs;
1442
1443 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
1444 void pm_uninit(struct packet_manager *pm);
1445 int pm_send_set_resources(struct packet_manager *pm,
1446 struct scheduling_resources *res);
1447 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues);
1448 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
1449 uint64_t fence_value);
1450
1451 int pm_send_unmap_queue(struct packet_manager *pm,
1452 enum kfd_unmap_queues_filter mode,
1453 uint32_t filter_param, bool reset);
1454
1455 void pm_release_ib(struct packet_manager *pm);
1456
1457 int pm_update_grace_period(struct packet_manager *pm, uint32_t grace_period);
1458
1459 /* Following PM funcs can be shared among VI and AI */
1460 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);
1461
1462 uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
1463
1464 /* Events */
1465 extern const struct kfd_event_interrupt_class event_interrupt_class_cik;
1466 extern const struct kfd_event_interrupt_class event_interrupt_class_v9;
1467 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3;
1468 extern const struct kfd_event_interrupt_class event_interrupt_class_v10;
1469 extern const struct kfd_event_interrupt_class event_interrupt_class_v11;
1470
1471 extern const struct kfd_device_global_init_class device_global_init_class_cik;
1472
1473 int kfd_event_init_process(struct kfd_process *p);
1474 void kfd_event_free_process(struct kfd_process *p);
1475 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma);
1476 int kfd_wait_on_events(struct kfd_process *p,
1477 uint32_t num_events, void __user *data,
1478 bool all, uint32_t *user_timeout_ms,
1479 uint32_t *wait_result);
1480 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,
1481 uint32_t valid_id_bits);
1482 void kfd_signal_hw_exception_event(u32 pasid);
1483 int kfd_set_event(struct kfd_process *p, uint32_t event_id);
1484 int kfd_reset_event(struct kfd_process *p, uint32_t event_id);
1485 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset);
1486
1487 int kfd_event_create(struct file *devkfd, struct kfd_process *p,
1488 uint32_t event_type, bool auto_reset, uint32_t node_id,
1489 uint32_t *event_id, uint32_t *event_trigger_data,
1490 uint64_t *event_page_offset, uint32_t *event_slot_index);
1491
1492 int kfd_get_num_events(struct kfd_process *p);
1493 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id);
1494
1495 void kfd_signal_vm_fault_event(struct kfd_node *dev, u32 pasid,
1496 struct kfd_vm_fault_info *info,
1497 struct kfd_hsa_memory_exception_data *data);
1498
1499 void kfd_signal_reset_event(struct kfd_node *dev);
1500
1501 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid);
1502
kfd_flush_tlb(struct kfd_process_device * pdd,enum TLB_FLUSH_TYPE type)1503 static inline void kfd_flush_tlb(struct kfd_process_device *pdd,
1504 enum TLB_FLUSH_TYPE type)
1505 {
1506 struct amdgpu_device *adev = pdd->dev->adev;
1507 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv);
1508
1509 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask);
1510 }
1511
kfd_flush_tlb_after_unmap(struct kfd_dev * dev)1512 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
1513 {
1514 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) ||
1515 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) ||
1516 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
1517 }
1518
1519 int kfd_send_exception_to_runtime(struct kfd_process *p,
1520 unsigned int queue_id,
1521 uint64_t error_reason);
1522 bool kfd_is_locked(void);
1523
1524 /* Compute profile */
1525 void kfd_inc_compute_active(struct kfd_node *dev);
1526 void kfd_dec_compute_active(struct kfd_node *dev);
1527
1528 /* Cgroup Support */
1529 /* Check with device cgroup if @kfd device is accessible */
kfd_devcgroup_check_permission(struct kfd_node * node)1530 static inline int kfd_devcgroup_check_permission(struct kfd_node *node)
1531 {
1532 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
1533 struct drm_device *ddev;
1534
1535 if (node->xcp)
1536 ddev = node->xcp->ddev;
1537 else
1538 ddev = adev_to_drm(node->adev);
1539
1540 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR,
1541 ddev->render->index,
1542 DEVCG_ACC_WRITE | DEVCG_ACC_READ);
1543 #else
1544 return 0;
1545 #endif
1546 }
1547
kfd_is_first_node(struct kfd_node * node)1548 static inline bool kfd_is_first_node(struct kfd_node *node)
1549 {
1550 return (node == node->kfd->nodes[0]);
1551 }
1552
1553 /* Debugfs */
1554 #if defined(CONFIG_DEBUG_FS)
1555
1556 void kfd_debugfs_init(void);
1557 void kfd_debugfs_fini(void);
1558 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data);
1559 int pqm_debugfs_mqds(struct seq_file *m, void *data);
1560 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data);
1561 int dqm_debugfs_hqds(struct seq_file *m, void *data);
1562 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data);
1563 int pm_debugfs_runlist(struct seq_file *m, void *data);
1564
1565 int kfd_debugfs_hang_hws(struct kfd_node *dev);
1566 int pm_debugfs_hang_hws(struct packet_manager *pm);
1567 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm);
1568
1569 #else
1570
kfd_debugfs_init(void)1571 static inline void kfd_debugfs_init(void) {}
kfd_debugfs_fini(void)1572 static inline void kfd_debugfs_fini(void) {}
1573
1574 #endif
1575
1576 #endif
1577