1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Nicera D3-323-AA PIR sensor.
4 *
5 * Copyright (C) 2025 Axis Communications AB
6 */
7
8 #include <linux/bitmap.h>
9 #include <linux/cleanup.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/types.h>
22
23 #include <linux/iio/events.h>
24 #include <linux/iio/iio.h>
25
26 /*
27 * Register bitmap.
28 * For some reason the first bit is denoted as F37 in the datasheet, the second
29 * as F38 and so on. Note the gap between F60 and F64.
30 */
31 #define D3323AA_REG_BIT_SLAVEA1 0 /* F37. */
32 #define D3323AA_REG_BIT_SLAVEA2 1 /* F38. */
33 #define D3323AA_REG_BIT_SLAVEA3 2 /* F39. */
34 #define D3323AA_REG_BIT_SLAVEA4 3 /* F40. */
35 #define D3323AA_REG_BIT_SLAVEA5 4 /* F41. */
36 #define D3323AA_REG_BIT_SLAVEA6 5 /* F42. */
37 #define D3323AA_REG_BIT_SLAVEA7 6 /* F43. */
38 #define D3323AA_REG_BIT_SLAVEA8 7 /* F44. */
39 #define D3323AA_REG_BIT_SLAVEA9 8 /* F45. */
40 #define D3323AA_REG_BIT_SLAVEA10 9 /* F46. */
41 #define D3323AA_REG_BIT_DETLVLABS0 10 /* F47. */
42 #define D3323AA_REG_BIT_DETLVLABS1 11 /* F48. */
43 #define D3323AA_REG_BIT_DETLVLABS2 12 /* F49. */
44 #define D3323AA_REG_BIT_DETLVLABS3 13 /* F50. */
45 #define D3323AA_REG_BIT_DETLVLABS4 14 /* F51. */
46 #define D3323AA_REG_BIT_DETLVLABS5 15 /* F52. */
47 #define D3323AA_REG_BIT_DETLVLABS6 16 /* F53. */
48 #define D3323AA_REG_BIT_DETLVLABS7 17 /* F54. */
49 #define D3323AA_REG_BIT_DSLP 18 /* F55. */
50 #define D3323AA_REG_BIT_FSTEP0 19 /* F56. */
51 #define D3323AA_REG_BIT_FSTEP1 20 /* F57. */
52 #define D3323AA_REG_BIT_FILSEL0 21 /* F58. */
53 #define D3323AA_REG_BIT_FILSEL1 22 /* F59. */
54 #define D3323AA_REG_BIT_FILSEL2 23 /* F60. */
55 #define D3323AA_REG_BIT_FDSET 24 /* F64. */
56 #define D3323AA_REG_BIT_F65 25
57 #define D3323AA_REG_BIT_F87 (D3323AA_REG_BIT_F65 + (87 - 65))
58
59 #define D3323AA_REG_NR_BITS (D3323AA_REG_BIT_F87 - D3323AA_REG_BIT_SLAVEA1 + 1)
60 #define D3323AA_THRESH_REG_NR_BITS \
61 (D3323AA_REG_BIT_DETLVLABS7 - D3323AA_REG_BIT_DETLVLABS0 + 1)
62 #define D3323AA_FILTER_TYPE_NR_BITS \
63 (D3323AA_REG_BIT_FILSEL2 - D3323AA_REG_BIT_FILSEL0 + 1)
64 #define D3323AA_FILTER_GAIN_REG_NR_BITS \
65 (D3323AA_REG_BIT_FSTEP1 - D3323AA_REG_BIT_FSTEP0 + 1)
66
67 #define D3323AA_THRESH_DEFAULT_VAL 56
68 #define D3323AA_FILTER_GAIN_DEFAULT_IDX 1
69 #define D3323AA_LP_FILTER_FREQ_DEFAULT_IDX 1
70
71 /*
72 * The pattern is 0b01101, but store it reversed (0b10110) due to writing from
73 * LSB on the wire (c.f. d3323aa_write_settings()).
74 */
75 #define D3323AA_SETTING_END_PATTERN 0x16
76 #define D3323AA_SETTING_END_PATTERN_NR_BITS 5
77
78 /*
79 * Device should be ready for configuration after this many milliseconds.
80 * Datasheet mentions "approx. 1.2 s". Measurements show around 1.23 s,
81 * therefore add 100 ms of slack.
82 */
83 #define D3323AA_RESET_TIMEOUT (1200 + 100)
84
85 /*
86 * The configuration of the device (write and read) should be done within this
87 * many milliseconds.
88 */
89 #define D3323AA_CONFIG_TIMEOUT 1400
90
91 /* Number of IRQs needed for configuration stage after reset. */
92 #define D3323AA_IRQ_RESET_COUNT 2
93
94 /*
95 * High-pass filter cutoff frequency for the band-pass filter. There is a
96 * corresponding low-pass cutoff frequency for each of the filter types
97 * (denoted A, B, C and D in the datasheet). The index in this array matches
98 * that corresponding value in d3323aa_lp_filter_freq.
99 * Note that this represents a fractional value (e.g. the first value
100 * corresponds to 40 / 100 = 0.4 Hz).
101 */
102 static const int d3323aa_hp_filter_freq[][2] = {
103 { 40, 100 },
104 { 30, 100 },
105 { 30, 100 },
106 { 1, 100 },
107 };
108
109 /*
110 * Low-pass filter cutoff frequency for the band-pass filter. There is a
111 * corresponding high-pass cutoff frequency for each of the filter types
112 * (denoted A, B, C and D in the datasheet). The index in this array matches
113 * that corresponding value in d3323aa_hp_filter_freq.
114 * Note that this represents a fractional value (e.g. the first value
115 * corresponds to 27 / 10 = 2.7 Hz).
116 */
117 static const int d3323aa_lp_filter_freq[][2] = {
118 { 27, 10 },
119 { 15, 10 },
120 { 5, 1 },
121 { 100, 1 },
122 };
123
124 /*
125 * Register bitmap values for filter types (denoted A, B, C and D in the
126 * datasheet). The index in this array matches the corresponding value in
127 * d3323aa_lp_filter_freq (which in turn matches d3323aa_hp_filter_freq). For
128 * example, the first value 7 corresponds to 2.7 Hz low-pass and 0.4 Hz
129 * high-pass cutoff frequency.
130 */
131 static const int d3323aa_lp_filter_regval[] = {
132 7,
133 0,
134 1,
135 2,
136 };
137
138 /*
139 * This is denoted as "step" in datasheet and corresponds to the gain at peak
140 * for the band-pass filter. The index in this array is the corresponding index
141 * in d3323aa_filter_gain_regval for the register bitmap value.
142 */
143 static const int d3323aa_filter_gain[] = { 1, 2, 3 };
144
145 /*
146 * Register bitmap values for the filter gain. The index in this array is the
147 * corresponding index in d3323aa_filter_gain for the gain value.
148 */
149 static const u8 d3323aa_filter_gain_regval[] = { 1, 3, 0 };
150
151 struct d3323aa_data {
152 struct completion reset_completion;
153 /*
154 * Since the setup process always requires a complete write of _all_
155 * the state variables, we need to synchronize them with a lock.
156 */
157 struct mutex statevar_lock;
158
159 struct device *dev;
160
161 /* Supply voltage. */
162 struct regulator *regulator_vdd;
163 /* Input clock or output detection signal (Vout). */
164 struct gpio_desc *gpiod_clkin_detectout;
165 /* Input (setting) or output data. */
166 struct gpio_desc *gpiod_data;
167
168 /*
169 * We only need the low-pass cutoff frequency to unambiguously choose
170 * the type of band-pass filter. For example, both filter type B and C
171 * have 0.3 Hz as high-pass cutoff frequency (see
172 * d3323aa_hp_filter_freq).
173 */
174 size_t lp_filter_freq_idx;
175 size_t filter_gain_idx;
176 u8 detect_thresh;
177 u8 irq_reset_count;
178
179 /* Indicator for operational mode (configuring or detecting). */
180 bool detecting;
181 };
182
d3323aa_read_settings(struct iio_dev * indio_dev,unsigned long * regbitmap)183 static int d3323aa_read_settings(struct iio_dev *indio_dev,
184 unsigned long *regbitmap)
185 {
186 struct d3323aa_data *data = iio_priv(indio_dev);
187 size_t i;
188 int ret;
189
190 /* Bit bang the clock and data pins. */
191 ret = gpiod_direction_output(data->gpiod_clkin_detectout, 0);
192 if (ret)
193 return ret;
194
195 ret = gpiod_direction_input(data->gpiod_data);
196 if (ret)
197 return ret;
198
199 dev_dbg(data->dev, "Reading settings...\n");
200
201 for (i = 0; i < D3323AA_REG_NR_BITS; ++i) {
202 /* Clock frequency needs to be 1 kHz. */
203 gpiod_set_value(data->gpiod_clkin_detectout, 1);
204 udelay(500);
205
206 /* The data seems to change when clock signal is high. */
207 if (gpiod_get_value(data->gpiod_data))
208 set_bit(i, regbitmap);
209
210 gpiod_set_value(data->gpiod_clkin_detectout, 0);
211 udelay(500);
212 }
213
214 /* The first bit (F37) is just dummy data. Discard it. */
215 clear_bit(0, regbitmap);
216
217 /* Datasheet says to wait 30 ms after reading the settings. */
218 msleep(30);
219
220 return 0;
221 }
222
d3323aa_write_settings(struct iio_dev * indio_dev,unsigned long * written_regbitmap)223 static int d3323aa_write_settings(struct iio_dev *indio_dev,
224 unsigned long *written_regbitmap)
225 {
226 #define REGBITMAP_LEN \
227 (D3323AA_REG_NR_BITS + D3323AA_SETTING_END_PATTERN_NR_BITS)
228 DECLARE_BITMAP(regbitmap, REGBITMAP_LEN);
229 struct d3323aa_data *data = iio_priv(indio_dev);
230 size_t i;
231 int ret;
232
233 /* Build the register bitmap. */
234 bitmap_zero(regbitmap, REGBITMAP_LEN);
235 bitmap_write(regbitmap, data->detect_thresh, D3323AA_REG_BIT_DETLVLABS0,
236 D3323AA_REG_BIT_DETLVLABS7 - D3323AA_REG_BIT_DETLVLABS0 +
237 1);
238 bitmap_write(regbitmap,
239 d3323aa_filter_gain_regval[data->filter_gain_idx],
240 D3323AA_REG_BIT_FSTEP0,
241 D3323AA_REG_BIT_FSTEP1 - D3323AA_REG_BIT_FSTEP0 + 1);
242 bitmap_write(regbitmap,
243 d3323aa_lp_filter_regval[data->lp_filter_freq_idx],
244 D3323AA_REG_BIT_FILSEL0,
245 D3323AA_REG_BIT_FILSEL2 - D3323AA_REG_BIT_FILSEL0 + 1);
246 /* Compulsory end pattern. */
247 bitmap_write(regbitmap, D3323AA_SETTING_END_PATTERN,
248 D3323AA_REG_NR_BITS, D3323AA_SETTING_END_PATTERN_NR_BITS);
249
250 /* Bit bang the clock and data pins. */
251 ret = gpiod_direction_output(data->gpiod_clkin_detectout, 0);
252 if (ret)
253 return ret;
254
255 ret = gpiod_direction_output(data->gpiod_data, 0);
256 if (ret)
257 return ret;
258
259 dev_dbg(data->dev, "Writing settings...\n");
260
261 /* First bit (F37) is not used when writing the register bitmap. */
262 for (i = 1; i < REGBITMAP_LEN; ++i) {
263 gpiod_set_value(data->gpiod_data, test_bit(i, regbitmap));
264
265 /* Clock frequency needs to be 1 kHz. */
266 gpiod_set_value(data->gpiod_clkin_detectout, 1);
267 udelay(500);
268 gpiod_set_value(data->gpiod_clkin_detectout, 0);
269 udelay(500);
270 }
271
272 /* Datasheet says to wait 30 ms after writing the settings. */
273 msleep(30);
274
275 bitmap_copy(written_regbitmap, regbitmap, D3323AA_REG_NR_BITS);
276
277 return 0;
278 }
279
d3323aa_irq_handler(int irq,void * dev_id)280 static irqreturn_t d3323aa_irq_handler(int irq, void *dev_id)
281 {
282 struct iio_dev *indio_dev = dev_id;
283 struct d3323aa_data *data = iio_priv(indio_dev);
284 enum iio_event_direction dir;
285 int val;
286
287 val = gpiod_get_value(data->gpiod_clkin_detectout);
288 if (val < 0) {
289 dev_err_ratelimited(data->dev,
290 "Could not read from GPIO vout-clk (%d)\n",
291 val);
292 return IRQ_HANDLED;
293 }
294
295 if (!data->detecting) {
296 /* Reset interrupt counting falling edges. */
297 if (!val && ++data->irq_reset_count == D3323AA_IRQ_RESET_COUNT)
298 complete(&data->reset_completion);
299
300 return IRQ_HANDLED;
301 }
302
303 /* Detection interrupt. */
304 dir = val ? IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING;
305 iio_push_event(indio_dev,
306 IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
307 IIO_EV_TYPE_THRESH, dir),
308 iio_get_time_ns(indio_dev));
309
310 return IRQ_HANDLED;
311 }
312
d3323aa_reset(struct iio_dev * indio_dev)313 static int d3323aa_reset(struct iio_dev *indio_dev)
314 {
315 struct d3323aa_data *data = iio_priv(indio_dev);
316 long time;
317 int ret;
318
319 /* During probe() the regulator may already be disabled. */
320 if (regulator_is_enabled(data->regulator_vdd)) {
321 ret = regulator_disable(data->regulator_vdd);
322 if (ret)
323 return ret;
324 }
325
326 /*
327 * Datasheet says VDD needs to be low at least for 30 ms. Let's add a
328 * couple more to allow VDD to completely discharge as well.
329 */
330 fsleep((30 + 5) * USEC_PER_MSEC);
331
332 /*
333 * When later enabling VDD, the device will signal with
334 * D3323AA_IRQ_RESET_COUNT falling edges on Vout/CLK that it is now
335 * ready for configuration. Datasheet says that this should happen
336 * within D3323AA_RESET_TIMEOUT ms. Count these two edges within that
337 * timeout.
338 */
339 data->irq_reset_count = 0;
340 reinit_completion(&data->reset_completion);
341 data->detecting = false;
342
343 ret = gpiod_direction_input(data->gpiod_clkin_detectout);
344 if (ret)
345 return ret;
346
347 dev_dbg(data->dev, "Resetting...\n");
348
349 ret = regulator_enable(data->regulator_vdd);
350 if (ret)
351 return ret;
352
353 /*
354 * Wait for VDD to completely charge up. Measurements have shown that
355 * Vout/CLK signal slowly ramps up during this period. Thus, the digital
356 * signal will have bogus values. It is therefore necessary to wait
357 * before we can count the "real" falling edges.
358 */
359 fsleep(2000);
360
361 time = wait_for_completion_killable_timeout(
362 &data->reset_completion,
363 msecs_to_jiffies(D3323AA_RESET_TIMEOUT));
364 if (time == 0) {
365 return -ETIMEDOUT;
366 } else if (time < 0) {
367 /* Got interrupted. */
368 return time;
369 }
370
371 dev_dbg(data->dev, "Reset completed\n");
372
373 return 0;
374 }
375
d3323aa_setup(struct iio_dev * indio_dev,size_t lp_filter_freq_idx,size_t filter_gain_idx,u8 detect_thresh)376 static int d3323aa_setup(struct iio_dev *indio_dev, size_t lp_filter_freq_idx,
377 size_t filter_gain_idx, u8 detect_thresh)
378 {
379 DECLARE_BITMAP(write_regbitmap, D3323AA_REG_NR_BITS);
380 DECLARE_BITMAP(read_regbitmap, D3323AA_REG_NR_BITS);
381 struct d3323aa_data *data = iio_priv(indio_dev);
382 unsigned long start_time;
383 int ret;
384
385 ret = d3323aa_reset(indio_dev);
386 if (ret) {
387 if (ret != -ERESTARTSYS)
388 dev_err(data->dev, "Could not reset device (%d)\n",
389 ret);
390
391 return ret;
392 }
393
394 /*
395 * Datasheet says to wait 10 us before setting the configuration.
396 * Moreover, the total configuration should be done within
397 * D3323AA_CONFIG_TIMEOUT ms. Clock it.
398 */
399 fsleep(10);
400 start_time = jiffies;
401
402 ret = d3323aa_write_settings(indio_dev, write_regbitmap);
403 if (ret) {
404 dev_err(data->dev, "Could not write settings (%d)\n", ret);
405 return ret;
406 }
407
408 ret = d3323aa_read_settings(indio_dev, read_regbitmap);
409 if (ret) {
410 dev_err(data->dev, "Could not read settings (%d)\n", ret);
411 return ret;
412 }
413
414 if (time_is_before_jiffies(start_time +
415 msecs_to_jiffies(D3323AA_CONFIG_TIMEOUT))) {
416 dev_err(data->dev, "Could not set up configuration in time\n");
417 return -EAGAIN;
418 }
419
420 /* Check if settings were set successfully. */
421 if (!bitmap_equal(write_regbitmap, read_regbitmap,
422 D3323AA_REG_NR_BITS)) {
423 dev_err(data->dev, "Settings data mismatch\n");
424 return -EIO;
425 }
426
427 /* Now in operational mode. */
428 ret = gpiod_direction_input(data->gpiod_clkin_detectout);
429 if (ret) {
430 dev_err(data->dev,
431 "Could not set GPIO vout-clk as input (%d)\n", ret);
432 return ret;
433 }
434
435 ret = gpiod_direction_input(data->gpiod_data);
436 if (ret) {
437 dev_err(data->dev, "Could not set GPIO data as input (%d)\n",
438 ret);
439 return ret;
440 }
441
442 data->lp_filter_freq_idx = lp_filter_freq_idx;
443 data->filter_gain_idx = filter_gain_idx;
444 data->detect_thresh = detect_thresh;
445 data->detecting = true;
446
447 dev_dbg(data->dev, "Setup done\n");
448
449 return 0;
450 }
451
d3323aa_set_lp_filter_freq(struct iio_dev * indio_dev,const int val,int val2)452 static int d3323aa_set_lp_filter_freq(struct iio_dev *indio_dev, const int val,
453 int val2)
454 {
455 struct d3323aa_data *data = iio_priv(indio_dev);
456 size_t idx;
457
458 /* Truncate fractional part to one digit. */
459 val2 /= 100000;
460
461 for (idx = 0; idx < ARRAY_SIZE(d3323aa_lp_filter_freq); ++idx) {
462 int integer = d3323aa_lp_filter_freq[idx][0] /
463 d3323aa_lp_filter_freq[idx][1];
464 int fract = d3323aa_lp_filter_freq[idx][0] %
465 d3323aa_lp_filter_freq[idx][1];
466
467 if (val == integer && val2 == fract)
468 break;
469 }
470
471 if (idx == ARRAY_SIZE(d3323aa_lp_filter_freq))
472 return -EINVAL;
473
474 return d3323aa_setup(indio_dev, idx, data->filter_gain_idx,
475 data->detect_thresh);
476 }
477
d3323aa_set_hp_filter_freq(struct iio_dev * indio_dev,const int val,int val2)478 static int d3323aa_set_hp_filter_freq(struct iio_dev *indio_dev, const int val,
479 int val2)
480 {
481 struct d3323aa_data *data = iio_priv(indio_dev);
482 size_t idx;
483
484 /* Truncate fractional part to two digits. */
485 val2 /= 10000;
486
487 for (idx = 0; idx < ARRAY_SIZE(d3323aa_hp_filter_freq); ++idx) {
488 int integer = d3323aa_hp_filter_freq[idx][0] /
489 d3323aa_hp_filter_freq[idx][1];
490 int fract = d3323aa_hp_filter_freq[idx][0] %
491 d3323aa_hp_filter_freq[idx][1];
492
493 if (val == integer && val2 == fract)
494 break;
495 }
496
497 if (idx == ARRAY_SIZE(d3323aa_hp_filter_freq))
498 return -EINVAL;
499
500 if (idx == data->lp_filter_freq_idx) {
501 /* Corresponding filter frequency already set. */
502 return 0;
503 }
504
505 if (idx == 1 && data->lp_filter_freq_idx == 2) {
506 /*
507 * The low-pass cutoff frequency is the only way to
508 * unambiguously choose the type of band-pass filter. For
509 * example, both filter type B (index 1) and C (index 2) have
510 * 0.3 Hz as high-pass cutoff frequency (see
511 * d3323aa_hp_filter_freq). Therefore, if one of these are
512 * requested _and_ the corresponding low-pass filter frequency
513 * is already set, we can't know which filter type is the wanted
514 * one. The low-pass filter frequency is the decider (i.e. in
515 * this case index 2).
516 */
517 return 0;
518 }
519
520 return d3323aa_setup(indio_dev, idx, data->filter_gain_idx,
521 data->detect_thresh);
522 }
523
d3323aa_set_filter_gain(struct iio_dev * indio_dev,const int val)524 static int d3323aa_set_filter_gain(struct iio_dev *indio_dev, const int val)
525 {
526 struct d3323aa_data *data = iio_priv(indio_dev);
527 size_t idx;
528
529 for (idx = 0; idx < ARRAY_SIZE(d3323aa_filter_gain); ++idx) {
530 if (d3323aa_filter_gain[idx] == val)
531 break;
532 }
533
534 if (idx == ARRAY_SIZE(d3323aa_filter_gain))
535 return -EINVAL;
536
537 return d3323aa_setup(indio_dev, data->lp_filter_freq_idx, idx,
538 data->detect_thresh);
539 }
540
d3323aa_set_threshold(struct iio_dev * indio_dev,const int val)541 static int d3323aa_set_threshold(struct iio_dev *indio_dev, const int val)
542 {
543 struct d3323aa_data *data = iio_priv(indio_dev);
544
545 if (val > ((1 << D3323AA_THRESH_REG_NR_BITS) - 1))
546 return -EINVAL;
547
548 return d3323aa_setup(indio_dev, data->lp_filter_freq_idx,
549 data->filter_gain_idx, val);
550 }
551
d3323aa_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)552 static int d3323aa_read_avail(struct iio_dev *indio_dev,
553 struct iio_chan_spec const *chan,
554 const int **vals, int *type, int *length,
555 long mask)
556 {
557 switch (mask) {
558 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
559 *vals = (int *)d3323aa_hp_filter_freq;
560 *type = IIO_VAL_FRACTIONAL;
561 *length = 2 * ARRAY_SIZE(d3323aa_hp_filter_freq);
562 return IIO_AVAIL_LIST;
563 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
564 *vals = (int *)d3323aa_lp_filter_freq;
565 *type = IIO_VAL_FRACTIONAL;
566 *length = 2 * ARRAY_SIZE(d3323aa_lp_filter_freq);
567 return IIO_AVAIL_LIST;
568 case IIO_CHAN_INFO_HARDWAREGAIN:
569 *vals = (int *)d3323aa_filter_gain;
570 *type = IIO_VAL_INT;
571 *length = ARRAY_SIZE(d3323aa_filter_gain);
572 return IIO_AVAIL_LIST;
573 default:
574 return -EINVAL;
575 }
576 }
577
d3323aa_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)578 static int d3323aa_read_raw(struct iio_dev *indio_dev,
579 struct iio_chan_spec const *chan, int *val,
580 int *val2, long mask)
581 {
582 struct d3323aa_data *data = iio_priv(indio_dev);
583
584 guard(mutex)(&data->statevar_lock);
585
586 switch (mask) {
587 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
588 *val = d3323aa_hp_filter_freq[data->lp_filter_freq_idx][0];
589 *val2 = d3323aa_hp_filter_freq[data->lp_filter_freq_idx][1];
590 return IIO_VAL_FRACTIONAL;
591 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
592 *val = d3323aa_lp_filter_freq[data->lp_filter_freq_idx][0];
593 *val2 = d3323aa_lp_filter_freq[data->lp_filter_freq_idx][1];
594 return IIO_VAL_FRACTIONAL;
595 case IIO_CHAN_INFO_HARDWAREGAIN:
596 *val = d3323aa_filter_gain[data->filter_gain_idx];
597 return IIO_VAL_INT;
598 default:
599 return -EINVAL;
600 }
601 }
602
d3323aa_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)603 static int d3323aa_write_raw(struct iio_dev *indio_dev,
604 struct iio_chan_spec const *chan, int val,
605 int val2, long mask)
606 {
607 struct d3323aa_data *data = iio_priv(indio_dev);
608
609 guard(mutex)(&data->statevar_lock);
610
611 switch (mask) {
612 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
613 return d3323aa_set_hp_filter_freq(indio_dev, val, val2);
614 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
615 return d3323aa_set_lp_filter_freq(indio_dev, val, val2);
616 case IIO_CHAN_INFO_HARDWAREGAIN:
617 return d3323aa_set_filter_gain(indio_dev, val);
618 default:
619 return -EINVAL;
620 }
621 }
622
d3323aa_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)623 static int d3323aa_read_event(struct iio_dev *indio_dev,
624 const struct iio_chan_spec *chan,
625 enum iio_event_type type,
626 enum iio_event_direction dir,
627 enum iio_event_info info, int *val, int *val2)
628 {
629 struct d3323aa_data *data = iio_priv(indio_dev);
630
631 guard(mutex)(&data->statevar_lock);
632
633 switch (info) {
634 case IIO_EV_INFO_VALUE:
635 *val = data->detect_thresh;
636 return IIO_VAL_INT;
637 default:
638 return -EINVAL;
639 }
640 }
641
d3323aa_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)642 static int d3323aa_write_event(struct iio_dev *indio_dev,
643 const struct iio_chan_spec *chan,
644 enum iio_event_type type,
645 enum iio_event_direction dir,
646 enum iio_event_info info, int val, int val2)
647 {
648 struct d3323aa_data *data = iio_priv(indio_dev);
649
650 guard(mutex)(&data->statevar_lock);
651
652 switch (info) {
653 case IIO_EV_INFO_VALUE:
654 return d3323aa_set_threshold(indio_dev, val);
655 default:
656 return -EINVAL;
657 }
658 }
659
660 static const struct iio_info d3323aa_info = {
661 .read_avail = d3323aa_read_avail,
662 .read_raw = d3323aa_read_raw,
663 .write_raw = d3323aa_write_raw,
664 .read_event_value = d3323aa_read_event,
665 .write_event_value = d3323aa_write_event,
666 };
667
668 static const struct iio_event_spec d3323aa_event_spec[] = {
669 {
670 .type = IIO_EV_TYPE_THRESH,
671 .dir = IIO_EV_DIR_RISING,
672 .mask_separate = BIT(IIO_EV_INFO_VALUE),
673 },
674 {
675 .type = IIO_EV_TYPE_THRESH,
676 .dir = IIO_EV_DIR_FALLING,
677 .mask_separate = BIT(IIO_EV_INFO_VALUE),
678 },
679 };
680
681 static const struct iio_chan_spec d3323aa_channels[] = {
682 {
683 .type = IIO_PROXIMITY,
684 .info_mask_separate =
685 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) |
686 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
687 BIT(IIO_CHAN_INFO_HARDWAREGAIN),
688 .info_mask_separate_available =
689 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) |
690 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
691 BIT(IIO_CHAN_INFO_HARDWAREGAIN),
692 .event_spec = d3323aa_event_spec,
693 .num_event_specs = ARRAY_SIZE(d3323aa_event_spec),
694 },
695 };
696
d3323aa_disable_regulator(void * indata)697 static void d3323aa_disable_regulator(void *indata)
698 {
699 struct d3323aa_data *data = indata;
700 int ret;
701
702 /*
703 * During probe() the regulator may be disabled. It is enabled during
704 * device setup (in d3323aa_reset(), where it is also briefly disabled).
705 * The check is therefore needed in order to have balanced
706 * regulator_enable/disable() calls.
707 */
708 if (!regulator_is_enabled(data->regulator_vdd))
709 return;
710
711 ret = regulator_disable(data->regulator_vdd);
712 if (ret)
713 dev_err(data->dev, "Could not disable regulator (%d)\n", ret);
714 }
715
d3323aa_probe(struct platform_device * pdev)716 static int d3323aa_probe(struct platform_device *pdev)
717 {
718 struct device *dev = &pdev->dev;
719 struct d3323aa_data *data;
720 struct iio_dev *indio_dev;
721 int ret;
722
723 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
724 if (!indio_dev)
725 return dev_err_probe(dev, -ENOMEM,
726 "Could not allocate iio device\n");
727
728 data = iio_priv(indio_dev);
729 data->dev = dev;
730
731 init_completion(&data->reset_completion);
732
733 ret = devm_mutex_init(dev, &data->statevar_lock);
734 if (ret)
735 return dev_err_probe(dev, ret, "Could not initialize mutex\n");
736
737 data->regulator_vdd = devm_regulator_get_exclusive(dev, "vdd");
738 if (IS_ERR(data->regulator_vdd))
739 return dev_err_probe(dev, PTR_ERR(data->regulator_vdd),
740 "Could not get regulator\n");
741
742 /*
743 * The regulator will be enabled for the first time during the
744 * device setup below (in d3323aa_reset()). However parameter changes
745 * from userspace can require a temporary disable of the regulator.
746 * To avoid complex handling of state, use a callback that will disable
747 * the regulator if it happens to be enabled at time of devm unwind.
748 */
749 ret = devm_add_action_or_reset(dev, d3323aa_disable_regulator, data);
750 if (ret)
751 return ret;
752
753 data->gpiod_clkin_detectout =
754 devm_gpiod_get(dev, "vout-clk", GPIOD_OUT_LOW);
755 if (IS_ERR(data->gpiod_clkin_detectout))
756 return dev_err_probe(dev, PTR_ERR(data->gpiod_clkin_detectout),
757 "Could not get GPIO vout-clk\n");
758
759 data->gpiod_data = devm_gpiod_get(dev, "data", GPIOD_OUT_LOW);
760 if (IS_ERR(data->gpiod_data))
761 return dev_err_probe(dev, PTR_ERR(data->gpiod_data),
762 "Could not get GPIO data\n");
763
764 ret = gpiod_to_irq(data->gpiod_clkin_detectout);
765 if (ret < 0)
766 return dev_err_probe(dev, ret, "Could not get IRQ\n");
767
768 /*
769 * Device signals with a rising or falling detection signal when the
770 * proximity data is above or below the threshold, respectively.
771 */
772 ret = devm_request_irq(dev, ret, d3323aa_irq_handler,
773 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
774 dev_name(dev), indio_dev);
775 if (ret)
776 return dev_err_probe(dev, ret, "Could not request IRQ\n");
777
778 ret = d3323aa_setup(indio_dev, D3323AA_LP_FILTER_FREQ_DEFAULT_IDX,
779 D3323AA_FILTER_GAIN_DEFAULT_IDX,
780 D3323AA_THRESH_DEFAULT_VAL);
781 if (ret)
782 return ret;
783
784 indio_dev->info = &d3323aa_info;
785 indio_dev->name = "d3323aa";
786 indio_dev->channels = d3323aa_channels;
787 indio_dev->num_channels = ARRAY_SIZE(d3323aa_channels);
788
789 ret = devm_iio_device_register(dev, indio_dev);
790 if (ret)
791 return dev_err_probe(dev, ret,
792 "Could not register iio device\n");
793
794 return 0;
795 }
796
797 static const struct of_device_id d3323aa_of_match[] = {
798 {
799 .compatible = "nicera,d3323aa",
800 },
801 { }
802 };
803 MODULE_DEVICE_TABLE(of, d3323aa_of_match);
804
805 static struct platform_driver d3323aa_driver = {
806 .probe = d3323aa_probe,
807 .driver = {
808 .name = "d3323aa",
809 .of_match_table = d3323aa_of_match,
810 },
811 };
812 module_platform_driver(d3323aa_driver);
813
814 MODULE_AUTHOR("Waqar Hameed <waqar.hameed@axis.com>");
815 MODULE_DESCRIPTION("Nicera D3-323-AA PIR sensor driver");
816 MODULE_LICENSE("GPL");
817