1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #include "bxe.h"
31 #include "bxe_elink.h"
32 #include "ecore_mfw_req.h"
33 #include "ecore_fw_defs.h"
34 #include "ecore_hsi.h"
35 #include "ecore_reg.h"
36
37
38 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
39 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
40 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
41 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
42 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
43
44 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
45 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
46 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
47 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
48 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
49 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
50 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
51 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
52 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
53 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
54 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
55 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
56 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
57 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
58 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
59 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
60 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
61
62 #define MDIO_REG_BANK_RX0 0x80b0
63 #define MDIO_RX0_RX_STATUS 0x10
64 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
65 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
66 #define MDIO_RX0_RX_EQ_BOOST 0x1c
67 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
68 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
69
70 #define MDIO_REG_BANK_RX1 0x80c0
71 #define MDIO_RX1_RX_EQ_BOOST 0x1c
72 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
73 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
74
75 #define MDIO_REG_BANK_RX2 0x80d0
76 #define MDIO_RX2_RX_EQ_BOOST 0x1c
77 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
78 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
79
80 #define MDIO_REG_BANK_RX3 0x80e0
81 #define MDIO_RX3_RX_EQ_BOOST 0x1c
82 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
83 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
84
85 #define MDIO_REG_BANK_RX_ALL 0x80f0
86 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
87 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
88 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
89
90 #define MDIO_REG_BANK_TX0 0x8060
91 #define MDIO_TX0_TX_DRIVER 0x17
92 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
93 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
94 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
95 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
96 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
97 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
98 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
99 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
100 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
101
102 #define MDIO_REG_BANK_TX1 0x8070
103 #define MDIO_TX1_TX_DRIVER 0x17
104 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
105 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
106 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
107 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
108 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
109 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
110 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
111 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
112 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
113
114 #define MDIO_REG_BANK_TX2 0x8080
115 #define MDIO_TX2_TX_DRIVER 0x17
116 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
117 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
118 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
119 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
120 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
121 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
122 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
123 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
124 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
125
126 #define MDIO_REG_BANK_TX3 0x8090
127 #define MDIO_TX3_TX_DRIVER 0x17
128 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
129 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
130 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
131 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
132 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
133 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
134 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
135 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
136 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
137
138 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
139 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
140
141 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
142 #define MDIO_BLOCK1_LANE_CTRL0 0x15
143 #define MDIO_BLOCK1_LANE_CTRL1 0x16
144 #define MDIO_BLOCK1_LANE_CTRL2 0x17
145 #define MDIO_BLOCK1_LANE_PRBS 0x19
146
147 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
148 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
149 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
150 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
151 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
152 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
153 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
154 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
155 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
156 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
157
158 #define MDIO_REG_BANK_GP_STATUS 0x8120
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
183 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
184 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
185 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
186 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
187 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
188 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
189
190
191 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
192 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
193 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
194 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
195 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
196 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
197 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
198
199 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
201 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
202 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
203 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
204 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
205 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
206 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
207 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
208 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
209 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
213 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
214 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
215 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
216 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
217 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
218 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
219 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
220 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
221 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
222 #define MDIO_SERDES_DIGITAL_MISC1 0x18
223 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
224 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
225 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
226 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
227 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
228 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
232 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
233 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
234 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
235 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
236 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
237 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
238 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
239 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
240 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
241
242 #define MDIO_REG_BANK_OVER_1G 0x8320
243 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
244 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
245 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
246 #define MDIO_OVER_1G_UP1 0x19
247 #define MDIO_OVER_1G_UP1_2_5G 0x0001
248 #define MDIO_OVER_1G_UP1_5G 0x0002
249 #define MDIO_OVER_1G_UP1_6G 0x0004
250 #define MDIO_OVER_1G_UP1_10G 0x0010
251 #define MDIO_OVER_1G_UP1_10GH 0x0008
252 #define MDIO_OVER_1G_UP1_12G 0x0020
253 #define MDIO_OVER_1G_UP1_12_5G 0x0040
254 #define MDIO_OVER_1G_UP1_13G 0x0080
255 #define MDIO_OVER_1G_UP1_15G 0x0100
256 #define MDIO_OVER_1G_UP1_16G 0x0200
257 #define MDIO_OVER_1G_UP2 0x1A
258 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
259 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
260 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
261 #define MDIO_OVER_1G_UP3 0x1B
262 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
263 #define MDIO_OVER_1G_LP_UP1 0x1C
264 #define MDIO_OVER_1G_LP_UP2 0x1D
265 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
266 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
267 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
268 #define MDIO_OVER_1G_LP_UP3 0x1E
269
270 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
271 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
272 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
273 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
274
275 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
276 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
277 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
278 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
279
280 #define MDIO_REG_BANK_CL73_USERB0 0x8370
281 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
282 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
283 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
284 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
285 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
286 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
287 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
288 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
289 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
290 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
291 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
292
293 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
294 #define MDIO_AER_BLOCK_AER_REG 0x1E
295
296 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
297 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
298 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
299 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
300 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
301 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
302 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
303 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
304 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
305 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
306 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
307 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
308 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
309 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
320 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
321 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
322 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
324 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
325 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
326 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
327 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
328 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
329 Theotherbitsarereservedandshouldbezero*/
330 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
331
332
333 #define MDIO_PMA_DEVAD 0x1
334 /*ieee*/
335 #define MDIO_PMA_REG_CTRL 0x0
336 #define MDIO_PMA_REG_STATUS 0x1
337 #define MDIO_PMA_REG_10G_CTRL2 0x7
338 #define MDIO_PMA_REG_TX_DISABLE 0x0009
339 #define MDIO_PMA_REG_RX_SD 0xa
340 /*bcm*/
341 #define MDIO_PMA_REG_BCM_CTRL 0x0096
342 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
343 #define MDIO_PMA_LASI_RXCTRL 0x9000
344 #define MDIO_PMA_LASI_TXCTRL 0x9001
345 #define MDIO_PMA_LASI_CTRL 0x9002
346 #define MDIO_PMA_LASI_RXSTAT 0x9003
347 #define MDIO_PMA_LASI_TXSTAT 0x9004
348 #define MDIO_PMA_LASI_STAT 0x9005
349 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
350 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
351 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
352 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
353 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
354 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
355 #define MDIO_PMA_REG_GEN_CTRL 0xca10
356 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
357 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
358 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
359 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
360 #define MDIO_PMA_REG_ROM_VER1 0xca19
361 #define MDIO_PMA_REG_ROM_VER2 0xca1a
362 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
363 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
364 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
365 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
366 #define MDIO_PMA_REG_LRM_MODE 0xca3f
367 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
368 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
369
370 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
371 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
372 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
373 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
374 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
375 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
376 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
377 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
378 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
379 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
380 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
381 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
382
383 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
384 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
385 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
386 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
387 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
388 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
389 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
390 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
391 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
392 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
393
394 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
395 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
396 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
397 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
398 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
399
400 #define MDIO_PMA_REG_7101_RESET 0xc000
401 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
402 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
403 #define MDIO_PMA_REG_7101_VER1 0xc026
404 #define MDIO_PMA_REG_7101_VER2 0xc027
405
406 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
407 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
408 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
409 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
410 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
411 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
412 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
413 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
414 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
415 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
416
417
418
419 #define MDIO_WIS_DEVAD 0x2
420 /*bcm*/
421 #define MDIO_WIS_REG_LASI_CNTL 0x9002
422 #define MDIO_WIS_REG_LASI_STATUS 0x9005
423
424 #define MDIO_PCS_DEVAD 0x3
425 #define MDIO_PCS_REG_STATUS 0x0020
426 #define MDIO_PCS_REG_LASI_STATUS 0x9005
427 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
428 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
429 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
430 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
431 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
432 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
433 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
434 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
435 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
436
437
438
439 #define MDIO_XS_DEVAD 0x4
440 #define MDIO_XS_REG_STATUS 0x0001
441 #define MDIO_XS_PLL_SEQUENCER 0x8000
442 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
443
444 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
445 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
446 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
447 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
448 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
449
450 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
451
452 #define MDIO_AN_DEVAD 0x7
453 /*ieee*/
454 #define MDIO_AN_REG_CTRL 0x0000
455 #define MDIO_AN_REG_STATUS 0x0001
456 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
457 #define MDIO_AN_REG_ADV_PAUSE 0x0010
458 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
459 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
460 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
461 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
462 #define MDIO_AN_REG_ADV 0x0011
463 #define MDIO_AN_REG_ADV2 0x0012
464 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
465 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
466 #define MDIO_AN_REG_MASTER_STATUS 0x0021
467 #define MDIO_AN_REG_EEE_ADV 0x003c
468 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
469 /*bcm*/
470 #define MDIO_AN_REG_LINK_STATUS 0x8304
471 #define MDIO_AN_REG_CL37_CL73 0x8370
472 #define MDIO_AN_REG_CL37_AN 0xffe0
473 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
474 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
475 #define MDIO_AN_REG_1000T_STATUS 0xffea
476
477 #define MDIO_AN_REG_8073_2_5G 0x8329
478 #define MDIO_AN_REG_8073_BAM 0x8350
479
480 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
481 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
482 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
483 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
484 #define MDIO_AN_REG_848xx_ID_MSB 0xffe2
485 #define BCM84858_PHY_ID 0x600d
486 #define MDIO_AN_REG_848xx_ID_LSB 0xffe3
487 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
488 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
489 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
490 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
491 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
492 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
493 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
494 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
495 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
496
497 /* BCM84823 only */
498 #define MDIO_CTL_DEVAD 0x1e
499 #define MDIO_CTL_REG_84823_MEDIA 0x401a
500 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
501 /* These pins configure the BCM84823 interface to MAC after reset. */
502 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
503 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
504 /* These pins configure the BCM84823 interface to Line after reset. */
505 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
506 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
507 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
510 */
511 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
512 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
513 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
514 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
515 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
516 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
517 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
518 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
519 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
520 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
521 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
522 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
523
524 /* BCM84833 only */
525 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
526 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
527 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
528 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
529 #define MDIO_84833_SUPER_ISOLATE 0x8000
530 /* These are mailbox register set used by 84833/84858. */
531 #define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
532 #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
533 #define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
534 #define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
535 #define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
536 #define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
537 #define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
538 #define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
539 #define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
540 #define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
541 #define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
542 #define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
543 #define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
544 #define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
545 #define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
546 #define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
547 #define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
548 #define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
549
550 /* Mailbox command set used by 84833/84858 */
551 #define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
552 #define PHY848xx_CMD_GET_EEE_MODE 0x8008
553 #define PHY848xx_CMD_SET_EEE_MODE 0x8009
554 #define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
555 /* Mailbox status set used by 84833 only */
556 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
557 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
558 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
559 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
560 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
561 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
562 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
563 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
564 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
565 /* Mailbox Process */
566 #define PHY84833_MB_PROCESS1 1
567 #define PHY84833_MB_PROCESS2 2
568 #define PHY84833_MB_PROCESS3 3
569
570
571 /* Mailbox status set used by 84858 only */
572 #define PHY84858_STATUS_CMD_RECEIVED 0x0001
573 #define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
574 #define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
575 #define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
576 #define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
577
578
579 /* Warpcore clause 45 addressing */
580 #define MDIO_WC_DEVAD 0x3
581 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
582 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
583 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
584 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
585 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
586 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
587 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
588 #define MDIO_WC_REG_PCS_STATUS2 0x0021
589 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
590 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
591 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
592 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
593 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
594 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
595 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
596 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
597 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
598 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
599 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
600 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
601 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
602 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
603 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
604 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
605 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
606 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
607 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
608 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
609 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
610 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
611 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
612 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
613 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
614 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
615 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
616 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
617 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
618 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
619 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
620 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
621 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
622 #define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
623 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
624 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
625 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
626 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
627 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
628 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
629 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
630 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
631 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
632 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
633 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
634 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
635 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
636 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
637 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
638 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
639 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
640 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
641 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
642 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
643 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
644 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
645 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
646 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
647 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
648 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
649 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
650 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
651 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
652 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
653 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
654 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
655 #define MDIO_WC_REG_DSC_SMC 0x8213
656 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
657 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
658 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
659 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
660 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
661 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
662 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
663 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
664 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
665 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
666 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
667 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
668 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
669 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
670 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
671 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
672 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
673 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
674 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
675 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
676 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
677 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
678 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
679 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
680 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
681 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
682 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
683 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
684 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
685 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
686 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
687 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
688 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
689 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
690 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
691 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
692 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
693 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
694 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
695 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
696 #define MDIO_WC_REG_RX66_SCW0 0x83c2
697 #define MDIO_WC_REG_RX66_SCW1 0x83c3
698 #define MDIO_WC_REG_RX66_SCW2 0x83c4
699 #define MDIO_WC_REG_RX66_SCW3 0x83c5
700 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
701 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
702 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
703 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
704 #define MDIO_WC_REG_FX100_CTRL1 0x8400
705 #define MDIO_WC_REG_FX100_CTRL3 0x8402
706 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
707 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
708 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
709 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
710 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
711 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
712 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
713 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
714 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
715 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
716 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
717 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
718 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
719 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
720
721 #define MDIO_WC_REG_AERBLK_AER 0xffde
722 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
723 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
724
725 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
726 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
727 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
728
729 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
730
731 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
732
733 /* 54618se */
734 #define MDIO_REG_GPHY_MII_STATUS 0x1
735 #define MDIO_REG_GPHY_PHYID_LSB 0x3
736 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
737 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
738 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
739 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
740 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
741 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
742 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
743 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
744 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
745 #define MDIO_REG_GPHY_AUX_STATUS 0x19
746 #define MDIO_REG_INTR_STATUS 0x1a
747 #define MDIO_REG_INTR_MASK 0x1b
748 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
749 #define MDIO_REG_GPHY_SHADOW 0x1c
750 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
751 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
752 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
753 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
754 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
755
756
757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
758 struct elink_params *params,
759 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
760 uint8_t *o_buf, uint8_t);
761 /********************************************************/
762 #define ELINK_ETH_HLEN 14
763 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
764 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
765 #define ELINK_ETH_MIN_PACKET_SIZE 60
766 #define ELINK_ETH_MAX_PACKET_SIZE 1500
767 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
768 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
769 #define WC_LANE_MAX 4
770 #define I2C_SWITCH_WIDTH 2
771 #define I2C_BSC0 0
772 #define I2C_BSC1 1
773 #define I2C_WA_RETRY_CNT 3
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
775 #define MCPR_IMC_COMMAND_READ_OP 1
776 #define MCPR_IMC_COMMAND_WRITE_OP 2
777
778 /* LED Blink rate that will achieve ~15.9Hz */
779 #define LED_BLINK_RATE_VAL_E3 354
780 #define LED_BLINK_RATE_VAL_E1X_E2 480
781 /***********************************************************/
782 /* Shortcut definitions */
783 /***********************************************************/
784
785 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
786
787 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
788 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
789 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
790 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
791 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
792 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
793 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
794 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
795 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
796 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
797 #define ELINK_NIG_MASK_MI_INT \
798 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
799 #define ELINK_NIG_MASK_XGXS0_LINK10G \
800 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
801 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
802 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
803 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
804 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
805
806 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
807 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
808 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
809
810 #define ELINK_XGXS_RESET_BITS \
811 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
812 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
813 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
814 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
815 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
816
817 #define ELINK_SERDES_RESET_BITS \
818 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
819 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
820 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
821 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
822
823 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
824 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
825 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
826 #define ELINK_AUTONEG_PARALLEL \
827 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
828 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
829 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
830 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
831
832 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
833 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
834 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
835 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
836 #define ELINK_GP_STATUS_SPEED_MASK \
837 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
838 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
839 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
840 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
841 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
842 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
843 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
844 #define ELINK_GP_STATUS_10G_HIG \
845 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
846 #define ELINK_GP_STATUS_10G_CX4 \
847 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
848 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
849 #define ELINK_GP_STATUS_10G_KX4 \
850 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
851 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
852 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
853 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
854 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
855 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
856 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
857 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
858 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
859 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
860 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
861 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
862 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
863 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
864 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
865 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
866 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
867 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
868 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
869 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
870 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
871
872 #define ELINK_LINK_UPDATE_MASK \
873 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
874 LINK_STATUS_LINK_UP | \
875 LINK_STATUS_PHYSICAL_LINK_FLAG | \
876 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
877 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
878 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
879 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
880 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
881 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
882
883 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
884 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
885 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
886 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
887 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
888
889
890 #define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
891 #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4)
892 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5)
893 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6)
894
895 #define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
896 #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1<<0)
897 #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1<<1)
898 #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1<<2)
899 #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3)
900
901 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
902 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
903 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
904
905 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
906 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
907 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
908
909 #define ELINK_EDC_MODE_LINEAR 0x0022
910 #define ELINK_EDC_MODE_LIMITING 0x0044
911 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
912 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
913
914 /* ETS defines*/
915 #define DCBX_INVALID_COS (0xFF)
916
917 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
918 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
919 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
920 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
921 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
922
923 #define ELINK_MAX_PACKET_SIZE (9700)
924 #define MAX_KR_LINK_RETRY 4
925 #define DEFAULT_TX_DRV_BRDCT 2
926 #define DEFAULT_TX_DRV_IFIR 0
927 #define DEFAULT_TX_DRV_POST2 3
928 #define DEFAULT_TX_DRV_IPRE_DRIVER 6
929
930 /**********************************************************/
931 /* INTERFACE */
932 /**********************************************************/
933
934 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
935 elink_cl45_write(_sc, _phy, \
936 (_phy)->def_md_devad, \
937 (_bank + (_addr & 0xf)), \
938 _val)
939
940 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
941 elink_cl45_read(_sc, _phy, \
942 (_phy)->def_md_devad, \
943 (_bank + (_addr & 0xf)), \
944 _val)
945
946 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
947 struct elink_vars *vars, uint8_t notify);
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
949 struct elink_params *params);
950
elink_bits_en(struct bxe_softc * sc,uint32_t reg,uint32_t bits)951 static uint32_t elink_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
952 {
953 uint32_t val = REG_RD(sc, reg);
954
955 val |= bits;
956 REG_WR(sc, reg, val);
957 return val;
958 }
959
elink_bits_dis(struct bxe_softc * sc,uint32_t reg,uint32_t bits)960 static uint32_t elink_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
961 {
962 uint32_t val = REG_RD(sc, reg);
963
964 val &= ~bits;
965 REG_WR(sc, reg, val);
966 return val;
967 }
968
969 /*
970 * elink_check_lfa - This function checks if link reinitialization is required,
971 * or link flap can be avoided.
972 *
973 * @params: link parameters
974 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
975 * condition code.
976 */
elink_check_lfa(struct elink_params * params)977 static int elink_check_lfa(struct elink_params *params)
978 {
979 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
980 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
981 uint32_t saved_val, req_val, eee_status;
982 struct bxe_softc *sc = params->sc;
983
984 additional_config =
985 REG_RD(sc, params->lfa_base +
986 offsetof(struct shmem_lfa, additional_config));
987
988 /* NOTE: must be first condition checked -
989 * to verify DCC bit is cleared in any case!
990 */
991 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
992 ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit\n");
993 REG_WR(sc, params->lfa_base +
994 offsetof(struct shmem_lfa, additional_config),
995 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
996 return LFA_DCC_LFA_DISABLED;
997 }
998
999 /* Verify that link is up */
1000 link_status = REG_RD(sc, params->shmem_base +
1001 offsetof(struct shmem_region,
1002 port_mb[params->port].link_status));
1003 if (!(link_status & LINK_STATUS_LINK_UP))
1004 return LFA_LINK_DOWN;
1005
1006 /* if loaded after BOOT from SAN, don't flap the link in any case and
1007 * rely on link set by preboot driver
1008 */
1009 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
1010 return 0;
1011
1012 /* Verify that loopback mode is not set */
1013 if (params->loopback_mode)
1014 return LFA_LOOPBACK_ENABLED;
1015
1016 /* Verify that MFW supports LFA */
1017 if (!params->lfa_base)
1018 return LFA_MFW_IS_TOO_OLD;
1019
1020 if (params->num_phys == 3) {
1021 cfg_size = 2;
1022 lfa_mask = 0xffffffff;
1023 } else {
1024 cfg_size = 1;
1025 lfa_mask = 0xffff;
1026 }
1027
1028 /* Compare Duplex */
1029 saved_val = REG_RD(sc, params->lfa_base +
1030 offsetof(struct shmem_lfa, req_duplex));
1031 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
1032 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1033 ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x\n",
1034 (saved_val & lfa_mask), (req_val & lfa_mask));
1035 return LFA_DUPLEX_MISMATCH;
1036 }
1037 /* Compare Flow Control */
1038 saved_val = REG_RD(sc, params->lfa_base +
1039 offsetof(struct shmem_lfa, req_flow_ctrl));
1040 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
1041 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1042 ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x\n",
1043 (saved_val & lfa_mask), (req_val & lfa_mask));
1044 return LFA_FLOW_CTRL_MISMATCH;
1045 }
1046 /* Compare Link Speed */
1047 saved_val = REG_RD(sc, params->lfa_base +
1048 offsetof(struct shmem_lfa, req_line_speed));
1049 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1050 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1051 ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x\n",
1052 (saved_val & lfa_mask), (req_val & lfa_mask));
1053 return LFA_LINK_SPEED_MISMATCH;
1054 }
1055
1056 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1057 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1058 offsetof(struct shmem_lfa,
1059 speed_cap_mask[cfg_idx]));
1060
1061 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1062 ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x\n",
1063 cur_speed_cap_mask,
1064 params->speed_cap_mask[cfg_idx]);
1065 return LFA_SPEED_CAP_MISMATCH;
1066 }
1067 }
1068
1069 cur_req_fc_auto_adv =
1070 REG_RD(sc, params->lfa_base +
1071 offsetof(struct shmem_lfa, additional_config)) &
1072 REQ_FC_AUTO_ADV_MASK;
1073
1074 if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1075 ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x\n",
1076 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1077 return LFA_FLOW_CTRL_MISMATCH;
1078 }
1079
1080 eee_status = REG_RD(sc, params->shmem2_base +
1081 offsetof(struct shmem2_region,
1082 eee_status[params->port]));
1083
1084 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1085 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1086 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1087 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1088 ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x\n", params->eee_mode,
1089 eee_status);
1090 return LFA_EEE_MISMATCH;
1091 }
1092
1093 /* LFA conditions are met */
1094 return 0;
1095 }
1096 /******************************************************************/
1097 /* EPIO/GPIO section */
1098 /******************************************************************/
elink_get_epio(struct bxe_softc * sc,uint32_t epio_pin,uint32_t * en)1099 static void elink_get_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t *en)
1100 {
1101 uint32_t epio_mask, gp_oenable;
1102 *en = 0;
1103 /* Sanity check */
1104 if (epio_pin > 31) {
1105 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get\n", epio_pin);
1106 return;
1107 }
1108
1109 epio_mask = 1 << epio_pin;
1110 /* Set this EPIO to output */
1111 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1112 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1113
1114 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1115 }
elink_set_epio(struct bxe_softc * sc,uint32_t epio_pin,uint32_t en)1116 static void elink_set_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t en)
1117 {
1118 uint32_t epio_mask, gp_output, gp_oenable;
1119
1120 /* Sanity check */
1121 if (epio_pin > 31) {
1122 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set\n", epio_pin);
1123 return;
1124 }
1125 ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d\n", epio_pin, en);
1126 epio_mask = 1 << epio_pin;
1127 /* Set this EPIO to output */
1128 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1129 if (en)
1130 gp_output |= epio_mask;
1131 else
1132 gp_output &= ~epio_mask;
1133
1134 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1135
1136 /* Set the value for this EPIO */
1137 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1138 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1139 }
1140
elink_set_cfg_pin(struct bxe_softc * sc,uint32_t pin_cfg,uint32_t val)1141 static void elink_set_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t val)
1142 {
1143 if (pin_cfg == PIN_CFG_NA)
1144 return;
1145 if (pin_cfg >= PIN_CFG_EPIO0) {
1146 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1147 } else {
1148 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1149 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1150 elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);
1151 }
1152 }
1153
elink_get_cfg_pin(struct bxe_softc * sc,uint32_t pin_cfg,uint32_t * val)1154 static uint32_t elink_get_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t *val)
1155 {
1156 if (pin_cfg == PIN_CFG_NA)
1157 return ELINK_STATUS_ERROR;
1158 if (pin_cfg >= PIN_CFG_EPIO0) {
1159 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1160 } else {
1161 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1162 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1163 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1164 }
1165 return ELINK_STATUS_OK;
1166
1167 }
1168 /******************************************************************/
1169 /* ETS section */
1170 /******************************************************************/
elink_ets_e2e3a0_disabled(struct elink_params * params)1171 static void elink_ets_e2e3a0_disabled(struct elink_params *params)
1172 {
1173 /* ETS disabled configuration*/
1174 struct bxe_softc *sc = params->sc;
1175
1176 ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration\n");
1177
1178 /* mapping between entry priority to client number (0,1,2 -debug and
1179 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1180 * 3bits client num.
1181 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1182 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
1183 */
1184
1185 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1186 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1187 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1188 * COS0 entry, 4 - COS1 entry.
1189 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1190 * bit4 bit3 bit2 bit1 bit0
1191 * MCP and debug are strict
1192 */
1193
1194 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1195 /* defines which entries (clients) are subjected to WFQ arbitration */
1196 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1197 /* For strict priority entries defines the number of consecutive
1198 * slots for the highest priority.
1199 */
1200 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1201 /* mapping between the CREDIT_WEIGHT registers and actual client
1202 * numbers
1203 */
1204 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
1205 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
1206 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
1207
1208 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
1209 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
1210 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
1211 /* ETS mode disable */
1212 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
1213 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
1214 * weight for COS0/COS1.
1215 */
1216 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
1217 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
1218 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
1219 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
1220 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
1221 /* Defines the number of consecutive slots for the strict priority */
1222 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1223 }
1224 /******************************************************************************
1225 * Description:
1226 * Getting min_w_val will be set according to line speed .
1227 *.
1228 ******************************************************************************/
elink_ets_get_min_w_val_nig(const struct elink_vars * vars)1229 static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
1230 {
1231 uint32_t min_w_val = 0;
1232 /* Calculate min_w_val.*/
1233 if (vars->link_up) {
1234 if (vars->line_speed == ELINK_SPEED_20000)
1235 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1236 else
1237 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
1238 } else
1239 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1240 /* If the link isn't up (static configuration for example ) The
1241 * link will be according to 20GBPS.
1242 */
1243 return min_w_val;
1244 }
1245 /******************************************************************************
1246 * Description:
1247 * Getting credit upper bound form min_w_val.
1248 *.
1249 ******************************************************************************/
elink_ets_get_credit_upper_bound(const uint32_t min_w_val)1250 static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)
1251 {
1252 const uint32_t credit_upper_bound = (uint32_t)ELINK_MAXVAL((150 * min_w_val),
1253 ELINK_MAX_PACKET_SIZE);
1254 return credit_upper_bound;
1255 }
1256 /******************************************************************************
1257 * Description:
1258 * Set credit upper bound for NIG.
1259 *.
1260 ******************************************************************************/
elink_ets_e3b0_set_credit_upper_bound_nig(const struct elink_params * params,const uint32_t min_w_val)1261 static void elink_ets_e3b0_set_credit_upper_bound_nig(
1262 const struct elink_params *params,
1263 const uint32_t min_w_val)
1264 {
1265 struct bxe_softc *sc = params->sc;
1266 const uint8_t port = params->port;
1267 const uint32_t credit_upper_bound =
1268 elink_ets_get_credit_upper_bound(min_w_val);
1269
1270 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
1271 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
1272 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
1273 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
1274 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
1275 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
1276 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
1277 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
1278 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
1279 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
1280 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
1281 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
1282
1283 if (!port) {
1284 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
1285 credit_upper_bound);
1286 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
1287 credit_upper_bound);
1288 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
1289 credit_upper_bound);
1290 }
1291 }
1292 /******************************************************************************
1293 * Description:
1294 * Will return the NIG ETS registers to init values.Except
1295 * credit_upper_bound.
1296 * That isn't used in this configuration (No WFQ is enabled) and will be
1297 * configured according to spec.
1298 *.
1299 ******************************************************************************/
elink_ets_e3b0_nig_disabled(const struct elink_params * params,const struct elink_vars * vars)1300 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
1301 const struct elink_vars *vars)
1302 {
1303 struct bxe_softc *sc = params->sc;
1304 const uint8_t port = params->port;
1305 const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);
1306 /* Mapping between entry priority to client number (0,1,2 -debug and
1307 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
1308 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
1309 * reset value or init tool
1310 */
1311 if (port) {
1312 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
1313 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
1314 } else {
1315 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
1316 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
1317 }
1318 /* For strict priority entries defines the number of consecutive
1319 * slots for the highest priority.
1320 */
1321 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
1322 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1323 /* Mapping between the CREDIT_WEIGHT registers and actual client
1324 * numbers
1325 */
1326 if (port) {
1327 /*Port 1 has 6 COS*/
1328 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
1329 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
1330 } else {
1331 /*Port 0 has 9 COS*/
1332 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
1333 0x43210876);
1334 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
1335 }
1336
1337 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1338 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1339 * COS0 entry, 4 - COS1 entry.
1340 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1341 * bit4 bit3 bit2 bit1 bit0
1342 * MCP and debug are strict
1343 */
1344 if (port)
1345 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
1346 else
1347 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
1348 /* defines which entries (clients) are subjected to WFQ arbitration */
1349 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1350 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1351
1352 /* Please notice the register address are note continuous and a
1353 * for here is note appropriate.In 2 port mode port0 only COS0-5
1354 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
1355 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
1356 * are never used for WFQ
1357 */
1358 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1359 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
1360 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1361 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
1362 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1363 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
1364 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
1365 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
1366 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
1367 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
1368 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
1369 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
1370 if (!port) {
1371 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
1372 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
1373 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
1374 }
1375
1376 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
1377 }
1378 /******************************************************************************
1379 * Description:
1380 * Set credit upper bound for PBF.
1381 *.
1382 ******************************************************************************/
elink_ets_e3b0_set_credit_upper_bound_pbf(const struct elink_params * params,const uint32_t min_w_val)1383 static void elink_ets_e3b0_set_credit_upper_bound_pbf(
1384 const struct elink_params *params,
1385 const uint32_t min_w_val)
1386 {
1387 struct bxe_softc *sc = params->sc;
1388 const uint32_t credit_upper_bound =
1389 elink_ets_get_credit_upper_bound(min_w_val);
1390 const uint8_t port = params->port;
1391 uint32_t base_upper_bound = 0;
1392 uint8_t max_cos = 0;
1393 uint8_t i = 0;
1394 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
1395 * port mode port1 has COS0-2 that can be used for WFQ.
1396 */
1397 if (!port) {
1398 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
1399 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1400 } else {
1401 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
1402 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1403 }
1404
1405 for (i = 0; i < max_cos; i++)
1406 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
1407 }
1408
1409 /******************************************************************************
1410 * Description:
1411 * Will return the PBF ETS registers to init values.Except
1412 * credit_upper_bound.
1413 * That isn't used in this configuration (No WFQ is enabled) and will be
1414 * configured according to spec.
1415 *.
1416 ******************************************************************************/
elink_ets_e3b0_pbf_disabled(const struct elink_params * params)1417 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
1418 {
1419 struct bxe_softc *sc = params->sc;
1420 const uint8_t port = params->port;
1421 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1422 uint8_t i = 0;
1423 uint32_t base_weight = 0;
1424 uint8_t max_cos = 0;
1425
1426 /* Mapping between entry priority to client number 0 - COS0
1427 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
1428 * TODO_ETS - Should be done by reset value or init tool
1429 */
1430 if (port)
1431 /* 0x688 (|011|0 10|00 1|000) */
1432 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
1433 else
1434 /* (10 1|100 |011|0 10|00 1|000) */
1435 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
1436
1437 /* TODO_ETS - Should be done by reset value or init tool */
1438 if (port)
1439 /* 0x688 (|011|0 10|00 1|000)*/
1440 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
1441 else
1442 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
1443 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
1444
1445 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
1446 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
1447
1448
1449 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1450 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
1451
1452 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1453 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
1454 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
1455 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
1456 */
1457 if (!port) {
1458 base_weight = PBF_REG_COS0_WEIGHT_P0;
1459 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1460 } else {
1461 base_weight = PBF_REG_COS0_WEIGHT_P1;
1462 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1463 }
1464
1465 for (i = 0; i < max_cos; i++)
1466 REG_WR(sc, base_weight + (0x4 * i), 0);
1467
1468 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1469 }
1470 /******************************************************************************
1471 * Description:
1472 * E3B0 disable will return basically the values to init values.
1473 *.
1474 ******************************************************************************/
elink_ets_e3b0_disabled(const struct elink_params * params,const struct elink_vars * vars)1475 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
1476 const struct elink_vars *vars)
1477 {
1478 struct bxe_softc *sc = params->sc;
1479
1480 if (!CHIP_IS_E3B0(sc)) {
1481 ELINK_DEBUG_P0(sc,
1482 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1483 return ELINK_STATUS_ERROR;
1484 }
1485
1486 elink_ets_e3b0_nig_disabled(params, vars);
1487
1488 elink_ets_e3b0_pbf_disabled(params);
1489
1490 return ELINK_STATUS_OK;
1491 }
1492
1493 /******************************************************************************
1494 * Description:
1495 * Disable will return basically the values to init values.
1496 *
1497 ******************************************************************************/
elink_ets_disabled(struct elink_params * params,struct elink_vars * vars)1498 elink_status_t elink_ets_disabled(struct elink_params *params,
1499 struct elink_vars *vars)
1500 {
1501 struct bxe_softc *sc = params->sc;
1502 elink_status_t elink_status = ELINK_STATUS_OK;
1503
1504 if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc)))
1505 elink_ets_e2e3a0_disabled(params);
1506 else if (CHIP_IS_E3B0(sc))
1507 elink_status = elink_ets_e3b0_disabled(params, vars);
1508 else {
1509 ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported\n");
1510 return ELINK_STATUS_ERROR;
1511 }
1512
1513 return elink_status;
1514 }
1515
1516 /******************************************************************************
1517 * Description
1518 * Set the COS mappimg to SP and BW until this point all the COS are not
1519 * set as SP or BW.
1520 ******************************************************************************/
elink_ets_e3b0_cli_map(const struct elink_params * params,const struct elink_ets_params * ets_params,const uint8_t cos_sp_bitmap,const uint8_t cos_bw_bitmap)1521 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
1522 const struct elink_ets_params *ets_params,
1523 const uint8_t cos_sp_bitmap,
1524 const uint8_t cos_bw_bitmap)
1525 {
1526 struct bxe_softc *sc = params->sc;
1527 const uint8_t port = params->port;
1528 const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
1529 const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;
1530 const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
1531 const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
1532
1533 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
1534 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
1535
1536 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1537 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
1538
1539 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1540 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
1541 nig_cli_subject2wfq_bitmap);
1542
1543 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1544 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
1545 pbf_cli_subject2wfq_bitmap);
1546
1547 return ELINK_STATUS_OK;
1548 }
1549
1550 /******************************************************************************
1551 * Description:
1552 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1553 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1554 ******************************************************************************/
elink_ets_e3b0_set_cos_bw(struct bxe_softc * sc,const uint8_t cos_entry,const uint32_t min_w_val_nig,const uint32_t min_w_val_pbf,const uint16_t total_bw,const uint8_t bw,const uint8_t port)1555 static elink_status_t elink_ets_e3b0_set_cos_bw(struct bxe_softc *sc,
1556 const uint8_t cos_entry,
1557 const uint32_t min_w_val_nig,
1558 const uint32_t min_w_val_pbf,
1559 const uint16_t total_bw,
1560 const uint8_t bw,
1561 const uint8_t port)
1562 {
1563 uint32_t nig_reg_adress_crd_weight = 0;
1564 uint32_t pbf_reg_adress_crd_weight = 0;
1565 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
1566 const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
1567 const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
1568
1569 switch (cos_entry) {
1570 case 0:
1571 nig_reg_adress_crd_weight =
1572 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1573 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
1574 pbf_reg_adress_crd_weight = (port) ?
1575 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
1576 break;
1577 case 1:
1578 nig_reg_adress_crd_weight = (port) ?
1579 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1580 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
1581 pbf_reg_adress_crd_weight = (port) ?
1582 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
1583 break;
1584 case 2:
1585 nig_reg_adress_crd_weight = (port) ?
1586 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1587 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
1588
1589 pbf_reg_adress_crd_weight = (port) ?
1590 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
1591 break;
1592 case 3:
1593 if (port)
1594 return ELINK_STATUS_ERROR;
1595 nig_reg_adress_crd_weight =
1596 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
1597 pbf_reg_adress_crd_weight =
1598 PBF_REG_COS3_WEIGHT_P0;
1599 break;
1600 case 4:
1601 if (port)
1602 return ELINK_STATUS_ERROR;
1603 nig_reg_adress_crd_weight =
1604 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
1605 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
1606 break;
1607 case 5:
1608 if (port)
1609 return ELINK_STATUS_ERROR;
1610 nig_reg_adress_crd_weight =
1611 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
1612 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
1613 break;
1614 }
1615
1616 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig);
1617
1618 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf);
1619
1620 return ELINK_STATUS_OK;
1621 }
1622 /******************************************************************************
1623 * Description:
1624 * Calculate the total BW.A value of 0 isn't legal.
1625 *
1626 ******************************************************************************/
elink_ets_e3b0_get_total_bw(const struct elink_params * params,struct elink_ets_params * ets_params,uint16_t * total_bw)1627 static elink_status_t elink_ets_e3b0_get_total_bw(
1628 const struct elink_params *params,
1629 struct elink_ets_params *ets_params,
1630 uint16_t *total_bw)
1631 {
1632 struct bxe_softc *sc = params->sc;
1633 uint8_t cos_idx = 0;
1634 uint8_t is_bw_cos_exist = 0;
1635
1636 *total_bw = 0 ;
1637 /* Calculate total BW requested */
1638 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
1639 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
1640 is_bw_cos_exist = 1;
1641 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
1642 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW"
1643 "was set to 0\n");
1644 /* This is to prevent a state when ramrods
1645 * can't be sent
1646 */
1647 ets_params->cos[cos_idx].params.bw_params.bw
1648 = 1;
1649 }
1650 *total_bw +=
1651 ets_params->cos[cos_idx].params.bw_params.bw;
1652 }
1653 }
1654
1655 /* Check total BW is valid */
1656 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
1657 if (*total_bw == 0) {
1658 ELINK_DEBUG_P0(sc,
1659 "elink_ets_E3B0_config total BW shouldn't be 0\n");
1660 return ELINK_STATUS_ERROR;
1661 }
1662 ELINK_DEBUG_P0(sc,
1663 "elink_ets_E3B0_config total BW should be 100\n");
1664 /* We can handle a case whre the BW isn't 100 this can happen
1665 * if the TC are joined.
1666 */
1667 }
1668 return ELINK_STATUS_OK;
1669 }
1670
1671 /******************************************************************************
1672 * Description:
1673 * Invalidate all the sp_pri_to_cos.
1674 *
1675 ******************************************************************************/
elink_ets_e3b0_sp_pri_to_cos_init(uint8_t * sp_pri_to_cos)1676 static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)
1677 {
1678 uint8_t pri = 0;
1679 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
1680 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
1681 }
1682 /******************************************************************************
1683 * Description:
1684 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1685 * according to sp_pri_to_cos.
1686 *
1687 ******************************************************************************/
elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params * params,uint8_t * sp_pri_to_cos,const uint8_t pri,const uint8_t cos_entry)1688 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params,
1689 uint8_t *sp_pri_to_cos, const uint8_t pri,
1690 const uint8_t cos_entry)
1691 {
1692 struct bxe_softc *sc = params->sc;
1693 const uint8_t port = params->port;
1694 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1695 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1696
1697 if (pri >= max_num_of_cos) {
1698 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1699 "parameter Illegal strict priority\n");
1700 return ELINK_STATUS_ERROR;
1701 }
1702
1703 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
1704 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1705 "parameter There can't be two COS's with "
1706 "the same strict pri\n");
1707 return ELINK_STATUS_ERROR;
1708 }
1709
1710 sp_pri_to_cos[pri] = cos_entry;
1711 return ELINK_STATUS_OK;
1712
1713 }
1714
1715 /******************************************************************************
1716 * Description:
1717 * Returns the correct value according to COS and priority in
1718 * the sp_pri_cli register.
1719 *
1720 ******************************************************************************/
elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos,const uint8_t cos_offset,const uint8_t pri_set,const uint8_t pri_offset,const uint8_t entry_size)1721 static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos, const uint8_t cos_offset,
1722 const uint8_t pri_set,
1723 const uint8_t pri_offset,
1724 const uint8_t entry_size)
1725 {
1726 uint64_t pri_cli_nig = 0;
1727 pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *
1728 (pri_set + pri_offset));
1729
1730 return pri_cli_nig;
1731 }
1732 /******************************************************************************
1733 * Description:
1734 * Returns the correct value according to COS and priority in the
1735 * sp_pri_cli register for NIG.
1736 *
1737 ******************************************************************************/
elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos,const uint8_t pri_set)1738 static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos, const uint8_t pri_set)
1739 {
1740 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1741 const uint8_t nig_cos_offset = 3;
1742 const uint8_t nig_pri_offset = 3;
1743
1744 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1745 nig_pri_offset, 4);
1746
1747 }
1748 /******************************************************************************
1749 * Description:
1750 * Returns the correct value according to COS and priority in the
1751 * sp_pri_cli register for PBF.
1752 *
1753 ******************************************************************************/
elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos,const uint8_t pri_set)1754 static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos, const uint8_t pri_set)
1755 {
1756 const uint8_t pbf_cos_offset = 0;
1757 const uint8_t pbf_pri_offset = 0;
1758
1759 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1760 pbf_pri_offset, 3);
1761
1762 }
1763
1764 /******************************************************************************
1765 * Description:
1766 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1767 * according to sp_pri_to_cos.(which COS has higher priority)
1768 *
1769 ******************************************************************************/
elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params * params,uint8_t * sp_pri_to_cos)1770 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params,
1771 uint8_t *sp_pri_to_cos)
1772 {
1773 struct bxe_softc *sc = params->sc;
1774 uint8_t i = 0;
1775 const uint8_t port = params->port;
1776 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1777 uint64_t pri_cli_nig = 0x210;
1778 uint32_t pri_cli_pbf = 0x0;
1779 uint8_t pri_set = 0;
1780 uint8_t pri_bitmask = 0;
1781 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1782 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1783
1784 uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;
1785
1786 /* Set all the strict priority first */
1787 for (i = 0; i < max_num_of_cos; i++) {
1788 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1789 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
1790 ELINK_DEBUG_P0(sc,
1791 "elink_ets_e3b0_sp_set_pri_cli_reg "
1792 "invalid cos entry\n");
1793 return ELINK_STATUS_ERROR;
1794 }
1795
1796 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1797 sp_pri_to_cos[i], pri_set);
1798
1799 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1800 sp_pri_to_cos[i], pri_set);
1801 pri_bitmask = 1 << sp_pri_to_cos[i];
1802 /* COS is used remove it from bitmap.*/
1803 if (!(pri_bitmask & cos_bit_to_set)) {
1804 ELINK_DEBUG_P0(sc,
1805 "elink_ets_e3b0_sp_set_pri_cli_reg "
1806 "invalid There can't be two COS's with"
1807 " the same strict pri\n");
1808 return ELINK_STATUS_ERROR;
1809 }
1810 cos_bit_to_set &= ~pri_bitmask;
1811 pri_set++;
1812 }
1813 }
1814
1815 /* Set all the Non strict priority i= COS*/
1816 for (i = 0; i < max_num_of_cos; i++) {
1817 pri_bitmask = 1 << i;
1818 /* Check if COS was already used for SP */
1819 if (pri_bitmask & cos_bit_to_set) {
1820 /* COS wasn't used for SP */
1821 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1822 i, pri_set);
1823
1824 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1825 i, pri_set);
1826 /* COS is used remove it from bitmap.*/
1827 cos_bit_to_set &= ~pri_bitmask;
1828 pri_set++;
1829 }
1830 }
1831
1832 if (pri_set != max_num_of_cos) {
1833 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
1834 "entries were set\n");
1835 return ELINK_STATUS_ERROR;
1836 }
1837
1838 if (port) {
1839 /* Only 6 usable clients*/
1840 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1841 (uint32_t)pri_cli_nig);
1842
1843 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1844 } else {
1845 /* Only 9 usable clients*/
1846 const uint32_t pri_cli_nig_lsb = (uint32_t) (pri_cli_nig);
1847 const uint32_t pri_cli_nig_msb = (uint32_t) ((pri_cli_nig >> 32) & 0xF);
1848
1849 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1850 pri_cli_nig_lsb);
1851 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1852 pri_cli_nig_msb);
1853
1854 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1855 }
1856 return ELINK_STATUS_OK;
1857 }
1858
1859 /******************************************************************************
1860 * Description:
1861 * Configure the COS to ETS according to BW and SP settings.
1862 ******************************************************************************/
elink_ets_e3b0_config(const struct elink_params * params,const struct elink_vars * vars,struct elink_ets_params * ets_params)1863 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
1864 const struct elink_vars *vars,
1865 struct elink_ets_params *ets_params)
1866 {
1867 struct bxe_softc *sc = params->sc;
1868 elink_status_t elink_status = ELINK_STATUS_OK;
1869 const uint8_t port = params->port;
1870 uint16_t total_bw = 0;
1871 const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
1872 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1873 uint8_t cos_bw_bitmap = 0;
1874 uint8_t cos_sp_bitmap = 0;
1875 uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
1876 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1877 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1878 uint8_t cos_entry = 0;
1879
1880 if (!CHIP_IS_E3B0(sc)) {
1881 ELINK_DEBUG_P0(sc,
1882 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1883 return ELINK_STATUS_ERROR;
1884 }
1885
1886 if ((ets_params->num_of_cos > max_num_of_cos)) {
1887 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS "
1888 "isn't supported\n");
1889 return ELINK_STATUS_ERROR;
1890 }
1891
1892 /* Prepare sp strict priority parameters*/
1893 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1894
1895 /* Prepare BW parameters*/
1896 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
1897 &total_bw);
1898 if (elink_status != ELINK_STATUS_OK) {
1899 ELINK_DEBUG_P0(sc,
1900 "elink_ets_E3B0_config get_total_bw failed\n");
1901 return ELINK_STATUS_ERROR;
1902 }
1903
1904 /* Upper bound is set according to current link speed (min_w_val
1905 * should be the same for upper bound and COS credit val).
1906 */
1907 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1908 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1909
1910
1911 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1912 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
1913 cos_bw_bitmap |= (1 << cos_entry);
1914 /* The function also sets the BW in HW(not the mappin
1915 * yet)
1916 */
1917 elink_status = elink_ets_e3b0_set_cos_bw(
1918 sc, cos_entry, min_w_val_nig, min_w_val_pbf,
1919 total_bw,
1920 ets_params->cos[cos_entry].params.bw_params.bw,
1921 port);
1922 } else if (elink_cos_state_strict ==
1923 ets_params->cos[cos_entry].state){
1924 cos_sp_bitmap |= (1 << cos_entry);
1925
1926 elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
1927 params,
1928 sp_pri_to_cos,
1929 ets_params->cos[cos_entry].params.sp_params.pri,
1930 cos_entry);
1931
1932 } else {
1933 ELINK_DEBUG_P0(sc,
1934 "elink_ets_e3b0_config cos state not valid\n");
1935 return ELINK_STATUS_ERROR;
1936 }
1937 if (elink_status != ELINK_STATUS_OK) {
1938 ELINK_DEBUG_P0(sc,
1939 "elink_ets_e3b0_config set cos bw failed\n");
1940 return elink_status;
1941 }
1942 }
1943
1944 /* Set SP register (which COS has higher priority) */
1945 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
1946 sp_pri_to_cos);
1947
1948 if (elink_status != ELINK_STATUS_OK) {
1949 ELINK_DEBUG_P0(sc,
1950 "elink_ets_E3B0_config set_pri_cli_reg failed\n");
1951 return elink_status;
1952 }
1953
1954 /* Set client mapping of BW and strict */
1955 elink_status = elink_ets_e3b0_cli_map(params, ets_params,
1956 cos_sp_bitmap,
1957 cos_bw_bitmap);
1958
1959 if (elink_status != ELINK_STATUS_OK) {
1960 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed\n");
1961 return elink_status;
1962 }
1963 return ELINK_STATUS_OK;
1964 }
elink_ets_bw_limit_common(const struct elink_params * params)1965 static void elink_ets_bw_limit_common(const struct elink_params *params)
1966 {
1967 /* ETS disabled configuration */
1968 struct bxe_softc *sc = params->sc;
1969 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1970 /* Defines which entries (clients) are subjected to WFQ arbitration
1971 * COS0 0x8
1972 * COS1 0x10
1973 */
1974 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1975 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1976 * client numbers (WEIGHT_0 does not actually have to represent
1977 * client 0)
1978 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1979 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1980 */
1981 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1982
1983 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1984 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1985 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1986 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1987
1988 /* ETS mode enabled*/
1989 REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
1990
1991 /* Defines the number of consecutive slots for the strict priority */
1992 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1993 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1994 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1995 * entry, 4 - COS1 entry.
1996 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1997 * bit4 bit3 bit2 bit1 bit0
1998 * MCP and debug are strict
1999 */
2000 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
2001
2002 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
2003 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
2004 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
2005 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
2006 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
2007 }
2008
elink_ets_bw_limit(const struct elink_params * params,const uint32_t cos0_bw,const uint32_t cos1_bw)2009 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
2010 const uint32_t cos1_bw)
2011 {
2012 /* ETS disabled configuration*/
2013 struct bxe_softc *sc = params->sc;
2014 const uint32_t total_bw = cos0_bw + cos1_bw;
2015 uint32_t cos0_credit_weight = 0;
2016 uint32_t cos1_credit_weight = 0;
2017
2018 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
2019
2020 if ((!total_bw) ||
2021 (!cos0_bw) ||
2022 (!cos1_bw)) {
2023 ELINK_DEBUG_P0(sc, "Total BW can't be zero\n");
2024 return;
2025 }
2026
2027 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2028 total_bw;
2029 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2030 total_bw;
2031
2032 elink_ets_bw_limit_common(params);
2033
2034 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
2035 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
2036
2037 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
2038 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
2039 }
2040
elink_ets_strict(const struct elink_params * params,const uint8_t strict_cos)2041 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos)
2042 {
2043 /* ETS disabled configuration*/
2044 struct bxe_softc *sc = params->sc;
2045 uint32_t val = 0;
2046
2047 ELINK_DEBUG_P0(sc, "ETS enabled strict configuration\n");
2048 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
2049 * as strict. Bits 0,1,2 - debug and management entries,
2050 * 3 - COS0 entry, 4 - COS1 entry.
2051 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
2052 * bit4 bit3 bit2 bit1 bit0
2053 * MCP and debug are strict
2054 */
2055 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2056 /* For strict priority entries defines the number of consecutive slots
2057 * for the highest priority.
2058 */
2059 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2060 /* ETS mode disable */
2061 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
2062 /* Defines the number of consecutive slots for the strict priority */
2063 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
2064
2065 /* Defines the number of consecutive slots for the strict priority */
2066 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
2067
2068 /* Mapping between entry priority to client number (0,1,2 -debug and
2069 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
2070 * 3bits client num.
2071 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
2072 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
2073 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
2074 */
2075 val = (!strict_cos) ? 0x2318 : 0x22E0;
2076 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
2077
2078 return ELINK_STATUS_OK;
2079 }
2080
2081 /******************************************************************/
2082 /* PFC section */
2083 /******************************************************************/
elink_update_pfc_xmac(struct elink_params * params,struct elink_vars * vars,uint8_t is_lb)2084 static void elink_update_pfc_xmac(struct elink_params *params,
2085 struct elink_vars *vars,
2086 uint8_t is_lb)
2087 {
2088 struct bxe_softc *sc = params->sc;
2089 uint32_t xmac_base;
2090 uint32_t pause_val, pfc0_val, pfc1_val;
2091
2092 /* XMAC base adrr */
2093 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2094
2095 /* Initialize pause and pfc registers */
2096 pause_val = 0x18000;
2097 pfc0_val = 0xFFFF8000;
2098 pfc1_val = 0x2;
2099
2100 /* No PFC support */
2101 if (!(params->feature_config_flags &
2102 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2103
2104 /* RX flow control - Process pause frame in receive direction
2105 */
2106 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2107 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
2108
2109 /* TX flow control - Send pause packet when buffer is full */
2110 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2111 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
2112 } else {/* PFC support */
2113 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
2114 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
2115 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
2116 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
2117 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2118 /* Write pause and PFC registers */
2119 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2120 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2121 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2122 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2123
2124 }
2125
2126 /* Write pause and PFC registers */
2127 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2128 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2129 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2130
2131
2132 /* Set MAC address for source TX Pause/PFC frames */
2133 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
2134 ((params->mac_addr[2] << 24) |
2135 (params->mac_addr[3] << 16) |
2136 (params->mac_addr[4] << 8) |
2137 (params->mac_addr[5])));
2138 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
2139 ((params->mac_addr[0] << 8) |
2140 (params->mac_addr[1])));
2141
2142 DELAY(30);
2143 }
2144
elink_emac_get_pfc_stat(struct elink_params * params,uint32_t pfc_frames_sent[2],uint32_t pfc_frames_received[2])2145 static void elink_emac_get_pfc_stat(struct elink_params *params,
2146 uint32_t pfc_frames_sent[2],
2147 uint32_t pfc_frames_received[2])
2148 {
2149 /* Read pfc statistic */
2150 struct bxe_softc *sc = params->sc;
2151 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2152 uint32_t val_xon = 0;
2153 uint32_t val_xoff = 0;
2154
2155 ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC\n");
2156
2157 /* PFC received frames */
2158 val_xoff = REG_RD(sc, emac_base +
2159 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
2160 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
2161 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
2162 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
2163
2164 pfc_frames_received[0] = val_xon + val_xoff;
2165
2166 /* PFC received sent */
2167 val_xoff = REG_RD(sc, emac_base +
2168 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
2169 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
2170 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
2171 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
2172
2173 pfc_frames_sent[0] = val_xon + val_xoff;
2174 }
2175
2176 /* Read pfc statistic*/
elink_pfc_statistic(struct elink_params * params,struct elink_vars * vars,uint32_t pfc_frames_sent[2],uint32_t pfc_frames_received[2])2177 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
2178 uint32_t pfc_frames_sent[2],
2179 uint32_t pfc_frames_received[2])
2180 {
2181 /* Read pfc statistic */
2182 struct bxe_softc *sc = params->sc;
2183
2184 ELINK_DEBUG_P0(sc, "pfc statistic\n");
2185
2186 if (!vars->link_up)
2187 return;
2188
2189 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
2190 ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC\n");
2191 elink_emac_get_pfc_stat(params, pfc_frames_sent,
2192 pfc_frames_received);
2193 }
2194 }
2195 /******************************************************************/
2196 /* MAC/PBF section */
2197 /******************************************************************/
elink_set_mdio_clk(struct bxe_softc * sc,uint32_t chip_id,uint32_t emac_base)2198 static void elink_set_mdio_clk(struct bxe_softc *sc, uint32_t chip_id,
2199 uint32_t emac_base)
2200 {
2201 uint32_t new_mode, cur_mode;
2202 uint32_t clc_cnt;
2203 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
2204 * (a value of 49==0x31) and make sure that the AUTO poll is off
2205 */
2206 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
2207
2208 if (USES_WARPCORE(sc))
2209 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2210 else
2211 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2212
2213 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
2214 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
2215 return;
2216
2217 new_mode = cur_mode &
2218 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
2219 new_mode |= clc_cnt;
2220 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
2221
2222 ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x\n",
2223 cur_mode, new_mode);
2224 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
2225 DELAY(40);
2226 }
2227
elink_is_4_port_mode(struct bxe_softc * sc)2228 static uint8_t elink_is_4_port_mode(struct bxe_softc *sc)
2229 {
2230 uint32_t port4mode_ovwr_val;
2231 /* Check 4-port override enabled */
2232 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
2233 if (port4mode_ovwr_val & (1<<0)) {
2234 /* Return 4-port mode override value */
2235 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
2236 }
2237 /* Return 4-port mode from input pin */
2238 return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
2239 }
2240
elink_set_mdio_emac_per_phy(struct bxe_softc * sc,struct elink_params * params)2241 static void elink_set_mdio_emac_per_phy(struct bxe_softc *sc,
2242 struct elink_params *params)
2243 {
2244 uint8_t phy_index;
2245
2246 /* Set mdio clock per phy */
2247 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
2248 phy_index++)
2249 elink_set_mdio_clk(sc, params->chip_id,
2250 params->phy[phy_index].mdio_ctrl);
2251 }
2252
elink_emac_init(struct elink_params * params,struct elink_vars * vars)2253 static void elink_emac_init(struct elink_params *params,
2254 struct elink_vars *vars)
2255 {
2256 /* reset and unreset the emac core */
2257 struct bxe_softc *sc = params->sc;
2258 uint8_t port = params->port;
2259 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2260 uint32_t val;
2261 uint16_t timeout;
2262
2263 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2264 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2265 DELAY(5);
2266 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2267 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2268
2269 /* init emac - use read-modify-write */
2270 /* self clear reset */
2271 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2272 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2273
2274 timeout = 200;
2275 do {
2276 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2277 ELINK_DEBUG_P1(sc, "EMAC reset reg is %u\n", val);
2278 if (!timeout) {
2279 ELINK_DEBUG_P0(sc, "EMAC timeout!\n");
2280 return;
2281 }
2282 timeout--;
2283 } while (val & EMAC_MODE_RESET);
2284
2285 elink_set_mdio_emac_per_phy(sc, params);
2286 /* Set mac address */
2287 val = ((params->mac_addr[0] << 8) |
2288 params->mac_addr[1]);
2289 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
2290
2291 val = ((params->mac_addr[2] << 24) |
2292 (params->mac_addr[3] << 16) |
2293 (params->mac_addr[4] << 8) |
2294 params->mac_addr[5]);
2295 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
2296 }
2297
elink_set_xumac_nig(struct elink_params * params,uint16_t tx_pause_en,uint8_t enable)2298 static void elink_set_xumac_nig(struct elink_params *params,
2299 uint16_t tx_pause_en,
2300 uint8_t enable)
2301 {
2302 struct bxe_softc *sc = params->sc;
2303
2304 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
2305 enable);
2306 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
2307 enable);
2308 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
2309 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
2310 }
2311
elink_set_umac_rxtx(struct elink_params * params,uint8_t en)2312 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
2313 {
2314 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2315 uint32_t val;
2316 struct bxe_softc *sc = params->sc;
2317 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
2318 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
2319 return;
2320 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
2321 if (en)
2322 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
2323 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2324 else
2325 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
2326 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2327 /* Disable RX and TX */
2328 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2329 }
2330
elink_umac_enable(struct elink_params * params,struct elink_vars * vars,uint8_t lb)2331 static void elink_umac_enable(struct elink_params *params,
2332 struct elink_vars *vars, uint8_t lb)
2333 {
2334 uint32_t val;
2335 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2336 struct bxe_softc *sc = params->sc;
2337 /* Reset UMAC */
2338 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2339 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2340 DELAY(1000 * 1);
2341
2342 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2343 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2344
2345 ELINK_DEBUG_P0(sc, "enabling UMAC\n");
2346
2347 /* This register opens the gate for the UMAC despite its name */
2348 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
2349
2350 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
2351 UMAC_COMMAND_CONFIG_REG_PAD_EN |
2352 UMAC_COMMAND_CONFIG_REG_SW_RESET |
2353 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
2354 switch (vars->line_speed) {
2355 case ELINK_SPEED_10:
2356 val |= (0<<2);
2357 break;
2358 case ELINK_SPEED_100:
2359 val |= (1<<2);
2360 break;
2361 case ELINK_SPEED_1000:
2362 val |= (2<<2);
2363 break;
2364 case ELINK_SPEED_2500:
2365 val |= (3<<2);
2366 break;
2367 default:
2368 ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d\n",
2369 vars->line_speed);
2370 break;
2371 }
2372 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2373 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
2374
2375 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2376 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
2377
2378 if (vars->duplex == DUPLEX_HALF)
2379 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
2380
2381 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2382 DELAY(50);
2383
2384 /* Configure UMAC for EEE */
2385 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2386 ELINK_DEBUG_P0(sc, "configured UMAC for EEE\n");
2387 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
2388 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
2389 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
2390 } else {
2391 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
2392 }
2393
2394 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
2395 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
2396 ((params->mac_addr[2] << 24) |
2397 (params->mac_addr[3] << 16) |
2398 (params->mac_addr[4] << 8) |
2399 (params->mac_addr[5])));
2400 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
2401 ((params->mac_addr[0] << 8) |
2402 (params->mac_addr[1])));
2403
2404 /* Enable RX and TX */
2405 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
2406 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
2407 UMAC_COMMAND_CONFIG_REG_RX_ENA;
2408 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2409 DELAY(50);
2410
2411 /* Remove SW Reset */
2412 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
2413
2414 /* Check loopback mode */
2415 if (lb)
2416 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
2417 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2418
2419 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
2420 * length used by the MAC receive logic to check frames.
2421 */
2422 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
2423 elink_set_xumac_nig(params,
2424 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2425 vars->mac_type = ELINK_MAC_TYPE_UMAC;
2426
2427 }
2428
2429 /* Define the XMAC mode */
elink_xmac_init(struct elink_params * params,uint32_t max_speed)2430 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
2431 {
2432 struct bxe_softc *sc = params->sc;
2433 uint32_t is_port4mode = elink_is_4_port_mode(sc);
2434
2435 /* In 4-port mode, need to set the mode only once, so if XMAC is
2436 * already out of reset, it means the mode has already been set,
2437 * and it must not* reset the XMAC again, since it controls both
2438 * ports of the path
2439 */
2440
2441 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
2442 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
2443 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
2444 is_port4mode &&
2445 (REG_RD(sc, MISC_REG_RESET_REG_2) &
2446 MISC_REGISTERS_RESET_REG_2_XMAC)) {
2447 ELINK_DEBUG_P0(sc,
2448 "XMAC already out of reset in 4-port mode\n");
2449 return;
2450 }
2451
2452 /* Hard reset */
2453 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2454 MISC_REGISTERS_RESET_REG_2_XMAC);
2455 DELAY(1000 * 1);
2456
2457 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2458 MISC_REGISTERS_RESET_REG_2_XMAC);
2459 if (is_port4mode) {
2460 ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path\n");
2461
2462 /* Set the number of ports on the system side to up to 2 */
2463 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
2464
2465 /* Set the number of ports on the Warp Core to 10G */
2466 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2467 } else {
2468 /* Set the number of ports on the system side to 1 */
2469 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
2470 if (max_speed == ELINK_SPEED_10000) {
2471 ELINK_DEBUG_P0(sc,
2472 "Init XMAC to 10G x 1 port per path\n");
2473 /* Set the number of ports on the Warp Core to 10G */
2474 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2475 } else {
2476 ELINK_DEBUG_P0(sc,
2477 "Init XMAC to 20G x 2 ports per path\n");
2478 /* Set the number of ports on the Warp Core to 20G */
2479 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
2480 }
2481 }
2482 /* Soft reset */
2483 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2484 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2485 DELAY(1000 * 1);
2486
2487 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2488 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2489
2490 }
2491
elink_set_xmac_rxtx(struct elink_params * params,uint8_t en)2492 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
2493 {
2494 uint8_t port = params->port;
2495 struct bxe_softc *sc = params->sc;
2496 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2497 uint32_t val;
2498
2499 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2500 MISC_REGISTERS_RESET_REG_2_XMAC) {
2501 /* Send an indication to change the state in the NIG back to XON
2502 * Clearing this bit enables the next set of this bit to get
2503 * rising edge
2504 */
2505 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
2506 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2507 (pfc_ctrl & ~(1<<1)));
2508 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2509 (pfc_ctrl | (1<<1)));
2510 ELINK_DEBUG_P1(sc, "Disable XMAC on port %x\n", port);
2511 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
2512 if (en)
2513 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2514 else
2515 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2516 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2517 }
2518 }
2519
elink_xmac_enable(struct elink_params * params,struct elink_vars * vars,uint8_t lb)2520 static elink_status_t elink_xmac_enable(struct elink_params *params,
2521 struct elink_vars *vars, uint8_t lb)
2522 {
2523 uint32_t val, xmac_base;
2524 struct bxe_softc *sc = params->sc;
2525 ELINK_DEBUG_P0(sc, "enabling XMAC\n");
2526
2527 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2528
2529 elink_xmac_init(params, vars->line_speed);
2530
2531 /* This register determines on which events the MAC will assert
2532 * error on the i/f to the NIG along w/ EOP.
2533 */
2534
2535 /* This register tells the NIG whether to send traffic to UMAC
2536 * or XMAC
2537 */
2538 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
2539
2540 /* When XMAC is in XLGMII mode, disable sending idles for fault
2541 * detection.
2542 */
2543 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
2544 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
2545 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
2546 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
2547 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
2548 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
2549 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
2550 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
2551 }
2552 /* Set Max packet size */
2553 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
2554
2555 /* CRC append for Tx packets */
2556 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
2557
2558 /* update PFC */
2559 elink_update_pfc_xmac(params, vars, 0);
2560
2561 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2562 ELINK_DEBUG_P0(sc, "Setting XMAC for EEE\n");
2563 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
2564 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
2565 } else {
2566 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
2567 }
2568
2569 /* Enable TX and RX */
2570 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
2571
2572 /* Set MAC in XLGMII mode for dual-mode */
2573 if ((vars->line_speed == ELINK_SPEED_20000) &&
2574 (params->phy[ELINK_INT_PHY].supported &
2575 ELINK_SUPPORTED_20000baseKR2_Full))
2576 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
2577
2578 /* Check loopback mode */
2579 if (lb)
2580 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
2581 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2582 elink_set_xumac_nig(params,
2583 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2584
2585 vars->mac_type = ELINK_MAC_TYPE_XMAC;
2586
2587 return ELINK_STATUS_OK;
2588 }
2589
elink_emac_enable(struct elink_params * params,struct elink_vars * vars,uint8_t lb)2590 static elink_status_t elink_emac_enable(struct elink_params *params,
2591 struct elink_vars *vars, uint8_t lb)
2592 {
2593 struct bxe_softc *sc = params->sc;
2594 uint8_t port = params->port;
2595 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2596 uint32_t val;
2597
2598 ELINK_DEBUG_P0(sc, "enabling EMAC\n");
2599
2600 /* Disable BMAC */
2601 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2602 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2603
2604 /* enable emac and not bmac */
2605 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2606
2607 #ifdef ELINK_INCLUDE_EMUL
2608 /* for paladium */
2609 if (CHIP_REV_IS_EMUL(sc)) {
2610 /* Use lane 1 (of lanes 0-3) */
2611 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2612 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2613 }
2614 /* for fpga */
2615 else
2616 #endif
2617 #ifdef ELINK_INCLUDE_FPGA
2618 if (CHIP_REV_IS_FPGA(sc)) {
2619 /* Use lane 1 (of lanes 0-3) */
2620 ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA\n");
2621
2622 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2623 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2624 } else
2625 #endif
2626 /* ASIC */
2627 if (vars->phy_flags & PHY_XGXS_FLAG) {
2628 uint32_t ser_lane = ((params->lane_config &
2629 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2630 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2631
2632 ELINK_DEBUG_P0(sc, "XGXS\n");
2633 /* select the master lanes (out of 0-3) */
2634 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2635 /* select XGXS */
2636 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2637
2638 } else { /* SerDes */
2639 ELINK_DEBUG_P0(sc, "SerDes\n");
2640 /* select SerDes */
2641 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2642 }
2643
2644 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2645 EMAC_RX_MODE_RESET);
2646 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2647 EMAC_TX_MODE_RESET);
2648
2649 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2650 if (CHIP_REV_IS_SLOW(sc)) {
2651 /* config GMII mode */
2652 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2653 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2654 } else { /* ASIC */
2655 #endif
2656 /* pause enable/disable */
2657 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2658 EMAC_RX_MODE_FLOW_EN);
2659
2660 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2661 (EMAC_TX_MODE_EXT_PAUSE_EN |
2662 EMAC_TX_MODE_FLOW_EN));
2663 if (!(params->feature_config_flags &
2664 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2665 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2666 elink_bits_en(sc, emac_base +
2667 EMAC_REG_EMAC_RX_MODE,
2668 EMAC_RX_MODE_FLOW_EN);
2669
2670 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2671 elink_bits_en(sc, emac_base +
2672 EMAC_REG_EMAC_TX_MODE,
2673 (EMAC_TX_MODE_EXT_PAUSE_EN |
2674 EMAC_TX_MODE_FLOW_EN));
2675 } else
2676 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2677 EMAC_TX_MODE_FLOW_EN);
2678 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2679 }
2680 #endif
2681
2682 /* KEEP_VLAN_TAG, promiscuous */
2683 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
2684 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2685
2686 /* Setting this bit causes MAC control frames (except for pause
2687 * frames) to be passed on for processing. This setting has no
2688 * affect on the operation of the pause frames. This bit effects
2689 * all packets regardless of RX Parser packet sorting logic.
2690 * Turn the PFC off to make sure we are in Xon state before
2691 * enabling it.
2692 */
2693 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
2694 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2695 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2696 /* Enable PFC again */
2697 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
2698 EMAC_REG_RX_PFC_MODE_RX_EN |
2699 EMAC_REG_RX_PFC_MODE_TX_EN |
2700 EMAC_REG_RX_PFC_MODE_PRIORITIES);
2701
2702 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
2703 ((0x0101 <<
2704 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
2705 (0x00ff <<
2706 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
2707 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
2708 }
2709 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
2710
2711 /* Set Loopback */
2712 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2713 if (lb)
2714 val |= 0x810;
2715 else
2716 val &= ~0x810;
2717 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
2718
2719 /* Enable emac */
2720 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2721
2722 /* Enable emac for jumbo packets */
2723 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
2724 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2725 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
2726
2727 /* Strip CRC */
2728 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2729
2730 /* Disable the NIG in/out to the bmac */
2731 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2732 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2733 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2734
2735 /* Enable the NIG in/out to the emac */
2736 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2737 val = 0;
2738 if ((params->feature_config_flags &
2739 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2740 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2741 val = 1;
2742
2743 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2744 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2745
2746 #ifdef ELINK_INCLUDE_EMUL
2747 if (CHIP_REV_IS_EMUL(sc)) {
2748 /* Take the BigMac out of reset */
2749 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2750 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2751
2752 /* Enable access for bmac registers */
2753 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2754 } else
2755 #endif
2756 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2757
2758 vars->mac_type = ELINK_MAC_TYPE_EMAC;
2759 return ELINK_STATUS_OK;
2760 }
2761
elink_update_pfc_bmac1(struct elink_params * params,struct elink_vars * vars)2762 static void elink_update_pfc_bmac1(struct elink_params *params,
2763 struct elink_vars *vars)
2764 {
2765 uint32_t wb_data[2];
2766 struct bxe_softc *sc = params->sc;
2767 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2768 NIG_REG_INGRESS_BMAC0_MEM;
2769
2770 uint32_t val = 0x14;
2771 if ((!(params->feature_config_flags &
2772 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2773 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2774 /* Enable BigMAC to react on received Pause packets */
2775 val |= (1<<5);
2776 wb_data[0] = val;
2777 wb_data[1] = 0;
2778 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2779
2780 /* TX control */
2781 val = 0xc0;
2782 if (!(params->feature_config_flags &
2783 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2784 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2785 val |= 0x800000;
2786 wb_data[0] = val;
2787 wb_data[1] = 0;
2788 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2789 }
2790
elink_update_pfc_bmac2(struct elink_params * params,struct elink_vars * vars,uint8_t is_lb)2791 static void elink_update_pfc_bmac2(struct elink_params *params,
2792 struct elink_vars *vars,
2793 uint8_t is_lb)
2794 {
2795 /* Set rx control: Strip CRC and enable BigMAC to relay
2796 * control packets to the system as well
2797 */
2798 uint32_t wb_data[2];
2799 struct bxe_softc *sc = params->sc;
2800 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2801 NIG_REG_INGRESS_BMAC0_MEM;
2802 uint32_t val = 0x14;
2803
2804 if ((!(params->feature_config_flags &
2805 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2806 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2807 /* Enable BigMAC to react on received Pause packets */
2808 val |= (1<<5);
2809 wb_data[0] = val;
2810 wb_data[1] = 0;
2811 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2812 DELAY(30);
2813
2814 /* Tx control */
2815 val = 0xc0;
2816 if (!(params->feature_config_flags &
2817 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2818 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2819 val |= 0x800000;
2820 wb_data[0] = val;
2821 wb_data[1] = 0;
2822 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2823
2824 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2825 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2826 /* Enable PFC RX & TX & STATS and set 8 COS */
2827 wb_data[0] = 0x0;
2828 wb_data[0] |= (1<<0); /* RX */
2829 wb_data[0] |= (1<<1); /* TX */
2830 wb_data[0] |= (1<<2); /* Force initial Xon */
2831 wb_data[0] |= (1<<3); /* 8 cos */
2832 wb_data[0] |= (1<<5); /* STATS */
2833 wb_data[1] = 0;
2834 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2835 wb_data, 2);
2836 /* Clear the force Xon */
2837 wb_data[0] &= ~(1<<2);
2838 } else {
2839 ELINK_DEBUG_P0(sc, "PFC is disabled\n");
2840 /* Disable PFC RX & TX & STATS and set 8 COS */
2841 wb_data[0] = 0x8;
2842 wb_data[1] = 0;
2843 }
2844
2845 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2846
2847 /* Set Time (based unit is 512 bit time) between automatic
2848 * re-sending of PP packets amd enable automatic re-send of
2849 * Per-Priroity Packet as long as pp_gen is asserted and
2850 * pp_disable is low.
2851 */
2852 val = 0x8000;
2853 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2854 val |= (1<<16); /* enable automatic re-send */
2855
2856 wb_data[0] = val;
2857 wb_data[1] = 0;
2858 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2859 wb_data, 2);
2860
2861 /* mac control */
2862 val = 0x3; /* Enable RX and TX */
2863 if (is_lb) {
2864 val |= 0x4; /* Local loopback */
2865 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
2866 }
2867 /* When PFC enabled, Pass pause frames towards the NIG. */
2868 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2869 val |= ((1<<6)|(1<<5));
2870
2871 wb_data[0] = val;
2872 wb_data[1] = 0;
2873 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2874 }
2875
2876 /******************************************************************************
2877 * Description:
2878 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2879 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2880 ******************************************************************************/
elink_pfc_nig_rx_priority_mask(struct bxe_softc * sc,uint8_t cos_entry,uint32_t priority_mask,uint8_t port)2881 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bxe_softc *sc,
2882 uint8_t cos_entry,
2883 uint32_t priority_mask, uint8_t port)
2884 {
2885 uint32_t nig_reg_rx_priority_mask_add = 0;
2886
2887 switch (cos_entry) {
2888 case 0:
2889 nig_reg_rx_priority_mask_add = (port) ?
2890 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2891 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2892 break;
2893 case 1:
2894 nig_reg_rx_priority_mask_add = (port) ?
2895 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2896 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2897 break;
2898 case 2:
2899 nig_reg_rx_priority_mask_add = (port) ?
2900 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2901 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2902 break;
2903 case 3:
2904 if (port)
2905 return ELINK_STATUS_ERROR;
2906 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2907 break;
2908 case 4:
2909 if (port)
2910 return ELINK_STATUS_ERROR;
2911 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2912 break;
2913 case 5:
2914 if (port)
2915 return ELINK_STATUS_ERROR;
2916 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2917 break;
2918 }
2919
2920 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
2921
2922 return ELINK_STATUS_OK;
2923 }
elink_update_mng(struct elink_params * params,uint32_t link_status)2924 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
2925 {
2926 struct bxe_softc *sc = params->sc;
2927
2928 REG_WR(sc, params->shmem_base +
2929 offsetof(struct shmem_region,
2930 port_mb[params->port].link_status), link_status);
2931 }
2932
elink_update_pfc_nig(struct elink_params * params,struct elink_vars * vars,struct elink_nig_brb_pfc_port_params * nig_params)2933 static void elink_update_pfc_nig(struct elink_params *params,
2934 struct elink_vars *vars,
2935 struct elink_nig_brb_pfc_port_params *nig_params)
2936 {
2937 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2938 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2939 uint32_t pkt_priority_to_cos = 0;
2940 struct bxe_softc *sc = params->sc;
2941 uint8_t port = params->port;
2942
2943 int set_pfc = params->feature_config_flags &
2944 ELINK_FEATURE_CONFIG_PFC_ENABLED;
2945 ELINK_DEBUG_P0(sc, "updating pfc nig parameters\n");
2946
2947 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2948 * MAC control frames (that are not pause packets)
2949 * will be forwarded to the XCM.
2950 */
2951 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
2952 NIG_REG_LLH0_XCM_MASK);
2953 /* NIG params will override non PFC params, since it's possible to
2954 * do transition from PFC to SAFC
2955 */
2956 if (set_pfc) {
2957 pause_enable = 0;
2958 llfc_out_en = 0;
2959 llfc_enable = 0;
2960 if (CHIP_IS_E3(sc))
2961 ppp_enable = 0;
2962 else
2963 ppp_enable = 1;
2964 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2965 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2966 xcm_out_en = 0;
2967 hwpfc_enable = 1;
2968 } else {
2969 if (nig_params) {
2970 llfc_out_en = nig_params->llfc_out_en;
2971 llfc_enable = nig_params->llfc_enable;
2972 pause_enable = nig_params->pause_enable;
2973 } else /* Default non PFC mode - PAUSE */
2974 pause_enable = 1;
2975
2976 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2977 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2978 xcm_out_en = 1;
2979 }
2980
2981 if (CHIP_IS_E3(sc))
2982 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2983 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2984 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2985 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2986 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2987 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2988 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2989 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2990
2991 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2992 NIG_REG_PPP_ENABLE_0, ppp_enable);
2993
2994 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2995 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2996
2997 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2998 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2999
3000 /* Output enable for RX_XCM # IF */
3001 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
3002 NIG_REG_XCM0_OUT_EN, xcm_out_en);
3003
3004 /* HW PFC TX enable */
3005 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
3006 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
3007
3008 if (nig_params) {
3009 uint8_t i = 0;
3010 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
3011
3012 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
3013 elink_pfc_nig_rx_priority_mask(sc, i,
3014 nig_params->rx_cos_priority_mask[i], port);
3015
3016 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
3017 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
3018 nig_params->llfc_high_priority_classes);
3019
3020 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
3021 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
3022 nig_params->llfc_low_priority_classes);
3023 }
3024 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
3025 NIG_REG_P0_PKT_PRIORITY_TO_COS,
3026 pkt_priority_to_cos);
3027 }
3028
elink_update_pfc(struct elink_params * params,struct elink_vars * vars,struct elink_nig_brb_pfc_port_params * pfc_params)3029 elink_status_t elink_update_pfc(struct elink_params *params,
3030 struct elink_vars *vars,
3031 struct elink_nig_brb_pfc_port_params *pfc_params)
3032 {
3033 /* The PFC and pause are orthogonal to one another, meaning when
3034 * PFC is enabled, the pause are disabled, and when PFC is
3035 * disabled, pause are set according to the pause result.
3036 */
3037 uint32_t val;
3038 struct bxe_softc *sc = params->sc;
3039 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
3040
3041 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
3042 vars->link_status |= LINK_STATUS_PFC_ENABLED;
3043 else
3044 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
3045
3046 elink_update_mng(params, vars->link_status);
3047
3048 /* Update NIG params */
3049 elink_update_pfc_nig(params, vars, pfc_params);
3050
3051 if (!vars->link_up)
3052 return ELINK_STATUS_OK;
3053
3054 ELINK_DEBUG_P0(sc, "About to update PFC in BMAC\n");
3055
3056 if (CHIP_IS_E3(sc)) {
3057 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
3058 elink_update_pfc_xmac(params, vars, 0);
3059 } else {
3060 val = REG_RD(sc, MISC_REG_RESET_REG_2);
3061 if ((val &
3062 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
3063 == 0) {
3064 ELINK_DEBUG_P0(sc, "About to update PFC in EMAC\n");
3065 elink_emac_enable(params, vars, 0);
3066 return ELINK_STATUS_OK;
3067 }
3068 if (CHIP_IS_E2(sc))
3069 elink_update_pfc_bmac2(params, vars, bmac_loopback);
3070 else
3071 elink_update_pfc_bmac1(params, vars);
3072
3073 val = 0;
3074 if ((params->feature_config_flags &
3075 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3076 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3077 val = 1;
3078 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
3079 }
3080 return ELINK_STATUS_OK;
3081 }
3082
elink_bmac1_enable(struct elink_params * params,struct elink_vars * vars,uint8_t is_lb)3083 static elink_status_t elink_bmac1_enable(struct elink_params *params,
3084 struct elink_vars *vars,
3085 uint8_t is_lb)
3086 {
3087 struct bxe_softc *sc = params->sc;
3088 uint8_t port = params->port;
3089 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3090 NIG_REG_INGRESS_BMAC0_MEM;
3091 uint32_t wb_data[2];
3092 uint32_t val;
3093
3094 ELINK_DEBUG_P0(sc, "Enabling BigMAC1\n");
3095
3096 /* XGXS control */
3097 wb_data[0] = 0x3c;
3098 wb_data[1] = 0;
3099 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
3100 wb_data, 2);
3101
3102 /* TX MAC SA */
3103 wb_data[0] = ((params->mac_addr[2] << 24) |
3104 (params->mac_addr[3] << 16) |
3105 (params->mac_addr[4] << 8) |
3106 params->mac_addr[5]);
3107 wb_data[1] = ((params->mac_addr[0] << 8) |
3108 params->mac_addr[1]);
3109 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
3110
3111 /* MAC control */
3112 val = 0x3;
3113 if (is_lb) {
3114 val |= 0x4;
3115 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
3116 }
3117 wb_data[0] = val;
3118 wb_data[1] = 0;
3119 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
3120
3121 /* Set rx mtu */
3122 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3123 wb_data[1] = 0;
3124 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
3125
3126 elink_update_pfc_bmac1(params, vars);
3127
3128 /* Set tx mtu */
3129 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3130 wb_data[1] = 0;
3131 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
3132
3133 /* Set cnt max size */
3134 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3135 wb_data[1] = 0;
3136 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3137
3138 /* Configure SAFC */
3139 wb_data[0] = 0x1000200;
3140 wb_data[1] = 0;
3141 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
3142 wb_data, 2);
3143 #ifdef ELINK_INCLUDE_EMUL
3144 /* Fix for emulation */
3145 if (CHIP_REV_IS_EMUL(sc)) {
3146 wb_data[0] = 0xf000;
3147 wb_data[1] = 0;
3148 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
3149 wb_data, 2);
3150 }
3151 #endif
3152
3153 return ELINK_STATUS_OK;
3154 }
3155
elink_bmac2_enable(struct elink_params * params,struct elink_vars * vars,uint8_t is_lb)3156 static elink_status_t elink_bmac2_enable(struct elink_params *params,
3157 struct elink_vars *vars,
3158 uint8_t is_lb)
3159 {
3160 struct bxe_softc *sc = params->sc;
3161 uint8_t port = params->port;
3162 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3163 NIG_REG_INGRESS_BMAC0_MEM;
3164 uint32_t wb_data[2];
3165
3166 ELINK_DEBUG_P0(sc, "Enabling BigMAC2\n");
3167
3168 wb_data[0] = 0;
3169 wb_data[1] = 0;
3170 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3171 DELAY(30);
3172
3173 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
3174 wb_data[0] = 0x3c;
3175 wb_data[1] = 0;
3176 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
3177 wb_data, 2);
3178
3179 DELAY(30);
3180
3181 /* TX MAC SA */
3182 wb_data[0] = ((params->mac_addr[2] << 24) |
3183 (params->mac_addr[3] << 16) |
3184 (params->mac_addr[4] << 8) |
3185 params->mac_addr[5]);
3186 wb_data[1] = ((params->mac_addr[0] << 8) |
3187 params->mac_addr[1]);
3188 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
3189 wb_data, 2);
3190
3191 DELAY(30);
3192
3193 /* Configure SAFC */
3194 wb_data[0] = 0x1000200;
3195 wb_data[1] = 0;
3196 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
3197 wb_data, 2);
3198 DELAY(30);
3199
3200 /* Set RX MTU */
3201 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3202 wb_data[1] = 0;
3203 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
3204 DELAY(30);
3205
3206 /* Set TX MTU */
3207 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3208 wb_data[1] = 0;
3209 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
3210 DELAY(30);
3211 /* Set cnt max size */
3212 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
3213 wb_data[1] = 0;
3214 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3215 DELAY(30);
3216 elink_update_pfc_bmac2(params, vars, is_lb);
3217
3218 return ELINK_STATUS_OK;
3219 }
3220
elink_bmac_enable(struct elink_params * params,struct elink_vars * vars,uint8_t is_lb,uint8_t reset_bmac)3221 static elink_status_t elink_bmac_enable(struct elink_params *params,
3222 struct elink_vars *vars,
3223 uint8_t is_lb, uint8_t reset_bmac)
3224 {
3225 elink_status_t rc = ELINK_STATUS_OK;
3226 uint8_t port = params->port;
3227 struct bxe_softc *sc = params->sc;
3228 uint32_t val;
3229 /* Reset and unreset the BigMac */
3230 if (reset_bmac) {
3231 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3232 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3233 DELAY(1000 * 1);
3234 }
3235
3236 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3237 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3238
3239 /* Enable access for bmac registers */
3240 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
3241
3242 /* Enable BMAC according to BMAC type*/
3243 if (CHIP_IS_E2(sc))
3244 rc = elink_bmac2_enable(params, vars, is_lb);
3245 else
3246 rc = elink_bmac1_enable(params, vars, is_lb);
3247 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
3248 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
3249 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
3250 val = 0;
3251 if ((params->feature_config_flags &
3252 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3253 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3254 val = 1;
3255 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
3256 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
3257 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
3258 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
3259 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
3260 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
3261
3262 vars->mac_type = ELINK_MAC_TYPE_BMAC;
3263 return rc;
3264 }
3265
elink_set_bmac_rx(struct bxe_softc * sc,uint32_t chip_id,uint8_t port,uint8_t en)3266 static void elink_set_bmac_rx(struct bxe_softc *sc, uint32_t chip_id, uint8_t port, uint8_t en)
3267 {
3268 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3269 NIG_REG_INGRESS_BMAC0_MEM;
3270 uint32_t wb_data[2];
3271 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
3272
3273 if (CHIP_IS_E2(sc))
3274 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
3275 else
3276 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
3277 /* Only if the bmac is out of reset */
3278 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
3279 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
3280 nig_bmac_enable) {
3281 /* Clear Rx Enable bit in BMAC_CONTROL register */
3282 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
3283 if (en)
3284 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
3285 else
3286 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
3287 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
3288 DELAY(1000 * 1);
3289 }
3290 }
3291
elink_pbf_update(struct elink_params * params,uint32_t flow_ctrl,uint32_t line_speed)3292 static elink_status_t elink_pbf_update(struct elink_params *params, uint32_t flow_ctrl,
3293 uint32_t line_speed)
3294 {
3295 struct bxe_softc *sc = params->sc;
3296 uint8_t port = params->port;
3297 uint32_t init_crd, crd;
3298 uint32_t count = 1000;
3299
3300 /* Disable port */
3301 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
3302
3303 /* Wait for init credit */
3304 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);
3305 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3306 ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
3307
3308 while ((init_crd != crd) && count) {
3309 DELAY(1000 * 5);
3310 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3311 count--;
3312 }
3313 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3314 if (init_crd != crd) {
3315 ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x\n",
3316 init_crd, crd);
3317 return ELINK_STATUS_ERROR;
3318 }
3319
3320 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
3321 line_speed == ELINK_SPEED_10 ||
3322 line_speed == ELINK_SPEED_100 ||
3323 line_speed == ELINK_SPEED_1000 ||
3324 line_speed == ELINK_SPEED_2500) {
3325 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
3326 /* Update threshold */
3327 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);
3328 /* Update init credit */
3329 init_crd = 778; /* (800-18-4) */
3330
3331 } else {
3332 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
3333 ELINK_ETH_OVREHEAD)/16;
3334 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
3335 /* Update threshold */
3336 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh);
3337 /* Update init credit */
3338 switch (line_speed) {
3339 case ELINK_SPEED_10000:
3340 init_crd = thresh + 553 - 22;
3341 break;
3342 default:
3343 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
3344 line_speed);
3345 return ELINK_STATUS_ERROR;
3346 }
3347 }
3348 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd);
3349 ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d\n",
3350 line_speed, init_crd);
3351
3352 /* Probe the credit changes */
3353 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);
3354 DELAY(1000 * 5);
3355 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);
3356
3357 /* Enable port */
3358 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
3359 return ELINK_STATUS_OK;
3360 }
3361
3362 /**
3363 * elink_get_emac_base - retrive emac base address
3364 *
3365 * @bp: driver handle
3366 * @mdc_mdio_access: access type
3367 * @port: port id
3368 *
3369 * This function selects the MDC/MDIO access (through emac0 or
3370 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
3371 * phy has a default access mode, which could also be overridden
3372 * by nvram configuration. This parameter, whether this is the
3373 * default phy configuration, or the nvram overrun
3374 * configuration, is passed here as mdc_mdio_access and selects
3375 * the emac_base for the CL45 read/writes operations
3376 */
elink_get_emac_base(struct bxe_softc * sc,uint32_t mdc_mdio_access,uint8_t port)3377 static uint32_t elink_get_emac_base(struct bxe_softc *sc,
3378 uint32_t mdc_mdio_access, uint8_t port)
3379 {
3380 uint32_t emac_base = 0;
3381 switch (mdc_mdio_access) {
3382 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
3383 break;
3384 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
3385 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3386 emac_base = GRCBASE_EMAC1;
3387 else
3388 emac_base = GRCBASE_EMAC0;
3389 break;
3390 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
3391 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3392 emac_base = GRCBASE_EMAC0;
3393 else
3394 emac_base = GRCBASE_EMAC1;
3395 break;
3396 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
3397 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3398 break;
3399 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
3400 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3401 break;
3402 default:
3403 break;
3404 }
3405 return emac_base;
3406
3407 }
3408
3409 /******************************************************************/
3410 /* CL22 access functions */
3411 /******************************************************************/
elink_cl22_write(struct bxe_softc * sc,struct elink_phy * phy,uint16_t reg,uint16_t val)3412 static elink_status_t elink_cl22_write(struct bxe_softc *sc,
3413 struct elink_phy *phy,
3414 uint16_t reg, uint16_t val)
3415 {
3416 uint32_t tmp, mode;
3417 uint8_t i;
3418 elink_status_t rc = ELINK_STATUS_OK;
3419 /* Switch to CL22 */
3420 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3421 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3422 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3423
3424 /* Address */
3425 tmp = ((phy->addr << 21) | (reg << 16) | val |
3426 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3427 EMAC_MDIO_COMM_START_BUSY);
3428 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3429
3430 for (i = 0; i < 50; i++) {
3431 DELAY(10);
3432
3433 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3434 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3435 DELAY(5);
3436 break;
3437 }
3438 }
3439 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3440 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3441 rc = ELINK_STATUS_TIMEOUT;
3442 }
3443 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3444 return rc;
3445 }
3446
elink_cl22_read(struct bxe_softc * sc,struct elink_phy * phy,uint16_t reg,uint16_t * ret_val)3447 static elink_status_t elink_cl22_read(struct bxe_softc *sc,
3448 struct elink_phy *phy,
3449 uint16_t reg, uint16_t *ret_val)
3450 {
3451 uint32_t val, mode;
3452 uint16_t i;
3453 elink_status_t rc = ELINK_STATUS_OK;
3454
3455 /* Switch to CL22 */
3456 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3457 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3458 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3459
3460 /* Address */
3461 val = ((phy->addr << 21) | (reg << 16) |
3462 EMAC_MDIO_COMM_COMMAND_READ_22 |
3463 EMAC_MDIO_COMM_START_BUSY);
3464 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3465
3466 for (i = 0; i < 50; i++) {
3467 DELAY(10);
3468
3469 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3470 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3471 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3472 DELAY(5);
3473 break;
3474 }
3475 }
3476 if (val & EMAC_MDIO_COMM_START_BUSY) {
3477 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3478
3479 *ret_val = 0;
3480 rc = ELINK_STATUS_TIMEOUT;
3481 }
3482 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3483 return rc;
3484 }
3485
3486 /******************************************************************/
3487 /* CL45 access functions */
3488 /******************************************************************/
elink_cl45_read(struct bxe_softc * sc,struct elink_phy * phy,uint8_t devad,uint16_t reg,uint16_t * ret_val)3489 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,
3490 uint8_t devad, uint16_t reg, uint16_t *ret_val)
3491 {
3492 uint32_t val;
3493 uint16_t i;
3494 elink_status_t rc = ELINK_STATUS_OK;
3495 uint32_t chip_id;
3496 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3497 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3498 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3499 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3500 }
3501
3502 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3503 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3504 EMAC_MDIO_STATUS_10MB);
3505 /* Address */
3506 val = ((phy->addr << 21) | (devad << 16) | reg |
3507 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3508 EMAC_MDIO_COMM_START_BUSY);
3509 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3510
3511 for (i = 0; i < 50; i++) {
3512 DELAY(10);
3513
3514 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3515 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3516 DELAY(5);
3517 break;
3518 }
3519 }
3520 if (val & EMAC_MDIO_COMM_START_BUSY) {
3521 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3522 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3523
3524 *ret_val = 0;
3525 rc = ELINK_STATUS_TIMEOUT;
3526 } else {
3527 /* Data */
3528 val = ((phy->addr << 21) | (devad << 16) |
3529 EMAC_MDIO_COMM_COMMAND_READ_45 |
3530 EMAC_MDIO_COMM_START_BUSY);
3531 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3532
3533 for (i = 0; i < 50; i++) {
3534 DELAY(10);
3535
3536 val = REG_RD(sc, phy->mdio_ctrl +
3537 EMAC_REG_EMAC_MDIO_COMM);
3538 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3539 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3540 break;
3541 }
3542 }
3543 if (val & EMAC_MDIO_COMM_START_BUSY) {
3544 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3545 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3546
3547 *ret_val = 0;
3548 rc = ELINK_STATUS_TIMEOUT;
3549 }
3550 }
3551 /* Work around for E3 A0 */
3552 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3553 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3554 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3555 uint16_t temp_val;
3556 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3557 }
3558 }
3559
3560 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3561 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3562 EMAC_MDIO_STATUS_10MB);
3563 return rc;
3564 }
3565
elink_cl45_write(struct bxe_softc * sc,struct elink_phy * phy,uint8_t devad,uint16_t reg,uint16_t val)3566 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,
3567 uint8_t devad, uint16_t reg, uint16_t val)
3568 {
3569 uint32_t tmp;
3570 uint8_t i;
3571 elink_status_t rc = ELINK_STATUS_OK;
3572 uint32_t chip_id;
3573 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3574 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3575 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3576 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3577 }
3578
3579 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3580 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3581 EMAC_MDIO_STATUS_10MB);
3582
3583 /* Address */
3584 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3585 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3586 EMAC_MDIO_COMM_START_BUSY);
3587 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3588
3589 for (i = 0; i < 50; i++) {
3590 DELAY(10);
3591
3592 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3593 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3594 DELAY(5);
3595 break;
3596 }
3597 }
3598 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3599 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3600 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3601
3602 rc = ELINK_STATUS_TIMEOUT;
3603 } else {
3604 /* Data */
3605 tmp = ((phy->addr << 21) | (devad << 16) | val |
3606 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3607 EMAC_MDIO_COMM_START_BUSY);
3608 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3609
3610 for (i = 0; i < 50; i++) {
3611 DELAY(10);
3612
3613 tmp = REG_RD(sc, phy->mdio_ctrl +
3614 EMAC_REG_EMAC_MDIO_COMM);
3615 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3616 DELAY(5);
3617 break;
3618 }
3619 }
3620 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3621 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3622 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3623
3624 rc = ELINK_STATUS_TIMEOUT;
3625 }
3626 }
3627 /* Work around for E3 A0 */
3628 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3629 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3630 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3631 uint16_t temp_val;
3632 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3633 }
3634 }
3635 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3636 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3637 EMAC_MDIO_STATUS_10MB);
3638 return rc;
3639 }
3640
3641 /******************************************************************/
3642 /* EEE section */
3643 /******************************************************************/
elink_eee_has_cap(struct elink_params * params)3644 static uint8_t elink_eee_has_cap(struct elink_params *params)
3645 {
3646 struct bxe_softc *sc = params->sc;
3647
3648 if (REG_RD(sc, params->shmem2_base) <=
3649 offsetof(struct shmem2_region, eee_status[params->port]))
3650 return 0;
3651
3652 return 1;
3653 }
3654
elink_eee_nvram_to_time(uint32_t nvram_mode,uint32_t * idle_timer)3655 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, uint32_t *idle_timer)
3656 {
3657 switch (nvram_mode) {
3658 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
3659 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
3660 break;
3661 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
3662 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
3663 break;
3664 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
3665 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
3666 break;
3667 default:
3668 *idle_timer = 0;
3669 break;
3670 }
3671
3672 return ELINK_STATUS_OK;
3673 }
3674
elink_eee_time_to_nvram(uint32_t idle_timer,uint32_t * nvram_mode)3675 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, uint32_t *nvram_mode)
3676 {
3677 switch (idle_timer) {
3678 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
3679 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
3680 break;
3681 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
3682 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
3683 break;
3684 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
3685 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
3686 break;
3687 default:
3688 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
3689 break;
3690 }
3691
3692 return ELINK_STATUS_OK;
3693 }
3694
elink_eee_calc_timer(struct elink_params * params)3695 static uint32_t elink_eee_calc_timer(struct elink_params *params)
3696 {
3697 uint32_t eee_mode, eee_idle;
3698 struct bxe_softc *sc = params->sc;
3699
3700 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
3701 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3702 /* time value in eee_mode --> used directly*/
3703 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
3704 } else {
3705 /* hsi value in eee_mode --> time */
3706 if (elink_eee_nvram_to_time(params->eee_mode &
3707 ELINK_EEE_MODE_NVRAM_MASK,
3708 &eee_idle))
3709 return 0;
3710 }
3711 } else {
3712 /* hsi values in nvram --> time*/
3713 eee_mode = ((REG_RD(sc, params->shmem_base +
3714 offsetof(struct shmem_region, dev_info.
3715 port_feature_config[params->port].
3716 eee_power_mode)) &
3717 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
3718 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
3719
3720 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
3721 return 0;
3722 }
3723
3724 return eee_idle;
3725 }
3726
elink_eee_set_timers(struct elink_params * params,struct elink_vars * vars)3727 static elink_status_t elink_eee_set_timers(struct elink_params *params,
3728 struct elink_vars *vars)
3729 {
3730 uint32_t eee_idle = 0, eee_mode;
3731 struct bxe_softc *sc = params->sc;
3732
3733 eee_idle = elink_eee_calc_timer(params);
3734
3735 if (eee_idle) {
3736 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3737 eee_idle);
3738 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
3739 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
3740 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
3741 ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0\n");
3742 return ELINK_STATUS_ERROR;
3743 }
3744
3745 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
3746 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3747 /* eee_idle in 1u --> eee_status in 16u */
3748 eee_idle >>= 4;
3749 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
3750 SHMEM_EEE_TIME_OUTPUT_BIT;
3751 } else {
3752 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
3753 return ELINK_STATUS_ERROR;
3754 vars->eee_status |= eee_mode;
3755 }
3756
3757 return ELINK_STATUS_OK;
3758 }
3759
elink_eee_initial_config(struct elink_params * params,struct elink_vars * vars,uint8_t mode)3760 static elink_status_t elink_eee_initial_config(struct elink_params *params,
3761 struct elink_vars *vars, uint8_t mode)
3762 {
3763 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
3764
3765 /* Propagate params' bits --> vars (for migration exposure) */
3766 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
3767 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
3768 else
3769 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
3770
3771 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
3772 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
3773 else
3774 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
3775
3776 return elink_eee_set_timers(params, vars);
3777 }
3778
elink_eee_disable(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)3779 static elink_status_t elink_eee_disable(struct elink_phy *phy,
3780 struct elink_params *params,
3781 struct elink_vars *vars)
3782 {
3783 struct bxe_softc *sc = params->sc;
3784
3785 /* Make Certain LPI is disabled */
3786 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3787
3788 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3789
3790 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3791
3792 return ELINK_STATUS_OK;
3793 }
3794
elink_eee_advertise(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars,uint8_t modes)3795 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
3796 struct elink_params *params,
3797 struct elink_vars *vars, uint8_t modes)
3798 {
3799 struct bxe_softc *sc = params->sc;
3800 uint16_t val = 0;
3801
3802 /* Mask events preventing LPI generation */
3803 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3804
3805 if (modes & SHMEM_EEE_10G_ADV) {
3806 ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE\n");
3807 val |= 0x8;
3808 }
3809 if (modes & SHMEM_EEE_1G_ADV) {
3810 ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE\n");
3811 val |= 0x4;
3812 }
3813
3814 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3815
3816 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3817 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3818
3819 return ELINK_STATUS_OK;
3820 }
3821
elink_update_mng_eee(struct elink_params * params,uint32_t eee_status)3822 static void elink_update_mng_eee(struct elink_params *params, uint32_t eee_status)
3823 {
3824 struct bxe_softc *sc = params->sc;
3825
3826 if (elink_eee_has_cap(params))
3827 REG_WR(sc, params->shmem2_base +
3828 offsetof(struct shmem2_region,
3829 eee_status[params->port]), eee_status);
3830 }
3831
elink_eee_an_resolve(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)3832 static void elink_eee_an_resolve(struct elink_phy *phy,
3833 struct elink_params *params,
3834 struct elink_vars *vars)
3835 {
3836 struct bxe_softc *sc = params->sc;
3837 uint16_t adv = 0, lp = 0;
3838 uint32_t lp_adv = 0;
3839 uint8_t neg = 0;
3840
3841 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3842 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3843
3844 if (lp & 0x2) {
3845 lp_adv |= SHMEM_EEE_100M_ADV;
3846 if (adv & 0x2) {
3847 if (vars->line_speed == ELINK_SPEED_100)
3848 neg = 1;
3849 ELINK_DEBUG_P0(sc, "EEE negotiated - 100M\n");
3850 }
3851 }
3852 if (lp & 0x14) {
3853 lp_adv |= SHMEM_EEE_1G_ADV;
3854 if (adv & 0x14) {
3855 if (vars->line_speed == ELINK_SPEED_1000)
3856 neg = 1;
3857 ELINK_DEBUG_P0(sc, "EEE negotiated - 1G\n");
3858 }
3859 }
3860 if (lp & 0x68) {
3861 lp_adv |= SHMEM_EEE_10G_ADV;
3862 if (adv & 0x68) {
3863 if (vars->line_speed == ELINK_SPEED_10000)
3864 neg = 1;
3865 ELINK_DEBUG_P0(sc, "EEE negotiated - 10G\n");
3866 }
3867 }
3868
3869 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3870 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3871
3872 if (neg) {
3873 ELINK_DEBUG_P0(sc, "EEE is active\n");
3874 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3875 }
3876 }
3877
3878 /******************************************************************/
3879 /* BSC access functions from E3 */
3880 /******************************************************************/
elink_bsc_module_sel(struct elink_params * params)3881 static void elink_bsc_module_sel(struct elink_params *params)
3882 {
3883 int idx;
3884 uint32_t board_cfg, sfp_ctrl;
3885 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3886 struct bxe_softc *sc = params->sc;
3887 uint8_t port = params->port;
3888 /* Read I2C output PINs */
3889 board_cfg = REG_RD(sc, params->shmem_base +
3890 offsetof(struct shmem_region,
3891 dev_info.shared_hw_config.board));
3892 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3893 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3894 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3895
3896 /* Read I2C output value */
3897 sfp_ctrl = REG_RD(sc, params->shmem_base +
3898 offsetof(struct shmem_region,
3899 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3900 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3901 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3902 ELINK_DEBUG_P0(sc, "Setting BSC switch\n");
3903 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3904 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
3905 }
3906
elink_bsc_read(struct bxe_softc * sc,uint8_t sl_devid,uint16_t sl_addr,uint8_t lc_addr,uint8_t xfer_cnt,uint32_t * data_array)3907 static elink_status_t elink_bsc_read(struct bxe_softc *sc,
3908 uint8_t sl_devid,
3909 uint16_t sl_addr,
3910 uint8_t lc_addr,
3911 uint8_t xfer_cnt,
3912 uint32_t *data_array)
3913 {
3914 uint32_t val, i;
3915 elink_status_t rc = ELINK_STATUS_OK;
3916
3917 if (xfer_cnt > 16) {
3918 ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes\n",
3919 xfer_cnt);
3920 return ELINK_STATUS_ERROR;
3921 }
3922
3923 xfer_cnt = 16 - lc_addr;
3924
3925 /* Enable the engine */
3926 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3927 val |= MCPR_IMC_COMMAND_ENABLE;
3928 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3929
3930 /* Program slave device ID */
3931 val = (sl_devid << 16) | sl_addr;
3932 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3933
3934 /* Start xfer with 0 byte to update the address pointer ???*/
3935 val = (MCPR_IMC_COMMAND_ENABLE) |
3936 (MCPR_IMC_COMMAND_WRITE_OP <<
3937 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3938 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3939 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3940
3941 /* Poll for completion */
3942 i = 0;
3943 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3944 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3945 DELAY(10);
3946 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3947 if (i++ > 1000) {
3948 ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try\n",
3949 i);
3950 rc = ELINK_STATUS_TIMEOUT;
3951 break;
3952 }
3953 }
3954 if (rc == ELINK_STATUS_TIMEOUT)
3955 return rc;
3956
3957 /* Start xfer with read op */
3958 val = (MCPR_IMC_COMMAND_ENABLE) |
3959 (MCPR_IMC_COMMAND_READ_OP <<
3960 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3961 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3962 (xfer_cnt);
3963 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3964
3965 /* Poll for completion */
3966 i = 0;
3967 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3968 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3969 DELAY(10);
3970 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3971 if (i++ > 1000) {
3972 ELINK_DEBUG_P1(sc, "rd op timed out after %d try\n", i);
3973 rc = ELINK_STATUS_TIMEOUT;
3974 break;
3975 }
3976 }
3977 if (rc == ELINK_STATUS_TIMEOUT)
3978 return rc;
3979
3980 for (i = (lc_addr >> 2); i < 4; i++) {
3981 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3982 #ifdef __BIG_ENDIAN
3983 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3984 ((data_array[i] & 0x0000ff00) << 8) |
3985 ((data_array[i] & 0x00ff0000) >> 8) |
3986 ((data_array[i] & 0xff000000) >> 24);
3987 #endif
3988 }
3989 return rc;
3990 }
3991
elink_cl45_read_or_write(struct bxe_softc * sc,struct elink_phy * phy,uint8_t devad,uint16_t reg,uint16_t or_val)3992 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,
3993 uint8_t devad, uint16_t reg, uint16_t or_val)
3994 {
3995 uint16_t val;
3996 elink_cl45_read(sc, phy, devad, reg, &val);
3997 elink_cl45_write(sc, phy, devad, reg, val | or_val);
3998 }
3999
elink_cl45_read_and_write(struct bxe_softc * sc,struct elink_phy * phy,uint8_t devad,uint16_t reg,uint16_t and_val)4000 static void elink_cl45_read_and_write(struct bxe_softc *sc,
4001 struct elink_phy *phy,
4002 uint8_t devad, uint16_t reg, uint16_t and_val)
4003 {
4004 uint16_t val;
4005 elink_cl45_read(sc, phy, devad, reg, &val);
4006 elink_cl45_write(sc, phy, devad, reg, val & and_val);
4007 }
4008
elink_phy_read(struct elink_params * params,uint8_t phy_addr,uint8_t devad,uint16_t reg,uint16_t * ret_val)4009 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
4010 uint8_t devad, uint16_t reg, uint16_t *ret_val)
4011 {
4012 uint8_t phy_index;
4013 /* Probe for the phy according to the given phy_addr, and execute
4014 * the read request on it
4015 */
4016 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4017 if (params->phy[phy_index].addr == phy_addr) {
4018 return elink_cl45_read(params->sc,
4019 ¶ms->phy[phy_index], devad,
4020 reg, ret_val);
4021 }
4022 }
4023 return ELINK_STATUS_ERROR;
4024 }
4025
elink_phy_write(struct elink_params * params,uint8_t phy_addr,uint8_t devad,uint16_t reg,uint16_t val)4026 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
4027 uint8_t devad, uint16_t reg, uint16_t val)
4028 {
4029 uint8_t phy_index;
4030 /* Probe for the phy according to the given phy_addr, and execute
4031 * the write request on it
4032 */
4033 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4034 if (params->phy[phy_index].addr == phy_addr) {
4035 return elink_cl45_write(params->sc,
4036 ¶ms->phy[phy_index], devad,
4037 reg, val);
4038 }
4039 }
4040 return ELINK_STATUS_ERROR;
4041 }
4042
elink_get_warpcore_lane(struct elink_phy * phy,struct elink_params * params)4043 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,
4044 struct elink_params *params)
4045 {
4046 uint8_t lane = 0;
4047 struct bxe_softc *sc = params->sc;
4048 uint32_t path_swap, path_swap_ovr;
4049 uint8_t path, port;
4050
4051 path = SC_PATH(sc);
4052 port = params->port;
4053
4054 if (elink_is_4_port_mode(sc)) {
4055 uint32_t port_swap, port_swap_ovr;
4056
4057 /* Figure out path swap value */
4058 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
4059 if (path_swap_ovr & 0x1)
4060 path_swap = (path_swap_ovr & 0x2);
4061 else
4062 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
4063
4064 if (path_swap)
4065 path = path ^ 1;
4066
4067 /* Figure out port swap value */
4068 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
4069 if (port_swap_ovr & 0x1)
4070 port_swap = (port_swap_ovr & 0x2);
4071 else
4072 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
4073
4074 if (port_swap)
4075 port = port ^ 1;
4076
4077 lane = (port<<1) + path;
4078 } else { /* Two port mode - no port swap */
4079
4080 /* Figure out path swap value */
4081 path_swap_ovr =
4082 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
4083 if (path_swap_ovr & 0x1) {
4084 path_swap = (path_swap_ovr & 0x2);
4085 } else {
4086 path_swap =
4087 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
4088 }
4089 if (path_swap)
4090 path = path ^ 1;
4091
4092 lane = path << 1 ;
4093 }
4094 return lane;
4095 }
4096
4097
elink_set_aer_mmd(struct elink_params * params,struct elink_phy * phy)4098 static void elink_set_aer_mmd(struct elink_params *params,
4099 struct elink_phy *phy)
4100 {
4101 uint32_t ser_lane;
4102 uint16_t offset, aer_val;
4103 struct bxe_softc *sc = params->sc;
4104 ser_lane = ((params->lane_config &
4105 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4106 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4107
4108 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
4109 (phy->addr + ser_lane) : 0;
4110
4111 if (USES_WARPCORE(sc)) {
4112 aer_val = elink_get_warpcore_lane(phy, params);
4113 /* In Dual-lane mode, two lanes are joined together,
4114 * so in order to configure them, the AER broadcast method is
4115 * used here.
4116 * 0x200 is the broadcast address for lanes 0,1
4117 * 0x201 is the broadcast address for lanes 2,3
4118 */
4119 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4120 aer_val = (aer_val >> 1) | 0x200;
4121 } else if (CHIP_IS_E2(sc))
4122 aer_val = 0x3800 + offset - 1;
4123 else
4124 aer_val = 0x3800 + offset;
4125
4126 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4127 MDIO_AER_BLOCK_AER_REG, aer_val);
4128
4129 }
4130
4131 /******************************************************************/
4132 /* Internal phy section */
4133 /******************************************************************/
4134
elink_set_serdes_access(struct bxe_softc * sc,uint8_t port)4135 static void elink_set_serdes_access(struct bxe_softc *sc, uint8_t port)
4136 {
4137 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
4138
4139 /* Set Clause 22 */
4140 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
4141 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
4142 DELAY(500);
4143 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
4144 DELAY(500);
4145 /* Set Clause 45 */
4146 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
4147 }
4148
elink_serdes_deassert(struct bxe_softc * sc,uint8_t port)4149 static void elink_serdes_deassert(struct bxe_softc *sc, uint8_t port)
4150 {
4151 uint32_t val;
4152
4153 ELINK_DEBUG_P0(sc, "elink_serdes_deassert\n");
4154
4155 val = ELINK_SERDES_RESET_BITS << (port*16);
4156
4157 /* Reset and unreset the SerDes/XGXS */
4158 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4159 DELAY(500);
4160 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4161
4162 elink_set_serdes_access(sc, port);
4163
4164 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
4165 ELINK_DEFAULT_PHY_DEV_ADDR);
4166 }
4167
elink_xgxs_specific_func(struct elink_phy * phy,struct elink_params * params,uint32_t action)4168 static void elink_xgxs_specific_func(struct elink_phy *phy,
4169 struct elink_params *params,
4170 uint32_t action)
4171 {
4172 struct bxe_softc *sc = params->sc;
4173 switch (action) {
4174 case ELINK_PHY_INIT:
4175 /* Set correct devad */
4176 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
4177 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
4178 phy->def_md_devad);
4179 break;
4180 }
4181 }
4182
elink_xgxs_deassert(struct elink_params * params)4183 static void elink_xgxs_deassert(struct elink_params *params)
4184 {
4185 struct bxe_softc *sc = params->sc;
4186 uint8_t port;
4187 uint32_t val;
4188 ELINK_DEBUG_P0(sc, "elink_xgxs_deassert\n");
4189 port = params->port;
4190
4191 val = ELINK_XGXS_RESET_BITS << (port*16);
4192
4193 /* Reset and unreset the SerDes/XGXS */
4194 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4195 DELAY(500);
4196 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4197 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
4198 ELINK_PHY_INIT);
4199 }
4200
elink_calc_ieee_aneg_adv(struct elink_phy * phy,struct elink_params * params,uint16_t * ieee_fc)4201 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
4202 struct elink_params *params, uint16_t *ieee_fc)
4203 {
4204 struct bxe_softc *sc = params->sc;
4205 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
4206 /* Resolve pause mode and advertisement Please refer to Table
4207 * 28B-3 of the 802.3ab-1999 spec
4208 */
4209
4210 switch (phy->req_flow_ctrl) {
4211 case ELINK_FLOW_CTRL_AUTO:
4212 switch (params->req_fc_auto_adv) {
4213 case ELINK_FLOW_CTRL_BOTH:
4214 case ELINK_FLOW_CTRL_RX:
4215 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4216 break;
4217 case ELINK_FLOW_CTRL_TX:
4218 *ieee_fc |=
4219 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4220 break;
4221 default:
4222 break;
4223 }
4224 break;
4225 case ELINK_FLOW_CTRL_TX:
4226 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4227 break;
4228
4229 case ELINK_FLOW_CTRL_RX:
4230 case ELINK_FLOW_CTRL_BOTH:
4231 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4232 break;
4233
4234 case ELINK_FLOW_CTRL_NONE:
4235 default:
4236 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
4237 break;
4238 }
4239 ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x\n", *ieee_fc);
4240 }
4241
set_phy_vars(struct elink_params * params,struct elink_vars * vars)4242 static void set_phy_vars(struct elink_params *params,
4243 struct elink_vars *vars)
4244 {
4245 struct bxe_softc *sc = params->sc;
4246 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
4247 uint8_t phy_config_swapped = params->multi_phy_config &
4248 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
4249 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
4250 phy_index++) {
4251 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
4252 actual_phy_idx = phy_index;
4253 if (phy_config_swapped) {
4254 if (phy_index == ELINK_EXT_PHY1)
4255 actual_phy_idx = ELINK_EXT_PHY2;
4256 else if (phy_index == ELINK_EXT_PHY2)
4257 actual_phy_idx = ELINK_EXT_PHY1;
4258 }
4259 params->phy[actual_phy_idx].req_flow_ctrl =
4260 params->req_flow_ctrl[link_cfg_idx];
4261
4262 params->phy[actual_phy_idx].req_line_speed =
4263 params->req_line_speed[link_cfg_idx];
4264
4265 params->phy[actual_phy_idx].speed_cap_mask =
4266 params->speed_cap_mask[link_cfg_idx];
4267
4268 params->phy[actual_phy_idx].req_duplex =
4269 params->req_duplex[link_cfg_idx];
4270
4271 if (params->req_line_speed[link_cfg_idx] ==
4272 ELINK_SPEED_AUTO_NEG)
4273 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
4274
4275 ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x,"
4276 " speed_cap_mask %x\n",
4277 params->phy[actual_phy_idx].req_flow_ctrl,
4278 params->phy[actual_phy_idx].req_line_speed,
4279 params->phy[actual_phy_idx].speed_cap_mask);
4280 }
4281 }
4282
elink_ext_phy_set_pause(struct elink_params * params,struct elink_phy * phy,struct elink_vars * vars)4283 static void elink_ext_phy_set_pause(struct elink_params *params,
4284 struct elink_phy *phy,
4285 struct elink_vars *vars)
4286 {
4287 uint16_t val;
4288 struct bxe_softc *sc = params->sc;
4289 /* Read modify write pause advertizing */
4290 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
4291
4292 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
4293
4294 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4295 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4296 if ((vars->ieee_fc &
4297 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4298 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4299 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
4300 }
4301 if ((vars->ieee_fc &
4302 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4303 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4304 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
4305 }
4306 ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val);
4307 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
4308 }
4309
elink_pause_resolve(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars,uint32_t pause_result)4310 static void elink_pause_resolve(struct elink_phy *phy,
4311 struct elink_params *params,
4312 struct elink_vars *vars,
4313 uint32_t pause_result)
4314 {
4315 struct bxe_softc *sc = params->sc;
4316 /* LD LP */
4317 switch (pause_result) { /* ASYM P ASYM P */
4318 case 0xb: /* 1 0 1 1 */
4319 ELINK_DEBUG_P0(sc, "Flow Control: TX only\n");
4320 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
4321 break;
4322
4323 case 0xe: /* 1 1 1 0 */
4324 ELINK_DEBUG_P0(sc, "Flow Control: RX only\n");
4325 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
4326 break;
4327
4328 case 0x5: /* 0 1 0 1 */
4329 case 0x7: /* 0 1 1 1 */
4330 case 0xd: /* 1 1 0 1 */
4331 case 0xf: /* 1 1 1 1 */
4332 /* If the user selected to advertise RX ONLY,
4333 * although we advertised both, need to enable
4334 * RX only.
4335 */
4336
4337 if (params->req_fc_auto_adv == ELINK_FLOW_CTRL_BOTH) {
4338 ELINK_DEBUG_P0(sc, "Flow Control: RX & TX\n");
4339 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
4340 } else {
4341 ELINK_DEBUG_P0(sc, "Flow Control: RX only\n");
4342 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
4343 }
4344 break;
4345 default:
4346 ELINK_DEBUG_P0(sc, "Flow Control: None\n");
4347 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4348 break;
4349 }
4350 if (pause_result & (1<<0))
4351 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
4352 if (pause_result & (1<<1))
4353 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
4354
4355 }
4356
elink_ext_phy_update_adv_fc(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)4357 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
4358 struct elink_params *params,
4359 struct elink_vars *vars)
4360 {
4361 uint16_t ld_pause; /* local */
4362 uint16_t lp_pause; /* link partner */
4363 uint16_t pause_result;
4364 struct bxe_softc *sc = params->sc;
4365 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
4366 elink_cl22_read(sc, phy, 0x4, &ld_pause);
4367 elink_cl22_read(sc, phy, 0x5, &lp_pause);
4368 } else if (CHIP_IS_E3(sc) &&
4369 ELINK_SINGLE_MEDIA_DIRECT(params)) {
4370 uint8_t lane = elink_get_warpcore_lane(phy, params);
4371 uint16_t gp_status, gp_mask;
4372 elink_cl45_read(sc, phy,
4373 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
4374 &gp_status);
4375 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
4376 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
4377 lane;
4378 if ((gp_status & gp_mask) == gp_mask) {
4379 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4380 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4381 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4382 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4383 } else {
4384 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4385 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
4386 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4387 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
4388 ld_pause = ((ld_pause &
4389 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4390 << 3);
4391 lp_pause = ((lp_pause &
4392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4393 << 3);
4394 }
4395 } else {
4396 elink_cl45_read(sc, phy,
4397 MDIO_AN_DEVAD,
4398 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4399 elink_cl45_read(sc, phy,
4400 MDIO_AN_DEVAD,
4401 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4402 }
4403 pause_result = (ld_pause &
4404 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
4405 pause_result |= (lp_pause &
4406 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
4407 ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x\n", pause_result);
4408 elink_pause_resolve(phy, params, vars, pause_result);
4409
4410 }
4411
elink_ext_phy_resolve_fc(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)4412 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
4413 struct elink_params *params,
4414 struct elink_vars *vars)
4415 {
4416 uint8_t ret = 0;
4417 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4418 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
4419 /* Update the advertised flow-controlled of LD/LP in AN */
4420 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
4421 elink_ext_phy_update_adv_fc(phy, params, vars);
4422 /* But set the flow-control result as the requested one */
4423 vars->flow_ctrl = phy->req_flow_ctrl;
4424 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4425 vars->flow_ctrl = params->req_fc_auto_adv;
4426 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
4427 ret = 1;
4428 elink_ext_phy_update_adv_fc(phy, params, vars);
4429 }
4430 return ret;
4431 }
4432 /******************************************************************/
4433 /* Warpcore section */
4434 /******************************************************************/
4435 /* The init_internal_warpcore should mirror the xgxs,
4436 * i.e. reset the lane (if needed), set aer for the
4437 * init configuration, and set/clear SGMII flag. Internal
4438 * phy init is done purely in phy_init stage.
4439 */
4440 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
4441 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
4442 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
4443 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
4444 (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
4445
4446 #define WC_TX_FIR(post, main, pre) \
4447 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
4448 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
4449 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
4450
elink_update_link_attr(struct elink_params * params,uint32_t link_attr)4451 static void elink_update_link_attr(struct elink_params *params, uint32_t link_attr)
4452 {
4453 struct bxe_softc *sc = params->sc;
4454
4455 if (SHMEM2_HAS(sc, link_attr_sync))
4456 REG_WR(sc, params->shmem2_base +
4457 offsetof(struct shmem2_region,
4458 link_attr_sync[params->port]), link_attr);
4459 }
4460
elink_warpcore_enable_AN_KR2(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)4461 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
4462 struct elink_params *params,
4463 struct elink_vars *vars)
4464 {
4465 struct bxe_softc *sc = params->sc;
4466 uint16_t i;
4467 static struct elink_reg_set reg_set[] = {
4468 /* Step 1 - Program the TX/RX alignment markers */
4469 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
4470 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
4471 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
4472 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
4473 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
4474 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
4475 /* Step 2 - Configure the NP registers */
4476 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
4477 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
4478 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
4479 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
4480 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
4481 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
4482 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
4483 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
4484 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
4485 };
4486 ELINK_DEBUG_P0(sc, "Enabling 20G-KR2\n");
4487
4488 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4489 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
4490
4491 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4492 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4493 reg_set[i].val);
4494
4495 /* Start KR2 work-around timer which handles BCM8073 link-parner */
4496 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
4497 elink_update_link_attr(params, params->link_attr_sync);
4498 }
4499
elink_disable_kr2(struct elink_params * params,struct elink_vars * vars,struct elink_phy * phy)4500 static void elink_disable_kr2(struct elink_params *params,
4501 struct elink_vars *vars,
4502 struct elink_phy *phy)
4503 {
4504 struct bxe_softc *sc = params->sc;
4505 int i;
4506 static struct elink_reg_set reg_set[] = {
4507 /* Step 1 - Program the TX/RX alignment markers */
4508 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
4509 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
4510 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
4511 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
4512 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
4513 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
4514 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
4515 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
4516 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
4517 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
4518 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
4519 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
4520 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
4521 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
4522 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
4523 };
4524 ELINK_DEBUG_P0(sc, "Disabling 20G-KR2\n");
4525
4526 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4527 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4528 reg_set[i].val);
4529 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
4530 elink_update_link_attr(params, params->link_attr_sync);
4531
4532 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
4533 }
4534
elink_warpcore_set_lpi_passthrough(struct elink_phy * phy,struct elink_params * params)4535 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
4536 struct elink_params *params)
4537 {
4538 struct bxe_softc *sc = params->sc;
4539
4540 ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through\n");
4541 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4542 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
4543 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4544 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
4545 }
4546
elink_warpcore_restart_AN_KR(struct elink_phy * phy,struct elink_params * params)4547 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
4548 struct elink_params *params)
4549 {
4550 /* Restart autoneg on the leading lane only */
4551 struct bxe_softc *sc = params->sc;
4552 uint16_t lane = elink_get_warpcore_lane(phy, params);
4553 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4554 MDIO_AER_BLOCK_AER_REG, lane);
4555 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4556 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4557
4558 /* Restore AER */
4559 elink_set_aer_mmd(params, phy);
4560 }
4561
elink_warpcore_enable_AN_KR(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)4562 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
4563 struct elink_params *params,
4564 struct elink_vars *vars) {
4565 uint16_t lane, i, cl72_ctrl, an_adv = 0, val;
4566 uint32_t wc_lane_config;
4567 struct bxe_softc *sc = params->sc;
4568 static struct elink_reg_set reg_set[] = {
4569 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4570 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
4571 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
4572 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
4573 /* Disable Autoneg: re-enable it after adv is done. */
4574 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
4575 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
4576 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
4577 };
4578 ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR\n");
4579 /* Set to default registers that may be overridden by 10G force */
4580 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4581 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4582 reg_set[i].val);
4583
4584 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4585 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
4586 cl72_ctrl &= 0x08ff;
4587 cl72_ctrl |= 0x3800;
4588 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4589 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
4590
4591 /* Check adding advertisement for 1G KX */
4592 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4593 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
4594 (vars->line_speed == ELINK_SPEED_1000)) {
4595 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
4596 an_adv |= (1<<5);
4597
4598 /* Enable CL37 1G Parallel Detect */
4599 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
4600 ELINK_DEBUG_P0(sc, "Advertize 1G\n");
4601 }
4602 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4603 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4604 (vars->line_speed == ELINK_SPEED_10000)) {
4605 /* Check adding advertisement for 10G KR */
4606 an_adv |= (1<<7);
4607 /* Enable 10G Parallel Detect */
4608 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4609 MDIO_AER_BLOCK_AER_REG, 0);
4610
4611 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4612 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
4613 elink_set_aer_mmd(params, phy);
4614 ELINK_DEBUG_P0(sc, "Advertize 10G\n");
4615 }
4616
4617 /* Set Transmit PMD settings */
4618 lane = elink_get_warpcore_lane(phy, params);
4619 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4620 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4621 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
4622 /* Configure the next lane if dual mode */
4623 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4624 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4625 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
4626 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
4627 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4628 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
4629 0x03f0);
4630 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4631 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
4632 0x03f0);
4633
4634 /* Advertised speeds */
4635 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4636 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
4637
4638 /* Advertised and set FEC (Forward Error Correction) */
4639 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4640 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
4641 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
4642 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
4643
4644 /* Enable CL37 BAM */
4645 if (REG_RD(sc, params->shmem_base +
4646 offsetof(struct shmem_region, dev_info.
4647 port_hw_config[params->port].default_cfg)) &
4648 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4649 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4650 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
4651 1);
4652 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
4653 }
4654
4655 /* Advertise pause */
4656 elink_ext_phy_set_pause(params, phy, vars);
4657 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
4658 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4659 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
4660
4661 /* Over 1G - AN local device user page 1 */
4662 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4663 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
4664
4665 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
4666 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
4667 (phy->req_line_speed == ELINK_SPEED_20000)) {
4668
4669 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4670 MDIO_AER_BLOCK_AER_REG, lane);
4671
4672 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4673 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
4674 (1<<11));
4675
4676 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4677 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
4678 elink_set_aer_mmd(params, phy);
4679
4680 elink_warpcore_enable_AN_KR2(phy, params, vars);
4681 } else {
4682 /* Enable Auto-Detect to support 1G over CL37 as well */
4683 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4684 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
4685 wc_lane_config = REG_RD(sc, params->shmem_base +
4686 offsetof(struct shmem_region, dev_info.
4687 shared_hw_config.wc_lane_config));
4688 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4689 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
4690 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
4691 * parallel-detect loop when CL73 and CL37 are enabled.
4692 */
4693 val |= 1 << 11;
4694
4695 /* Restore Polarity settings in case it was run over by
4696 * previous link owner
4697 */
4698 if (wc_lane_config &
4699 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
4700 val |= 3 << 2;
4701 else
4702 val &= ~(3 << 2);
4703 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4704 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
4705 val);
4706
4707 elink_disable_kr2(params, vars, phy);
4708 }
4709
4710 /* Enable Autoneg: only on the main lane */
4711 elink_warpcore_restart_AN_KR(phy, params);
4712 }
4713
elink_warpcore_set_10G_KR(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)4714 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
4715 struct elink_params *params,
4716 struct elink_vars *vars)
4717 {
4718 struct bxe_softc *sc = params->sc;
4719 uint16_t val16, i, lane;
4720 static struct elink_reg_set reg_set[] = {
4721 /* Disable Autoneg */
4722 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4723 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
4724 0x3f00},
4725 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
4726 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
4727 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
4728 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
4729 /* Leave cl72 training enable, needed for KR */
4730 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
4731 };
4732
4733 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4734 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4735 reg_set[i].val);
4736
4737 lane = elink_get_warpcore_lane(phy, params);
4738 /* Global registers */
4739 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4740 MDIO_AER_BLOCK_AER_REG, 0);
4741 /* Disable CL36 PCS Tx */
4742 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4743 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4744 val16 &= ~(0x0011 << lane);
4745 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4746 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4747
4748 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4749 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4750 val16 |= (0x0303 << (lane << 1));
4751 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4752 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4753 /* Restore AER */
4754 elink_set_aer_mmd(params, phy);
4755 /* Set speed via PMA/PMD register */
4756 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4757 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4758
4759 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4760 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
4761
4762 /* Enable encoded forced speed */
4763 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4764 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
4765
4766 /* Turn TX scramble payload only the 64/66 scrambler */
4767 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4768 MDIO_WC_REG_TX66_CONTROL, 0x9);
4769
4770 /* Turn RX scramble payload only the 64/66 scrambler */
4771 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4772 MDIO_WC_REG_RX66_CONTROL, 0xF9);
4773
4774 /* Set and clear loopback to cause a reset to 64/66 decoder */
4775 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4776 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
4777 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4778 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
4779
4780 }
4781
elink_warpcore_set_10G_XFI(struct elink_phy * phy,struct elink_params * params,uint8_t is_xfi)4782 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
4783 struct elink_params *params,
4784 uint8_t is_xfi)
4785 {
4786 struct bxe_softc *sc = params->sc;
4787 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
4788 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
4789 uint32_t ifir_val, ipost2_val, ipre_driver_val;
4790 /* Hold rxSeqStart */
4791 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4792 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
4793
4794 /* Hold tx_fifo_reset */
4795 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4796 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
4797
4798 /* Disable CL73 AN */
4799 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4800
4801 /* Disable 100FX Enable and Auto-Detect */
4802 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4803 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
4804
4805 /* Disable 100FX Idle detect */
4806 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4807 MDIO_WC_REG_FX100_CTRL3, 0x0080);
4808
4809 /* Set Block address to Remote PHY & Clear forced_speed[5] */
4810 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4811 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
4812
4813 /* Turn off auto-detect & fiber mode */
4814 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4815 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4816 0xFFEE);
4817
4818 /* Set filter_force_link, disable_false_link and parallel_detect */
4819 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4820 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4821 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4822 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4823 ((val | 0x0006) & 0xFFFE));
4824
4825 /* Set XFI / SFI */
4826 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4827 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4828
4829 misc1_val &= ~(0x1f);
4830
4831 if (is_xfi) {
4832 misc1_val |= 0x5;
4833 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4834 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
4835 } else {
4836 cfg_tap_val = REG_RD(sc, params->shmem_base +
4837 offsetof(struct shmem_region, dev_info.
4838 port_hw_config[params->port].
4839 sfi_tap_values));
4840
4841 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4842
4843 misc1_val |= 0x9;
4844
4845 /* TAP values are controlled by nvram, if value there isn't 0 */
4846 if (tx_equal)
4847 tap_val = (uint16_t)tx_equal;
4848 else
4849 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4850
4851 ifir_val = DEFAULT_TX_DRV_IFIR;
4852 ipost2_val = DEFAULT_TX_DRV_POST2;
4853 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4854 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4855
4856 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
4857 * configuration.
4858 */
4859 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4860 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4861 PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4862 ifir_val = (cfg_tap_val &
4863 PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4864 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4865 ipre_driver_val = (cfg_tap_val &
4866 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4867 >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4868 ipost2_val = (cfg_tap_val &
4869 PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4870 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4871 }
4872
4873 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4874 tx_drv_brdct = (cfg_tap_val &
4875 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4876 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4877 }
4878
4879 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4880 ipre_driver_val, ifir_val);
4881 }
4882 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4883 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4884
4885 /* Set Transmit PMD settings */
4886 lane = elink_get_warpcore_lane(phy, params);
4887 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4888 MDIO_WC_REG_TX_FIR_TAP,
4889 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4890 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4891 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4892 tx_driver_val);
4893
4894 /* Enable fiber mode, enable and invert sig_det */
4895 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4896 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4897
4898 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4899 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4900 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4901
4902 elink_warpcore_set_lpi_passthrough(phy, params);
4903
4904 /* 10G XFI Full Duplex */
4905 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4906 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4907
4908 /* Release tx_fifo_reset */
4909 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4910 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4911 0xFFFE);
4912 /* Release rxSeqStart */
4913 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4914 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4915 }
4916
elink_warpcore_set_20G_force_KR2(struct elink_phy * phy,struct elink_params * params)4917 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
4918 struct elink_params *params)
4919 {
4920 uint16_t val;
4921 struct bxe_softc *sc = params->sc;
4922 /* Set global registers, so set AER lane to 0 */
4923 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4924 MDIO_AER_BLOCK_AER_REG, 0);
4925
4926 /* Disable sequencer */
4927 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4928 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4929
4930 elink_set_aer_mmd(params, phy);
4931
4932 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
4933 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4934 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4935 MDIO_AN_REG_CTRL, 0);
4936 /* Turn off CL73 */
4937 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4938 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4939 val &= ~(1<<5);
4940 val |= (1<<6);
4941 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4942 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4943
4944 /* Set 20G KR2 force speed */
4945 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4946 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4947
4948 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4949 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4950
4951 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4952 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4953 val &= ~(3<<14);
4954 val |= (1<<15);
4955 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4956 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4957 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4958 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4959
4960 /* Enable sequencer (over lane 0) */
4961 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4962 MDIO_AER_BLOCK_AER_REG, 0);
4963
4964 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4965 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4966
4967 elink_set_aer_mmd(params, phy);
4968 }
4969
elink_warpcore_set_20G_DXGXS(struct bxe_softc * sc,struct elink_phy * phy,uint16_t lane)4970 static void elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc,
4971 struct elink_phy *phy,
4972 uint16_t lane)
4973 {
4974 /* Rx0 anaRxControl1G */
4975 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4976 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4977
4978 /* Rx2 anaRxControl1G */
4979 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4980 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4981
4982 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4983 MDIO_WC_REG_RX66_SCW0, 0xE070);
4984
4985 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4986 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4987
4988 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4989 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4990
4991 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4992 MDIO_WC_REG_RX66_SCW3, 0x8090);
4993
4994 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4995 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4996
4997 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4998 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4999
5000 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5001 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
5002
5003 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5004 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
5005
5006 /* Serdes Digital Misc1 */
5007 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5008 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
5009
5010 /* Serdes Digital4 Misc3 */
5011 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5012 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
5013
5014 /* Set Transmit PMD settings */
5015 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5016 MDIO_WC_REG_TX_FIR_TAP,
5017 (WC_TX_FIR(0x12, 0x2d, 0x00) |
5018 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
5019 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5020 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
5021 WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
5022 }
5023
elink_warpcore_set_sgmii_speed(struct elink_phy * phy,struct elink_params * params,uint8_t fiber_mode,uint8_t always_autoneg)5024 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
5025 struct elink_params *params,
5026 uint8_t fiber_mode,
5027 uint8_t always_autoneg)
5028 {
5029 struct bxe_softc *sc = params->sc;
5030 uint16_t val16, digctrl_kx1, digctrl_kx2;
5031
5032 /* Clear XFI clock comp in non-10G single lane mode. */
5033 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5034 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
5035
5036 elink_warpcore_set_lpi_passthrough(phy, params);
5037
5038 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5039 /* SGMII Autoneg */
5040 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5041 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
5042 0x1000);
5043 ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n");
5044 } else {
5045 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5046 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
5047 val16 &= 0xcebf;
5048 switch (phy->req_line_speed) {
5049 case ELINK_SPEED_10:
5050 break;
5051 case ELINK_SPEED_100:
5052 val16 |= 0x2000;
5053 break;
5054 case ELINK_SPEED_1000:
5055 val16 |= 0x0040;
5056 break;
5057 default:
5058 ELINK_DEBUG_P1(sc,
5059 "Speed not supported: 0x%x\n", phy->req_line_speed);
5060 return;
5061 }
5062
5063 if (phy->req_duplex == DUPLEX_FULL)
5064 val16 |= 0x0100;
5065
5066 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5067 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
5068
5069 ELINK_DEBUG_P1(sc, "set SGMII force speed %d\n",
5070 phy->req_line_speed);
5071 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5072 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
5073 ELINK_DEBUG_P1(sc, " (readback) %x\n", val16);
5074 }
5075
5076 /* SGMII Slave mode and disable signal detect */
5077 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5078 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
5079 if (fiber_mode)
5080 digctrl_kx1 = 1;
5081 else
5082 digctrl_kx1 &= 0xff4a;
5083
5084 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5085 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5086 digctrl_kx1);
5087
5088 /* Turn off parallel detect */
5089 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5090 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
5091 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5092 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5093 (digctrl_kx2 & ~(1<<2)));
5094
5095 /* Re-enable parallel detect */
5096 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5097 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5098 (digctrl_kx2 | (1<<2)));
5099
5100 /* Enable autodet */
5101 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5102 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5103 (digctrl_kx1 | 0x10));
5104 }
5105
5106
elink_warpcore_reset_lane(struct bxe_softc * sc,struct elink_phy * phy,uint8_t reset)5107 static void elink_warpcore_reset_lane(struct bxe_softc *sc,
5108 struct elink_phy *phy,
5109 uint8_t reset)
5110 {
5111 uint16_t val;
5112 /* Take lane out of reset after configuration is finished */
5113 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5114 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5115 if (reset)
5116 val |= 0xC000;
5117 else
5118 val &= 0x3FFF;
5119 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5120 MDIO_WC_REG_DIGITAL5_MISC6, val);
5121 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5122 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5123 }
5124
5125 /* Clear SFI/XFI link settings registers */
elink_warpcore_clear_regs(struct elink_phy * phy,struct elink_params * params,uint16_t lane)5126 static void elink_warpcore_clear_regs(struct elink_phy *phy,
5127 struct elink_params *params,
5128 uint16_t lane)
5129 {
5130 struct bxe_softc *sc = params->sc;
5131 uint16_t i;
5132 static struct elink_reg_set wc_regs[] = {
5133 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
5134 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
5135 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
5136 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
5137 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5138 0x0195},
5139 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5140 0x0007},
5141 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
5142 0x0002},
5143 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
5144 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
5145 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
5146 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
5147 };
5148 /* Set XFI clock comp as default. */
5149 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5150 MDIO_WC_REG_RX66_CONTROL, (3<<13));
5151
5152 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
5153 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
5154 wc_regs[i].val);
5155
5156 lane = elink_get_warpcore_lane(phy, params);
5157 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5158 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
5159
5160 }
5161
elink_get_mod_abs_int_cfg(struct bxe_softc * sc,uint32_t chip_id,uint32_t shmem_base,uint8_t port,uint8_t * gpio_num,uint8_t * gpio_port)5162 static elink_status_t elink_get_mod_abs_int_cfg(struct bxe_softc *sc,
5163 uint32_t chip_id,
5164 uint32_t shmem_base, uint8_t port,
5165 uint8_t *gpio_num, uint8_t *gpio_port)
5166 {
5167 uint32_t cfg_pin;
5168 *gpio_num = 0;
5169 *gpio_port = 0;
5170 if (CHIP_IS_E3(sc)) {
5171 cfg_pin = (REG_RD(sc, shmem_base +
5172 offsetof(struct shmem_region,
5173 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5174 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
5175 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
5176
5177 /* Should not happen. This function called upon interrupt
5178 * triggered by GPIO ( since EPIO can only generate interrupts
5179 * to MCP).
5180 * So if this function was called and none of the GPIOs was set,
5181 * it means the shit hit the fan.
5182 */
5183 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
5184 (cfg_pin > PIN_CFG_GPIO3_P1)) {
5185 ELINK_DEBUG_P1(sc,
5186 "No cfg pin %x for module detect indication\n",
5187 cfg_pin);
5188 return ELINK_STATUS_ERROR;
5189 }
5190
5191 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
5192 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
5193 } else {
5194 *gpio_num = MISC_REGISTERS_GPIO_3;
5195 *gpio_port = port;
5196 }
5197
5198 return ELINK_STATUS_OK;
5199 }
5200
elink_is_sfp_module_plugged(struct elink_phy * phy,struct elink_params * params)5201 static int elink_is_sfp_module_plugged(struct elink_phy *phy,
5202 struct elink_params *params)
5203 {
5204 struct bxe_softc *sc = params->sc;
5205 uint8_t gpio_num, gpio_port;
5206 uint32_t gpio_val;
5207 if (elink_get_mod_abs_int_cfg(sc, params->chip_id,
5208 params->shmem_base, params->port,
5209 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
5210 return 0;
5211 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
5212
5213 /* Call the handling function in case module is detected */
5214 if (gpio_val == 0)
5215 return 1;
5216 else
5217 return 0;
5218 }
elink_warpcore_get_sigdet(struct elink_phy * phy,struct elink_params * params)5219 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
5220 struct elink_params *params)
5221 {
5222 uint16_t gp2_status_reg0, lane;
5223 struct bxe_softc *sc = params->sc;
5224
5225 lane = elink_get_warpcore_lane(phy, params);
5226
5227 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
5228 &gp2_status_reg0);
5229
5230 return (gp2_status_reg0 >> (8+lane)) & 0x1;
5231 }
5232
elink_warpcore_config_runtime(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)5233 static void elink_warpcore_config_runtime(struct elink_phy *phy,
5234 struct elink_params *params,
5235 struct elink_vars *vars)
5236 {
5237 struct bxe_softc *sc = params->sc;
5238 uint32_t serdes_net_if;
5239 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
5240
5241 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
5242
5243 if (!vars->turn_to_run_wc_rt)
5244 return;
5245
5246 if (vars->rx_tx_asic_rst) {
5247 uint16_t lane = elink_get_warpcore_lane(phy, params);
5248 serdes_net_if = (REG_RD(sc, params->shmem_base +
5249 offsetof(struct shmem_region, dev_info.
5250 port_hw_config[params->port].default_cfg)) &
5251 PORT_HW_CFG_NET_SERDES_IF_MASK);
5252
5253 switch (serdes_net_if) {
5254 case PORT_HW_CFG_NET_SERDES_IF_KR:
5255 /* Do we get link yet? */
5256 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
5257 &gp_status1);
5258 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
5259 /*10G KR*/
5260 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
5261
5262 if (lnkup_kr || lnkup) {
5263 vars->rx_tx_asic_rst = 0;
5264 } else {
5265 /* Reset the lane to see if link comes up.*/
5266 elink_warpcore_reset_lane(sc, phy, 1);
5267 elink_warpcore_reset_lane(sc, phy, 0);
5268
5269 /* Restart Autoneg */
5270 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
5271 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
5272
5273 vars->rx_tx_asic_rst--;
5274 ELINK_DEBUG_P1(sc, "0x%x retry left\n",
5275 vars->rx_tx_asic_rst);
5276 }
5277 break;
5278
5279 default:
5280 break;
5281 }
5282
5283 } /*params->rx_tx_asic_rst*/
5284
5285 }
elink_warpcore_config_sfi(struct elink_phy * phy,struct elink_params * params)5286 static void elink_warpcore_config_sfi(struct elink_phy *phy,
5287 struct elink_params *params)
5288 {
5289 uint16_t lane = elink_get_warpcore_lane(phy, params);
5290 struct bxe_softc *sc = params->sc;
5291 elink_warpcore_clear_regs(phy, params, lane);
5292 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
5293 ELINK_SPEED_10000) &&
5294 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
5295 ELINK_DEBUG_P0(sc, "Setting 10G SFI\n");
5296 elink_warpcore_set_10G_XFI(phy, params, 0);
5297 } else {
5298 ELINK_DEBUG_P0(sc, "Setting 1G Fiber\n");
5299 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
5300 }
5301 }
5302
elink_sfp_e3_set_transmitter(struct elink_params * params,struct elink_phy * phy,uint8_t tx_en)5303 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
5304 struct elink_phy *phy,
5305 uint8_t tx_en)
5306 {
5307 struct bxe_softc *sc = params->sc;
5308 uint32_t cfg_pin;
5309 uint8_t port = params->port;
5310
5311 cfg_pin = REG_RD(sc, params->shmem_base +
5312 offsetof(struct shmem_region,
5313 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5314 PORT_HW_CFG_E3_TX_LASER_MASK;
5315 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
5316 ELINK_DEBUG_P1(sc, "Setting WC TX to %d\n", tx_en);
5317
5318 /* For 20G, the expected pin to be used is 3 pins after the current */
5319 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
5320 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
5321 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
5322 }
5323
elink_warpcore_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)5324 static void elink_warpcore_config_init(struct elink_phy *phy,
5325 struct elink_params *params,
5326 struct elink_vars *vars)
5327 {
5328 struct bxe_softc *sc = params->sc;
5329 uint32_t serdes_net_if;
5330 uint8_t fiber_mode;
5331 uint16_t lane = elink_get_warpcore_lane(phy, params);
5332 serdes_net_if = (REG_RD(sc, params->shmem_base +
5333 offsetof(struct shmem_region, dev_info.
5334 port_hw_config[params->port].default_cfg)) &
5335 PORT_HW_CFG_NET_SERDES_IF_MASK);
5336 ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, "
5337 "serdes_net_if = 0x%x\n",
5338 vars->line_speed, serdes_net_if);
5339 elink_set_aer_mmd(params, phy);
5340 elink_warpcore_reset_lane(sc, phy, 1);
5341 vars->phy_flags |= PHY_XGXS_FLAG;
5342 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
5343 (phy->req_line_speed &&
5344 ((phy->req_line_speed == ELINK_SPEED_100) ||
5345 (phy->req_line_speed == ELINK_SPEED_10)))) {
5346 vars->phy_flags |= PHY_SGMII_FLAG;
5347 ELINK_DEBUG_P0(sc, "Setting SGMII mode\n");
5348 elink_warpcore_clear_regs(phy, params, lane);
5349 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
5350 } else {
5351 switch (serdes_net_if) {
5352 case PORT_HW_CFG_NET_SERDES_IF_KR:
5353 /* Enable KR Auto Neg */
5354 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
5355 elink_warpcore_enable_AN_KR(phy, params, vars);
5356 else {
5357 ELINK_DEBUG_P0(sc, "Setting KR 10G-Force\n");
5358 elink_warpcore_set_10G_KR(phy, params, vars);
5359 }
5360 break;
5361
5362 case PORT_HW_CFG_NET_SERDES_IF_XFI:
5363 elink_warpcore_clear_regs(phy, params, lane);
5364 if (vars->line_speed == ELINK_SPEED_10000) {
5365 ELINK_DEBUG_P0(sc, "Setting 10G XFI\n");
5366 elink_warpcore_set_10G_XFI(phy, params, 1);
5367 } else {
5368 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5369 ELINK_DEBUG_P0(sc, "1G Fiber\n");
5370 fiber_mode = 1;
5371 } else {
5372 ELINK_DEBUG_P0(sc, "10/100/1G SGMII\n");
5373 fiber_mode = 0;
5374 }
5375 elink_warpcore_set_sgmii_speed(phy,
5376 params,
5377 fiber_mode,
5378 0);
5379 }
5380
5381 break;
5382
5383 case PORT_HW_CFG_NET_SERDES_IF_SFI:
5384 /* Issue Module detection if module is plugged, or
5385 * enabled transmitter to avoid current leakage in case
5386 * no module is connected
5387 */
5388 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
5389 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5390 if (elink_is_sfp_module_plugged(phy, params))
5391 elink_sfp_module_detection(phy, params);
5392 else
5393 elink_sfp_e3_set_transmitter(params,
5394 phy, 1);
5395 }
5396
5397 elink_warpcore_config_sfi(phy, params);
5398 break;
5399
5400 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
5401 if (vars->line_speed != ELINK_SPEED_20000) {
5402 ELINK_DEBUG_P0(sc, "Speed not supported yet\n");
5403 return;
5404 }
5405 ELINK_DEBUG_P0(sc, "Setting 20G DXGXS\n");
5406 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
5407 /* Issue Module detection */
5408
5409 elink_sfp_module_detection(phy, params);
5410 break;
5411 case PORT_HW_CFG_NET_SERDES_IF_KR2:
5412 if (!params->loopback_mode) {
5413 elink_warpcore_enable_AN_KR(phy, params, vars);
5414 } else {
5415 ELINK_DEBUG_P0(sc, "Setting KR 20G-Force\n");
5416 elink_warpcore_set_20G_force_KR2(phy, params);
5417 }
5418 break;
5419 default:
5420 ELINK_DEBUG_P1(sc,
5421 "Unsupported Serdes Net Interface 0x%x\n",
5422 serdes_net_if);
5423 return;
5424 }
5425 }
5426
5427 /* Take lane out of reset after configuration is finished */
5428 elink_warpcore_reset_lane(sc, phy, 0);
5429 ELINK_DEBUG_P0(sc, "Exit config init\n");
5430 }
5431
elink_warpcore_link_reset(struct elink_phy * phy,struct elink_params * params)5432 static void elink_warpcore_link_reset(struct elink_phy *phy,
5433 struct elink_params *params)
5434 {
5435 struct bxe_softc *sc = params->sc;
5436 uint16_t val16, lane;
5437 elink_sfp_e3_set_transmitter(params, phy, 0);
5438 elink_set_mdio_emac_per_phy(sc, params);
5439 elink_set_aer_mmd(params, phy);
5440 /* Global register */
5441 elink_warpcore_reset_lane(sc, phy, 1);
5442
5443 /* Clear loopback settings (if any) */
5444 /* 10G & 20G */
5445 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5446 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
5447
5448 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5449 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
5450
5451 /* Update those 1-copy registers */
5452 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5453 MDIO_AER_BLOCK_AER_REG, 0);
5454 /* Enable 1G MDIO (1-copy) */
5455 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5456 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5457 ~0x10);
5458
5459 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5460 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
5461 lane = elink_get_warpcore_lane(phy, params);
5462 /* Disable CL36 PCS Tx */
5463 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5464 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
5465 val16 |= (0x11 << lane);
5466 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5467 val16 |= (0x22 << lane);
5468 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5469 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
5470
5471 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5472 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
5473 val16 &= ~(0x0303 << (lane << 1));
5474 val16 |= (0x0101 << (lane << 1));
5475 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
5476 val16 &= ~(0x0c0c << (lane << 1));
5477 val16 |= (0x0404 << (lane << 1));
5478 }
5479
5480 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5481 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
5482 /* Restore AER */
5483 elink_set_aer_mmd(params, phy);
5484
5485 }
5486
elink_set_warpcore_loopback(struct elink_phy * phy,struct elink_params * params)5487 static void elink_set_warpcore_loopback(struct elink_phy *phy,
5488 struct elink_params *params)
5489 {
5490 struct bxe_softc *sc = params->sc;
5491 uint16_t val16;
5492 uint32_t lane;
5493 ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d\n",
5494 params->loopback_mode, phy->req_line_speed);
5495
5496 if (phy->req_line_speed < ELINK_SPEED_10000 ||
5497 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5498 /* 10/100/1000/20G-KR2 */
5499
5500 /* Update those 1-copy registers */
5501 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5502 MDIO_AER_BLOCK_AER_REG, 0);
5503 /* Enable 1G MDIO (1-copy) */
5504 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5505 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5506 0x10);
5507 /* Set 1G loopback based on lane (1-copy) */
5508 lane = elink_get_warpcore_lane(phy, params);
5509 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5510 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
5511 val16 |= (1<<lane);
5512 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5513 val16 |= (2<<lane);
5514 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5515 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
5516 val16);
5517
5518 /* Switch back to 4-copy registers */
5519 elink_set_aer_mmd(params, phy);
5520 } else {
5521 /* 10G / 20G-DXGXS */
5522 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5523 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
5524 0x4000);
5525 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5526 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
5527 }
5528 }
5529
5530
5531
elink_sync_link(struct elink_params * params,struct elink_vars * vars)5532 static void elink_sync_link(struct elink_params *params,
5533 struct elink_vars *vars)
5534 {
5535 struct bxe_softc *sc = params->sc;
5536 uint8_t link_10g_plus;
5537 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5538 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
5539 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
5540 if (vars->link_up) {
5541 ELINK_DEBUG_P0(sc, "phy link up\n");
5542 ELINK_DEBUG_P1(sc, "link status = %x\n", vars->link_status);
5543
5544 vars->phy_link_up = 1;
5545 vars->duplex = DUPLEX_FULL;
5546 switch (vars->link_status &
5547 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
5548 case ELINK_LINK_10THD:
5549 vars->duplex = DUPLEX_HALF;
5550 /* Fall thru */
5551 case ELINK_LINK_10TFD:
5552 vars->line_speed = ELINK_SPEED_10;
5553 break;
5554
5555 case ELINK_LINK_100TXHD:
5556 vars->duplex = DUPLEX_HALF;
5557 /* Fall thru */
5558 case ELINK_LINK_100T4:
5559 case ELINK_LINK_100TXFD:
5560 vars->line_speed = ELINK_SPEED_100;
5561 break;
5562
5563 case ELINK_LINK_1000THD:
5564 vars->duplex = DUPLEX_HALF;
5565 /* Fall thru */
5566 case ELINK_LINK_1000TFD:
5567 vars->line_speed = ELINK_SPEED_1000;
5568 break;
5569
5570 case ELINK_LINK_2500THD:
5571 vars->duplex = DUPLEX_HALF;
5572 /* Fall thru */
5573 case ELINK_LINK_2500TFD:
5574 vars->line_speed = ELINK_SPEED_2500;
5575 break;
5576
5577 case ELINK_LINK_10GTFD:
5578 vars->line_speed = ELINK_SPEED_10000;
5579 break;
5580 case ELINK_LINK_20GTFD:
5581 vars->line_speed = ELINK_SPEED_20000;
5582 break;
5583 default:
5584 break;
5585 }
5586 vars->flow_ctrl = 0;
5587 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
5588 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
5589
5590 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
5591 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
5592
5593 if (!vars->flow_ctrl)
5594 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5595
5596 if (vars->line_speed &&
5597 ((vars->line_speed == ELINK_SPEED_10) ||
5598 (vars->line_speed == ELINK_SPEED_100))) {
5599 vars->phy_flags |= PHY_SGMII_FLAG;
5600 } else {
5601 vars->phy_flags &= ~PHY_SGMII_FLAG;
5602 }
5603 if (vars->line_speed &&
5604 USES_WARPCORE(sc) &&
5605 (vars->line_speed == ELINK_SPEED_1000))
5606 vars->phy_flags |= PHY_SGMII_FLAG;
5607 /* Anything 10 and over uses the bmac */
5608 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
5609
5610 if (link_10g_plus) {
5611 if (USES_WARPCORE(sc))
5612 vars->mac_type = ELINK_MAC_TYPE_XMAC;
5613 else
5614 vars->mac_type = ELINK_MAC_TYPE_BMAC;
5615 } else {
5616 if (USES_WARPCORE(sc))
5617 vars->mac_type = ELINK_MAC_TYPE_UMAC;
5618 else
5619 vars->mac_type = ELINK_MAC_TYPE_EMAC;
5620 }
5621 } else { /* Link down */
5622 ELINK_DEBUG_P0(sc, "phy link down\n");
5623
5624 vars->phy_link_up = 0;
5625
5626 vars->line_speed = 0;
5627 vars->duplex = DUPLEX_FULL;
5628 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5629
5630 /* Indicate no mac active */
5631 vars->mac_type = ELINK_MAC_TYPE_NONE;
5632 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5633 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
5634 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
5635 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
5636 }
5637 }
5638
elink_link_status_update(struct elink_params * params,struct elink_vars * vars)5639 void elink_link_status_update(struct elink_params *params,
5640 struct elink_vars *vars)
5641 {
5642 struct bxe_softc *sc = params->sc;
5643 uint8_t port = params->port;
5644 uint32_t sync_offset, media_types;
5645 /* Update PHY configuration */
5646 set_phy_vars(params, vars);
5647
5648 vars->link_status = REG_RD(sc, params->shmem_base +
5649 offsetof(struct shmem_region,
5650 port_mb[port].link_status));
5651
5652 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
5653 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
5654 params->loopback_mode != ELINK_LOOPBACK_EXT)
5655 vars->link_status |= LINK_STATUS_LINK_UP;
5656
5657 if (elink_eee_has_cap(params))
5658 vars->eee_status = REG_RD(sc, params->shmem2_base +
5659 offsetof(struct shmem2_region,
5660 eee_status[params->port]));
5661
5662 vars->phy_flags = PHY_XGXS_FLAG;
5663 elink_sync_link(params, vars);
5664 /* Sync media type */
5665 sync_offset = params->shmem_base +
5666 offsetof(struct shmem_region,
5667 dev_info.port_hw_config[port].media_type);
5668 media_types = REG_RD(sc, sync_offset);
5669
5670 params->phy[ELINK_INT_PHY].media_type =
5671 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
5672 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
5673 params->phy[ELINK_EXT_PHY1].media_type =
5674 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
5675 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
5676 params->phy[ELINK_EXT_PHY2].media_type =
5677 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
5678 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
5679 ELINK_DEBUG_P1(sc, "media_types = 0x%x\n", media_types);
5680
5681 /* Sync AEU offset */
5682 sync_offset = params->shmem_base +
5683 offsetof(struct shmem_region,
5684 dev_info.port_hw_config[port].aeu_int_mask);
5685
5686 vars->aeu_int_mask = REG_RD(sc, sync_offset);
5687
5688 /* Sync PFC status */
5689 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
5690 params->feature_config_flags |=
5691 ELINK_FEATURE_CONFIG_PFC_ENABLED;
5692 else
5693 params->feature_config_flags &=
5694 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
5695
5696 if (SHMEM2_HAS(sc, link_attr_sync))
5697 params->link_attr_sync = SHMEM2_RD(sc,
5698 link_attr_sync[params->port]);
5699
5700 ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
5701 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
5702 ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x\n",
5703 vars->line_speed, vars->duplex, vars->flow_ctrl);
5704 }
5705
elink_set_master_ln(struct elink_params * params,struct elink_phy * phy)5706 static void elink_set_master_ln(struct elink_params *params,
5707 struct elink_phy *phy)
5708 {
5709 struct bxe_softc *sc = params->sc;
5710 uint16_t new_master_ln, ser_lane;
5711 ser_lane = ((params->lane_config &
5712 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5713 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5714
5715 /* Set the master_ln for AN */
5716 CL22_RD_OVER_CL45(sc, phy,
5717 MDIO_REG_BANK_XGXS_BLOCK2,
5718 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5719 &new_master_ln);
5720
5721 CL22_WR_OVER_CL45(sc, phy,
5722 MDIO_REG_BANK_XGXS_BLOCK2 ,
5723 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5724 (new_master_ln | ser_lane));
5725 }
5726
elink_reset_unicore(struct elink_params * params,struct elink_phy * phy,uint8_t set_serdes)5727 static elink_status_t elink_reset_unicore(struct elink_params *params,
5728 struct elink_phy *phy,
5729 uint8_t set_serdes)
5730 {
5731 struct bxe_softc *sc = params->sc;
5732 uint16_t mii_control;
5733 uint16_t i;
5734 CL22_RD_OVER_CL45(sc, phy,
5735 MDIO_REG_BANK_COMBO_IEEE0,
5736 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
5737
5738 /* Reset the unicore */
5739 CL22_WR_OVER_CL45(sc, phy,
5740 MDIO_REG_BANK_COMBO_IEEE0,
5741 MDIO_COMBO_IEEE0_MII_CONTROL,
5742 (mii_control |
5743 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
5744 if (set_serdes)
5745 elink_set_serdes_access(sc, params->port);
5746
5747 /* Wait for the reset to self clear */
5748 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
5749 DELAY(5);
5750
5751 /* The reset erased the previous bank value */
5752 CL22_RD_OVER_CL45(sc, phy,
5753 MDIO_REG_BANK_COMBO_IEEE0,
5754 MDIO_COMBO_IEEE0_MII_CONTROL,
5755 &mii_control);
5756
5757 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
5758 DELAY(5);
5759 return ELINK_STATUS_OK;
5760 }
5761 }
5762
5763 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5764 // " Port %d\n",
5765
5766 ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!\n");
5767 return ELINK_STATUS_ERROR;
5768
5769 }
5770
elink_set_swap_lanes(struct elink_params * params,struct elink_phy * phy)5771 static void elink_set_swap_lanes(struct elink_params *params,
5772 struct elink_phy *phy)
5773 {
5774 struct bxe_softc *sc = params->sc;
5775 /* Each two bits represents a lane number:
5776 * No swap is 0123 => 0x1b no need to enable the swap
5777 */
5778 uint16_t rx_lane_swap, tx_lane_swap;
5779
5780 rx_lane_swap = ((params->lane_config &
5781 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
5782 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
5783 tx_lane_swap = ((params->lane_config &
5784 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
5785 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
5786
5787 if (rx_lane_swap != 0x1b) {
5788 CL22_WR_OVER_CL45(sc, phy,
5789 MDIO_REG_BANK_XGXS_BLOCK2,
5790 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
5791 (rx_lane_swap |
5792 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
5793 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
5794 } else {
5795 CL22_WR_OVER_CL45(sc, phy,
5796 MDIO_REG_BANK_XGXS_BLOCK2,
5797 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
5798 }
5799
5800 if (tx_lane_swap != 0x1b) {
5801 CL22_WR_OVER_CL45(sc, phy,
5802 MDIO_REG_BANK_XGXS_BLOCK2,
5803 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
5804 (tx_lane_swap |
5805 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
5806 } else {
5807 CL22_WR_OVER_CL45(sc, phy,
5808 MDIO_REG_BANK_XGXS_BLOCK2,
5809 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
5810 }
5811 }
5812
elink_set_parallel_detection(struct elink_phy * phy,struct elink_params * params)5813 static void elink_set_parallel_detection(struct elink_phy *phy,
5814 struct elink_params *params)
5815 {
5816 struct bxe_softc *sc = params->sc;
5817 uint16_t control2;
5818 CL22_RD_OVER_CL45(sc, phy,
5819 MDIO_REG_BANK_SERDES_DIGITAL,
5820 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5821 &control2);
5822 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5823 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5824 else
5825 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5826 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5827 phy->speed_cap_mask, control2);
5828 CL22_WR_OVER_CL45(sc, phy,
5829 MDIO_REG_BANK_SERDES_DIGITAL,
5830 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5831 control2);
5832
5833 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5834 (phy->speed_cap_mask &
5835 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5836 ELINK_DEBUG_P0(sc, "XGXS\n");
5837
5838 CL22_WR_OVER_CL45(sc, phy,
5839 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5840 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5841 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5842
5843 CL22_RD_OVER_CL45(sc, phy,
5844 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5845 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5846 &control2);
5847
5848
5849 control2 |=
5850 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5851
5852 CL22_WR_OVER_CL45(sc, phy,
5853 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5854 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5855 control2);
5856
5857 /* Disable parallel detection of HiG */
5858 CL22_WR_OVER_CL45(sc, phy,
5859 MDIO_REG_BANK_XGXS_BLOCK2,
5860 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5861 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5862 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5863 }
5864 }
5865
elink_set_autoneg(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars,uint8_t enable_cl73)5866 static void elink_set_autoneg(struct elink_phy *phy,
5867 struct elink_params *params,
5868 struct elink_vars *vars,
5869 uint8_t enable_cl73)
5870 {
5871 struct bxe_softc *sc = params->sc;
5872 uint16_t reg_val;
5873
5874 /* CL37 Autoneg */
5875 CL22_RD_OVER_CL45(sc, phy,
5876 MDIO_REG_BANK_COMBO_IEEE0,
5877 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5878
5879 /* CL37 Autoneg Enabled */
5880 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5881 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5882 else /* CL37 Autoneg Disabled */
5883 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5884 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5885
5886 CL22_WR_OVER_CL45(sc, phy,
5887 MDIO_REG_BANK_COMBO_IEEE0,
5888 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5889
5890 /* Enable/Disable Autodetection */
5891
5892 CL22_RD_OVER_CL45(sc, phy,
5893 MDIO_REG_BANK_SERDES_DIGITAL,
5894 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5895 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5896 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5897 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5898 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5899 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5900 else
5901 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5902
5903 CL22_WR_OVER_CL45(sc, phy,
5904 MDIO_REG_BANK_SERDES_DIGITAL,
5905 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5906
5907 /* Enable TetonII and BAM autoneg */
5908 CL22_RD_OVER_CL45(sc, phy,
5909 MDIO_REG_BANK_BAM_NEXT_PAGE,
5910 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5911 ®_val);
5912 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
5913 /* Enable BAM aneg Mode and TetonII aneg Mode */
5914 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5915 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5916 } else {
5917 /* TetonII and BAM Autoneg Disabled */
5918 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5919 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5920 }
5921 CL22_WR_OVER_CL45(sc, phy,
5922 MDIO_REG_BANK_BAM_NEXT_PAGE,
5923 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5924 reg_val);
5925
5926 if (enable_cl73) {
5927 /* Enable Cl73 FSM status bits */
5928 CL22_WR_OVER_CL45(sc, phy,
5929 MDIO_REG_BANK_CL73_USERB0,
5930 MDIO_CL73_USERB0_CL73_UCTRL,
5931 0xe);
5932
5933 /* Enable BAM Station Manager*/
5934 CL22_WR_OVER_CL45(sc, phy,
5935 MDIO_REG_BANK_CL73_USERB0,
5936 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5937 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5938 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5939 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5940
5941 /* Advertise CL73 link speeds */
5942 CL22_RD_OVER_CL45(sc, phy,
5943 MDIO_REG_BANK_CL73_IEEEB1,
5944 MDIO_CL73_IEEEB1_AN_ADV2,
5945 ®_val);
5946 if (phy->speed_cap_mask &
5947 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5948 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5949 if (phy->speed_cap_mask &
5950 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5951 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5952
5953 CL22_WR_OVER_CL45(sc, phy,
5954 MDIO_REG_BANK_CL73_IEEEB1,
5955 MDIO_CL73_IEEEB1_AN_ADV2,
5956 reg_val);
5957
5958 /* CL73 Autoneg Enabled */
5959 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5960
5961 } else /* CL73 Autoneg Disabled */
5962 reg_val = 0;
5963
5964 CL22_WR_OVER_CL45(sc, phy,
5965 MDIO_REG_BANK_CL73_IEEEB0,
5966 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5967 }
5968
5969 /* Program SerDes, forced speed */
elink_program_serdes(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)5970 static void elink_program_serdes(struct elink_phy *phy,
5971 struct elink_params *params,
5972 struct elink_vars *vars)
5973 {
5974 struct bxe_softc *sc = params->sc;
5975 uint16_t reg_val;
5976
5977 /* Program duplex, disable autoneg and sgmii*/
5978 CL22_RD_OVER_CL45(sc, phy,
5979 MDIO_REG_BANK_COMBO_IEEE0,
5980 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5981 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5982 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5983 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5984 if (phy->req_duplex == DUPLEX_FULL)
5985 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5986 CL22_WR_OVER_CL45(sc, phy,
5987 MDIO_REG_BANK_COMBO_IEEE0,
5988 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5989
5990 /* Program speed
5991 * - needed only if the speed is greater than 1G (2.5G or 10G)
5992 */
5993 CL22_RD_OVER_CL45(sc, phy,
5994 MDIO_REG_BANK_SERDES_DIGITAL,
5995 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5996 /* Clearing the speed value before setting the right speed */
5997 ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5998
5999 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
6000 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
6001
6002 if (!((vars->line_speed == ELINK_SPEED_1000) ||
6003 (vars->line_speed == ELINK_SPEED_100) ||
6004 (vars->line_speed == ELINK_SPEED_10))) {
6005
6006 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
6007 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
6008 if (vars->line_speed == ELINK_SPEED_10000)
6009 reg_val |=
6010 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
6011 }
6012
6013 CL22_WR_OVER_CL45(sc, phy,
6014 MDIO_REG_BANK_SERDES_DIGITAL,
6015 MDIO_SERDES_DIGITAL_MISC1, reg_val);
6016
6017 }
6018
elink_set_brcm_cl37_advertisement(struct elink_phy * phy,struct elink_params * params)6019 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
6020 struct elink_params *params)
6021 {
6022 struct bxe_softc *sc = params->sc;
6023 uint16_t val = 0;
6024
6025 /* Set extended capabilities */
6026 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
6027 val |= MDIO_OVER_1G_UP1_2_5G;
6028 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6029 val |= MDIO_OVER_1G_UP1_10G;
6030 CL22_WR_OVER_CL45(sc, phy,
6031 MDIO_REG_BANK_OVER_1G,
6032 MDIO_OVER_1G_UP1, val);
6033
6034 CL22_WR_OVER_CL45(sc, phy,
6035 MDIO_REG_BANK_OVER_1G,
6036 MDIO_OVER_1G_UP3, 0x400);
6037 }
6038
elink_set_ieee_aneg_advertisement(struct elink_phy * phy,struct elink_params * params,uint16_t ieee_fc)6039 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
6040 struct elink_params *params,
6041 uint16_t ieee_fc)
6042 {
6043 struct bxe_softc *sc = params->sc;
6044 uint16_t val;
6045 /* For AN, we are always publishing full duplex */
6046
6047 CL22_WR_OVER_CL45(sc, phy,
6048 MDIO_REG_BANK_COMBO_IEEE0,
6049 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
6050 CL22_RD_OVER_CL45(sc, phy,
6051 MDIO_REG_BANK_CL73_IEEEB1,
6052 MDIO_CL73_IEEEB1_AN_ADV1, &val);
6053 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
6054 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
6055 CL22_WR_OVER_CL45(sc, phy,
6056 MDIO_REG_BANK_CL73_IEEEB1,
6057 MDIO_CL73_IEEEB1_AN_ADV1, val);
6058 }
6059
elink_restart_autoneg(struct elink_phy * phy,struct elink_params * params,uint8_t enable_cl73)6060 static void elink_restart_autoneg(struct elink_phy *phy,
6061 struct elink_params *params,
6062 uint8_t enable_cl73)
6063 {
6064 struct bxe_softc *sc = params->sc;
6065 uint16_t mii_control;
6066
6067 ELINK_DEBUG_P0(sc, "elink_restart_autoneg\n");
6068 /* Enable and restart BAM/CL37 aneg */
6069
6070 if (enable_cl73) {
6071 CL22_RD_OVER_CL45(sc, phy,
6072 MDIO_REG_BANK_CL73_IEEEB0,
6073 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6074 &mii_control);
6075
6076 CL22_WR_OVER_CL45(sc, phy,
6077 MDIO_REG_BANK_CL73_IEEEB0,
6078 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6079 (mii_control |
6080 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
6081 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
6082 } else {
6083
6084 CL22_RD_OVER_CL45(sc, phy,
6085 MDIO_REG_BANK_COMBO_IEEE0,
6086 MDIO_COMBO_IEEE0_MII_CONTROL,
6087 &mii_control);
6088 ELINK_DEBUG_P1(sc,
6089 "elink_restart_autoneg mii_control before = 0x%x\n",
6090 mii_control);
6091 CL22_WR_OVER_CL45(sc, phy,
6092 MDIO_REG_BANK_COMBO_IEEE0,
6093 MDIO_COMBO_IEEE0_MII_CONTROL,
6094 (mii_control |
6095 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6096 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
6097 }
6098 }
6099
elink_initialize_sgmii_process(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)6100 static void elink_initialize_sgmii_process(struct elink_phy *phy,
6101 struct elink_params *params,
6102 struct elink_vars *vars)
6103 {
6104 struct bxe_softc *sc = params->sc;
6105 uint16_t control1;
6106
6107 /* In SGMII mode, the unicore is always slave */
6108
6109 CL22_RD_OVER_CL45(sc, phy,
6110 MDIO_REG_BANK_SERDES_DIGITAL,
6111 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6112 &control1);
6113 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
6114 /* Set sgmii mode (and not fiber) */
6115 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
6116 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
6117 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
6118 CL22_WR_OVER_CL45(sc, phy,
6119 MDIO_REG_BANK_SERDES_DIGITAL,
6120 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6121 control1);
6122
6123 /* If forced speed */
6124 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
6125 /* Set speed, disable autoneg */
6126 uint16_t mii_control;
6127
6128 CL22_RD_OVER_CL45(sc, phy,
6129 MDIO_REG_BANK_COMBO_IEEE0,
6130 MDIO_COMBO_IEEE0_MII_CONTROL,
6131 &mii_control);
6132 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6133 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
6134 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
6135
6136 switch (vars->line_speed) {
6137 case ELINK_SPEED_100:
6138 mii_control |=
6139 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
6140 break;
6141 case ELINK_SPEED_1000:
6142 mii_control |=
6143 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
6144 break;
6145 case ELINK_SPEED_10:
6146 /* There is nothing to set for 10M */
6147 break;
6148 default:
6149 /* Invalid speed for SGMII */
6150 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6151 vars->line_speed);
6152 break;
6153 }
6154
6155 /* Setting the full duplex */
6156 if (phy->req_duplex == DUPLEX_FULL)
6157 mii_control |=
6158 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
6159 CL22_WR_OVER_CL45(sc, phy,
6160 MDIO_REG_BANK_COMBO_IEEE0,
6161 MDIO_COMBO_IEEE0_MII_CONTROL,
6162 mii_control);
6163
6164 } else { /* AN mode */
6165 /* Enable and restart AN */
6166 elink_restart_autoneg(phy, params, 0);
6167 }
6168 }
6169
6170 /* Link management
6171 */
elink_direct_parallel_detect_used(struct elink_phy * phy,struct elink_params * params)6172 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
6173 struct elink_params *params)
6174 {
6175 struct bxe_softc *sc = params->sc;
6176 uint16_t pd_10g, status2_1000x;
6177 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6178 return ELINK_STATUS_OK;
6179 CL22_RD_OVER_CL45(sc, phy,
6180 MDIO_REG_BANK_SERDES_DIGITAL,
6181 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6182 &status2_1000x);
6183 CL22_RD_OVER_CL45(sc, phy,
6184 MDIO_REG_BANK_SERDES_DIGITAL,
6185 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6186 &status2_1000x);
6187 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
6188 ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d\n",
6189 params->port);
6190 return 1;
6191 }
6192
6193 CL22_RD_OVER_CL45(sc, phy,
6194 MDIO_REG_BANK_10G_PARALLEL_DETECT,
6195 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
6196 &pd_10g);
6197
6198 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
6199 ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d\n",
6200 params->port);
6201 return 1;
6202 }
6203 return ELINK_STATUS_OK;
6204 }
6205
elink_update_adv_fc(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars,uint32_t gp_status)6206 static void elink_update_adv_fc(struct elink_phy *phy,
6207 struct elink_params *params,
6208 struct elink_vars *vars,
6209 uint32_t gp_status)
6210 {
6211 uint16_t ld_pause; /* local driver */
6212 uint16_t lp_pause; /* link partner */
6213 uint16_t pause_result;
6214 struct bxe_softc *sc = params->sc;
6215 if ((gp_status &
6216 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6217 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
6218 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6219 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
6220
6221 CL22_RD_OVER_CL45(sc, phy,
6222 MDIO_REG_BANK_CL73_IEEEB1,
6223 MDIO_CL73_IEEEB1_AN_ADV1,
6224 &ld_pause);
6225 CL22_RD_OVER_CL45(sc, phy,
6226 MDIO_REG_BANK_CL73_IEEEB1,
6227 MDIO_CL73_IEEEB1_AN_LP_ADV1,
6228 &lp_pause);
6229 pause_result = (ld_pause &
6230 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
6231 pause_result |= (lp_pause &
6232 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
6233 ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x\n", pause_result);
6234 } else {
6235 CL22_RD_OVER_CL45(sc, phy,
6236 MDIO_REG_BANK_COMBO_IEEE0,
6237 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
6238 &ld_pause);
6239 CL22_RD_OVER_CL45(sc, phy,
6240 MDIO_REG_BANK_COMBO_IEEE0,
6241 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
6242 &lp_pause);
6243 pause_result = (ld_pause &
6244 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
6245 pause_result |= (lp_pause &
6246 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
6247 ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x\n", pause_result);
6248 }
6249 elink_pause_resolve(phy, params, vars, pause_result);
6250
6251 }
6252
elink_flow_ctrl_resolve(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars,uint32_t gp_status)6253 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
6254 struct elink_params *params,
6255 struct elink_vars *vars,
6256 uint32_t gp_status)
6257 {
6258 struct bxe_softc *sc = params->sc;
6259 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6260
6261 /* Resolve from gp_status in case of AN complete and not sgmii */
6262 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
6263 /* Update the advertised flow-controlled of LD/LP in AN */
6264 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6265 elink_update_adv_fc(phy, params, vars, gp_status);
6266 /* But set the flow-control result as the requested one */
6267 vars->flow_ctrl = phy->req_flow_ctrl;
6268 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6269 vars->flow_ctrl = params->req_fc_auto_adv;
6270 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
6271 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
6272 if (elink_direct_parallel_detect_used(phy, params)) {
6273 vars->flow_ctrl = params->req_fc_auto_adv;
6274 return;
6275 }
6276 elink_update_adv_fc(phy, params, vars, gp_status);
6277 }
6278 ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl);
6279 }
6280
elink_check_fallback_to_cl37(struct elink_phy * phy,struct elink_params * params)6281 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
6282 struct elink_params *params)
6283 {
6284 struct bxe_softc *sc = params->sc;
6285 uint16_t rx_status, ustat_val, cl37_fsm_received;
6286 ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37\n");
6287 /* Step 1: Make sure signal is detected */
6288 CL22_RD_OVER_CL45(sc, phy,
6289 MDIO_REG_BANK_RX0,
6290 MDIO_RX0_RX_STATUS,
6291 &rx_status);
6292 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
6293 (MDIO_RX0_RX_STATUS_SIGDET)) {
6294 ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73."
6295 "rx_status(0x80b0) = 0x%x\n", rx_status);
6296 CL22_WR_OVER_CL45(sc, phy,
6297 MDIO_REG_BANK_CL73_IEEEB0,
6298 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6299 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
6300 return;
6301 }
6302 /* Step 2: Check CL73 state machine */
6303 CL22_RD_OVER_CL45(sc, phy,
6304 MDIO_REG_BANK_CL73_USERB0,
6305 MDIO_CL73_USERB0_CL73_USTAT1,
6306 &ustat_val);
6307 if ((ustat_val &
6308 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6309 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
6310 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6311 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
6312 ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. "
6313 "ustat_val(0x8371) = 0x%x\n", ustat_val);
6314 return;
6315 }
6316 /* Step 3: Check CL37 Message Pages received to indicate LP
6317 * supports only CL37
6318 */
6319 CL22_RD_OVER_CL45(sc, phy,
6320 MDIO_REG_BANK_REMOTE_PHY,
6321 MDIO_REMOTE_PHY_MISC_RX_STATUS,
6322 &cl37_fsm_received);
6323 if ((cl37_fsm_received &
6324 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6325 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
6326 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6327 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
6328 ELINK_DEBUG_P1(sc, "No CL37 FSM were received. "
6329 "misc_rx_status(0x8330) = 0x%x\n",
6330 cl37_fsm_received);
6331 return;
6332 }
6333 /* The combined cl37/cl73 fsm state information indicating that
6334 * we are connected to a device which does not support cl73, but
6335 * does support cl37 BAM. In this case we disable cl73 and
6336 * restart cl37 auto-neg
6337 */
6338
6339 /* Disable CL73 */
6340 CL22_WR_OVER_CL45(sc, phy,
6341 MDIO_REG_BANK_CL73_IEEEB0,
6342 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6343 0);
6344 /* Restart CL37 autoneg */
6345 elink_restart_autoneg(phy, params, 0);
6346 ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg\n");
6347 }
6348
elink_xgxs_an_resolve(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars,uint32_t gp_status)6349 static void elink_xgxs_an_resolve(struct elink_phy *phy,
6350 struct elink_params *params,
6351 struct elink_vars *vars,
6352 uint32_t gp_status)
6353 {
6354 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
6355 vars->link_status |=
6356 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6357
6358 if (elink_direct_parallel_detect_used(phy, params))
6359 vars->link_status |=
6360 LINK_STATUS_PARALLEL_DETECTION_USED;
6361 }
elink_get_link_speed_duplex(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars,uint16_t is_link_up,uint16_t speed_mask,uint16_t is_duplex)6362 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
6363 struct elink_params *params,
6364 struct elink_vars *vars,
6365 uint16_t is_link_up,
6366 uint16_t speed_mask,
6367 uint16_t is_duplex)
6368 {
6369 struct bxe_softc *sc = params->sc;
6370 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6371 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
6372 if (is_link_up) {
6373 ELINK_DEBUG_P0(sc, "phy link up\n");
6374
6375 vars->phy_link_up = 1;
6376 vars->link_status |= LINK_STATUS_LINK_UP;
6377
6378 switch (speed_mask) {
6379 case ELINK_GP_STATUS_10M:
6380 vars->line_speed = ELINK_SPEED_10;
6381 if (is_duplex == DUPLEX_FULL)
6382 vars->link_status |= ELINK_LINK_10TFD;
6383 else
6384 vars->link_status |= ELINK_LINK_10THD;
6385 break;
6386
6387 case ELINK_GP_STATUS_100M:
6388 vars->line_speed = ELINK_SPEED_100;
6389 if (is_duplex == DUPLEX_FULL)
6390 vars->link_status |= ELINK_LINK_100TXFD;
6391 else
6392 vars->link_status |= ELINK_LINK_100TXHD;
6393 break;
6394
6395 case ELINK_GP_STATUS_1G:
6396 case ELINK_GP_STATUS_1G_KX:
6397 vars->line_speed = ELINK_SPEED_1000;
6398 if (is_duplex == DUPLEX_FULL)
6399 vars->link_status |= ELINK_LINK_1000TFD;
6400 else
6401 vars->link_status |= ELINK_LINK_1000THD;
6402 break;
6403
6404 case ELINK_GP_STATUS_2_5G:
6405 vars->line_speed = ELINK_SPEED_2500;
6406 if (is_duplex == DUPLEX_FULL)
6407 vars->link_status |= ELINK_LINK_2500TFD;
6408 else
6409 vars->link_status |= ELINK_LINK_2500THD;
6410 break;
6411
6412 case ELINK_GP_STATUS_5G:
6413 case ELINK_GP_STATUS_6G:
6414 ELINK_DEBUG_P1(sc,
6415 "link speed unsupported gp_status 0x%x\n",
6416 speed_mask);
6417 return ELINK_STATUS_ERROR;
6418
6419 case ELINK_GP_STATUS_10G_KX4:
6420 case ELINK_GP_STATUS_10G_HIG:
6421 case ELINK_GP_STATUS_10G_CX4:
6422 case ELINK_GP_STATUS_10G_KR:
6423 case ELINK_GP_STATUS_10G_SFI:
6424 case ELINK_GP_STATUS_10G_XFI:
6425 vars->line_speed = ELINK_SPEED_10000;
6426 vars->link_status |= ELINK_LINK_10GTFD;
6427 break;
6428 case ELINK_GP_STATUS_20G_DXGXS:
6429 case ELINK_GP_STATUS_20G_KR2:
6430 vars->line_speed = ELINK_SPEED_20000;
6431 vars->link_status |= ELINK_LINK_20GTFD;
6432 break;
6433 default:
6434 ELINK_DEBUG_P1(sc,
6435 "link speed unsupported gp_status 0x%x\n",
6436 speed_mask);
6437 return ELINK_STATUS_ERROR;
6438 }
6439 } else { /* link_down */
6440 ELINK_DEBUG_P0(sc, "phy link down\n");
6441
6442 vars->phy_link_up = 0;
6443
6444 vars->duplex = DUPLEX_FULL;
6445 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6446 vars->mac_type = ELINK_MAC_TYPE_NONE;
6447 }
6448 ELINK_DEBUG_P2(sc, " in elink_get_link_speed_duplex vars->link_status = %x, vars->duplex = %x\n",
6449 vars->link_status, vars->duplex);
6450 ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d\n",
6451 vars->phy_link_up, vars->line_speed);
6452 return ELINK_STATUS_OK;
6453 }
6454
elink_link_settings_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)6455 static elink_status_t elink_link_settings_status(struct elink_phy *phy,
6456 struct elink_params *params,
6457 struct elink_vars *vars)
6458 {
6459 struct bxe_softc *sc = params->sc;
6460
6461 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
6462 elink_status_t rc = ELINK_STATUS_OK;
6463
6464 /* Read gp_status */
6465 CL22_RD_OVER_CL45(sc, phy,
6466 MDIO_REG_BANK_GP_STATUS,
6467 MDIO_GP_STATUS_TOP_AN_STATUS1,
6468 &gp_status);
6469 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) {
6470 duplex = DUPLEX_FULL;
6471 ELINK_DEBUG_P1(sc, "duplex status read from phy is = %x\n",
6472 duplex);
6473 } else {
6474 ELINK_DEBUG_P1(sc, "phy status does not allow interface to be FULL_DUPLEX : %x\n",
6475 gp_status);
6476 }
6477
6478
6479 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
6480 link_up = 1;
6481 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
6482 ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
6483 gp_status, link_up, speed_mask);
6484 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
6485 duplex);
6486 if (rc == ELINK_STATUS_ERROR)
6487 return rc;
6488
6489 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
6490 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
6491 vars->duplex = duplex;
6492 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
6493 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6494 elink_xgxs_an_resolve(phy, params, vars,
6495 gp_status);
6496 }
6497 } else { /* Link_down */
6498 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
6499 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6500 /* Check signal is detected */
6501 elink_check_fallback_to_cl37(phy, params);
6502 }
6503 }
6504
6505 /* Read LP advertised speeds*/
6506 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6507 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
6508 uint16_t val;
6509
6510 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
6511 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
6512
6513 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6514 vars->link_status |=
6515 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6516 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6517 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6518 vars->link_status |=
6519 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6520
6521 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
6522 MDIO_OVER_1G_LP_UP1, &val);
6523
6524 if (val & MDIO_OVER_1G_UP1_2_5G)
6525 vars->link_status |=
6526 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6527 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6528 vars->link_status |=
6529 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6530 }
6531
6532 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6533 vars->duplex, vars->flow_ctrl, vars->link_status);
6534 return rc;
6535 }
6536
elink_warpcore_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)6537 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
6538 struct elink_params *params,
6539 struct elink_vars *vars)
6540 {
6541 struct bxe_softc *sc = params->sc;
6542 uint8_t lane;
6543 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
6544 elink_status_t rc = ELINK_STATUS_OK;
6545 lane = elink_get_warpcore_lane(phy, params);
6546 /* Read gp_status */
6547 if ((params->loopback_mode) &&
6548 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
6549 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6550 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6551 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6552 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6553 link_up &= 0x1;
6554 ELINK_DEBUG_P1(sc, "params->loopback_mode link_up read = %x\n",
6555 link_up);
6556 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
6557 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
6558 uint16_t temp_link_up;
6559 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6560 1, &temp_link_up);
6561 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6562 1, &link_up);
6563 ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n",
6564 temp_link_up, link_up);
6565 link_up &= (1<<2);
6566 if (link_up)
6567 elink_ext_phy_resolve_fc(phy, params, vars);
6568 } else {
6569 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6570 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6571 &gp_status1);
6572 ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x\n", gp_status1);
6573 /* Check for either KR, 1G, or AN up. */
6574 link_up = ((gp_status1 >> 8) |
6575 (gp_status1 >> 12) |
6576 (gp_status1)) &
6577 (1 << lane);
6578 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
6579 uint16_t an_link;
6580 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6581 MDIO_AN_REG_STATUS, &an_link);
6582 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6583 MDIO_AN_REG_STATUS, &an_link);
6584 link_up |= (an_link & (1<<2));
6585 ELINK_DEBUG_P2(sc,"an_link = %x, link_up = %x\n", an_link,
6586 link_up);
6587 }
6588 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
6589 uint16_t pd, gp_status4;
6590 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
6591 /* Check Autoneg complete */
6592 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6593 MDIO_WC_REG_GP2_STATUS_GP_2_4,
6594 &gp_status4);
6595 if (gp_status4 & ((1<<12)<<lane))
6596 vars->link_status |=
6597 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6598
6599 /* Check parallel detect used */
6600 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6601 MDIO_WC_REG_PAR_DET_10G_STATUS,
6602 &pd);
6603 if (pd & (1<<15))
6604 vars->link_status |=
6605 LINK_STATUS_PARALLEL_DETECTION_USED;
6606 ELINK_DEBUG_P2(sc, "pd = %x, link_status = %x\n",
6607 pd, vars->link_status);
6608 }
6609 elink_ext_phy_resolve_fc(phy, params, vars);
6610 vars->duplex = duplex;
6611 ELINK_DEBUG_P3(sc, " ELINK_SINGLE_MEDIA_DIRECT duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6612 vars->duplex, vars->flow_ctrl, vars->link_status);
6613 }
6614 }
6615 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6616 vars->duplex, vars->flow_ctrl, vars->link_status);
6617 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
6618 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6619 uint16_t val;
6620
6621 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6622 MDIO_AN_REG_LP_AUTO_NEG2, &val);
6623
6624 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6625 vars->link_status |=
6626 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6627 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6628 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6629 vars->link_status |=
6630 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6631 ELINK_DEBUG_P2(sc, "val = %x, link_status = %x\n",
6632 val, vars->link_status);
6633 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6634 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
6635
6636 if (val & MDIO_OVER_1G_UP1_2_5G)
6637 vars->link_status |=
6638 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6639 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6640 vars->link_status |=
6641 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6642 ELINK_DEBUG_P2(sc, "val = %x, link_status = %x\n",
6643 val, vars->link_status);
6644
6645 }
6646
6647
6648 if (lane < 2) {
6649 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6650 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
6651 } else {
6652 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6653 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
6654 }
6655 ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed);
6656
6657 if ((lane & 1) == 0)
6658 gp_speed <<= 8;
6659 gp_speed &= 0x3f00;
6660 link_up = !!link_up;
6661
6662 /* Reset the TX FIFO to fix SGMII issue */
6663 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
6664 duplex);
6665
6666 /* In case of KR link down, start up the recovering procedure */
6667 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
6668 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
6669 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
6670
6671 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6672 vars->duplex, vars->flow_ctrl, vars->link_status);
6673 return rc;
6674 }
elink_set_gmii_tx_driver(struct elink_params * params)6675 static void elink_set_gmii_tx_driver(struct elink_params *params)
6676 {
6677 struct bxe_softc *sc = params->sc;
6678 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6679 uint16_t lp_up2;
6680 uint16_t tx_driver;
6681 uint16_t bank;
6682
6683 /* Read precomp */
6684 CL22_RD_OVER_CL45(sc, phy,
6685 MDIO_REG_BANK_OVER_1G,
6686 MDIO_OVER_1G_LP_UP2, &lp_up2);
6687
6688 /* Bits [10:7] at lp_up2, positioned at [15:12] */
6689 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
6690 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
6691 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
6692
6693 if (lp_up2 == 0)
6694 return;
6695
6696 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
6697 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
6698 CL22_RD_OVER_CL45(sc, phy,
6699 bank,
6700 MDIO_TX0_TX_DRIVER, &tx_driver);
6701
6702 /* Replace tx_driver bits [15:12] */
6703 if (lp_up2 !=
6704 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
6705 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
6706 tx_driver |= lp_up2;
6707 CL22_WR_OVER_CL45(sc, phy,
6708 bank,
6709 MDIO_TX0_TX_DRIVER, tx_driver);
6710 }
6711 }
6712 }
6713
elink_emac_program(struct elink_params * params,struct elink_vars * vars)6714 static elink_status_t elink_emac_program(struct elink_params *params,
6715 struct elink_vars *vars)
6716 {
6717 struct bxe_softc *sc = params->sc;
6718 uint8_t port = params->port;
6719 uint16_t mode = 0;
6720
6721 ELINK_DEBUG_P0(sc, "setting link speed & duplex\n");
6722 elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 +
6723 EMAC_REG_EMAC_MODE,
6724 (EMAC_MODE_25G_MODE |
6725 EMAC_MODE_PORT_MII_10M |
6726 EMAC_MODE_HALF_DUPLEX));
6727 switch (vars->line_speed) {
6728 case ELINK_SPEED_10:
6729 mode |= EMAC_MODE_PORT_MII_10M;
6730 break;
6731
6732 case ELINK_SPEED_100:
6733 mode |= EMAC_MODE_PORT_MII;
6734 break;
6735
6736 case ELINK_SPEED_1000:
6737 mode |= EMAC_MODE_PORT_GMII;
6738 break;
6739
6740 case ELINK_SPEED_2500:
6741 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
6742 break;
6743
6744 default:
6745 /* 10G not valid for EMAC */
6746 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6747 vars->line_speed);
6748 return ELINK_STATUS_ERROR;
6749 }
6750
6751 if (vars->duplex == DUPLEX_HALF)
6752 mode |= EMAC_MODE_HALF_DUPLEX;
6753 elink_bits_en(sc,
6754 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
6755 mode);
6756
6757 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
6758 return ELINK_STATUS_OK;
6759 }
6760
elink_set_preemphasis(struct elink_phy * phy,struct elink_params * params)6761 static void elink_set_preemphasis(struct elink_phy *phy,
6762 struct elink_params *params)
6763 {
6764
6765 uint16_t bank, i = 0;
6766 struct bxe_softc *sc = params->sc;
6767
6768 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
6769 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
6770 CL22_WR_OVER_CL45(sc, phy,
6771 bank,
6772 MDIO_RX0_RX_EQ_BOOST,
6773 phy->rx_preemphasis[i]);
6774 }
6775
6776 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
6777 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
6778 CL22_WR_OVER_CL45(sc, phy,
6779 bank,
6780 MDIO_TX0_TX_DRIVER,
6781 phy->tx_preemphasis[i]);
6782 }
6783 }
6784
elink_xgxs_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)6785 static void elink_xgxs_config_init(struct elink_phy *phy,
6786 struct elink_params *params,
6787 struct elink_vars *vars)
6788 {
6789 struct bxe_softc *sc = params->sc;
6790 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6791 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6792 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
6793 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6794 (params->feature_config_flags &
6795 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
6796 elink_set_preemphasis(phy, params);
6797
6798 /* Forced speed requested? */
6799 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
6800 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6801 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
6802 ELINK_DEBUG_P0(sc, "not SGMII, no AN\n");
6803
6804 /* Disable autoneg */
6805 elink_set_autoneg(phy, params, vars, 0);
6806
6807 /* Program speed and duplex */
6808 elink_program_serdes(phy, params, vars);
6809
6810 } else { /* AN_mode */
6811 ELINK_DEBUG_P0(sc, "not SGMII, AN\n");
6812
6813 /* AN enabled */
6814 elink_set_brcm_cl37_advertisement(phy, params);
6815
6816 /* Program duplex & pause advertisement (for aneg) */
6817 elink_set_ieee_aneg_advertisement(phy, params,
6818 vars->ieee_fc);
6819
6820 /* Enable autoneg */
6821 elink_set_autoneg(phy, params, vars, enable_cl73);
6822
6823 /* Enable and restart AN */
6824 elink_restart_autoneg(phy, params, enable_cl73);
6825 }
6826
6827 } else { /* SGMII mode */
6828 ELINK_DEBUG_P0(sc, "SGMII\n");
6829
6830 elink_initialize_sgmii_process(phy, params, vars);
6831 }
6832 }
6833
elink_prepare_xgxs(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)6834 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
6835 struct elink_params *params,
6836 struct elink_vars *vars)
6837 {
6838 elink_status_t rc;
6839 vars->phy_flags |= PHY_XGXS_FLAG;
6840 if ((phy->req_line_speed &&
6841 ((phy->req_line_speed == ELINK_SPEED_100) ||
6842 (phy->req_line_speed == ELINK_SPEED_10))) ||
6843 (!phy->req_line_speed &&
6844 (phy->speed_cap_mask >=
6845 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
6846 (phy->speed_cap_mask <
6847 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6848 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
6849 vars->phy_flags |= PHY_SGMII_FLAG;
6850 else
6851 vars->phy_flags &= ~PHY_SGMII_FLAG;
6852
6853 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6854 elink_set_aer_mmd(params, phy);
6855 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6856 elink_set_master_ln(params, phy);
6857
6858 rc = elink_reset_unicore(params, phy, 0);
6859 /* Reset the SerDes and wait for reset bit return low */
6860 if (rc != ELINK_STATUS_OK)
6861 return rc;
6862
6863 elink_set_aer_mmd(params, phy);
6864 /* Setting the masterLn_def again after the reset */
6865 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6866 elink_set_master_ln(params, phy);
6867 elink_set_swap_lanes(params, phy);
6868 }
6869
6870 return rc;
6871 }
6872
elink_wait_reset_complete(struct bxe_softc * sc,struct elink_phy * phy,struct elink_params * params)6873 static uint16_t elink_wait_reset_complete(struct bxe_softc *sc,
6874 struct elink_phy *phy,
6875 struct elink_params *params)
6876 {
6877 uint16_t cnt, ctrl;
6878 /* Wait for soft reset to get cleared up to 1 sec */
6879 for (cnt = 0; cnt < 1000; cnt++) {
6880 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6881 elink_cl22_read(sc, phy,
6882 MDIO_PMA_REG_CTRL, &ctrl);
6883 else
6884 elink_cl45_read(sc, phy,
6885 MDIO_PMA_DEVAD,
6886 MDIO_PMA_REG_CTRL, &ctrl);
6887 if (!(ctrl & (1<<15)))
6888 break;
6889 DELAY(1000 * 1);
6890 }
6891
6892 if (cnt == 1000)
6893 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6894 // " Port %d\n",
6895
6896 ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6897 return cnt;
6898 }
6899
elink_link_int_enable(struct elink_params * params)6900 static void elink_link_int_enable(struct elink_params *params)
6901 {
6902 uint8_t port = params->port;
6903 uint32_t mask;
6904 struct bxe_softc *sc = params->sc;
6905
6906 /* Setting the status to report on link up for either XGXS or SerDes */
6907 if (CHIP_IS_E3(sc)) {
6908 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
6909 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
6910 mask |= ELINK_NIG_MASK_MI_INT;
6911 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6912 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
6913 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
6914 ELINK_DEBUG_P0(sc, "enabled XGXS interrupt\n");
6915 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6916 params->phy[ELINK_INT_PHY].type !=
6917 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6918 mask |= ELINK_NIG_MASK_MI_INT;
6919 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6920 }
6921
6922 } else { /* SerDes */
6923 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
6924 ELINK_DEBUG_P0(sc, "enabled SerDes interrupt\n");
6925 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6926 params->phy[ELINK_INT_PHY].type !=
6927 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6928 mask |= ELINK_NIG_MASK_MI_INT;
6929 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6930 }
6931 }
6932 elink_bits_en(sc,
6933 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6934 mask);
6935
6936 ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6937 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
6938 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6939 ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6940 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6941 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6942 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6943 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
6944 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6945 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6946 }
6947
elink_rearm_latch_signal(struct bxe_softc * sc,uint8_t port,uint8_t exp_mi_int)6948 static void elink_rearm_latch_signal(struct bxe_softc *sc, uint8_t port,
6949 uint8_t exp_mi_int)
6950 {
6951 uint32_t latch_status = 0;
6952
6953 /* Disable the MI INT ( external phy int ) by writing 1 to the
6954 * status register. Link down indication is high-active-signal,
6955 * so in this case we need to write the status to clear the XOR
6956 */
6957 /* Read Latched signals */
6958 latch_status = REG_RD(sc,
6959 NIG_REG_LATCH_STATUS_0 + port*8);
6960 ELINK_DEBUG_P1(sc, "latch_status = 0x%x\n", latch_status);
6961 /* Handle only those with latched-signal=up.*/
6962 if (exp_mi_int)
6963 elink_bits_en(sc,
6964 NIG_REG_STATUS_INTERRUPT_PORT0
6965 + port*4,
6966 ELINK_NIG_STATUS_EMAC0_MI_INT);
6967 else
6968 elink_bits_dis(sc,
6969 NIG_REG_STATUS_INTERRUPT_PORT0
6970 + port*4,
6971 ELINK_NIG_STATUS_EMAC0_MI_INT);
6972
6973 if (latch_status & 1) {
6974
6975 /* For all latched-signal=up : Re-Arm Latch signals */
6976 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8,
6977 (latch_status & 0xfffe) | (latch_status & 1));
6978 }
6979 /* For all latched-signal=up,Write original_signal to status */
6980 }
6981
elink_link_int_ack(struct elink_params * params,struct elink_vars * vars,uint8_t is_10g_plus)6982 static void elink_link_int_ack(struct elink_params *params,
6983 struct elink_vars *vars, uint8_t is_10g_plus)
6984 {
6985 struct bxe_softc *sc = params->sc;
6986 uint8_t port = params->port;
6987 uint32_t mask;
6988 /* First reset all status we assume only one line will be
6989 * change at a time
6990 */
6991 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6992 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6993 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6994 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
6995 if (vars->phy_link_up) {
6996 if (USES_WARPCORE(sc))
6997 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
6998 else {
6999 if (is_10g_plus)
7000 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
7001 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
7002 /* Disable the link interrupt by writing 1 to
7003 * the relevant lane in the status register
7004 */
7005 uint32_t ser_lane =
7006 ((params->lane_config &
7007 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
7008 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
7009 mask = ((1 << ser_lane) <<
7010 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
7011 } else
7012 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
7013 }
7014 ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x\n",
7015 mask);
7016 elink_bits_en(sc,
7017 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
7018 mask);
7019 }
7020 }
7021
elink_format_ver(uint32_t num,uint8_t * str,uint16_t * len)7022 static elink_status_t elink_format_ver(uint32_t num, uint8_t *str, uint16_t *len)
7023 {
7024 uint8_t *str_ptr = str;
7025 uint32_t mask = 0xf0000000;
7026 uint8_t shift = 8*4;
7027 uint8_t digit;
7028 uint8_t remove_leading_zeros = 1;
7029 if (*len < 10) {
7030 /* Need more than 10chars for this format */
7031 *str_ptr = '\0';
7032 (*len)--;
7033 return ELINK_STATUS_ERROR;
7034 }
7035 while (shift > 0) {
7036
7037 shift -= 4;
7038 digit = ((num & mask) >> shift);
7039 if (digit == 0 && remove_leading_zeros) {
7040 mask = mask >> 4;
7041 continue;
7042 } else if (digit < 0xa)
7043 *str_ptr = digit + '0';
7044 else
7045 *str_ptr = digit - 0xa + 'a';
7046 remove_leading_zeros = 0;
7047 str_ptr++;
7048 (*len)--;
7049 mask = mask >> 4;
7050 if (shift == 4*4) {
7051 *str_ptr = '.';
7052 str_ptr++;
7053 (*len)--;
7054 remove_leading_zeros = 1;
7055 }
7056 }
7057 return ELINK_STATUS_OK;
7058 }
7059
7060
elink_null_format_ver(uint32_t spirom_ver,uint8_t * str,uint16_t * len)7061 static elink_status_t elink_null_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
7062 {
7063 str[0] = '\0';
7064 (*len)--;
7065 return ELINK_STATUS_OK;
7066 }
7067
elink_get_ext_phy_fw_version(struct elink_params * params,uint8_t * version,uint16_t len)7068 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
7069 uint16_t len)
7070 {
7071 struct bxe_softc *sc;
7072 uint32_t spirom_ver = 0;
7073 elink_status_t status = ELINK_STATUS_OK;
7074 uint8_t *ver_p = version;
7075 uint16_t remain_len = len;
7076 if (version == NULL || params == NULL)
7077 return ELINK_STATUS_ERROR;
7078 sc = params->sc;
7079
7080 /* Extract first external phy*/
7081 version[0] = '\0';
7082 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
7083
7084 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
7085 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
7086 ver_p,
7087 &remain_len);
7088 ver_p += (len - remain_len);
7089 }
7090 if ((params->num_phys == ELINK_MAX_PHYS) &&
7091 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
7092 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
7093 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
7094 *ver_p = '/';
7095 ver_p++;
7096 remain_len--;
7097 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
7098 spirom_ver,
7099 ver_p,
7100 &remain_len);
7101 ver_p = version + (len - remain_len);
7102 }
7103 }
7104 *ver_p = '\0';
7105 return status;
7106 }
7107
elink_set_xgxs_loopback(struct elink_phy * phy,struct elink_params * params)7108 static void elink_set_xgxs_loopback(struct elink_phy *phy,
7109 struct elink_params *params)
7110 {
7111 uint8_t port = params->port;
7112 struct bxe_softc *sc = params->sc;
7113
7114 if (phy->req_line_speed != ELINK_SPEED_1000) {
7115 uint32_t md_devad = 0;
7116
7117 ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable\n");
7118
7119 if (!CHIP_IS_E3(sc)) {
7120 /* Change the uni_phy_addr in the nig */
7121 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
7122 port*0x18));
7123
7124 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7125 0x5);
7126 }
7127
7128 elink_cl45_write(sc, phy,
7129 5,
7130 (MDIO_REG_BANK_AER_BLOCK +
7131 (MDIO_AER_BLOCK_AER_REG & 0xf)),
7132 0x2800);
7133
7134 elink_cl45_write(sc, phy,
7135 5,
7136 (MDIO_REG_BANK_CL73_IEEEB0 +
7137 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
7138 0x6041);
7139 DELAY(1000 * 200);
7140 /* Set aer mmd back */
7141 elink_set_aer_mmd(params, phy);
7142
7143 if (!CHIP_IS_E3(sc)) {
7144 /* And md_devad */
7145 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7146 md_devad);
7147 }
7148 } else {
7149 uint16_t mii_ctrl;
7150 ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable\n");
7151 elink_cl45_read(sc, phy, 5,
7152 (MDIO_REG_BANK_COMBO_IEEE0 +
7153 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7154 &mii_ctrl);
7155 elink_cl45_write(sc, phy, 5,
7156 (MDIO_REG_BANK_COMBO_IEEE0 +
7157 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7158 mii_ctrl |
7159 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
7160 }
7161 }
7162
elink_set_led(struct elink_params * params,struct elink_vars * vars,uint8_t mode,uint32_t speed)7163 elink_status_t elink_set_led(struct elink_params *params,
7164 struct elink_vars *vars, uint8_t mode, uint32_t speed)
7165 {
7166 uint8_t port = params->port;
7167 uint16_t hw_led_mode = params->hw_led_mode;
7168 elink_status_t rc = ELINK_STATUS_OK;
7169 uint8_t phy_idx;
7170 uint32_t tmp;
7171 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7172 struct bxe_softc *sc = params->sc;
7173 ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d\n", port, mode);
7174 ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x\n",
7175 speed, hw_led_mode);
7176 /* In case */
7177 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7178 if (params->phy[phy_idx].set_link_led) {
7179 params->phy[phy_idx].set_link_led(
7180 ¶ms->phy[phy_idx], params, mode);
7181 }
7182 }
7183 #ifdef ELINK_INCLUDE_EMUL
7184 if (params->feature_config_flags &
7185 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
7186 return rc;
7187 #endif
7188
7189 switch (mode) {
7190 case ELINK_LED_MODE_FRONT_PANEL_OFF:
7191 case ELINK_LED_MODE_OFF:
7192 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);
7193 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7194 SHARED_HW_CFG_LED_MAC1);
7195
7196 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7197 if (params->phy[ELINK_EXT_PHY1].type ==
7198 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
7199 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
7200 EMAC_LED_100MB_OVERRIDE |
7201 EMAC_LED_10MB_OVERRIDE);
7202 else
7203 tmp |= EMAC_LED_OVERRIDE;
7204
7205 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
7206 break;
7207
7208 case ELINK_LED_MODE_OPER:
7209 /* For all other phys, OPER mode is same as ON, so in case
7210 * link is down, do nothing
7211 */
7212 if (!vars->link_up)
7213 break;
7214 case ELINK_LED_MODE_ON:
7215 if (((params->phy[ELINK_EXT_PHY1].type ==
7216 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
7217 (params->phy[ELINK_EXT_PHY1].type ==
7218 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
7219 CHIP_IS_E2(sc) && params->num_phys == 2) {
7220 /* This is a work-around for E2+8727 Configurations */
7221 if (mode == ELINK_LED_MODE_ON ||
7222 speed == ELINK_SPEED_10000){
7223 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7224 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7225
7226 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7227 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7228 (tmp | EMAC_LED_OVERRIDE));
7229 /* Return here without enabling traffic
7230 * LED blink and setting rate in ON mode.
7231 * In oper mode, enabling LED blink
7232 * and setting rate is needed.
7233 */
7234 if (mode == ELINK_LED_MODE_ON)
7235 return rc;
7236 }
7237 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
7238 /* This is a work-around for HW issue found when link
7239 * is up in CL73
7240 */
7241 if ((!CHIP_IS_E3(sc)) ||
7242 (CHIP_IS_E3(sc) &&
7243 mode == ELINK_LED_MODE_ON))
7244 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7245
7246 if (CHIP_IS_E1x(sc) ||
7247 CHIP_IS_E2(sc) ||
7248 (mode == ELINK_LED_MODE_ON))
7249 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7250 else
7251 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7252 hw_led_mode);
7253 } else if ((params->phy[ELINK_EXT_PHY1].type ==
7254 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
7255 (mode == ELINK_LED_MODE_ON)) {
7256 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7257 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7258 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp |
7259 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
7260 /* Break here; otherwise, it'll disable the
7261 * intended override.
7262 */
7263 break;
7264 } else {
7265 uint32_t nig_led_mode = ((params->hw_led_mode <<
7266 SHARED_HW_CFG_LED_MODE_SHIFT) ==
7267 SHARED_HW_CFG_LED_EXTPHY2) ?
7268 (SHARED_HW_CFG_LED_PHY1 >>
7269 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
7270 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7271 nig_led_mode);
7272 }
7273
7274 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7275 /* Set blinking rate to ~15.9Hz */
7276 if (CHIP_IS_E3(sc))
7277 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7278 LED_BLINK_RATE_VAL_E3);
7279 else
7280 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7281 LED_BLINK_RATE_VAL_E1X_E2);
7282 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
7283 port*4, 1);
7284 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7285 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7286 (tmp & (~EMAC_LED_OVERRIDE)));
7287
7288 if (CHIP_IS_E1(sc) &&
7289 ((speed == ELINK_SPEED_2500) ||
7290 (speed == ELINK_SPEED_1000) ||
7291 (speed == ELINK_SPEED_100) ||
7292 (speed == ELINK_SPEED_10))) {
7293 /* For speeds less than 10G LED scheme is different */
7294 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
7295 + port*4, 1);
7296 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
7297 port*4, 0);
7298 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
7299 port*4, 1);
7300 }
7301 break;
7302
7303 default:
7304 rc = ELINK_STATUS_ERROR;
7305 ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d\n",
7306 mode);
7307 break;
7308 }
7309 return rc;
7310
7311 }
7312
7313 /* This function comes to reflect the actual link state read DIRECTLY from the
7314 * HW
7315 */
elink_test_link(struct elink_params * params,struct elink_vars * vars,uint8_t is_serdes)7316 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
7317 uint8_t is_serdes)
7318 {
7319 struct bxe_softc *sc = params->sc;
7320 uint16_t gp_status = 0, phy_index = 0;
7321 uint8_t ext_phy_link_up = 0, serdes_phy_type;
7322 struct elink_vars temp_vars;
7323 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
7324 #ifdef ELINK_INCLUDE_FPGA
7325 if (CHIP_REV_IS_FPGA(sc))
7326 return ELINK_STATUS_OK;
7327 #endif
7328 #ifdef ELINK_INCLUDE_EMUL
7329 if (CHIP_REV_IS_EMUL(sc))
7330 return ELINK_STATUS_OK;
7331 #endif
7332
7333 if (CHIP_IS_E3(sc)) {
7334 uint16_t link_up;
7335 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
7336 > ELINK_SPEED_10000) {
7337 /* Check 20G link */
7338 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7339 1, &link_up);
7340 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7341 1, &link_up);
7342 link_up &= (1<<2);
7343 } else {
7344 /* Check 10G link and below*/
7345 uint8_t lane = elink_get_warpcore_lane(int_phy, params);
7346 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7347 MDIO_WC_REG_GP2_STATUS_GP_2_1,
7348 &gp_status);
7349 gp_status = ((gp_status >> 8) & 0xf) |
7350 ((gp_status >> 12) & 0xf);
7351 link_up = gp_status & (1 << lane);
7352 }
7353 if (!link_up)
7354 return ELINK_STATUS_NO_LINK;
7355 } else {
7356 CL22_RD_OVER_CL45(sc, int_phy,
7357 MDIO_REG_BANK_GP_STATUS,
7358 MDIO_GP_STATUS_TOP_AN_STATUS1,
7359 &gp_status);
7360 /* Link is up only if both local phy and external phy are up */
7361 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
7362 return ELINK_STATUS_NO_LINK;
7363 }
7364 /* In XGXS loopback mode, do not check external PHY */
7365 if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
7366 return ELINK_STATUS_OK;
7367
7368 switch (params->num_phys) {
7369 case 1:
7370 /* No external PHY */
7371 return ELINK_STATUS_OK;
7372 case 2:
7373 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
7374 ¶ms->phy[ELINK_EXT_PHY1],
7375 params, &temp_vars);
7376 break;
7377 case 3: /* Dual Media */
7378 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7379 phy_index++) {
7380 serdes_phy_type = ((params->phy[phy_index].media_type ==
7381 ELINK_ETH_PHY_SFPP_10G_FIBER) ||
7382 (params->phy[phy_index].media_type ==
7383 ELINK_ETH_PHY_SFP_1G_FIBER) ||
7384 (params->phy[phy_index].media_type ==
7385 ELINK_ETH_PHY_XFP_FIBER) ||
7386 (params->phy[phy_index].media_type ==
7387 ELINK_ETH_PHY_DA_TWINAX));
7388
7389 if (is_serdes != serdes_phy_type)
7390 continue;
7391 if (params->phy[phy_index].read_status) {
7392 ext_phy_link_up |=
7393 params->phy[phy_index].read_status(
7394 ¶ms->phy[phy_index],
7395 params, &temp_vars);
7396 }
7397 }
7398 break;
7399 }
7400 if (ext_phy_link_up)
7401 return ELINK_STATUS_OK;
7402 return ELINK_STATUS_NO_LINK;
7403 }
7404
elink_link_initialize(struct elink_params * params,struct elink_vars * vars)7405 static elink_status_t elink_link_initialize(struct elink_params *params,
7406 struct elink_vars *vars)
7407 {
7408 uint8_t phy_index, non_ext_phy;
7409 struct bxe_softc *sc = params->sc;
7410 /* In case of external phy existence, the line speed would be the
7411 * line speed linked up by the external phy. In case it is direct
7412 * only, then the line_speed during initialization will be
7413 * equal to the req_line_speed
7414 */
7415 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7416
7417 /* Initialize the internal phy in case this is a direct board
7418 * (no external phys), or this board has external phy which requires
7419 * to first.
7420 */
7421 if (!USES_WARPCORE(sc))
7422 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
7423 /* init ext phy and enable link state int */
7424 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
7425 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
7426
7427 if (non_ext_phy ||
7428 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7429 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
7430 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
7431 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
7432 (CHIP_IS_E1x(sc) ||
7433 CHIP_IS_E2(sc)))
7434 elink_set_parallel_detection(phy, params);
7435 if (params->phy[ELINK_INT_PHY].config_init)
7436 params->phy[ELINK_INT_PHY].config_init(phy, params, vars);
7437 }
7438
7439 /* Re-read this value in case it was changed inside config_init due to
7440 * limitations of optic module
7441 */
7442 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7443
7444 /* Init external phy*/
7445 if (non_ext_phy) {
7446 if (params->phy[ELINK_INT_PHY].supported &
7447 ELINK_SUPPORTED_FIBRE)
7448 vars->link_status |= LINK_STATUS_SERDES_LINK;
7449 } else {
7450 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7451 phy_index++) {
7452 /* No need to initialize second phy in case of first
7453 * phy only selection. In case of second phy, we do
7454 * need to initialize the first phy, since they are
7455 * connected.
7456 */
7457 if (params->phy[phy_index].supported &
7458 ELINK_SUPPORTED_FIBRE)
7459 vars->link_status |= LINK_STATUS_SERDES_LINK;
7460
7461 if (phy_index == ELINK_EXT_PHY2 &&
7462 (elink_phy_selection(params) ==
7463 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
7464 ELINK_DEBUG_P0(sc,
7465 "Not initializing second phy\n");
7466 continue;
7467 }
7468 params->phy[phy_index].config_init(
7469 ¶ms->phy[phy_index],
7470 params, vars);
7471 }
7472 }
7473 /* Reset the interrupt indication after phy was initialized */
7474 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
7475 params->port*4,
7476 (ELINK_NIG_STATUS_XGXS0_LINK10G |
7477 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
7478 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
7479 ELINK_NIG_MASK_MI_INT));
7480 return ELINK_STATUS_OK;
7481 }
7482
elink_int_link_reset(struct elink_phy * phy,struct elink_params * params)7483 static void elink_int_link_reset(struct elink_phy *phy,
7484 struct elink_params *params)
7485 {
7486 /* Reset the SerDes/XGXS */
7487 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
7488 (0x1ff << (params->port*16)));
7489 }
7490
elink_common_ext_link_reset(struct elink_phy * phy,struct elink_params * params)7491 static void elink_common_ext_link_reset(struct elink_phy *phy,
7492 struct elink_params *params)
7493 {
7494 struct bxe_softc *sc = params->sc;
7495 uint8_t gpio_port;
7496 /* HW reset */
7497 if (CHIP_IS_E2(sc))
7498 gpio_port = SC_PATH(sc);
7499 else
7500 gpio_port = params->port;
7501 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7502 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7503 gpio_port);
7504 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7505 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7506 gpio_port);
7507 ELINK_DEBUG_P0(sc, "reset external PHY\n");
7508 }
7509
elink_update_link_down(struct elink_params * params,struct elink_vars * vars)7510 static elink_status_t elink_update_link_down(struct elink_params *params,
7511 struct elink_vars *vars)
7512 {
7513 struct bxe_softc *sc = params->sc;
7514 uint8_t port = params->port;
7515
7516 ELINK_DEBUG_P1(sc, "Port %x: Link is down\n", port);
7517 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
7518 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
7519 /* Indicate no mac active */
7520 vars->mac_type = ELINK_MAC_TYPE_NONE;
7521
7522 /* Update shared memory */
7523 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7524 vars->line_speed = 0;
7525 elink_update_mng(params, vars->link_status);
7526
7527 /* Activate nig drain */
7528 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7529
7530 /* Disable emac */
7531 if (!CHIP_IS_E3(sc))
7532 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7533
7534 DELAY(1000 * 10);
7535 /* Reset BigMac/Xmac */
7536 if (CHIP_IS_E1x(sc) ||
7537 CHIP_IS_E2(sc))
7538 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
7539
7540 if (CHIP_IS_E3(sc)) {
7541 /* Prevent LPI Generation by chip */
7542 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7543 0);
7544 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7545 0);
7546 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
7547 SHMEM_EEE_ACTIVE_BIT);
7548
7549 elink_update_mng_eee(params, vars->eee_status);
7550 elink_set_xmac_rxtx(params, 0);
7551 elink_set_umac_rxtx(params, 0);
7552 }
7553
7554 return ELINK_STATUS_OK;
7555 }
7556
elink_update_link_up(struct elink_params * params,struct elink_vars * vars,uint8_t link_10g)7557 static elink_status_t elink_update_link_up(struct elink_params *params,
7558 struct elink_vars *vars,
7559 uint8_t link_10g)
7560 {
7561 struct bxe_softc *sc = params->sc;
7562 uint8_t phy_idx, port = params->port;
7563 elink_status_t rc = ELINK_STATUS_OK;
7564
7565 vars->link_status |= (LINK_STATUS_LINK_UP |
7566 LINK_STATUS_PHYSICAL_LINK_FLAG);
7567 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
7568
7569 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
7570 vars->link_status |=
7571 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
7572
7573 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
7574 vars->link_status |=
7575 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7576 if (USES_WARPCORE(sc)) {
7577 if (link_10g) {
7578 if (elink_xmac_enable(params, vars, 0) ==
7579 ELINK_STATUS_NO_LINK) {
7580 ELINK_DEBUG_P0(sc, "Found errors on XMAC\n");
7581 vars->link_up = 0;
7582 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7583 vars->link_status &= ~LINK_STATUS_LINK_UP;
7584 }
7585 } else
7586 elink_umac_enable(params, vars, 0);
7587 elink_set_led(params, vars,
7588 ELINK_LED_MODE_OPER, vars->line_speed);
7589
7590 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
7591 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
7592 ELINK_DEBUG_P0(sc, "Enabling LPI assertion\n");
7593 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
7594 (params->port << 2), 1);
7595 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
7596 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
7597 (params->port << 2), 0xfc20);
7598 }
7599 }
7600 if ((CHIP_IS_E1x(sc) ||
7601 CHIP_IS_E2(sc))) {
7602 if (link_10g) {
7603 if (elink_bmac_enable(params, vars, 0, 1) ==
7604 ELINK_STATUS_NO_LINK) {
7605 ELINK_DEBUG_P0(sc, "Found errors on BMAC\n");
7606 vars->link_up = 0;
7607 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7608 vars->link_status &= ~LINK_STATUS_LINK_UP;
7609 }
7610
7611 elink_set_led(params, vars,
7612 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
7613 } else {
7614 rc = elink_emac_program(params, vars);
7615 elink_emac_enable(params, vars, 0);
7616
7617 /* AN complete? */
7618 if ((vars->link_status &
7619 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
7620 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
7621 ELINK_SINGLE_MEDIA_DIRECT(params))
7622 elink_set_gmii_tx_driver(params);
7623 }
7624 }
7625
7626 /* PBF - link up */
7627 if (CHIP_IS_E1x(sc))
7628 rc |= elink_pbf_update(params, vars->flow_ctrl,
7629 vars->line_speed);
7630
7631 /* Disable drain */
7632 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7633
7634 /* Update shared memory */
7635 elink_update_mng(params, vars->link_status);
7636 elink_update_mng_eee(params, vars->eee_status);
7637 /* Check remote fault */
7638 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7639 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
7640 elink_check_half_open_conn(params, vars, 0);
7641 break;
7642 }
7643 }
7644 DELAY(1000 * 20);
7645 return rc;
7646 }
7647
elink_chng_link_count(struct elink_params * params,uint8_t clear)7648 static void elink_chng_link_count(struct elink_params *params, uint8_t clear)
7649 {
7650 struct bxe_softc *sc = params->sc;
7651 uint32_t addr, val;
7652
7653 /* Verify the link_change_count is supported by the MFW */
7654 if (!(SHMEM2_HAS(sc, link_change_count)))
7655 return;
7656
7657 addr = params->shmem2_base +
7658 offsetof(struct shmem2_region, link_change_count[params->port]);
7659 if (clear)
7660 val = 0;
7661 else
7662 val = REG_RD(sc, addr) + 1;
7663 REG_WR(sc, addr, val);
7664 }
7665
7666 /* The elink_link_update function should be called upon link
7667 * interrupt.
7668 * Link is considered up as follows:
7669 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
7670 * to be up
7671 * - SINGLE_MEDIA - The link between the 577xx and the external
7672 * phy (XGXS) need to up as well as the external link of the
7673 * phy (PHY_EXT1)
7674 * - DUAL_MEDIA - The link between the 577xx and the first
7675 * external phy needs to be up, and at least one of the 2
7676 * external phy link must be up.
7677 */
elink_link_update(struct elink_params * params,struct elink_vars * vars)7678 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars)
7679 {
7680 struct bxe_softc *sc = params->sc;
7681 struct elink_vars phy_vars[ELINK_MAX_PHYS];
7682 uint8_t port = params->port;
7683 uint8_t link_10g_plus, phy_index;
7684 uint32_t prev_link_status = vars->link_status;
7685 uint8_t ext_phy_link_up = 0, cur_link_up;
7686 elink_status_t rc = ELINK_STATUS_OK;
7687 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
7688 uint8_t active_external_phy = ELINK_INT_PHY;
7689 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
7690 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7691 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
7692 phy_index++) {
7693 phy_vars[phy_index].flow_ctrl = 0;
7694 phy_vars[phy_index].link_status = 0;
7695 phy_vars[phy_index].line_speed = 0;
7696 phy_vars[phy_index].duplex = DUPLEX_FULL;
7697 phy_vars[phy_index].phy_link_up = 0;
7698 phy_vars[phy_index].link_up = 0;
7699 phy_vars[phy_index].fault_detected = 0;
7700 /* different consideration, since vars holds inner state */
7701 phy_vars[phy_index].eee_status = vars->eee_status;
7702 }
7703
7704 if (USES_WARPCORE(sc))
7705 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
7706
7707 ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n",
7708 port, (vars->phy_flags & PHY_XGXS_FLAG),
7709 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7710
7711 ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
7712 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7713 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0,
7714 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7715
7716 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
7717 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7718 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
7719
7720 /* Disable emac */
7721 if (!CHIP_IS_E3(sc))
7722 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7723
7724 /* Step 1:
7725 * Check external link change only for external phys, and apply
7726 * priority selection between them in case the link on both phys
7727 * is up. Note that instead of the common vars, a temporary
7728 * vars argument is used since each phy may have different link/
7729 * speed/duplex result
7730 */
7731 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7732 phy_index++) {
7733 struct elink_phy *phy = ¶ms->phy[phy_index];
7734 if (!phy->read_status)
7735 continue;
7736 /* Read link status and params of this ext phy */
7737 cur_link_up = phy->read_status(phy, params,
7738 &phy_vars[phy_index]);
7739 if (cur_link_up) {
7740 ELINK_DEBUG_P1(sc, "phy in index %d link is up\n",
7741 phy_index);
7742 } else {
7743 ELINK_DEBUG_P1(sc, "phy in index %d link is down\n",
7744 phy_index);
7745 continue;
7746 }
7747
7748 if (!ext_phy_link_up) {
7749 ext_phy_link_up = 1;
7750 active_external_phy = phy_index;
7751 } else {
7752 switch (elink_phy_selection(params)) {
7753 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
7754 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7755 /* In this option, the first PHY makes sure to pass the
7756 * traffic through itself only.
7757 * Its not clear how to reset the link on the second phy
7758 */
7759 active_external_phy = ELINK_EXT_PHY1;
7760 break;
7761 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7762 /* In this option, the first PHY makes sure to pass the
7763 * traffic through the second PHY.
7764 */
7765 active_external_phy = ELINK_EXT_PHY2;
7766 break;
7767 default:
7768 /* Link indication on both PHYs with the following cases
7769 * is invalid:
7770 * - FIRST_PHY means that second phy wasn't initialized,
7771 * hence its link is expected to be down
7772 * - SECOND_PHY means that first phy should not be able
7773 * to link up by itself (using configuration)
7774 * - DEFAULT should be overridden during initialiazation
7775 */
7776 ELINK_DEBUG_P1(sc, "Invalid link indication"
7777 "mpc=0x%x. DISABLING LINK !!!\n",
7778 params->multi_phy_config);
7779 ext_phy_link_up = 0;
7780 break;
7781 }
7782 }
7783 }
7784 prev_line_speed = vars->line_speed;
7785 /* Step 2:
7786 * Read the status of the internal phy. In case of
7787 * DIRECT_SINGLE_MEDIA board, this link is the external link,
7788 * otherwise this is the link between the 577xx and the first
7789 * external phy
7790 */
7791 if (params->phy[ELINK_INT_PHY].read_status)
7792 params->phy[ELINK_INT_PHY].read_status(
7793 ¶ms->phy[ELINK_INT_PHY],
7794 params, vars);
7795 /* The INT_PHY flow control reside in the vars. This include the
7796 * case where the speed or flow control are not set to AUTO.
7797 * Otherwise, the active external phy flow control result is set
7798 * to the vars. The ext_phy_line_speed is needed to check if the
7799 * speed is different between the internal phy and external phy.
7800 * This case may be result of intermediate link speed change.
7801 */
7802 if (active_external_phy > ELINK_INT_PHY) {
7803 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
7804 /* Link speed is taken from the XGXS. AN and FC result from
7805 * the external phy.
7806 */
7807 vars->link_status |= phy_vars[active_external_phy].link_status;
7808
7809 /* if active_external_phy is first PHY and link is up - disable
7810 * disable TX on second external PHY
7811 */
7812 if (active_external_phy == ELINK_EXT_PHY1) {
7813 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
7814 ELINK_DEBUG_P0(sc,
7815 "Disabling TX on EXT_PHY2\n");
7816 params->phy[ELINK_EXT_PHY2].phy_specific_func(
7817 ¶ms->phy[ELINK_EXT_PHY2],
7818 params, ELINK_DISABLE_TX);
7819 }
7820 }
7821
7822 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
7823 vars->duplex = phy_vars[active_external_phy].duplex;
7824 if (params->phy[active_external_phy].supported &
7825 ELINK_SUPPORTED_FIBRE)
7826 vars->link_status |= LINK_STATUS_SERDES_LINK;
7827 else
7828 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
7829
7830 vars->eee_status = phy_vars[active_external_phy].eee_status;
7831
7832 ELINK_DEBUG_P1(sc, "Active external phy selected: %x\n",
7833 active_external_phy);
7834 }
7835
7836 ELINK_DEBUG_P3(sc, "vars : phy_flags = %x, mac_type = %x, phy_link_up = %x\n",
7837 vars->phy_flags, vars->mac_type, vars->phy_link_up);
7838 ELINK_DEBUG_P3(sc, "vars : link_up = %x, line_speed = %x, duplex = %x\n",
7839 vars->link_up, vars->line_speed, vars->duplex);
7840 ELINK_DEBUG_P3(sc, "vars : flow_ctrl = %x, ieee_fc = %x, link_status = %x\n",
7841 vars->flow_ctrl, vars->ieee_fc, vars->link_status);
7842 ELINK_DEBUG_P3(sc, "vars : eee_status = %x, fault_detected = %x, check_kr2_recovery_cnt = %x\n",
7843 vars->eee_status, vars->fault_detected, vars->check_kr2_recovery_cnt);
7844 ELINK_DEBUG_P3(sc, "vars : periodic_flags = %x, aeu_int_mask = %x, rx_tx_asic_rst = %x\n",
7845 vars->periodic_flags, vars->aeu_int_mask, vars->rx_tx_asic_rst);
7846 ELINK_DEBUG_P2(sc, "vars : turn_to_run_wc_rt = %x, rsrv2 = %x\n",
7847 vars->turn_to_run_wc_rt, vars->rsrv2);
7848
7849 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7850 phy_index++) {
7851 if (params->phy[phy_index].flags &
7852 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
7853 elink_rearm_latch_signal(sc, port,
7854 phy_index ==
7855 active_external_phy);
7856 break;
7857 }
7858 }
7859 ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
7860 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
7861 vars->link_status, ext_phy_line_speed);
7862 /* Upon link speed change set the NIG into drain mode. Comes to
7863 * deals with possible FIFO glitch due to clk change when speed
7864 * is decreased without link down indicator
7865 */
7866
7867 if (vars->phy_link_up) {
7868 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
7869 (ext_phy_line_speed != vars->line_speed)) {
7870 ELINK_DEBUG_P2(sc, "Internal link speed %d is"
7871 " different than the external"
7872 " link speed %d\n", vars->line_speed,
7873 ext_phy_line_speed);
7874 vars->phy_link_up = 0;
7875 ELINK_DEBUG_P0(sc, "phy_link_up set to 0\n");
7876 } else if (prev_line_speed != vars->line_speed) {
7877 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7878 0);
7879 DELAY(1000 * 1);
7880 }
7881 }
7882
7883 /* Anything 10 and over uses the bmac */
7884 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
7885
7886 elink_link_int_ack(params, vars, link_10g_plus);
7887
7888 /* In case external phy link is up, and internal link is down
7889 * (not initialized yet probably after link initialization, it
7890 * needs to be initialized.
7891 * Note that after link down-up as result of cable plug, the xgxs
7892 * link would probably become up again without the need
7893 * initialize it
7894 */
7895 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
7896 ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d,"
7897 " init_preceding = %d\n", ext_phy_link_up,
7898 vars->phy_link_up,
7899 params->phy[ELINK_EXT_PHY1].flags &
7900 ELINK_FLAGS_INIT_XGXS_FIRST);
7901 if (!(params->phy[ELINK_EXT_PHY1].flags &
7902 ELINK_FLAGS_INIT_XGXS_FIRST)
7903 && ext_phy_link_up && !vars->phy_link_up) {
7904 vars->line_speed = ext_phy_line_speed;
7905 if (vars->line_speed < ELINK_SPEED_1000)
7906 vars->phy_flags |= PHY_SGMII_FLAG;
7907 else
7908 vars->phy_flags &= ~PHY_SGMII_FLAG;
7909
7910 if (params->phy[ELINK_INT_PHY].config_init)
7911 params->phy[ELINK_INT_PHY].config_init(
7912 ¶ms->phy[ELINK_INT_PHY], params,
7913 vars);
7914 }
7915 }
7916 /* Link is up only if both local phy and external phy (in case of
7917 * non-direct board) are up and no fault detected on active PHY.
7918 */
7919 vars->link_up = (vars->phy_link_up &&
7920 (ext_phy_link_up ||
7921 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
7922 (phy_vars[active_external_phy].fault_detected == 0));
7923
7924 if(vars->link_up) {
7925 ELINK_DEBUG_P0(sc, "local phy and external phy are up\n");
7926 } else {
7927 ELINK_DEBUG_P0(sc, "either local phy or external phy or both are down\n");
7928 }
7929
7930 /* Update the PFC configuration in case it was changed */
7931 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
7932 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7933 else
7934 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7935
7936 if (vars->link_up)
7937 rc = elink_update_link_up(params, vars, link_10g_plus);
7938 else
7939 rc = elink_update_link_down(params, vars);
7940
7941 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7942 elink_chng_link_count(params, 0);
7943
7944 /* Update MCP link status was changed */
7945 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7946 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7947
7948 return rc;
7949 }
7950
7951 /*****************************************************************************/
7952 /* External Phy section */
7953 /*****************************************************************************/
elink_ext_phy_hw_reset(struct bxe_softc * sc,uint8_t port)7954 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port)
7955 {
7956 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7957 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7958 DELAY(1000 * 1);
7959 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7960 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7961 }
7962
elink_save_spirom_version(struct bxe_softc * sc,uint8_t port,uint32_t spirom_ver,uint32_t ver_addr)7963 static void elink_save_spirom_version(struct bxe_softc *sc, uint8_t port,
7964 uint32_t spirom_ver, uint32_t ver_addr)
7965 {
7966 ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n",
7967 (uint16_t)(spirom_ver>>16), (uint16_t)spirom_ver, port);
7968
7969 if (ver_addr)
7970 REG_WR(sc, ver_addr, spirom_ver);
7971 }
7972
elink_save_bcm_spirom_ver(struct bxe_softc * sc,struct elink_phy * phy,uint8_t port)7973 static void elink_save_bcm_spirom_ver(struct bxe_softc *sc,
7974 struct elink_phy *phy,
7975 uint8_t port)
7976 {
7977 uint16_t fw_ver1, fw_ver2;
7978
7979 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7980 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7981 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7982 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7983 elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1<<16 | fw_ver2),
7984 phy->ver_addr);
7985 }
7986
elink_ext_phy_10G_an_resolve(struct bxe_softc * sc,struct elink_phy * phy,struct elink_vars * vars)7987 static void elink_ext_phy_10G_an_resolve(struct bxe_softc *sc,
7988 struct elink_phy *phy,
7989 struct elink_vars *vars)
7990 {
7991 uint16_t val;
7992 elink_cl45_read(sc, phy,
7993 MDIO_AN_DEVAD,
7994 MDIO_AN_REG_STATUS, &val);
7995 elink_cl45_read(sc, phy,
7996 MDIO_AN_DEVAD,
7997 MDIO_AN_REG_STATUS, &val);
7998 if (val & (1<<5))
7999 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
8000 if ((val & (1<<0)) == 0)
8001 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
8002 }
8003
8004 /******************************************************************/
8005 /* common BCM8073/BCM8727 PHY SECTION */
8006 /******************************************************************/
elink_8073_resolve_fc(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)8007 static void elink_8073_resolve_fc(struct elink_phy *phy,
8008 struct elink_params *params,
8009 struct elink_vars *vars)
8010 {
8011 struct bxe_softc *sc = params->sc;
8012 if (phy->req_line_speed == ELINK_SPEED_10 ||
8013 phy->req_line_speed == ELINK_SPEED_100) {
8014 vars->flow_ctrl = phy->req_flow_ctrl;
8015 return;
8016 }
8017
8018 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
8019 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
8020 uint16_t pause_result;
8021 uint16_t ld_pause; /* local */
8022 uint16_t lp_pause; /* link partner */
8023 elink_cl45_read(sc, phy,
8024 MDIO_AN_DEVAD,
8025 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
8026
8027 elink_cl45_read(sc, phy,
8028 MDIO_AN_DEVAD,
8029 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
8030 pause_result = (ld_pause &
8031 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
8032 pause_result |= (lp_pause &
8033 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
8034
8035 elink_pause_resolve(phy, params, vars, pause_result);
8036 ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x\n",
8037 pause_result);
8038 }
8039 }
elink_8073_8727_external_rom_boot(struct bxe_softc * sc,struct elink_phy * phy,uint8_t port)8040 static elink_status_t elink_8073_8727_external_rom_boot(struct bxe_softc *sc,
8041 struct elink_phy *phy,
8042 uint8_t port)
8043 {
8044 uint32_t count = 0;
8045 uint16_t fw_ver1, fw_msgout;
8046 elink_status_t rc = ELINK_STATUS_OK;
8047
8048 /* Boot port from external ROM */
8049 /* EDC grst */
8050 elink_cl45_write(sc, phy,
8051 MDIO_PMA_DEVAD,
8052 MDIO_PMA_REG_GEN_CTRL,
8053 0x0001);
8054
8055 /* Ucode reboot and rst */
8056 elink_cl45_write(sc, phy,
8057 MDIO_PMA_DEVAD,
8058 MDIO_PMA_REG_GEN_CTRL,
8059 0x008c);
8060
8061 elink_cl45_write(sc, phy,
8062 MDIO_PMA_DEVAD,
8063 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8064
8065 /* Reset internal microprocessor */
8066 elink_cl45_write(sc, phy,
8067 MDIO_PMA_DEVAD,
8068 MDIO_PMA_REG_GEN_CTRL,
8069 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8070
8071 /* Release srst bit */
8072 elink_cl45_write(sc, phy,
8073 MDIO_PMA_DEVAD,
8074 MDIO_PMA_REG_GEN_CTRL,
8075 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8076
8077 /* Delay 100ms per the PHY specifications */
8078 DELAY(1000 * 100);
8079
8080 /* 8073 sometimes taking longer to download */
8081 do {
8082 count++;
8083 if (count > 300) {
8084 ELINK_DEBUG_P2(sc,
8085 "elink_8073_8727_external_rom_boot port %x:"
8086 "Download failed. fw version = 0x%x\n",
8087 port, fw_ver1);
8088 rc = ELINK_STATUS_ERROR;
8089 break;
8090 }
8091
8092 elink_cl45_read(sc, phy,
8093 MDIO_PMA_DEVAD,
8094 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
8095 elink_cl45_read(sc, phy,
8096 MDIO_PMA_DEVAD,
8097 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
8098
8099 DELAY(1000 * 1);
8100 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
8101 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
8102 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
8103
8104 /* Clear ser_boot_ctl bit */
8105 elink_cl45_write(sc, phy,
8106 MDIO_PMA_DEVAD,
8107 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8108 elink_save_bcm_spirom_ver(sc, phy, port);
8109
8110 ELINK_DEBUG_P2(sc,
8111 "elink_8073_8727_external_rom_boot port %x:"
8112 "Download complete. fw version = 0x%x\n",
8113 port, fw_ver1);
8114
8115 return rc;
8116 }
8117
8118 /******************************************************************/
8119 /* BCM8073 PHY SECTION */
8120 /******************************************************************/
elink_8073_is_snr_needed(struct bxe_softc * sc,struct elink_phy * phy)8121 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)
8122 {
8123 /* This is only required for 8073A1, version 102 only */
8124 uint16_t val;
8125
8126 /* Read 8073 HW revision*/
8127 elink_cl45_read(sc, phy,
8128 MDIO_PMA_DEVAD,
8129 MDIO_PMA_REG_8073_CHIP_REV, &val);
8130
8131 if (val != 1) {
8132 /* No need to workaround in 8073 A1 */
8133 return ELINK_STATUS_OK;
8134 }
8135
8136 elink_cl45_read(sc, phy,
8137 MDIO_PMA_DEVAD,
8138 MDIO_PMA_REG_ROM_VER2, &val);
8139
8140 /* SNR should be applied only for version 0x102 */
8141 if (val != 0x102)
8142 return ELINK_STATUS_OK;
8143
8144 return 1;
8145 }
8146
elink_8073_xaui_wa(struct bxe_softc * sc,struct elink_phy * phy)8147 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)
8148 {
8149 uint16_t val, cnt, cnt1 ;
8150
8151 elink_cl45_read(sc, phy,
8152 MDIO_PMA_DEVAD,
8153 MDIO_PMA_REG_8073_CHIP_REV, &val);
8154
8155 if (val > 0) {
8156 /* No need to workaround in 8073 A1 */
8157 return ELINK_STATUS_OK;
8158 }
8159 /* XAUI workaround in 8073 A0: */
8160
8161 /* After loading the boot ROM and restarting Autoneg, poll
8162 * Dev1, Reg $C820:
8163 */
8164
8165 for (cnt = 0; cnt < 1000; cnt++) {
8166 elink_cl45_read(sc, phy,
8167 MDIO_PMA_DEVAD,
8168 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8169 &val);
8170 /* If bit [14] = 0 or bit [13] = 0, continue on with
8171 * system initialization (XAUI work-around not required, as
8172 * these bits indicate 2.5G or 1G link up).
8173 */
8174 if (!(val & (1<<14)) || !(val & (1<<13))) {
8175 ELINK_DEBUG_P0(sc, "XAUI work-around not required\n");
8176 return ELINK_STATUS_OK;
8177 } else if (!(val & (1<<15))) {
8178 ELINK_DEBUG_P0(sc, "bit 15 went off\n");
8179 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
8180 * MSB (bit15) goes to 1 (indicating that the XAUI
8181 * workaround has completed), then continue on with
8182 * system initialization.
8183 */
8184 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
8185 elink_cl45_read(sc, phy,
8186 MDIO_PMA_DEVAD,
8187 MDIO_PMA_REG_8073_XAUI_WA, &val);
8188 if (val & (1<<15)) {
8189 ELINK_DEBUG_P0(sc,
8190 "XAUI workaround has completed\n");
8191 return ELINK_STATUS_OK;
8192 }
8193 DELAY(1000 * 3);
8194 }
8195 break;
8196 }
8197 DELAY(1000 * 3);
8198 }
8199 ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!\n");
8200 return ELINK_STATUS_ERROR;
8201 }
8202
elink_807x_force_10G(struct bxe_softc * sc,struct elink_phy * phy)8203 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)
8204 {
8205 /* Force KR or KX */
8206 elink_cl45_write(sc, phy,
8207 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8208 elink_cl45_write(sc, phy,
8209 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
8210 elink_cl45_write(sc, phy,
8211 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
8212 elink_cl45_write(sc, phy,
8213 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
8214 }
8215
elink_8073_set_pause_cl37(struct elink_params * params,struct elink_phy * phy,struct elink_vars * vars)8216 static void elink_8073_set_pause_cl37(struct elink_params *params,
8217 struct elink_phy *phy,
8218 struct elink_vars *vars)
8219 {
8220 uint16_t cl37_val;
8221 struct bxe_softc *sc = params->sc;
8222 elink_cl45_read(sc, phy,
8223 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
8224
8225 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8226 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
8227 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
8228 if ((vars->ieee_fc &
8229 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
8230 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
8231 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
8232 }
8233 if ((vars->ieee_fc &
8234 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
8235 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
8236 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
8237 }
8238 if ((vars->ieee_fc &
8239 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
8240 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
8241 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8242 }
8243 ELINK_DEBUG_P1(sc,
8244 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
8245
8246 elink_cl45_write(sc, phy,
8247 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
8248 DELAY(1000 * 500);
8249 }
8250
elink_8073_specific_func(struct elink_phy * phy,struct elink_params * params,uint32_t action)8251 static void elink_8073_specific_func(struct elink_phy *phy,
8252 struct elink_params *params,
8253 uint32_t action)
8254 {
8255 struct bxe_softc *sc = params->sc;
8256 switch (action) {
8257 case ELINK_PHY_INIT:
8258 /* Enable LASI */
8259 elink_cl45_write(sc, phy,
8260 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
8261 elink_cl45_write(sc, phy,
8262 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8263 break;
8264 }
8265 }
8266
elink_8073_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)8267 static elink_status_t elink_8073_config_init(struct elink_phy *phy,
8268 struct elink_params *params,
8269 struct elink_vars *vars)
8270 {
8271 struct bxe_softc *sc = params->sc;
8272 uint16_t val = 0, tmp1;
8273 uint8_t gpio_port;
8274 ELINK_DEBUG_P0(sc, "Init 8073\n");
8275
8276 if (CHIP_IS_E2(sc))
8277 gpio_port = SC_PATH(sc);
8278 else
8279 gpio_port = params->port;
8280 /* Restore normal power mode*/
8281 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8282 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8283
8284 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8285 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8286
8287 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
8288 elink_8073_set_pause_cl37(params, phy, vars);
8289
8290 elink_cl45_read(sc, phy,
8291 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8292
8293 elink_cl45_read(sc, phy,
8294 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8295
8296 ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
8297
8298 /* Swap polarity if required - Must be done only in non-1G mode */
8299 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8300 /* Configure the 8073 to swap _P and _N of the KR lines */
8301 ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073\n");
8302 /* 10G Rx/Tx and 1G Tx signal polarity swap */
8303 elink_cl45_read(sc, phy,
8304 MDIO_PMA_DEVAD,
8305 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
8306 elink_cl45_write(sc, phy,
8307 MDIO_PMA_DEVAD,
8308 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
8309 (val | (3<<9)));
8310 }
8311
8312
8313 /* Enable CL37 BAM */
8314 if (REG_RD(sc, params->shmem_base +
8315 offsetof(struct shmem_region, dev_info.
8316 port_hw_config[params->port].default_cfg)) &
8317 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
8318
8319 elink_cl45_read(sc, phy,
8320 MDIO_AN_DEVAD,
8321 MDIO_AN_REG_8073_BAM, &val);
8322 elink_cl45_write(sc, phy,
8323 MDIO_AN_DEVAD,
8324 MDIO_AN_REG_8073_BAM, val | 1);
8325 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
8326 }
8327 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
8328 elink_807x_force_10G(sc, phy);
8329 ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X\n");
8330 return ELINK_STATUS_OK;
8331 } else {
8332 elink_cl45_write(sc, phy,
8333 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
8334 }
8335 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
8336 if (phy->req_line_speed == ELINK_SPEED_10000) {
8337 val = (1<<7);
8338 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
8339 val = (1<<5);
8340 /* Note that 2.5G works only when used with 1G
8341 * advertisement
8342 */
8343 } else
8344 val = (1<<5);
8345 } else {
8346 val = 0;
8347 if (phy->speed_cap_mask &
8348 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
8349 val |= (1<<7);
8350
8351 /* Note that 2.5G works only when used with 1G advertisement */
8352 if (phy->speed_cap_mask &
8353 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
8354 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8355 val |= (1<<5);
8356 ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x\n", val);
8357 }
8358
8359 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
8360 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
8361
8362 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
8363 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
8364 (phy->req_line_speed == ELINK_SPEED_2500)) {
8365 uint16_t phy_ver;
8366 /* Allow 2.5G for A1 and above */
8367 elink_cl45_read(sc, phy,
8368 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
8369 &phy_ver);
8370 ELINK_DEBUG_P0(sc, "Add 2.5G\n");
8371 if (phy_ver > 0)
8372 tmp1 |= 1;
8373 else
8374 tmp1 &= 0xfffe;
8375 } else {
8376 ELINK_DEBUG_P0(sc, "Disable 2.5G\n");
8377 tmp1 &= 0xfffe;
8378 }
8379
8380 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
8381 /* Add support for CL37 (passive mode) II */
8382
8383 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
8384 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
8385 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
8386 0x20 : 0x40)));
8387
8388 /* Add support for CL37 (passive mode) III */
8389 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8390
8391 /* The SNR will improve about 2db by changing BW and FEE main
8392 * tap. Rest commands are executed after link is up
8393 * Change FFE main cursor to 5 in EDC register
8394 */
8395 if (elink_8073_is_snr_needed(sc, phy))
8396 elink_cl45_write(sc, phy,
8397 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
8398 0xFB0C);
8399
8400 /* Enable FEC (Forware Error Correction) Request in the AN */
8401 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
8402 tmp1 |= (1<<15);
8403 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
8404
8405 elink_ext_phy_set_pause(params, phy, vars);
8406
8407 /* Restart autoneg */
8408 DELAY(1000 * 500);
8409 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8410 ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
8411 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
8412 return ELINK_STATUS_OK;
8413 }
8414
elink_8073_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)8415 static uint8_t elink_8073_read_status(struct elink_phy *phy,
8416 struct elink_params *params,
8417 struct elink_vars *vars)
8418 {
8419 struct bxe_softc *sc = params->sc;
8420 uint8_t link_up = 0;
8421 uint16_t val1, val2;
8422 uint16_t link_status = 0;
8423 uint16_t an1000_status = 0;
8424
8425 elink_cl45_read(sc, phy,
8426 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8427
8428 ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x\n", val1);
8429
8430 /* Clear the interrupt LASI status register */
8431 elink_cl45_read(sc, phy,
8432 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8433 elink_cl45_read(sc, phy,
8434 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
8435 ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1);
8436 /* Clear MSG-OUT */
8437 elink_cl45_read(sc, phy,
8438 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8439
8440 /* Check the LASI */
8441 elink_cl45_read(sc, phy,
8442 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8443
8444 ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x\n", val2);
8445
8446 /* Check the link status */
8447 elink_cl45_read(sc, phy,
8448 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8449 ELINK_DEBUG_P1(sc, "KR PCS status 0x%x\n", val2);
8450
8451 elink_cl45_read(sc, phy,
8452 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8453 elink_cl45_read(sc, phy,
8454 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8455 link_up = ((val1 & 4) == 4);
8456 ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x\n", val1);
8457
8458 if (link_up &&
8459 ((phy->req_line_speed != ELINK_SPEED_10000))) {
8460 if (elink_8073_xaui_wa(sc, phy) != 0)
8461 return 0;
8462 }
8463 elink_cl45_read(sc, phy,
8464 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8465 elink_cl45_read(sc, phy,
8466 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8467
8468 /* Check the link status on 1.1.2 */
8469 elink_cl45_read(sc, phy,
8470 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8471 elink_cl45_read(sc, phy,
8472 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8473 ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"
8474 "an_link_status=0x%x\n", val2, val1, an1000_status);
8475
8476 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
8477 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
8478 /* The SNR will improve about 2dbby changing the BW and FEE main
8479 * tap. The 1st write to change FFE main tap is set before
8480 * restart AN. Change PLL Bandwidth in EDC register
8481 */
8482 elink_cl45_write(sc, phy,
8483 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
8484 0x26BC);
8485
8486 /* Change CDR Bandwidth in EDC register */
8487 elink_cl45_write(sc, phy,
8488 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
8489 0x0333);
8490 }
8491 elink_cl45_read(sc, phy,
8492 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8493 &link_status);
8494
8495 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
8496 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8497 link_up = 1;
8498 vars->line_speed = ELINK_SPEED_10000;
8499 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
8500 params->port);
8501 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
8502 link_up = 1;
8503 vars->line_speed = ELINK_SPEED_2500;
8504 ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
8505 params->port);
8506 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8507 link_up = 1;
8508 vars->line_speed = ELINK_SPEED_1000;
8509 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
8510 params->port);
8511 } else {
8512 link_up = 0;
8513 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
8514 params->port);
8515 }
8516
8517 if (link_up) {
8518 /* Swap polarity if required */
8519 if (params->lane_config &
8520 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8521 /* Configure the 8073 to swap P and N of the KR lines */
8522 elink_cl45_read(sc, phy,
8523 MDIO_XS_DEVAD,
8524 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
8525 /* Set bit 3 to invert Rx in 1G mode and clear this bit
8526 * when it`s in 10G mode.
8527 */
8528 if (vars->line_speed == ELINK_SPEED_1000) {
8529 ELINK_DEBUG_P0(sc, "Swapping 1G polarity for"
8530 "the 8073\n");
8531 val1 |= (1<<3);
8532 } else
8533 val1 &= ~(1<<3);
8534
8535 elink_cl45_write(sc, phy,
8536 MDIO_XS_DEVAD,
8537 MDIO_XS_REG_8073_RX_CTRL_PCIE,
8538 val1);
8539 }
8540 elink_ext_phy_10G_an_resolve(sc, phy, vars);
8541 elink_8073_resolve_fc(phy, params, vars);
8542 vars->duplex = DUPLEX_FULL;
8543 }
8544
8545 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
8546 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
8547 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
8548
8549 if (val1 & (1<<5))
8550 vars->link_status |=
8551 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
8552 if (val1 & (1<<7))
8553 vars->link_status |=
8554 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
8555 }
8556
8557 return link_up;
8558 }
8559
elink_8073_link_reset(struct elink_phy * phy,struct elink_params * params)8560 static void elink_8073_link_reset(struct elink_phy *phy,
8561 struct elink_params *params)
8562 {
8563 struct bxe_softc *sc = params->sc;
8564 uint8_t gpio_port;
8565 if (CHIP_IS_E2(sc))
8566 gpio_port = SC_PATH(sc);
8567 else
8568 gpio_port = params->port;
8569 ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode\n",
8570 gpio_port);
8571 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8572 MISC_REGISTERS_GPIO_OUTPUT_LOW,
8573 gpio_port);
8574 }
8575
8576 /******************************************************************/
8577 /* BCM8705 PHY SECTION */
8578 /******************************************************************/
elink_8705_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)8579 static elink_status_t elink_8705_config_init(struct elink_phy *phy,
8580 struct elink_params *params,
8581 struct elink_vars *vars)
8582 {
8583 struct bxe_softc *sc = params->sc;
8584 ELINK_DEBUG_P0(sc, "init 8705\n");
8585 /* Restore normal power mode*/
8586 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8587 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8588 /* HW reset */
8589 elink_ext_phy_hw_reset(sc, params->port);
8590 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8591 elink_wait_reset_complete(sc, phy, params);
8592
8593 elink_cl45_write(sc, phy,
8594 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
8595 elink_cl45_write(sc, phy,
8596 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
8597 elink_cl45_write(sc, phy,
8598 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
8599 elink_cl45_write(sc, phy,
8600 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
8601 /* BCM8705 doesn't have microcode, hence the 0 */
8602 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
8603 return ELINK_STATUS_OK;
8604 }
8605
elink_8705_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)8606 static uint8_t elink_8705_read_status(struct elink_phy *phy,
8607 struct elink_params *params,
8608 struct elink_vars *vars)
8609 {
8610 uint8_t link_up = 0;
8611 uint16_t val1, rx_sd;
8612 struct bxe_softc *sc = params->sc;
8613 ELINK_DEBUG_P0(sc, "read status 8705\n");
8614 elink_cl45_read(sc, phy,
8615 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8616 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8617
8618 elink_cl45_read(sc, phy,
8619 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8620 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8621
8622 elink_cl45_read(sc, phy,
8623 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8624
8625 elink_cl45_read(sc, phy,
8626 MDIO_PMA_DEVAD, 0xc809, &val1);
8627 elink_cl45_read(sc, phy,
8628 MDIO_PMA_DEVAD, 0xc809, &val1);
8629
8630 ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x\n", val1);
8631 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
8632 if (link_up) {
8633 vars->line_speed = ELINK_SPEED_10000;
8634 elink_ext_phy_resolve_fc(phy, params, vars);
8635 }
8636 return link_up;
8637 }
8638
8639 /******************************************************************/
8640 /* SFP+ module Section */
8641 /******************************************************************/
elink_set_disable_pmd_transmit(struct elink_params * params,struct elink_phy * phy,uint8_t pmd_dis)8642 static void elink_set_disable_pmd_transmit(struct elink_params *params,
8643 struct elink_phy *phy,
8644 uint8_t pmd_dis)
8645 {
8646 struct bxe_softc *sc = params->sc;
8647 /* Disable transmitter only for bootcodes which can enable it afterwards
8648 * (for D3 link)
8649 */
8650 if (pmd_dis) {
8651 if (params->feature_config_flags &
8652 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
8653 ELINK_DEBUG_P0(sc, "Disabling PMD transmitter\n");
8654 } else {
8655 ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter\n");
8656 return;
8657 }
8658 } else
8659 ELINK_DEBUG_P0(sc, "Enabling PMD transmitter\n");
8660 elink_cl45_write(sc, phy,
8661 MDIO_PMA_DEVAD,
8662 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
8663 }
8664
elink_get_gpio_port(struct elink_params * params)8665 static uint8_t elink_get_gpio_port(struct elink_params *params)
8666 {
8667 uint8_t gpio_port;
8668 uint32_t swap_val, swap_override;
8669 struct bxe_softc *sc = params->sc;
8670 if (CHIP_IS_E2(sc))
8671 gpio_port = SC_PATH(sc);
8672 else
8673 gpio_port = params->port;
8674 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8675 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8676 return gpio_port ^ (swap_val && swap_override);
8677 }
8678
elink_sfp_e1e2_set_transmitter(struct elink_params * params,struct elink_phy * phy,uint8_t tx_en)8679 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
8680 struct elink_phy *phy,
8681 uint8_t tx_en)
8682 {
8683 uint16_t val;
8684 uint8_t port = params->port;
8685 struct bxe_softc *sc = params->sc;
8686 uint32_t tx_en_mode;
8687
8688 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
8689 tx_en_mode = REG_RD(sc, params->shmem_base +
8690 offsetof(struct shmem_region,
8691 dev_info.port_hw_config[port].sfp_ctrl)) &
8692 PORT_HW_CFG_TX_LASER_MASK;
8693 ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
8694 "mode = %x\n", tx_en, port, tx_en_mode);
8695 switch (tx_en_mode) {
8696 case PORT_HW_CFG_TX_LASER_MDIO:
8697
8698 elink_cl45_read(sc, phy,
8699 MDIO_PMA_DEVAD,
8700 MDIO_PMA_REG_PHY_IDENTIFIER,
8701 &val);
8702
8703 if (tx_en)
8704 val &= ~(1<<15);
8705 else
8706 val |= (1<<15);
8707
8708 elink_cl45_write(sc, phy,
8709 MDIO_PMA_DEVAD,
8710 MDIO_PMA_REG_PHY_IDENTIFIER,
8711 val);
8712 break;
8713 case PORT_HW_CFG_TX_LASER_GPIO0:
8714 case PORT_HW_CFG_TX_LASER_GPIO1:
8715 case PORT_HW_CFG_TX_LASER_GPIO2:
8716 case PORT_HW_CFG_TX_LASER_GPIO3:
8717 {
8718 uint16_t gpio_pin;
8719 uint8_t gpio_port, gpio_mode;
8720 if (tx_en)
8721 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
8722 else
8723 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
8724
8725 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
8726 gpio_port = elink_get_gpio_port(params);
8727 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
8728 break;
8729 }
8730 default:
8731 ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
8732 break;
8733 }
8734 }
8735
elink_sfp_set_transmitter(struct elink_params * params,struct elink_phy * phy,uint8_t tx_en)8736 static void elink_sfp_set_transmitter(struct elink_params *params,
8737 struct elink_phy *phy,
8738 uint8_t tx_en)
8739 {
8740 struct bxe_softc *sc = params->sc;
8741 ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d\n", tx_en);
8742 if (CHIP_IS_E3(sc))
8743 elink_sfp_e3_set_transmitter(params, phy, tx_en);
8744 else
8745 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
8746 }
8747
elink_8726_read_sfp_module_eeprom(struct elink_phy * phy,struct elink_params * params,uint8_t dev_addr,uint16_t addr,uint8_t byte_cnt,uint8_t * o_buf,uint8_t is_init)8748 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
8749 struct elink_params *params,
8750 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8751 uint8_t *o_buf, uint8_t is_init)
8752 {
8753 struct bxe_softc *sc = params->sc;
8754 uint16_t val = 0;
8755 uint16_t i;
8756 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8757 ELINK_DEBUG_P0(sc,
8758 "Reading from eeprom is limited to 0xf\n");
8759 return ELINK_STATUS_ERROR;
8760 }
8761 /* Set the read command byte count */
8762 elink_cl45_write(sc, phy,
8763 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8764 (byte_cnt | (dev_addr << 8)));
8765
8766 /* Set the read command address */
8767 elink_cl45_write(sc, phy,
8768 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8769 addr);
8770
8771 /* Activate read command */
8772 elink_cl45_write(sc, phy,
8773 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8774 0x2c0f);
8775
8776 /* Wait up to 500us for command complete status */
8777 for (i = 0; i < 100; i++) {
8778 elink_cl45_read(sc, phy,
8779 MDIO_PMA_DEVAD,
8780 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8781 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8782 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8783 break;
8784 DELAY(5);
8785 }
8786
8787 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8788 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8789 ELINK_DEBUG_P1(sc,
8790 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8791 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8792 return ELINK_STATUS_ERROR;
8793 }
8794
8795 /* Read the buffer */
8796 for (i = 0; i < byte_cnt; i++) {
8797 elink_cl45_read(sc, phy,
8798 MDIO_PMA_DEVAD,
8799 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
8800 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
8801 }
8802
8803 for (i = 0; i < 100; i++) {
8804 elink_cl45_read(sc, phy,
8805 MDIO_PMA_DEVAD,
8806 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8807 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8808 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8809 return ELINK_STATUS_OK;
8810 DELAY(1000 * 1);
8811 }
8812 return ELINK_STATUS_ERROR;
8813 }
8814
elink_warpcore_power_module(struct elink_params * params,uint8_t power)8815 static void elink_warpcore_power_module(struct elink_params *params,
8816 uint8_t power)
8817 {
8818 uint32_t pin_cfg;
8819 struct bxe_softc *sc = params->sc;
8820
8821 pin_cfg = (REG_RD(sc, params->shmem_base +
8822 offsetof(struct shmem_region,
8823 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8824 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8825 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8826
8827 if (pin_cfg == PIN_CFG_NA)
8828 return;
8829 ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d\n",
8830 power, pin_cfg);
8831 /* Low ==> corresponding SFP+ module is powered
8832 * high ==> the SFP+ module is powered down
8833 */
8834 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
8835 }
elink_warpcore_read_sfp_module_eeprom(struct elink_phy * phy,struct elink_params * params,uint8_t dev_addr,uint16_t addr,uint8_t byte_cnt,uint8_t * o_buf,uint8_t is_init)8836 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,
8837 struct elink_params *params,
8838 uint8_t dev_addr,
8839 uint16_t addr, uint8_t byte_cnt,
8840 uint8_t *o_buf, uint8_t is_init)
8841 {
8842 elink_status_t rc = ELINK_STATUS_OK;
8843 uint8_t i, j = 0, cnt = 0;
8844 uint32_t data_array[4];
8845 uint16_t addr32;
8846 struct bxe_softc *sc = params->sc;
8847
8848 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8849 ELINK_DEBUG_P0(sc,
8850 "Reading from eeprom is limited to 16 bytes\n");
8851 return ELINK_STATUS_ERROR;
8852 }
8853
8854 /* 4 byte aligned address */
8855 addr32 = addr & (~0x3);
8856 do {
8857 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
8858 elink_warpcore_power_module(params, 0);
8859 /* Note that 100us are not enough here */
8860 DELAY(1000 * 1);
8861 elink_warpcore_power_module(params, 1);
8862 }
8863
8864 elink_bsc_module_sel(params);
8865 rc = elink_bsc_read(sc, dev_addr, addr32, 0, byte_cnt,
8866 data_array);
8867 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
8868
8869 if (rc == ELINK_STATUS_OK) {
8870 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
8871 o_buf[j] = *((uint8_t *)data_array + i);
8872 j++;
8873 }
8874 }
8875
8876 return rc;
8877 }
8878
elink_8727_read_sfp_module_eeprom(struct elink_phy * phy,struct elink_params * params,uint8_t dev_addr,uint16_t addr,uint8_t byte_cnt,uint8_t * o_buf,uint8_t is_init)8879 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
8880 struct elink_params *params,
8881 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8882 uint8_t *o_buf, uint8_t is_init)
8883 {
8884 struct bxe_softc *sc = params->sc;
8885 uint16_t val, i;
8886
8887 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8888 ELINK_DEBUG_P0(sc,
8889 "Reading from eeprom is limited to 0xf\n");
8890 return ELINK_STATUS_ERROR;
8891 }
8892
8893 /* Set 2-wire transfer rate of SFP+ module EEPROM
8894 * to 100Khz since some DACs(direct attached cables) do
8895 * not work at 400Khz.
8896 */
8897 elink_cl45_write(sc, phy,
8898 MDIO_PMA_DEVAD,
8899 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8900 ((dev_addr << 8) | 1));
8901
8902 /* Need to read from 1.8000 to clear it */
8903 elink_cl45_read(sc, phy,
8904 MDIO_PMA_DEVAD,
8905 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8906 &val);
8907
8908 /* Set the read command byte count */
8909 elink_cl45_write(sc, phy,
8910 MDIO_PMA_DEVAD,
8911 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8912 ((byte_cnt < 2) ? 2 : byte_cnt));
8913
8914 /* Set the read command address */
8915 elink_cl45_write(sc, phy,
8916 MDIO_PMA_DEVAD,
8917 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8918 addr);
8919 /* Set the destination address */
8920 elink_cl45_write(sc, phy,
8921 MDIO_PMA_DEVAD,
8922 0x8004,
8923 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8924
8925 /* Activate read command */
8926 elink_cl45_write(sc, phy,
8927 MDIO_PMA_DEVAD,
8928 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8929 0x8002);
8930 /* Wait appropriate time for two-wire command to finish before
8931 * polling the status register
8932 */
8933 DELAY(1000 * 1);
8934
8935 /* Wait up to 500us for command complete status */
8936 for (i = 0; i < 100; i++) {
8937 elink_cl45_read(sc, phy,
8938 MDIO_PMA_DEVAD,
8939 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8940 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8941 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8942 break;
8943 DELAY(5);
8944 }
8945
8946 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8947 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8948 ELINK_DEBUG_P1(sc,
8949 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8950 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8951 return ELINK_STATUS_TIMEOUT;
8952 }
8953
8954 /* Read the buffer */
8955 for (i = 0; i < byte_cnt; i++) {
8956 elink_cl45_read(sc, phy,
8957 MDIO_PMA_DEVAD,
8958 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8959 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8960 }
8961
8962 for (i = 0; i < 100; i++) {
8963 elink_cl45_read(sc, phy,
8964 MDIO_PMA_DEVAD,
8965 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8966 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8967 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8968 return ELINK_STATUS_OK;
8969 DELAY(1000 * 1);
8970 }
8971
8972 return ELINK_STATUS_ERROR;
8973 }
elink_read_sfp_module_eeprom(struct elink_phy * phy,struct elink_params * params,uint8_t dev_addr,uint16_t addr,uint16_t byte_cnt,uint8_t * o_buf)8974 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
8975 struct elink_params *params, uint8_t dev_addr,
8976 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf)
8977 {
8978 elink_status_t rc = 0;
8979 struct bxe_softc *sc = params->sc;
8980 uint8_t xfer_size;
8981 uint8_t *user_data = o_buf;
8982 read_sfp_module_eeprom_func_p read_func;
8983 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8984 ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x\n", dev_addr);
8985 return ELINK_STATUS_ERROR;
8986 }
8987
8988 switch (phy->type) {
8989 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8990 read_func = elink_8726_read_sfp_module_eeprom;
8991 break;
8992 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8993 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8994 read_func = elink_8727_read_sfp_module_eeprom;
8995 break;
8996 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8997 read_func = elink_warpcore_read_sfp_module_eeprom;
8998 break;
8999 default:
9000 return ELINK_OP_NOT_SUPPORTED;
9001 }
9002
9003 while (!rc && (byte_cnt > 0)) {
9004 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
9005 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
9006 rc = read_func(phy, params, dev_addr, addr, xfer_size,
9007 user_data, 0);
9008 byte_cnt -= xfer_size;
9009 user_data += xfer_size;
9010 addr += xfer_size;
9011 }
9012 return rc;
9013 }
9014
elink_get_edc_mode(struct elink_phy * phy,struct elink_params * params,uint16_t * edc_mode)9015 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
9016 struct elink_params *params,
9017 uint16_t *edc_mode)
9018 {
9019 struct bxe_softc *sc = params->sc;
9020 uint32_t sync_offset = 0, phy_idx, media_types;
9021 uint8_t val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
9022 *edc_mode = ELINK_EDC_MODE_LIMITING;
9023 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
9024 /* First check for copper cable */
9025 if (elink_read_sfp_module_eeprom(phy,
9026 params,
9027 ELINK_I2C_DEV_ADDR_A0,
9028 0,
9029 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1,
9030 (uint8_t *)val) != 0) {
9031 ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM\n");
9032 return ELINK_STATUS_ERROR;
9033 }
9034 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
9035 params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] <<
9036 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
9037 elink_update_link_attr(params, params->link_attr_sync);
9038 switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) {
9039 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
9040 {
9041 uint8_t copper_module_type;
9042 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
9043 /* Check if its active cable (includes SFP+ module)
9044 * of passive cable
9045 */
9046 copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR];
9047 if (copper_module_type &
9048 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
9049 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n");
9050 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9051 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
9052 else
9053 check_limiting_mode = 1;
9054 } else {
9055 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
9056 /* Even in case PASSIVE_DAC indication is not set,
9057 * treat it as a passive DAC cable, since some cables
9058 * don't have this indication.
9059 */
9060 if (copper_module_type &
9061 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
9062 ELINK_DEBUG_P0(sc,
9063 "Passive Copper cable detected\n");
9064 } else {
9065 ELINK_DEBUG_P0(sc,
9066 "Unknown copper-cable-type\n");
9067 }
9068 }
9069 break;
9070 }
9071 case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
9072 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
9073 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
9074 check_limiting_mode = 1;
9075 /* Module is considered as 1G in case it's NOT compliant with
9076 * any 10G ethernet protocol, but is 1G Ethernet compliant.
9077 */
9078 if (((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] &
9079 (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK |
9080 ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK |
9081 ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
9082 (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
9083 ELINK_DEBUG_P0(sc, "1G SFP module detected\n");
9084 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
9085 if (phy->req_line_speed != ELINK_SPEED_1000) {
9086 uint8_t gport = params->port;
9087 phy->req_line_speed = ELINK_SPEED_1000;
9088 if (!CHIP_IS_E1x(sc)) {
9089 gport = SC_PATH(sc) +
9090 (params->port << 1);
9091 }
9092 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
9093 // " Current SFP module in port %d is not"
9094 // " compliant with 10G Ethernet\n",
9095 }
9096
9097 if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] &
9098 ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) {
9099 /* Some 1G-baseT modules will not link up,
9100 * unless TX_EN is toggled with long delay in
9101 * between.
9102 */
9103 elink_sfp_set_transmitter(params, phy, 0);
9104 DELAY(1000 * 40);
9105 elink_sfp_set_transmitter(params, phy, 1);
9106 }
9107 } else {
9108 int idx, cfg_idx = 0;
9109 ELINK_DEBUG_P0(sc, "10G Optic module detected\n");
9110 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
9111 if (params->phy[idx].type == phy->type) {
9112 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
9113 break;
9114 }
9115 }
9116 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
9117 phy->req_line_speed = params->req_line_speed[cfg_idx];
9118 }
9119 break;
9120 default:
9121 ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!\n",
9122 val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]);
9123 return ELINK_STATUS_ERROR;
9124 }
9125 sync_offset = params->shmem_base +
9126 offsetof(struct shmem_region,
9127 dev_info.port_hw_config[params->port].media_type);
9128 media_types = REG_RD(sc, sync_offset);
9129 /* Update media type for non-PMF sync */
9130 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
9131 if (&(params->phy[phy_idx]) == phy) {
9132 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
9133 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
9134 media_types |= ((phy->media_type &
9135 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
9136 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
9137 break;
9138 }
9139 }
9140 REG_WR(sc, sync_offset, media_types);
9141 if (check_limiting_mode) {
9142 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
9143 if (elink_read_sfp_module_eeprom(phy,
9144 params,
9145 ELINK_I2C_DEV_ADDR_A0,
9146 ELINK_SFP_EEPROM_OPTIONS_ADDR,
9147 ELINK_SFP_EEPROM_OPTIONS_SIZE,
9148 options) != 0) {
9149 ELINK_DEBUG_P0(sc,
9150 "Failed to read Option field from module EEPROM\n");
9151 return ELINK_STATUS_ERROR;
9152 }
9153 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
9154 *edc_mode = ELINK_EDC_MODE_LINEAR;
9155 else
9156 *edc_mode = ELINK_EDC_MODE_LIMITING;
9157 }
9158 ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x\n", *edc_mode);
9159 return ELINK_STATUS_OK;
9160 }
9161 /* This function read the relevant field from the module (SFP+), and verify it
9162 * is compliant with this board
9163 */
elink_verify_sfp_module(struct elink_phy * phy,struct elink_params * params)9164 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
9165 struct elink_params *params)
9166 {
9167 struct bxe_softc *sc = params->sc;
9168 uint32_t val, cmd;
9169 uint32_t fw_resp, fw_cmd_param;
9170 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1];
9171 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1];
9172 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
9173 val = REG_RD(sc, params->shmem_base +
9174 offsetof(struct shmem_region, dev_info.
9175 port_feature_config[params->port].config));
9176 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9177 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
9178 ELINK_DEBUG_P0(sc, "NOT enforcing module verification\n");
9179 return ELINK_STATUS_OK;
9180 }
9181
9182 if (params->feature_config_flags &
9183 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
9184 /* Use specific phy request */
9185 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
9186 } else if (params->feature_config_flags &
9187 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
9188 /* Use first phy request only in case of non-dual media*/
9189 if (ELINK_DUAL_MEDIA(params)) {
9190 ELINK_DEBUG_P0(sc,
9191 "FW does not support OPT MDL verification\n");
9192 return ELINK_STATUS_ERROR;
9193 }
9194 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
9195 } else {
9196 /* No support in OPT MDL detection */
9197 ELINK_DEBUG_P0(sc,
9198 "FW does not support OPT MDL verification\n");
9199 return ELINK_STATUS_ERROR;
9200 }
9201
9202 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
9203 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
9204 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
9205 ELINK_DEBUG_P0(sc, "Approved module\n");
9206 return ELINK_STATUS_OK;
9207 }
9208
9209 /* Format the warning message */
9210 if (elink_read_sfp_module_eeprom(phy,
9211 params,
9212 ELINK_I2C_DEV_ADDR_A0,
9213 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
9214 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
9215 (uint8_t *)vendor_name))
9216 vendor_name[0] = '\0';
9217 else
9218 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
9219 if (elink_read_sfp_module_eeprom(phy,
9220 params,
9221 ELINK_I2C_DEV_ADDR_A0,
9222 ELINK_SFP_EEPROM_PART_NO_ADDR,
9223 ELINK_SFP_EEPROM_PART_NO_SIZE,
9224 (uint8_t *)vendor_pn))
9225 vendor_pn[0] = '\0';
9226 else
9227 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
9228
9229 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
9230 // " Port %d from %s part number %s\n",
9231
9232 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
9233 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
9234 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
9235 return ELINK_STATUS_ERROR;
9236 }
9237
elink_wait_for_sfp_module_initialized(struct elink_phy * phy,struct elink_params * params)9238 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,
9239 struct elink_params *params)
9240
9241 {
9242 uint8_t val;
9243 elink_status_t rc;
9244 struct bxe_softc *sc = params->sc;
9245 uint16_t timeout;
9246 /* Initialization time after hot-plug may take up to 300ms for
9247 * some phys type ( e.g. JDSU )
9248 */
9249
9250 for (timeout = 0; timeout < 60; timeout++) {
9251 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9252 rc = elink_warpcore_read_sfp_module_eeprom(
9253 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
9254 1);
9255 else
9256 rc = elink_read_sfp_module_eeprom(phy, params,
9257 ELINK_I2C_DEV_ADDR_A0,
9258 1, 1, &val);
9259 if (rc == 0) {
9260 ELINK_DEBUG_P1(sc,
9261 "SFP+ module initialization took %d ms\n",
9262 timeout * 5);
9263 return ELINK_STATUS_OK;
9264 }
9265 DELAY(1000 * 5);
9266 }
9267 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
9268 1, 1, &val);
9269 return rc;
9270 }
9271
elink_8727_power_module(struct bxe_softc * sc,struct elink_phy * phy,uint8_t is_power_up)9272 static void elink_8727_power_module(struct bxe_softc *sc,
9273 struct elink_phy *phy,
9274 uint8_t is_power_up) {
9275 /* Make sure GPIOs are not using for LED mode */
9276 uint16_t val;
9277 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
9278 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
9279 * output
9280 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
9281 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
9282 * where the 1st bit is the over-current(only input), and 2nd bit is
9283 * for power( only output )
9284 *
9285 * In case of NOC feature is disabled and power is up, set GPIO control
9286 * as input to enable listening of over-current indication
9287 */
9288 if (phy->flags & ELINK_FLAGS_NOC)
9289 return;
9290 if (is_power_up)
9291 val = (1<<4);
9292 else
9293 /* Set GPIO control to OUTPUT, and set the power bit
9294 * to according to the is_power_up
9295 */
9296 val = (1<<1);
9297
9298 elink_cl45_write(sc, phy,
9299 MDIO_PMA_DEVAD,
9300 MDIO_PMA_REG_8727_GPIO_CTRL,
9301 val);
9302 }
9303
elink_8726_set_limiting_mode(struct bxe_softc * sc,struct elink_phy * phy,uint16_t edc_mode)9304 static elink_status_t elink_8726_set_limiting_mode(struct bxe_softc *sc,
9305 struct elink_phy *phy,
9306 uint16_t edc_mode)
9307 {
9308 uint16_t cur_limiting_mode;
9309
9310 elink_cl45_read(sc, phy,
9311 MDIO_PMA_DEVAD,
9312 MDIO_PMA_REG_ROM_VER2,
9313 &cur_limiting_mode);
9314 ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x\n",
9315 cur_limiting_mode);
9316
9317 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
9318 ELINK_DEBUG_P0(sc, "Setting LIMITING MODE\n");
9319 elink_cl45_write(sc, phy,
9320 MDIO_PMA_DEVAD,
9321 MDIO_PMA_REG_ROM_VER2,
9322 ELINK_EDC_MODE_LIMITING);
9323 } else { /* LRM mode ( default )*/
9324
9325 ELINK_DEBUG_P0(sc, "Setting LRM MODE\n");
9326
9327 /* Changing to LRM mode takes quite few seconds. So do it only
9328 * if current mode is limiting (default is LRM)
9329 */
9330 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
9331 return ELINK_STATUS_OK;
9332
9333 elink_cl45_write(sc, phy,
9334 MDIO_PMA_DEVAD,
9335 MDIO_PMA_REG_LRM_MODE,
9336 0);
9337 elink_cl45_write(sc, phy,
9338 MDIO_PMA_DEVAD,
9339 MDIO_PMA_REG_ROM_VER2,
9340 0x128);
9341 elink_cl45_write(sc, phy,
9342 MDIO_PMA_DEVAD,
9343 MDIO_PMA_REG_MISC_CTRL0,
9344 0x4008);
9345 elink_cl45_write(sc, phy,
9346 MDIO_PMA_DEVAD,
9347 MDIO_PMA_REG_LRM_MODE,
9348 0xaaaa);
9349 }
9350 return ELINK_STATUS_OK;
9351 }
9352
elink_8727_set_limiting_mode(struct bxe_softc * sc,struct elink_phy * phy,uint16_t edc_mode)9353 static elink_status_t elink_8727_set_limiting_mode(struct bxe_softc *sc,
9354 struct elink_phy *phy,
9355 uint16_t edc_mode)
9356 {
9357 uint16_t phy_identifier;
9358 uint16_t rom_ver2_val;
9359 elink_cl45_read(sc, phy,
9360 MDIO_PMA_DEVAD,
9361 MDIO_PMA_REG_PHY_IDENTIFIER,
9362 &phy_identifier);
9363
9364 elink_cl45_write(sc, phy,
9365 MDIO_PMA_DEVAD,
9366 MDIO_PMA_REG_PHY_IDENTIFIER,
9367 (phy_identifier & ~(1<<9)));
9368
9369 elink_cl45_read(sc, phy,
9370 MDIO_PMA_DEVAD,
9371 MDIO_PMA_REG_ROM_VER2,
9372 &rom_ver2_val);
9373 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
9374 elink_cl45_write(sc, phy,
9375 MDIO_PMA_DEVAD,
9376 MDIO_PMA_REG_ROM_VER2,
9377 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
9378
9379 elink_cl45_write(sc, phy,
9380 MDIO_PMA_DEVAD,
9381 MDIO_PMA_REG_PHY_IDENTIFIER,
9382 (phy_identifier | (1<<9)));
9383
9384 return ELINK_STATUS_OK;
9385 }
9386
elink_8727_specific_func(struct elink_phy * phy,struct elink_params * params,uint32_t action)9387 static void elink_8727_specific_func(struct elink_phy *phy,
9388 struct elink_params *params,
9389 uint32_t action)
9390 {
9391 struct bxe_softc *sc = params->sc;
9392 uint16_t val;
9393 switch (action) {
9394 case ELINK_DISABLE_TX:
9395 elink_sfp_set_transmitter(params, phy, 0);
9396 break;
9397 case ELINK_ENABLE_TX:
9398 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
9399 elink_sfp_set_transmitter(params, phy, 1);
9400 break;
9401 case ELINK_PHY_INIT:
9402 elink_cl45_write(sc, phy,
9403 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9404 (1<<2) | (1<<5));
9405 elink_cl45_write(sc, phy,
9406 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9407 0);
9408 elink_cl45_write(sc, phy,
9409 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
9410 /* Make MOD_ABS give interrupt on change */
9411 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9412 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9413 &val);
9414 val |= (1<<12);
9415 if (phy->flags & ELINK_FLAGS_NOC)
9416 val |= (3<<5);
9417 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9418 * status which reflect SFP+ module over-current
9419 */
9420 if (!(phy->flags & ELINK_FLAGS_NOC))
9421 val &= 0xff8f; /* Reset bits 4-6 */
9422 elink_cl45_write(sc, phy,
9423 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9424 val);
9425 break;
9426 default:
9427 ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727\n",
9428 action);
9429 return;
9430 }
9431 }
9432
elink_set_e1e2_module_fault_led(struct elink_params * params,uint8_t gpio_mode)9433 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
9434 uint8_t gpio_mode)
9435 {
9436 struct bxe_softc *sc = params->sc;
9437
9438 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
9439 offsetof(struct shmem_region,
9440 dev_info.port_hw_config[params->port].sfp_ctrl)) &
9441 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
9442 switch (fault_led_gpio) {
9443 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
9444 return;
9445 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
9446 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
9447 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
9448 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
9449 {
9450 uint8_t gpio_port = elink_get_gpio_port(params);
9451 uint16_t gpio_pin = fault_led_gpio -
9452 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
9453 ELINK_DEBUG_P3(sc, "Set fault module-detected led "
9454 "pin %x port %x mode %x\n",
9455 gpio_pin, gpio_port, gpio_mode);
9456 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
9457 }
9458 break;
9459 default:
9460 ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x\n",
9461 fault_led_gpio);
9462 }
9463 }
9464
elink_set_e3_module_fault_led(struct elink_params * params,uint8_t gpio_mode)9465 static void elink_set_e3_module_fault_led(struct elink_params *params,
9466 uint8_t gpio_mode)
9467 {
9468 uint32_t pin_cfg;
9469 uint8_t port = params->port;
9470 struct bxe_softc *sc = params->sc;
9471 pin_cfg = (REG_RD(sc, params->shmem_base +
9472 offsetof(struct shmem_region,
9473 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
9474 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
9475 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
9476 ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d\n",
9477 gpio_mode, pin_cfg);
9478 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
9479 }
9480
elink_set_sfp_module_fault_led(struct elink_params * params,uint8_t gpio_mode)9481 static void elink_set_sfp_module_fault_led(struct elink_params *params,
9482 uint8_t gpio_mode)
9483 {
9484 struct bxe_softc *sc = params->sc;
9485 ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d\n", gpio_mode);
9486 if (CHIP_IS_E3(sc)) {
9487 /* Low ==> if SFP+ module is supported otherwise
9488 * High ==> if SFP+ module is not on the approved vendor list
9489 */
9490 elink_set_e3_module_fault_led(params, gpio_mode);
9491 } else
9492 elink_set_e1e2_module_fault_led(params, gpio_mode);
9493 }
9494
elink_warpcore_hw_reset(struct elink_phy * phy,struct elink_params * params)9495 static void elink_warpcore_hw_reset(struct elink_phy *phy,
9496 struct elink_params *params)
9497 {
9498 struct bxe_softc *sc = params->sc;
9499 elink_warpcore_power_module(params, 0);
9500 /* Put Warpcore in low power mode */
9501 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
9502
9503 /* Put LCPLL in low power mode */
9504 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
9505 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
9506 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
9507 }
9508
elink_power_sfp_module(struct elink_params * params,struct elink_phy * phy,uint8_t power)9509 static void elink_power_sfp_module(struct elink_params *params,
9510 struct elink_phy *phy,
9511 uint8_t power)
9512 {
9513 struct bxe_softc *sc = params->sc;
9514 ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x\n", power);
9515
9516 switch (phy->type) {
9517 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9519 elink_8727_power_module(params->sc, phy, power);
9520 break;
9521 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9522 elink_warpcore_power_module(params, power);
9523 break;
9524 default:
9525 break;
9526 }
9527 }
elink_warpcore_set_limiting_mode(struct elink_params * params,struct elink_phy * phy,uint16_t edc_mode)9528 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
9529 struct elink_phy *phy,
9530 uint16_t edc_mode)
9531 {
9532 uint16_t val = 0;
9533 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9534 struct bxe_softc *sc = params->sc;
9535
9536 uint8_t lane = elink_get_warpcore_lane(phy, params);
9537 /* This is a global register which controls all lanes */
9538 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9539 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9540 val &= ~(0xf << (lane << 2));
9541
9542 switch (edc_mode) {
9543 case ELINK_EDC_MODE_LINEAR:
9544 case ELINK_EDC_MODE_LIMITING:
9545 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9546 break;
9547 case ELINK_EDC_MODE_PASSIVE_DAC:
9548 case ELINK_EDC_MODE_ACTIVE_DAC:
9549 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
9550 break;
9551 default:
9552 break;
9553 }
9554
9555 val |= (mode << (lane << 2));
9556 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
9557 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
9558 /* A must read */
9559 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9560 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9561
9562 /* Restart microcode to re-read the new mode */
9563 elink_warpcore_reset_lane(sc, phy, 1);
9564 elink_warpcore_reset_lane(sc, phy, 0);
9565
9566 }
9567
elink_set_limiting_mode(struct elink_params * params,struct elink_phy * phy,uint16_t edc_mode)9568 static void elink_set_limiting_mode(struct elink_params *params,
9569 struct elink_phy *phy,
9570 uint16_t edc_mode)
9571 {
9572 switch (phy->type) {
9573 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
9574 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
9575 break;
9576 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9577 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9578 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
9579 break;
9580 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9581 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
9582 break;
9583 }
9584 }
9585
elink_sfp_module_detection(struct elink_phy * phy,struct elink_params * params)9586 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
9587 struct elink_params *params)
9588 {
9589 struct bxe_softc *sc = params->sc;
9590 uint16_t edc_mode;
9591 elink_status_t rc = ELINK_STATUS_OK;
9592
9593 uint32_t val = REG_RD(sc, params->shmem_base +
9594 offsetof(struct shmem_region, dev_info.
9595 port_feature_config[params->port].config));
9596 /* Enabled transmitter by default */
9597 elink_sfp_set_transmitter(params, phy, 1);
9598 ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d\n",
9599 params->port);
9600 /* Power up module */
9601 elink_power_sfp_module(params, phy, 1);
9602 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
9603 ELINK_DEBUG_P0(sc, "Failed to get valid module type\n");
9604 return ELINK_STATUS_ERROR;
9605 } else if (elink_verify_sfp_module(phy, params) != 0) {
9606 /* Check SFP+ module compatibility */
9607 ELINK_DEBUG_P0(sc, "Module verification failed!!\n");
9608 rc = ELINK_STATUS_ERROR;
9609 /* Turn on fault module-detected led */
9610 elink_set_sfp_module_fault_led(params,
9611 MISC_REGISTERS_GPIO_HIGH);
9612
9613 /* Check if need to power down the SFP+ module */
9614 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9615 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
9616 ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!\n");
9617 elink_power_sfp_module(params, phy, 0);
9618 return rc;
9619 }
9620 } else {
9621 /* Turn off fault module-detected led */
9622 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
9623 }
9624
9625 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
9626 * is done automatically
9627 */
9628 elink_set_limiting_mode(params, phy, edc_mode);
9629
9630 /* Disable transmit for this module if the module is not approved, and
9631 * laser needs to be disabled.
9632 */
9633 if ((rc != 0) &&
9634 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9635 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
9636 elink_sfp_set_transmitter(params, phy, 0);
9637
9638 return rc;
9639 }
9640
elink_handle_module_detect_int(struct elink_params * params)9641 void elink_handle_module_detect_int(struct elink_params *params)
9642 {
9643 struct bxe_softc *sc = params->sc;
9644 struct elink_phy *phy;
9645 uint32_t gpio_val;
9646 uint8_t gpio_num, gpio_port;
9647 if (CHIP_IS_E3(sc)) {
9648 phy = ¶ms->phy[ELINK_INT_PHY];
9649 /* Always enable TX laser,will be disabled in case of fault */
9650 elink_sfp_set_transmitter(params, phy, 1);
9651 } else {
9652 phy = ¶ms->phy[ELINK_EXT_PHY1];
9653 }
9654 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,
9655 params->port, &gpio_num, &gpio_port) ==
9656 ELINK_STATUS_ERROR) {
9657 ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config\n");
9658 return;
9659 }
9660
9661 /* Set valid module led off */
9662 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
9663
9664 /* Get current gpio val reflecting module plugged in / out*/
9665 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
9666
9667 /* Call the handling function in case module is detected */
9668 if (gpio_val == 0) {
9669 elink_set_mdio_emac_per_phy(sc, params);
9670 elink_set_aer_mmd(params, phy);
9671
9672 elink_power_sfp_module(params, phy, 1);
9673 elink_cb_gpio_int_write(sc, gpio_num,
9674 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
9675 gpio_port);
9676 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
9677 elink_sfp_module_detection(phy, params);
9678 if (CHIP_IS_E3(sc)) {
9679 uint16_t rx_tx_in_reset;
9680 /* In case WC is out of reset, reconfigure the
9681 * link speed while taking into account 1G
9682 * module limitation.
9683 */
9684 elink_cl45_read(sc, phy,
9685 MDIO_WC_DEVAD,
9686 MDIO_WC_REG_DIGITAL5_MISC6,
9687 &rx_tx_in_reset);
9688 if ((!rx_tx_in_reset) &&
9689 (params->link_flags &
9690 ELINK_PHY_INITIALIZED)) {
9691 elink_warpcore_reset_lane(sc, phy, 1);
9692 elink_warpcore_config_sfi(phy, params);
9693 elink_warpcore_reset_lane(sc, phy, 0);
9694 }
9695 }
9696 } else {
9697 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
9698 }
9699 } else {
9700 elink_cb_gpio_int_write(sc, gpio_num,
9701 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
9702 gpio_port);
9703 /* Module was plugged out.
9704 * Disable transmit for this module
9705 */
9706 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
9707 }
9708 }
9709
9710 /******************************************************************/
9711 /* Used by 8706 and 8727 */
9712 /******************************************************************/
elink_sfp_mask_fault(struct bxe_softc * sc,struct elink_phy * phy,uint16_t alarm_status_offset,uint16_t alarm_ctrl_offset)9713 static void elink_sfp_mask_fault(struct bxe_softc *sc,
9714 struct elink_phy *phy,
9715 uint16_t alarm_status_offset,
9716 uint16_t alarm_ctrl_offset)
9717 {
9718 uint16_t alarm_status, val;
9719 elink_cl45_read(sc, phy,
9720 MDIO_PMA_DEVAD, alarm_status_offset,
9721 &alarm_status);
9722 elink_cl45_read(sc, phy,
9723 MDIO_PMA_DEVAD, alarm_status_offset,
9724 &alarm_status);
9725 /* Mask or enable the fault event. */
9726 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
9727 if (alarm_status & (1<<0))
9728 val &= ~(1<<0);
9729 else
9730 val |= (1<<0);
9731 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
9732 }
9733 /******************************************************************/
9734 /* common BCM8706/BCM8726 PHY SECTION */
9735 /******************************************************************/
elink_8706_8726_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)9736 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
9737 struct elink_params *params,
9738 struct elink_vars *vars)
9739 {
9740 uint8_t link_up = 0;
9741 uint16_t val1, val2, rx_sd, pcs_status;
9742 struct bxe_softc *sc = params->sc;
9743 ELINK_DEBUG_P0(sc, "XGXS 8706/8726\n");
9744 /* Clear RX Alarm*/
9745 elink_cl45_read(sc, phy,
9746 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
9747
9748 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
9749 MDIO_PMA_LASI_TXCTRL);
9750
9751 /* Clear LASI indication*/
9752 elink_cl45_read(sc, phy,
9753 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9754 elink_cl45_read(sc, phy,
9755 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
9756 ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
9757
9758 elink_cl45_read(sc, phy,
9759 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
9760 elink_cl45_read(sc, phy,
9761 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
9762 elink_cl45_read(sc, phy,
9763 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9764 elink_cl45_read(sc, phy,
9765 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9766
9767 ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
9768 " link_status 0x%x\n", rx_sd, pcs_status, val2);
9769 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
9770 * are set, or if the autoneg bit 1 is set
9771 */
9772 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
9773 if (link_up) {
9774 if (val2 & (1<<1))
9775 vars->line_speed = ELINK_SPEED_1000;
9776 else
9777 vars->line_speed = ELINK_SPEED_10000;
9778 elink_ext_phy_resolve_fc(phy, params, vars);
9779 vars->duplex = DUPLEX_FULL;
9780 }
9781
9782 /* Capture 10G link fault. Read twice to clear stale value. */
9783 if (vars->line_speed == ELINK_SPEED_10000) {
9784 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9785 MDIO_PMA_LASI_TXSTAT, &val1);
9786 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9787 MDIO_PMA_LASI_TXSTAT, &val1);
9788 if (val1 & (1<<0))
9789 vars->fault_detected = 1;
9790 }
9791
9792 return link_up;
9793 }
9794
9795 /******************************************************************/
9796 /* BCM8706 PHY SECTION */
9797 /******************************************************************/
elink_8706_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)9798 static uint8_t elink_8706_config_init(struct elink_phy *phy,
9799 struct elink_params *params,
9800 struct elink_vars *vars)
9801 {
9802 uint32_t tx_en_mode;
9803 uint16_t cnt, val, tmp1;
9804 struct bxe_softc *sc = params->sc;
9805
9806 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9807 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9808 /* HW reset */
9809 elink_ext_phy_hw_reset(sc, params->port);
9810 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
9811 elink_wait_reset_complete(sc, phy, params);
9812
9813 /* Wait until fw is loaded */
9814 for (cnt = 0; cnt < 100; cnt++) {
9815 elink_cl45_read(sc, phy,
9816 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
9817 if (val)
9818 break;
9819 DELAY(1000 * 10);
9820 }
9821 ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms\n", cnt);
9822 if ((params->feature_config_flags &
9823 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9824 uint8_t i;
9825 uint16_t reg;
9826 for (i = 0; i < 4; i++) {
9827 reg = MDIO_XS_8706_REG_BANK_RX0 +
9828 i*(MDIO_XS_8706_REG_BANK_RX1 -
9829 MDIO_XS_8706_REG_BANK_RX0);
9830 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
9831 /* Clear first 3 bits of the control */
9832 val &= ~0x7;
9833 /* Set control bits according to configuration */
9834 val |= (phy->rx_preemphasis[i] & 0x7);
9835 ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BCM8706"
9836 " reg 0x%x <-- val 0x%x\n", reg, val);
9837 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
9838 }
9839 }
9840 /* Force speed */
9841 if (phy->req_line_speed == ELINK_SPEED_10000) {
9842 ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps\n");
9843
9844 elink_cl45_write(sc, phy,
9845 MDIO_PMA_DEVAD,
9846 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
9847 elink_cl45_write(sc, phy,
9848 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9849 0);
9850 /* Arm LASI for link and Tx fault. */
9851 elink_cl45_write(sc, phy,
9852 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
9853 } else {
9854 /* Force 1Gbps using autoneg with 1G advertisement */
9855
9856 /* Allow CL37 through CL73 */
9857 ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg\n");
9858 elink_cl45_write(sc, phy,
9859 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9860
9861 /* Enable Full-Duplex advertisement on CL37 */
9862 elink_cl45_write(sc, phy,
9863 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
9864 /* Enable CL37 AN */
9865 elink_cl45_write(sc, phy,
9866 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9867 /* 1G support */
9868 elink_cl45_write(sc, phy,
9869 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
9870
9871 /* Enable clause 73 AN */
9872 elink_cl45_write(sc, phy,
9873 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9874 elink_cl45_write(sc, phy,
9875 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9876 0x0400);
9877 elink_cl45_write(sc, phy,
9878 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9879 0x0004);
9880 }
9881 elink_save_bcm_spirom_ver(sc, phy, params->port);
9882
9883 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9884 * power mode, if TX Laser is disabled
9885 */
9886
9887 tx_en_mode = REG_RD(sc, params->shmem_base +
9888 offsetof(struct shmem_region,
9889 dev_info.port_hw_config[params->port].sfp_ctrl))
9890 & PORT_HW_CFG_TX_LASER_MASK;
9891
9892 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9893 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
9894 elink_cl45_read(sc, phy,
9895 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
9896 tmp1 |= 0x1;
9897 elink_cl45_write(sc, phy,
9898 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
9899 }
9900
9901 return ELINK_STATUS_OK;
9902 }
9903
elink_8706_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)9904 static elink_status_t elink_8706_read_status(struct elink_phy *phy,
9905 struct elink_params *params,
9906 struct elink_vars *vars)
9907 {
9908 return elink_8706_8726_read_status(phy, params, vars);
9909 }
9910
9911 /******************************************************************/
9912 /* BCM8726 PHY SECTION */
9913 /******************************************************************/
elink_8726_config_loopback(struct elink_phy * phy,struct elink_params * params)9914 static void elink_8726_config_loopback(struct elink_phy *phy,
9915 struct elink_params *params)
9916 {
9917 struct bxe_softc *sc = params->sc;
9918 ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726\n");
9919 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9920 }
9921
elink_8726_external_rom_boot(struct elink_phy * phy,struct elink_params * params)9922 static void elink_8726_external_rom_boot(struct elink_phy *phy,
9923 struct elink_params *params)
9924 {
9925 struct bxe_softc *sc = params->sc;
9926 /* Need to wait 100ms after reset */
9927 DELAY(1000 * 100);
9928
9929 /* Micro controller re-boot */
9930 elink_cl45_write(sc, phy,
9931 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9932
9933 /* Set soft reset */
9934 elink_cl45_write(sc, phy,
9935 MDIO_PMA_DEVAD,
9936 MDIO_PMA_REG_GEN_CTRL,
9937 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9938
9939 elink_cl45_write(sc, phy,
9940 MDIO_PMA_DEVAD,
9941 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9942
9943 elink_cl45_write(sc, phy,
9944 MDIO_PMA_DEVAD,
9945 MDIO_PMA_REG_GEN_CTRL,
9946 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9947
9948 /* Wait for 150ms for microcode load */
9949 DELAY(1000 * 150);
9950
9951 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9952 elink_cl45_write(sc, phy,
9953 MDIO_PMA_DEVAD,
9954 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9955
9956 DELAY(1000 * 200);
9957 elink_save_bcm_spirom_ver(sc, phy, params->port);
9958 }
9959
elink_8726_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)9960 static uint8_t elink_8726_read_status(struct elink_phy *phy,
9961 struct elink_params *params,
9962 struct elink_vars *vars)
9963 {
9964 struct bxe_softc *sc = params->sc;
9965 uint16_t val1;
9966 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
9967 if (link_up) {
9968 elink_cl45_read(sc, phy,
9969 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9970 &val1);
9971 if (val1 & (1<<15)) {
9972 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
9973 link_up = 0;
9974 vars->line_speed = 0;
9975 }
9976 }
9977 return link_up;
9978 }
9979
9980
elink_8726_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)9981 static elink_status_t elink_8726_config_init(struct elink_phy *phy,
9982 struct elink_params *params,
9983 struct elink_vars *vars)
9984 {
9985 struct bxe_softc *sc = params->sc;
9986 ELINK_DEBUG_P0(sc, "Initializing BCM8726\n");
9987
9988 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9989 elink_wait_reset_complete(sc, phy, params);
9990
9991 elink_8726_external_rom_boot(phy, params);
9992
9993 /* Need to call module detected on initialization since the module
9994 * detection triggered by actual module insertion might occur before
9995 * driver is loaded, and when driver is loaded, it reset all
9996 * registers, including the transmitter
9997 */
9998 elink_sfp_module_detection(phy, params);
9999
10000 if (phy->req_line_speed == ELINK_SPEED_1000) {
10001 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
10002 elink_cl45_write(sc, phy,
10003 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
10004 elink_cl45_write(sc, phy,
10005 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
10006 elink_cl45_write(sc, phy,
10007 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
10008 elink_cl45_write(sc, phy,
10009 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
10010 0x400);
10011 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10012 (phy->speed_cap_mask &
10013 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
10014 ((phy->speed_cap_mask &
10015 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
10016 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
10017 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
10018 /* Set Flow control */
10019 elink_ext_phy_set_pause(params, phy, vars);
10020 elink_cl45_write(sc, phy,
10021 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
10022 elink_cl45_write(sc, phy,
10023 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
10024 elink_cl45_write(sc, phy,
10025 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
10026 elink_cl45_write(sc, phy,
10027 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
10028 elink_cl45_write(sc, phy,
10029 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
10030 /* Enable RX-ALARM control to receive interrupt for 1G speed
10031 * change
10032 */
10033 elink_cl45_write(sc, phy,
10034 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
10035 elink_cl45_write(sc, phy,
10036 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
10037 0x400);
10038
10039 } else { /* Default 10G. Set only LASI control */
10040 elink_cl45_write(sc, phy,
10041 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
10042 }
10043
10044 /* Set TX PreEmphasis if needed */
10045 if ((params->feature_config_flags &
10046 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
10047 ELINK_DEBUG_P2(sc,
10048 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10049 phy->tx_preemphasis[0],
10050 phy->tx_preemphasis[1]);
10051 elink_cl45_write(sc, phy,
10052 MDIO_PMA_DEVAD,
10053 MDIO_PMA_REG_8726_TX_CTRL1,
10054 phy->tx_preemphasis[0]);
10055
10056 elink_cl45_write(sc, phy,
10057 MDIO_PMA_DEVAD,
10058 MDIO_PMA_REG_8726_TX_CTRL2,
10059 phy->tx_preemphasis[1]);
10060 }
10061
10062 return ELINK_STATUS_OK;
10063
10064 }
10065
elink_8726_link_reset(struct elink_phy * phy,struct elink_params * params)10066 static void elink_8726_link_reset(struct elink_phy *phy,
10067 struct elink_params *params)
10068 {
10069 struct bxe_softc *sc = params->sc;
10070 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port);
10071 /* Set serial boot control for external load */
10072 elink_cl45_write(sc, phy,
10073 MDIO_PMA_DEVAD,
10074 MDIO_PMA_REG_GEN_CTRL, 0x0001);
10075 }
10076
10077 /******************************************************************/
10078 /* BCM8727 PHY SECTION */
10079 /******************************************************************/
10080
elink_8727_set_link_led(struct elink_phy * phy,struct elink_params * params,uint8_t mode)10081 static void elink_8727_set_link_led(struct elink_phy *phy,
10082 struct elink_params *params, uint8_t mode)
10083 {
10084 struct bxe_softc *sc = params->sc;
10085 uint16_t led_mode_bitmask = 0;
10086 uint16_t gpio_pins_bitmask = 0;
10087 uint16_t val;
10088 /* Only NOC flavor requires to set the LED specifically */
10089 if (!(phy->flags & ELINK_FLAGS_NOC))
10090 return;
10091 switch (mode) {
10092 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10093 case ELINK_LED_MODE_OFF:
10094 led_mode_bitmask = 0;
10095 gpio_pins_bitmask = 0x03;
10096 break;
10097 case ELINK_LED_MODE_ON:
10098 led_mode_bitmask = 0;
10099 gpio_pins_bitmask = 0x02;
10100 break;
10101 case ELINK_LED_MODE_OPER:
10102 led_mode_bitmask = 0x60;
10103 gpio_pins_bitmask = 0x11;
10104 break;
10105 }
10106 elink_cl45_read(sc, phy,
10107 MDIO_PMA_DEVAD,
10108 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
10109 &val);
10110 val &= 0xff8f;
10111 val |= led_mode_bitmask;
10112 elink_cl45_write(sc, phy,
10113 MDIO_PMA_DEVAD,
10114 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
10115 val);
10116 elink_cl45_read(sc, phy,
10117 MDIO_PMA_DEVAD,
10118 MDIO_PMA_REG_8727_GPIO_CTRL,
10119 &val);
10120 val &= 0xffe0;
10121 val |= gpio_pins_bitmask;
10122 elink_cl45_write(sc, phy,
10123 MDIO_PMA_DEVAD,
10124 MDIO_PMA_REG_8727_GPIO_CTRL,
10125 val);
10126 }
elink_8727_hw_reset(struct elink_phy * phy,struct elink_params * params)10127 static void elink_8727_hw_reset(struct elink_phy *phy,
10128 struct elink_params *params) {
10129 uint32_t swap_val, swap_override;
10130 uint8_t port;
10131 /* The PHY reset is controlled by GPIO 1. Fake the port number
10132 * to cancel the swap done in set_gpio()
10133 */
10134 struct bxe_softc *sc = params->sc;
10135 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
10136 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
10137 port = (swap_val && swap_override) ^ 1;
10138 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
10139 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
10140 }
10141
elink_8727_config_speed(struct elink_phy * phy,struct elink_params * params)10142 static void elink_8727_config_speed(struct elink_phy *phy,
10143 struct elink_params *params)
10144 {
10145 struct bxe_softc *sc = params->sc;
10146 uint16_t tmp1, val;
10147 /* Set option 1G speed */
10148 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
10149 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
10150 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
10151 elink_cl45_write(sc, phy,
10152 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
10153 elink_cl45_write(sc, phy,
10154 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
10155 elink_cl45_read(sc, phy,
10156 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
10157 ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);
10158 /* Power down the XAUI until link is up in case of dual-media
10159 * and 1G
10160 */
10161 if (ELINK_DUAL_MEDIA(params)) {
10162 elink_cl45_read(sc, phy,
10163 MDIO_PMA_DEVAD,
10164 MDIO_PMA_REG_8727_PCS_GP, &val);
10165 val |= (3<<10);
10166 elink_cl45_write(sc, phy,
10167 MDIO_PMA_DEVAD,
10168 MDIO_PMA_REG_8727_PCS_GP, val);
10169 }
10170 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10171 ((phy->speed_cap_mask &
10172 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
10173 ((phy->speed_cap_mask &
10174 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
10175 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
10176
10177 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
10178 elink_cl45_write(sc, phy,
10179 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
10180 elink_cl45_write(sc, phy,
10181 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
10182 } else {
10183 /* Since the 8727 has only single reset pin, need to set the 10G
10184 * registers although it is default
10185 */
10186 elink_cl45_write(sc, phy,
10187 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
10188 0x0020);
10189 elink_cl45_write(sc, phy,
10190 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
10191 elink_cl45_write(sc, phy,
10192 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
10193 elink_cl45_write(sc, phy,
10194 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
10195 0x0008);
10196 }
10197 }
10198
elink_8727_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)10199 static elink_status_t elink_8727_config_init(struct elink_phy *phy,
10200 struct elink_params *params,
10201 struct elink_vars *vars)
10202 {
10203 uint32_t tx_en_mode;
10204 uint16_t tmp1, mod_abs, tmp2;
10205 struct bxe_softc *sc = params->sc;
10206 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
10207
10208 elink_wait_reset_complete(sc, phy, params);
10209
10210 ELINK_DEBUG_P0(sc, "Initializing BCM8727\n");
10211
10212 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
10213 /* Initially configure MOD_ABS to interrupt when module is
10214 * presence( bit 8)
10215 */
10216 elink_cl45_read(sc, phy,
10217 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10218 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
10219 * When the EDC is off it locks onto a reference clock and avoids
10220 * becoming 'lost'
10221 */
10222 mod_abs &= ~(1<<8);
10223 if (!(phy->flags & ELINK_FLAGS_NOC))
10224 mod_abs &= ~(1<<9);
10225 elink_cl45_write(sc, phy,
10226 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10227
10228 /* Enable/Disable PHY transmitter output */
10229 elink_set_disable_pmd_transmit(params, phy, 0);
10230
10231 elink_8727_power_module(sc, phy, 1);
10232
10233 elink_cl45_read(sc, phy,
10234 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
10235
10236 elink_cl45_read(sc, phy,
10237 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
10238
10239 elink_8727_config_speed(phy, params);
10240
10241
10242 /* Set TX PreEmphasis if needed */
10243 if ((params->feature_config_flags &
10244 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
10245 ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10246 phy->tx_preemphasis[0],
10247 phy->tx_preemphasis[1]);
10248 elink_cl45_write(sc, phy,
10249 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
10250 phy->tx_preemphasis[0]);
10251
10252 elink_cl45_write(sc, phy,
10253 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
10254 phy->tx_preemphasis[1]);
10255 }
10256
10257 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
10258 * power mode, if TX Laser is disabled
10259 */
10260 tx_en_mode = REG_RD(sc, params->shmem_base +
10261 offsetof(struct shmem_region,
10262 dev_info.port_hw_config[params->port].sfp_ctrl))
10263 & PORT_HW_CFG_TX_LASER_MASK;
10264
10265 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
10266
10267 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
10268 elink_cl45_read(sc, phy,
10269 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
10270 tmp2 |= 0x1000;
10271 tmp2 &= 0xFFEF;
10272 elink_cl45_write(sc, phy,
10273 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
10274 elink_cl45_read(sc, phy,
10275 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10276 &tmp2);
10277 elink_cl45_write(sc, phy,
10278 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10279 (tmp2 & 0x7fff));
10280 }
10281
10282 return ELINK_STATUS_OK;
10283 }
10284
elink_8727_handle_mod_abs(struct elink_phy * phy,struct elink_params * params)10285 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
10286 struct elink_params *params)
10287 {
10288 struct bxe_softc *sc = params->sc;
10289 uint16_t mod_abs, rx_alarm_status;
10290 uint32_t val = REG_RD(sc, params->shmem_base +
10291 offsetof(struct shmem_region, dev_info.
10292 port_feature_config[params->port].
10293 config));
10294 elink_cl45_read(sc, phy,
10295 MDIO_PMA_DEVAD,
10296 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10297 if (mod_abs & (1<<8)) {
10298
10299 /* Module is absent */
10300 ELINK_DEBUG_P0(sc,
10301 "MOD_ABS indication show module is absent\n");
10302 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
10303 /* 1. Set mod_abs to detect next module
10304 * presence event
10305 * 2. Set EDC off by setting OPTXLOS signal input to low
10306 * (bit 9).
10307 * When the EDC is off it locks onto a reference clock and
10308 * avoids becoming 'lost'.
10309 */
10310 mod_abs &= ~(1<<8);
10311 if (!(phy->flags & ELINK_FLAGS_NOC))
10312 mod_abs &= ~(1<<9);
10313 elink_cl45_write(sc, phy,
10314 MDIO_PMA_DEVAD,
10315 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10316
10317 /* Clear RX alarm since it stays up as long as
10318 * the mod_abs wasn't changed
10319 */
10320 elink_cl45_read(sc, phy,
10321 MDIO_PMA_DEVAD,
10322 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10323
10324 } else {
10325 /* Module is present */
10326 ELINK_DEBUG_P0(sc,
10327 "MOD_ABS indication show module is present\n");
10328 /* First disable transmitter, and if the module is ok, the
10329 * module_detection will enable it
10330 * 1. Set mod_abs to detect next module absent event ( bit 8)
10331 * 2. Restore the default polarity of the OPRXLOS signal and
10332 * this signal will then correctly indicate the presence or
10333 * absence of the Rx signal. (bit 9)
10334 */
10335 mod_abs |= (1<<8);
10336 if (!(phy->flags & ELINK_FLAGS_NOC))
10337 mod_abs |= (1<<9);
10338 elink_cl45_write(sc, phy,
10339 MDIO_PMA_DEVAD,
10340 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10341
10342 /* Clear RX alarm since it stays up as long as the mod_abs
10343 * wasn't changed. This is need to be done before calling the
10344 * module detection, otherwise it will clear* the link update
10345 * alarm
10346 */
10347 elink_cl45_read(sc, phy,
10348 MDIO_PMA_DEVAD,
10349 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10350
10351
10352 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
10353 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
10354 elink_sfp_set_transmitter(params, phy, 0);
10355
10356 if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
10357 elink_sfp_module_detection(phy, params);
10358 else
10359 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
10360
10361 /* Reconfigure link speed based on module type limitations */
10362 elink_8727_config_speed(phy, params);
10363 }
10364
10365 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n",
10366 rx_alarm_status);
10367 /* No need to check link status in case of module plugged in/out */
10368 }
10369
elink_8727_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)10370 static uint8_t elink_8727_read_status(struct elink_phy *phy,
10371 struct elink_params *params,
10372 struct elink_vars *vars)
10373
10374 {
10375 struct bxe_softc *sc = params->sc;
10376 uint8_t link_up = 0;
10377 uint16_t link_status = 0;
10378 uint16_t rx_alarm_status, lasi_ctrl, val1;
10379
10380 /* If PHY is not initialized, do not check link status */
10381 elink_cl45_read(sc, phy,
10382 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
10383 &lasi_ctrl);
10384 if (!lasi_ctrl)
10385 return 0;
10386
10387 /* Check the LASI on Rx */
10388 elink_cl45_read(sc, phy,
10389 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
10390 &rx_alarm_status);
10391 vars->line_speed = 0;
10392 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
10393
10394 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
10395 MDIO_PMA_LASI_TXCTRL);
10396
10397 elink_cl45_read(sc, phy,
10398 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10399
10400 ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x\n", val1);
10401
10402 /* Clear MSG-OUT */
10403 elink_cl45_read(sc, phy,
10404 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
10405
10406 /* If a module is present and there is need to check
10407 * for over current
10408 */
10409 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
10410 /* Check over-current using 8727 GPIO0 input*/
10411 elink_cl45_read(sc, phy,
10412 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
10413 &val1);
10414
10415 if ((val1 & (1<<8)) == 0) {
10416 uint8_t oc_port = params->port;
10417 if (!CHIP_IS_E1x(sc))
10418 oc_port = SC_PATH(sc) + (params->port << 1);
10419 ELINK_DEBUG_P1(sc,
10420 "8727 Power fault has been detected on port %d\n",
10421 oc_port);
10422 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
10423 // "been detected and the power to "
10424 // "that SFP+ module has been removed "
10425 // "to prevent failure of the card. "
10426 // "Please remove the SFP+ module and "
10427 // "restart the system to clear this "
10428 // "error.\n",
10429 /* Disable all RX_ALARMs except for mod_abs */
10430 elink_cl45_write(sc, phy,
10431 MDIO_PMA_DEVAD,
10432 MDIO_PMA_LASI_RXCTRL, (1<<5));
10433
10434 elink_cl45_read(sc, phy,
10435 MDIO_PMA_DEVAD,
10436 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
10437 /* Wait for module_absent_event */
10438 val1 |= (1<<8);
10439 elink_cl45_write(sc, phy,
10440 MDIO_PMA_DEVAD,
10441 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
10442 /* Clear RX alarm */
10443 elink_cl45_read(sc, phy,
10444 MDIO_PMA_DEVAD,
10445 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10446 elink_8727_power_module(params->sc, phy, 0);
10447 return 0;
10448 }
10449 } /* Over current check */
10450
10451 /* When module absent bit is set, check module */
10452 if (rx_alarm_status & (1<<5)) {
10453 elink_8727_handle_mod_abs(phy, params);
10454 /* Enable all mod_abs and link detection bits */
10455 elink_cl45_write(sc, phy,
10456 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
10457 ((1<<5) | (1<<2)));
10458 }
10459
10460 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
10461 ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser\n");
10462 elink_sfp_set_transmitter(params, phy, 1);
10463 } else {
10464 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
10465 return 0;
10466 }
10467
10468 elink_cl45_read(sc, phy,
10469 MDIO_PMA_DEVAD,
10470 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
10471
10472 /* Bits 0..2 --> speed detected,
10473 * Bits 13..15--> link is down
10474 */
10475 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
10476 link_up = 1;
10477 vars->line_speed = ELINK_SPEED_10000;
10478 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
10479 params->port);
10480 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
10481 link_up = 1;
10482 vars->line_speed = ELINK_SPEED_1000;
10483 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
10484 params->port);
10485 } else {
10486 link_up = 0;
10487 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
10488 params->port);
10489 }
10490
10491 /* Capture 10G link fault. */
10492 if (vars->line_speed == ELINK_SPEED_10000) {
10493 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10494 MDIO_PMA_LASI_TXSTAT, &val1);
10495
10496 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10497 MDIO_PMA_LASI_TXSTAT, &val1);
10498
10499 if (val1 & (1<<0)) {
10500 vars->fault_detected = 1;
10501 }
10502 }
10503
10504 if (link_up) {
10505 elink_ext_phy_resolve_fc(phy, params, vars);
10506 vars->duplex = DUPLEX_FULL;
10507 ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex);
10508 }
10509
10510 if ((ELINK_DUAL_MEDIA(params)) &&
10511 (phy->req_line_speed == ELINK_SPEED_1000)) {
10512 elink_cl45_read(sc, phy,
10513 MDIO_PMA_DEVAD,
10514 MDIO_PMA_REG_8727_PCS_GP, &val1);
10515 /* In case of dual-media board and 1G, power up the XAUI side,
10516 * otherwise power it down. For 10G it is done automatically
10517 */
10518 if (link_up)
10519 val1 &= ~(3<<10);
10520 else
10521 val1 |= (3<<10);
10522 elink_cl45_write(sc, phy,
10523 MDIO_PMA_DEVAD,
10524 MDIO_PMA_REG_8727_PCS_GP, val1);
10525 }
10526 return link_up;
10527 }
10528
elink_8727_link_reset(struct elink_phy * phy,struct elink_params * params)10529 static void elink_8727_link_reset(struct elink_phy *phy,
10530 struct elink_params *params)
10531 {
10532 struct bxe_softc *sc = params->sc;
10533
10534 /* Enable/Disable PHY transmitter output */
10535 elink_set_disable_pmd_transmit(params, phy, 1);
10536
10537 /* Disable Transmitter */
10538 elink_sfp_set_transmitter(params, phy, 0);
10539 /* Clear LASI */
10540 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
10541
10542 }
10543
10544 /******************************************************************/
10545 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
10546 /******************************************************************/
elink_is_8483x_8485x(struct elink_phy * phy)10547 static int elink_is_8483x_8485x(struct elink_phy *phy)
10548 {
10549 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10550 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
10551 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
10552 }
10553
elink_save_848xx_spirom_version(struct elink_phy * phy,struct bxe_softc * sc,uint8_t port)10554 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
10555 struct bxe_softc *sc,
10556 uint8_t port)
10557 {
10558 uint16_t val, fw_ver2, cnt, i;
10559 static struct elink_reg_set reg_set[] = {
10560 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
10561 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
10562 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
10563 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
10564 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
10565 };
10566 uint16_t fw_ver1;
10567
10568 if (elink_is_8483x_8485x(phy)) {
10569 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
10570 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
10571 phy->ver_addr);
10572 } else {
10573 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
10574 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
10575 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10576 elink_cl45_write(sc, phy, reg_set[i].devad,
10577 reg_set[i].reg, reg_set[i].val);
10578
10579 for (cnt = 0; cnt < 100; cnt++) {
10580 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10581 if (val & 1)
10582 break;
10583 DELAY(5);
10584 }
10585 if (cnt == 100) {
10586 ELINK_DEBUG_P0(sc, "Unable to read 848xx "
10587 "phy fw version(1)\n");
10588 elink_save_spirom_version(sc, port, 0,
10589 phy->ver_addr);
10590 return;
10591 }
10592
10593
10594 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
10595 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
10596 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
10597 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
10598 for (cnt = 0; cnt < 100; cnt++) {
10599 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10600 if (val & 1)
10601 break;
10602 DELAY(5);
10603 }
10604 if (cnt == 100) {
10605 ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
10606 "version(2)\n");
10607 elink_save_spirom_version(sc, port, 0,
10608 phy->ver_addr);
10609 return;
10610 }
10611
10612 /* lower 16 bits of the register SPI_FW_STATUS */
10613 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
10614 /* upper 16 bits of register SPI_FW_STATUS */
10615 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
10616
10617 elink_save_spirom_version(sc, port, (fw_ver2<<16) | fw_ver1,
10618 phy->ver_addr);
10619 }
10620
10621 }
elink_848xx_set_led(struct bxe_softc * sc,struct elink_phy * phy)10622 static void elink_848xx_set_led(struct bxe_softc *sc,
10623 struct elink_phy *phy)
10624 {
10625 uint16_t val, offset, i;
10626 static struct elink_reg_set reg_set[] = {
10627 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
10628 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
10629 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
10630 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
10631 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
10632 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
10633 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
10634 };
10635 /* PHYC_CTL_LED_CTL */
10636 elink_cl45_read(sc, phy,
10637 MDIO_PMA_DEVAD,
10638 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10639 val &= 0xFE00;
10640 val |= 0x0092;
10641
10642 elink_cl45_write(sc, phy,
10643 MDIO_PMA_DEVAD,
10644 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10645
10646 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10647 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
10648 reg_set[i].val);
10649
10650 if (elink_is_8483x_8485x(phy))
10651 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
10652 else
10653 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
10654
10655 /* stretch_en for LED3*/
10656 elink_cl45_read_or_write(sc, phy,
10657 MDIO_PMA_DEVAD, offset,
10658 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
10659 }
10660
elink_848xx_specific_func(struct elink_phy * phy,struct elink_params * params,uint32_t action)10661 static void elink_848xx_specific_func(struct elink_phy *phy,
10662 struct elink_params *params,
10663 uint32_t action)
10664 {
10665 struct bxe_softc *sc = params->sc;
10666 switch (action) {
10667 case ELINK_PHY_INIT:
10668 if (!elink_is_8483x_8485x(phy)) {
10669 /* Save spirom version */
10670 elink_save_848xx_spirom_version(phy, sc, params->port);
10671 }
10672 /* This phy uses the NIG latch mechanism since link indication
10673 * arrives through its LED4 and not via its LASI signal, so we
10674 * get steady signal instead of clear on read
10675 */
10676 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4,
10677 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
10678
10679 elink_848xx_set_led(sc, phy);
10680 break;
10681 }
10682 }
10683
elink_848xx_cmn_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)10684 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
10685 struct elink_params *params,
10686 struct elink_vars *vars)
10687 {
10688 struct bxe_softc *sc = params->sc;
10689 uint16_t autoneg_val, an_1000_val, an_10_100_val;
10690
10691 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
10692 elink_cl45_write(sc, phy,
10693 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
10694
10695 /* set 1000 speed advertisement */
10696 elink_cl45_read(sc, phy,
10697 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10698 &an_1000_val);
10699
10700 elink_ext_phy_set_pause(params, phy, vars);
10701 elink_cl45_read(sc, phy,
10702 MDIO_AN_DEVAD,
10703 MDIO_AN_REG_8481_LEGACY_AN_ADV,
10704 &an_10_100_val);
10705 elink_cl45_read(sc, phy,
10706 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10707 &autoneg_val);
10708 /* Disable forced speed */
10709 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10710 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
10711
10712 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10713 (phy->speed_cap_mask &
10714 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10715 (phy->req_line_speed == ELINK_SPEED_1000)) {
10716 an_1000_val |= (1<<8);
10717 autoneg_val |= (1<<9 | 1<<12);
10718 if (phy->req_duplex == DUPLEX_FULL)
10719 an_1000_val |= (1<<9);
10720 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
10721 } else
10722 an_1000_val &= ~((1<<8) | (1<<9));
10723
10724 elink_cl45_write(sc, phy,
10725 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10726 an_1000_val);
10727
10728 /* Set 10/100 speed advertisement */
10729 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10730 if (phy->speed_cap_mask &
10731 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10732 /* Enable autoneg and restart autoneg for legacy speeds
10733 */
10734 autoneg_val |= (1<<9 | 1<<12);
10735 an_10_100_val |= (1<<8);
10736 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
10737 }
10738
10739 if (phy->speed_cap_mask &
10740 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10741 /* Enable autoneg and restart autoneg for legacy speeds
10742 */
10743 autoneg_val |= (1<<9 | 1<<12);
10744 an_10_100_val |= (1<<7);
10745 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
10746 }
10747
10748 if ((phy->speed_cap_mask &
10749 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
10750 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
10751 an_10_100_val |= (1<<6);
10752 autoneg_val |= (1<<9 | 1<<12);
10753 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
10754 }
10755
10756 if ((phy->speed_cap_mask &
10757 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
10758 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
10759 an_10_100_val |= (1<<5);
10760 autoneg_val |= (1<<9 | 1<<12);
10761 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
10762 }
10763 }
10764
10765 /* Only 10/100 are allowed to work in FORCE mode */
10766 if ((phy->req_line_speed == ELINK_SPEED_100) &&
10767 (phy->supported &
10768 (ELINK_SUPPORTED_100baseT_Half |
10769 ELINK_SUPPORTED_100baseT_Full))) {
10770 autoneg_val |= (1<<13);
10771 /* Enabled AUTO-MDIX when autoneg is disabled */
10772 elink_cl45_write(sc, phy,
10773 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10774 (1<<15 | 1<<9 | 7<<0));
10775 /* The PHY needs this set even for forced link. */
10776 an_10_100_val |= (1<<8) | (1<<7);
10777 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
10778 }
10779 if ((phy->req_line_speed == ELINK_SPEED_10) &&
10780 (phy->supported &
10781 (ELINK_SUPPORTED_10baseT_Half |
10782 ELINK_SUPPORTED_10baseT_Full))) {
10783 /* Enabled AUTO-MDIX when autoneg is disabled */
10784 elink_cl45_write(sc, phy,
10785 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10786 (1<<15 | 1<<9 | 7<<0));
10787 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
10788 }
10789
10790 elink_cl45_write(sc, phy,
10791 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
10792 an_10_100_val);
10793
10794 if (phy->req_duplex == DUPLEX_FULL)
10795 autoneg_val |= (1<<8);
10796
10797 /* Always write this if this is not 84833/4.
10798 * For 84833/4, write it only when it's a forced speed.
10799 */
10800 if (!elink_is_8483x_8485x(phy) ||
10801 ((autoneg_val & (1<<12)) == 0))
10802 elink_cl45_write(sc, phy,
10803 MDIO_AN_DEVAD,
10804 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
10805
10806 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10807 (phy->speed_cap_mask &
10808 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
10809 (phy->req_line_speed == ELINK_SPEED_10000)) {
10810 ELINK_DEBUG_P0(sc, "Advertising 10G\n");
10811 /* Restart autoneg for 10G*/
10812
10813 elink_cl45_read_or_write(
10814 sc, phy,
10815 MDIO_AN_DEVAD,
10816 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10817 0x1000);
10818 elink_cl45_write(sc, phy,
10819 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
10820 0x3200);
10821 } else
10822 elink_cl45_write(sc, phy,
10823 MDIO_AN_DEVAD,
10824 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10825 1);
10826
10827 return ELINK_STATUS_OK;
10828 }
10829
elink_8481_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)10830 static elink_status_t elink_8481_config_init(struct elink_phy *phy,
10831 struct elink_params *params,
10832 struct elink_vars *vars)
10833 {
10834 struct bxe_softc *sc = params->sc;
10835 /* Restore normal power mode*/
10836 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10837 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10838
10839 /* HW reset */
10840 elink_ext_phy_hw_reset(sc, params->port);
10841 elink_wait_reset_complete(sc, phy, params);
10842
10843 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10844 return elink_848xx_cmn_config_init(phy, params, vars);
10845 }
10846
10847 #define PHY848xx_CMDHDLR_WAIT 300
10848 #define PHY848xx_CMDHDLR_MAX_ARGS 5
10849
elink_84858_cmd_hdlr(struct elink_phy * phy,struct elink_params * params,uint16_t fw_cmd,uint16_t cmd_args[],int argc)10850 static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,
10851 struct elink_params *params,
10852 uint16_t fw_cmd,
10853 uint16_t cmd_args[], int argc)
10854 {
10855 int idx;
10856 uint16_t val;
10857 struct bxe_softc *sc = params->sc;
10858
10859 /* Step 1: Poll the STATUS register to see whether the previous command
10860 * is in progress or the system is busy (CMD_IN_PROGRESS or
10861 * SYSTEM_BUSY). If previous command is in progress or system is busy,
10862 * check again until the previous command finishes execution and the
10863 * system is available for taking command
10864 */
10865
10866 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10867 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10868 MDIO_848xx_CMD_HDLR_STATUS, &val);
10869 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
10870 (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
10871 break;
10872 DELAY(1000 * 1);
10873 }
10874 if (idx >= PHY848xx_CMDHDLR_WAIT) {
10875 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n");
10876 return ELINK_STATUS_ERROR;
10877 }
10878
10879 /* Step2: If any parameters are required for the function, write them
10880 * to the required DATA registers
10881 */
10882
10883 for (idx = 0; idx < argc; idx++) {
10884 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10885 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10886 cmd_args[idx]);
10887 }
10888
10889 /* Step3: When the firmware is ready for commands, write the 'Command
10890 * code' to the CMD register
10891 */
10892 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10893 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10894
10895 /* Step4: Once the command has been written, poll the STATUS register
10896 * to check whether the command has completed (CMD_COMPLETED_PASS/
10897 * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
10898 */
10899
10900 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10901 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10902 MDIO_848xx_CMD_HDLR_STATUS, &val);
10903 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
10904 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
10905 break;
10906 DELAY(1000 * 1);
10907 }
10908 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10909 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
10910 ELINK_DEBUG_P0(sc, "FW cmd failed.\n");
10911 return ELINK_STATUS_ERROR;
10912 }
10913 /* Step5: Once the command has completed, read the specficied DATA
10914 * registers for any saved results for the command, if applicable
10915 */
10916
10917 /* Gather returning data */
10918 for (idx = 0; idx < argc; idx++) {
10919 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10920 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10921 &cmd_args[idx]);
10922 }
10923
10924 return ELINK_STATUS_OK;
10925 }
10926
elink_84833_cmd_hdlr(struct elink_phy * phy,struct elink_params * params,uint16_t fw_cmd,uint16_t cmd_args[],int argc,int process)10927 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
10928 struct elink_params *params, uint16_t fw_cmd,
10929 uint16_t cmd_args[], int argc, int process)
10930 {
10931 int idx;
10932 uint16_t val;
10933 struct bxe_softc *sc = params->sc;
10934 elink_status_t rc = ELINK_STATUS_OK;
10935
10936 if (process == PHY84833_MB_PROCESS2) {
10937 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10938 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10939 MDIO_848xx_CMD_HDLR_STATUS,
10940 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10941 }
10942
10943 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10944 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10945 MDIO_848xx_CMD_HDLR_STATUS, &val);
10946 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10947 break;
10948 DELAY(1000 * 1);
10949 }
10950 if (idx >= PHY848xx_CMDHDLR_WAIT) {
10951 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n");
10952 /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR
10953 * clear the status to CMD_CLEAR_COMPLETE
10954 */
10955 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
10956 val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
10957 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10958 MDIO_848xx_CMD_HDLR_STATUS,
10959 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10960 }
10961 return ELINK_STATUS_ERROR;
10962 }
10963 if (process == PHY84833_MB_PROCESS1 ||
10964 process == PHY84833_MB_PROCESS2) {
10965 /* Prepare argument(s) */
10966 for (idx = 0; idx < argc; idx++) {
10967 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10968 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10969 cmd_args[idx]);
10970 }
10971 }
10972
10973 /* Issue command */
10974 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10975 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10976 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10977 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10978 MDIO_848xx_CMD_HDLR_STATUS, &val);
10979 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10980 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10981 break;
10982 DELAY(1000 * 1);
10983 }
10984 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10985 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10986 ELINK_DEBUG_P0(sc, "FW cmd failed.\n");
10987 rc = ELINK_STATUS_ERROR;
10988 }
10989 if (process == PHY84833_MB_PROCESS3 && rc == ELINK_STATUS_OK) {
10990 /* Gather returning data */
10991 for (idx = 0; idx < argc; idx++) {
10992 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10993 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10994 &cmd_args[idx]);
10995 }
10996 }
10997 if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
10998 val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
10999 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11000 MDIO_848xx_CMD_HDLR_STATUS,
11001 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
11002 }
11003 return rc;
11004 }
11005
elink_848xx_cmd_hdlr(struct elink_phy * phy,struct elink_params * params,uint16_t fw_cmd,uint16_t cmd_args[],int argc,int process)11006 static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,
11007 struct elink_params *params,
11008 uint16_t fw_cmd,
11009 uint16_t cmd_args[], int argc,
11010 int process)
11011 {
11012 struct bxe_softc *sc = params->sc;
11013
11014 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
11015 (REG_RD(sc, params->shmem2_base +
11016 offsetof(struct shmem2_region,
11017 link_attr_sync[params->port])) & LINK_ATTR_84858)) {
11018 return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
11019 argc);
11020 } else {
11021 return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
11022 argc, process);
11023 }
11024 }
11025
elink_848xx_pair_swap_cfg(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)11026 static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,
11027 struct elink_params *params,
11028 struct elink_vars *vars)
11029 {
11030 uint32_t pair_swap;
11031 uint16_t data[PHY848xx_CMDHDLR_MAX_ARGS];
11032 elink_status_t status;
11033 struct bxe_softc *sc = params->sc;
11034
11035 /* Check for configuration. */
11036 pair_swap = REG_RD(sc, params->shmem_base +
11037 offsetof(struct shmem_region,
11038 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
11039 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
11040
11041 if (pair_swap == 0)
11042 return ELINK_STATUS_OK;
11043
11044 /* Only the second argument is used for this command */
11045 data[1] = (uint16_t)pair_swap;
11046
11047 status = elink_848xx_cmd_hdlr(phy, params,
11048 PHY848xx_CMD_SET_PAIR_SWAP, data,
11049 2, PHY84833_MB_PROCESS2);
11050 if (status == ELINK_STATUS_OK)
11051 ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x\n", data[1]);
11052
11053 return status;
11054 }
11055
elink_84833_get_reset_gpios(struct bxe_softc * sc,uint32_t shmem_base_path[],uint32_t chip_id)11056 static uint8_t elink_84833_get_reset_gpios(struct bxe_softc *sc,
11057 uint32_t shmem_base_path[],
11058 uint32_t chip_id)
11059 {
11060 uint32_t reset_pin[2];
11061 uint32_t idx;
11062 uint8_t reset_gpios;
11063 if (CHIP_IS_E3(sc)) {
11064 /* Assume that these will be GPIOs, not EPIOs. */
11065 for (idx = 0; idx < 2; idx++) {
11066 /* Map config param to register bit. */
11067 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
11068 offsetof(struct shmem_region,
11069 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
11070 reset_pin[idx] = (reset_pin[idx] &
11071 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11072 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11073 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
11074 reset_pin[idx] = (1 << reset_pin[idx]);
11075 }
11076 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
11077 } else {
11078 /* E2, look from diff place of shmem. */
11079 for (idx = 0; idx < 2; idx++) {
11080 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
11081 offsetof(struct shmem_region,
11082 dev_info.port_hw_config[0].default_cfg));
11083 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
11084 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
11085 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
11086 reset_pin[idx] = (1 << reset_pin[idx]);
11087 }
11088 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
11089 }
11090
11091 return reset_gpios;
11092 }
11093
elink_84833_hw_reset_phy(struct elink_phy * phy,struct elink_params * params)11094 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
11095 struct elink_params *params)
11096 {
11097 struct bxe_softc *sc = params->sc;
11098 uint8_t reset_gpios;
11099 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
11100 offsetof(struct shmem2_region,
11101 other_shmem_base_addr));
11102
11103 uint32_t shmem_base_path[2];
11104
11105 /* Work around for 84833 LED failure inside RESET status */
11106 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11107 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
11108 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
11109 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11110 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
11111 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
11112
11113 shmem_base_path[0] = params->shmem_base;
11114 shmem_base_path[1] = other_shmem_base_addr;
11115
11116 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
11117 params->chip_id);
11118
11119 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
11120 DELAY(10);
11121 ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x\n",
11122 reset_gpios);
11123
11124 return ELINK_STATUS_OK;
11125 }
11126
elink_8483x_disable_eee(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)11127 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
11128 struct elink_params *params,
11129 struct elink_vars *vars)
11130 {
11131 elink_status_t rc;
11132 struct bxe_softc *sc = params->sc;
11133 uint16_t cmd_args = 0;
11134
11135 ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE\n");
11136
11137 /* Prevent Phy from working in EEE and advertising it */
11138 rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
11139 &cmd_args, 1, PHY84833_MB_PROCESS1);
11140 if (rc != ELINK_STATUS_OK) {
11141 ELINK_DEBUG_P0(sc, "EEE disable failed.\n");
11142 return rc;
11143 }
11144
11145 return elink_eee_disable(phy, params, vars);
11146 }
11147
elink_8483x_enable_eee(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)11148 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
11149 struct elink_params *params,
11150 struct elink_vars *vars)
11151 {
11152 elink_status_t rc;
11153 struct bxe_softc *sc = params->sc;
11154 uint16_t cmd_args = 1;
11155
11156 rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
11157 &cmd_args, 1, PHY84833_MB_PROCESS1);
11158 if (rc != ELINK_STATUS_OK) {
11159 ELINK_DEBUG_P0(sc, "EEE enable failed.\n");
11160 return rc;
11161 }
11162
11163 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
11164 }
11165
11166 #define PHY84833_CONSTANT_LATENCY 1193
elink_848x3_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)11167 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
11168 struct elink_params *params,
11169 struct elink_vars *vars)
11170 {
11171 struct bxe_softc *sc = params->sc;
11172 uint8_t port, initialize = 1;
11173 uint16_t val;
11174 uint32_t actual_phy_selection;
11175 uint16_t cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
11176 elink_status_t rc = ELINK_STATUS_OK;
11177
11178 DELAY(1000 * 1);
11179
11180 if (!(CHIP_IS_E1x(sc)))
11181 port = SC_PATH(sc);
11182 else
11183 port = params->port;
11184
11185 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11186 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
11187 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11188 port);
11189 } else {
11190 /* MDIO reset */
11191 elink_cl45_write(sc, phy,
11192 MDIO_PMA_DEVAD,
11193 MDIO_PMA_REG_CTRL, 0x8000);
11194 }
11195
11196 elink_wait_reset_complete(sc, phy, params);
11197
11198 /* Wait for GPHY to come out of reset */
11199 DELAY(1000 * 50);
11200 if (!elink_is_8483x_8485x(phy)) {
11201 /* BCM84823 requires that XGXS links up first @ 10G for normal
11202 * behavior.
11203 */
11204 uint16_t temp;
11205 temp = vars->line_speed;
11206 vars->line_speed = ELINK_SPEED_10000;
11207 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
11208 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
11209 vars->line_speed = temp;
11210 }
11211 /* Check if this is actually BCM84858 */
11212 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
11213 uint16_t hw_rev;
11214
11215 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11216 MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
11217 if (hw_rev == BCM84858_PHY_ID) {
11218 params->link_attr_sync |= LINK_ATTR_84858;
11219 elink_update_link_attr(params, params->link_attr_sync);
11220 }
11221 }
11222
11223 /* Set dual-media configuration according to configuration */
11224 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11225 MDIO_CTL_REG_84823_MEDIA, &val);
11226 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
11227 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
11228 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
11229 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
11230 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
11231
11232 if (CHIP_IS_E3(sc)) {
11233 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
11234 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
11235 } else {
11236 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
11237 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
11238 }
11239
11240 actual_phy_selection = elink_phy_selection(params);
11241
11242 switch (actual_phy_selection) {
11243 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
11244 /* Do nothing. Essentially this is like the priority copper */
11245 break;
11246 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11247 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
11248 break;
11249 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11250 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
11251 break;
11252 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11253 /* Do nothing here. The first PHY won't be initialized at all */
11254 break;
11255 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11256 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
11257 initialize = 0;
11258 break;
11259 }
11260 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
11261 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
11262
11263 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11264 MDIO_CTL_REG_84823_MEDIA, val);
11265 ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n",
11266 params->multi_phy_config, val);
11267
11268 if (elink_is_8483x_8485x(phy)) {
11269 elink_848xx_pair_swap_cfg(phy, params, vars);
11270
11271 /* Keep AutogrEEEn disabled. */
11272 cmd_args[0] = 0x0;
11273 cmd_args[1] = 0x0;
11274 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
11275 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
11276 rc = elink_848xx_cmd_hdlr(phy, params,
11277 PHY848xx_CMD_SET_EEE_MODE, cmd_args,
11278 4, PHY84833_MB_PROCESS1);
11279 if (rc != ELINK_STATUS_OK)
11280 ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.\n");
11281 }
11282 if (initialize)
11283 rc = elink_848xx_cmn_config_init(phy, params, vars);
11284 else
11285 elink_save_848xx_spirom_version(phy, sc, params->port);
11286 /* 84833 PHY has a better feature and doesn't need to support this. */
11287 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11288 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
11289 offsetof(struct shmem_region,
11290 dev_info.port_hw_config[params->port].default_cfg)) &
11291 PORT_HW_CFG_ENABLE_CMS_MASK;
11292
11293 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11294 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
11295 if (cms_enable)
11296 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
11297 else
11298 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
11299 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11300 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
11301 }
11302
11303 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11304 MDIO_84833_TOP_CFG_FW_REV, &val);
11305
11306 /* Configure EEE support */
11307 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
11308 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
11309 elink_eee_has_cap(params)) {
11310 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
11311 if (rc != ELINK_STATUS_OK) {
11312 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11313 elink_8483x_disable_eee(phy, params, vars);
11314 return rc;
11315 }
11316
11317 if ((phy->req_duplex == DUPLEX_FULL) &&
11318 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11319 (elink_eee_calc_timer(params) ||
11320 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
11321 rc = elink_8483x_enable_eee(phy, params, vars);
11322 else
11323 rc = elink_8483x_disable_eee(phy, params, vars);
11324 if (rc != ELINK_STATUS_OK) {
11325 ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement\n");
11326 return rc;
11327 }
11328 } else {
11329 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
11330 }
11331
11332 if (elink_is_8483x_8485x(phy)) {
11333 /* Bring PHY out of super isolate mode as the final step. */
11334 elink_cl45_read_and_write(sc, phy,
11335 MDIO_CTL_DEVAD,
11336 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
11337 (uint16_t)~MDIO_84833_SUPER_ISOLATE);
11338 }
11339 return rc;
11340 }
11341
elink_848xx_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)11342 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
11343 struct elink_params *params,
11344 struct elink_vars *vars)
11345 {
11346 struct bxe_softc *sc = params->sc;
11347 uint16_t val, val1, val2;
11348 uint8_t link_up = 0;
11349
11350
11351 /* Check 10G-BaseT link status */
11352 /* Check PMD signal ok */
11353 elink_cl45_read(sc, phy,
11354 MDIO_AN_DEVAD, 0xFFFA, &val1);
11355 elink_cl45_read(sc, phy,
11356 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
11357 &val2);
11358 ELINK_DEBUG_P1(sc, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
11359
11360 /* Check link 10G */
11361 if (val2 & (1<<11)) {
11362 vars->line_speed = ELINK_SPEED_10000;
11363 vars->duplex = DUPLEX_FULL;
11364 link_up = 1;
11365 elink_ext_phy_10G_an_resolve(sc, phy, vars);
11366 } else { /* Check Legacy speed link */
11367 uint16_t legacy_status, legacy_speed;
11368
11369 /* Enable expansion register 0x42 (Operation mode status) */
11370 elink_cl45_write(sc, phy,
11371 MDIO_AN_DEVAD,
11372 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
11373
11374 /* Get legacy speed operation status */
11375 elink_cl45_read(sc, phy,
11376 MDIO_AN_DEVAD,
11377 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
11378 &legacy_status);
11379
11380 ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x\n",
11381 legacy_status);
11382 link_up = ((legacy_status & (1<<11)) == (1<<11));
11383 legacy_speed = (legacy_status & (3<<9));
11384 if (legacy_speed == (0<<9))
11385 vars->line_speed = ELINK_SPEED_10;
11386 else if (legacy_speed == (1<<9))
11387 vars->line_speed = ELINK_SPEED_100;
11388 else if (legacy_speed == (2<<9))
11389 vars->line_speed = ELINK_SPEED_1000;
11390 else { /* Should not happen: Treat as link down */
11391 vars->line_speed = 0;
11392 link_up = 0;
11393 }
11394
11395 if (params->feature_config_flags &
11396 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
11397 uint16_t mii_ctrl;
11398
11399 elink_cl45_read(sc, phy,
11400 MDIO_AN_DEVAD,
11401 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
11402 &mii_ctrl);
11403 /* For IEEE testing, check for a fake link. */
11404 link_up |= ((mii_ctrl & 0x3040) == 0x40);
11405 }
11406
11407 if (link_up) {
11408 if (legacy_status & (1<<8))
11409 vars->duplex = DUPLEX_FULL;
11410 else
11411 vars->duplex = DUPLEX_HALF;
11412
11413 ELINK_DEBUG_P2(sc,
11414 "Link is up in %dMbps, is_duplex_full= %d\n",
11415 vars->line_speed,
11416 (vars->duplex == DUPLEX_FULL));
11417 /* Check legacy speed AN resolution */
11418 elink_cl45_read(sc, phy,
11419 MDIO_AN_DEVAD,
11420 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
11421 &val);
11422 if (val & (1<<5))
11423 vars->link_status |=
11424 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11425 elink_cl45_read(sc, phy,
11426 MDIO_AN_DEVAD,
11427 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
11428 &val);
11429 if ((val & (1<<0)) == 0)
11430 vars->link_status |=
11431 LINK_STATUS_PARALLEL_DETECTION_USED;
11432 }
11433 }
11434 if (link_up) {
11435 ELINK_DEBUG_P1(sc, "BCM848x3: link speed is %d\n",
11436 vars->line_speed);
11437 elink_ext_phy_resolve_fc(phy, params, vars);
11438
11439 /* Read LP advertised speeds */
11440 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11441 MDIO_AN_REG_CL37_FC_LP, &val);
11442 if (val & (1<<5))
11443 vars->link_status |=
11444 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11445 if (val & (1<<6))
11446 vars->link_status |=
11447 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11448 if (val & (1<<7))
11449 vars->link_status |=
11450 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11451 if (val & (1<<8))
11452 vars->link_status |=
11453 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11454 if (val & (1<<9))
11455 vars->link_status |=
11456 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11457
11458 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11459 MDIO_AN_REG_1000T_STATUS, &val);
11460
11461 if (val & (1<<10))
11462 vars->link_status |=
11463 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11464 if (val & (1<<11))
11465 vars->link_status |=
11466 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11467
11468 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11469 MDIO_AN_REG_MASTER_STATUS, &val);
11470
11471 if (val & (1<<11))
11472 vars->link_status |=
11473 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11474
11475 /* Determine if EEE was negotiated */
11476 if (elink_is_8483x_8485x(phy))
11477 elink_eee_an_resolve(phy, params, vars);
11478 }
11479
11480 return link_up;
11481 }
11482
elink_848xx_format_ver(uint32_t raw_ver,uint8_t * str,uint16_t * len)11483 static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str, uint16_t *len)
11484 {
11485 elink_status_t status = ELINK_STATUS_OK;
11486 uint32_t spirom_ver;
11487 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
11488 status = elink_format_ver(spirom_ver, str, len);
11489 return status;
11490 }
11491
elink_8481_hw_reset(struct elink_phy * phy,struct elink_params * params)11492 static void elink_8481_hw_reset(struct elink_phy *phy,
11493 struct elink_params *params)
11494 {
11495 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11496 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
11497 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11498 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
11499 }
11500
elink_8481_link_reset(struct elink_phy * phy,struct elink_params * params)11501 static void elink_8481_link_reset(struct elink_phy *phy,
11502 struct elink_params *params)
11503 {
11504 elink_cl45_write(params->sc, phy,
11505 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
11506 elink_cl45_write(params->sc, phy,
11507 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
11508 }
11509
elink_848x3_link_reset(struct elink_phy * phy,struct elink_params * params)11510 static void elink_848x3_link_reset(struct elink_phy *phy,
11511 struct elink_params *params)
11512 {
11513 struct bxe_softc *sc = params->sc;
11514 uint8_t port;
11515 uint16_t val16;
11516
11517 if (!(CHIP_IS_E1x(sc)))
11518 port = SC_PATH(sc);
11519 else
11520 port = params->port;
11521
11522 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11523 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
11524 MISC_REGISTERS_GPIO_OUTPUT_LOW,
11525 port);
11526 } else {
11527 elink_cl45_read(sc, phy,
11528 MDIO_CTL_DEVAD,
11529 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
11530 val16 |= MDIO_84833_SUPER_ISOLATE;
11531 elink_cl45_write(sc, phy,
11532 MDIO_CTL_DEVAD,
11533 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
11534 }
11535 }
11536
elink_848xx_set_link_led(struct elink_phy * phy,struct elink_params * params,uint8_t mode)11537 static void elink_848xx_set_link_led(struct elink_phy *phy,
11538 struct elink_params *params, uint8_t mode)
11539 {
11540 struct bxe_softc *sc = params->sc;
11541 uint16_t val;
11542 uint8_t port;
11543
11544 if (!(CHIP_IS_E1x(sc)))
11545 port = SC_PATH(sc);
11546 else
11547 port = params->port;
11548 switch (mode) {
11549 case ELINK_LED_MODE_OFF:
11550
11551 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port);
11552
11553 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11554 SHARED_HW_CFG_LED_EXTPHY1) {
11555
11556 /* Set LED masks */
11557 elink_cl45_write(sc, phy,
11558 MDIO_PMA_DEVAD,
11559 MDIO_PMA_REG_8481_LED1_MASK,
11560 0x0);
11561
11562 elink_cl45_write(sc, phy,
11563 MDIO_PMA_DEVAD,
11564 MDIO_PMA_REG_8481_LED2_MASK,
11565 0x0);
11566
11567 elink_cl45_write(sc, phy,
11568 MDIO_PMA_DEVAD,
11569 MDIO_PMA_REG_8481_LED3_MASK,
11570 0x0);
11571
11572 elink_cl45_write(sc, phy,
11573 MDIO_PMA_DEVAD,
11574 MDIO_PMA_REG_8481_LED5_MASK,
11575 0x0);
11576
11577 } else {
11578 elink_cl45_write(sc, phy,
11579 MDIO_PMA_DEVAD,
11580 MDIO_PMA_REG_8481_LED1_MASK,
11581 0x0);
11582 }
11583 break;
11584 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11585
11586 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
11587 port);
11588
11589 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11590 SHARED_HW_CFG_LED_EXTPHY1) {
11591
11592 /* Set LED masks */
11593 elink_cl45_write(sc, phy,
11594 MDIO_PMA_DEVAD,
11595 MDIO_PMA_REG_8481_LED1_MASK,
11596 0x0);
11597
11598 elink_cl45_write(sc, phy,
11599 MDIO_PMA_DEVAD,
11600 MDIO_PMA_REG_8481_LED2_MASK,
11601 0x0);
11602
11603 elink_cl45_write(sc, phy,
11604 MDIO_PMA_DEVAD,
11605 MDIO_PMA_REG_8481_LED3_MASK,
11606 0x0);
11607
11608 elink_cl45_write(sc, phy,
11609 MDIO_PMA_DEVAD,
11610 MDIO_PMA_REG_8481_LED5_MASK,
11611 0x20);
11612
11613 } else {
11614 elink_cl45_write(sc, phy,
11615 MDIO_PMA_DEVAD,
11616 MDIO_PMA_REG_8481_LED1_MASK,
11617 0x0);
11618 if (phy->type ==
11619 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11620 /* Disable MI_INT interrupt before setting LED4
11621 * source to constant off.
11622 */
11623 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11624 params->port*4) &
11625 ELINK_NIG_MASK_MI_INT) {
11626 params->link_flags |=
11627 ELINK_LINK_FLAGS_INT_DISABLED;
11628
11629 elink_bits_dis(
11630 sc,
11631 NIG_REG_MASK_INTERRUPT_PORT0 +
11632 params->port*4,
11633 ELINK_NIG_MASK_MI_INT);
11634 }
11635 elink_cl45_write(sc, phy,
11636 MDIO_PMA_DEVAD,
11637 MDIO_PMA_REG_8481_SIGNAL_MASK,
11638 0x0);
11639 }
11640 }
11641 break;
11642 case ELINK_LED_MODE_ON:
11643
11644 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port);
11645
11646 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11647 SHARED_HW_CFG_LED_EXTPHY1) {
11648 /* Set control reg */
11649 elink_cl45_read(sc, phy,
11650 MDIO_PMA_DEVAD,
11651 MDIO_PMA_REG_8481_LINK_SIGNAL,
11652 &val);
11653 val &= 0x8000;
11654 val |= 0x2492;
11655
11656 elink_cl45_write(sc, phy,
11657 MDIO_PMA_DEVAD,
11658 MDIO_PMA_REG_8481_LINK_SIGNAL,
11659 val);
11660
11661 /* Set LED masks */
11662 elink_cl45_write(sc, phy,
11663 MDIO_PMA_DEVAD,
11664 MDIO_PMA_REG_8481_LED1_MASK,
11665 0x0);
11666
11667 elink_cl45_write(sc, phy,
11668 MDIO_PMA_DEVAD,
11669 MDIO_PMA_REG_8481_LED2_MASK,
11670 0x20);
11671
11672 elink_cl45_write(sc, phy,
11673 MDIO_PMA_DEVAD,
11674 MDIO_PMA_REG_8481_LED3_MASK,
11675 0x20);
11676
11677 elink_cl45_write(sc, phy,
11678 MDIO_PMA_DEVAD,
11679 MDIO_PMA_REG_8481_LED5_MASK,
11680 0x0);
11681 } else {
11682 elink_cl45_write(sc, phy,
11683 MDIO_PMA_DEVAD,
11684 MDIO_PMA_REG_8481_LED1_MASK,
11685 0x20);
11686 if (phy->type ==
11687 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11688 /* Disable MI_INT interrupt before setting LED4
11689 * source to constant on.
11690 */
11691 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11692 params->port*4) &
11693 ELINK_NIG_MASK_MI_INT) {
11694 params->link_flags |=
11695 ELINK_LINK_FLAGS_INT_DISABLED;
11696
11697 elink_bits_dis(
11698 sc,
11699 NIG_REG_MASK_INTERRUPT_PORT0 +
11700 params->port*4,
11701 ELINK_NIG_MASK_MI_INT);
11702 }
11703 elink_cl45_write(sc, phy,
11704 MDIO_PMA_DEVAD,
11705 MDIO_PMA_REG_8481_SIGNAL_MASK,
11706 0x20);
11707 }
11708 }
11709 break;
11710
11711 case ELINK_LED_MODE_OPER:
11712
11713 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port);
11714
11715 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11716 SHARED_HW_CFG_LED_EXTPHY1) {
11717
11718 /* Set control reg */
11719 elink_cl45_read(sc, phy,
11720 MDIO_PMA_DEVAD,
11721 MDIO_PMA_REG_8481_LINK_SIGNAL,
11722 &val);
11723
11724 if (!((val &
11725 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
11726 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
11727 ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL\n");
11728 elink_cl45_write(sc, phy,
11729 MDIO_PMA_DEVAD,
11730 MDIO_PMA_REG_8481_LINK_SIGNAL,
11731 0xa492);
11732 }
11733
11734 /* Set LED masks */
11735 elink_cl45_write(sc, phy,
11736 MDIO_PMA_DEVAD,
11737 MDIO_PMA_REG_8481_LED1_MASK,
11738 0x10);
11739
11740 elink_cl45_write(sc, phy,
11741 MDIO_PMA_DEVAD,
11742 MDIO_PMA_REG_8481_LED2_MASK,
11743 0x80);
11744
11745 elink_cl45_write(sc, phy,
11746 MDIO_PMA_DEVAD,
11747 MDIO_PMA_REG_8481_LED3_MASK,
11748 0x98);
11749
11750 elink_cl45_write(sc, phy,
11751 MDIO_PMA_DEVAD,
11752 MDIO_PMA_REG_8481_LED5_MASK,
11753 0x40);
11754
11755 } else {
11756 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
11757 * sources are all wired through LED1, rather than only
11758 * 10G in other modes.
11759 */
11760 val = ((params->hw_led_mode <<
11761 SHARED_HW_CFG_LED_MODE_SHIFT) ==
11762 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
11763
11764 elink_cl45_write(sc, phy,
11765 MDIO_PMA_DEVAD,
11766 MDIO_PMA_REG_8481_LED1_MASK,
11767 val);
11768
11769 /* Tell LED3 to blink on source */
11770 elink_cl45_read(sc, phy,
11771 MDIO_PMA_DEVAD,
11772 MDIO_PMA_REG_8481_LINK_SIGNAL,
11773 &val);
11774 val &= ~(7<<6);
11775 val |= (1<<6); /* A83B[8:6]= 1 */
11776 elink_cl45_write(sc, phy,
11777 MDIO_PMA_DEVAD,
11778 MDIO_PMA_REG_8481_LINK_SIGNAL,
11779 val);
11780 if (phy->type ==
11781 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11782 /* Restore LED4 source to external link,
11783 * and re-enable interrupts.
11784 */
11785 elink_cl45_write(sc, phy,
11786 MDIO_PMA_DEVAD,
11787 MDIO_PMA_REG_8481_SIGNAL_MASK,
11788 0x40);
11789 if (params->link_flags &
11790 ELINK_LINK_FLAGS_INT_DISABLED) {
11791 elink_link_int_enable(params);
11792 params->link_flags &=
11793 ~ELINK_LINK_FLAGS_INT_DISABLED;
11794 }
11795 }
11796 }
11797 break;
11798 }
11799
11800 /* This is a workaround for E3+84833 until autoneg
11801 * restart is fixed in f/w
11802 */
11803 if (CHIP_IS_E3(sc)) {
11804 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
11805 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11806 }
11807 }
11808
11809 /******************************************************************/
11810 /* 54618SE PHY SECTION */
11811 /******************************************************************/
elink_54618se_specific_func(struct elink_phy * phy,struct elink_params * params,uint32_t action)11812 static void elink_54618se_specific_func(struct elink_phy *phy,
11813 struct elink_params *params,
11814 uint32_t action)
11815 {
11816 struct bxe_softc *sc = params->sc;
11817 uint16_t temp;
11818 switch (action) {
11819 case ELINK_PHY_INIT:
11820 /* Configure LED4: set to INTR (0x6). */
11821 /* Accessing shadow register 0xe. */
11822 elink_cl22_write(sc, phy,
11823 MDIO_REG_GPHY_SHADOW,
11824 MDIO_REG_GPHY_SHADOW_LED_SEL2);
11825 elink_cl22_read(sc, phy,
11826 MDIO_REG_GPHY_SHADOW,
11827 &temp);
11828 temp &= ~(0xf << 4);
11829 temp |= (0x6 << 4);
11830 elink_cl22_write(sc, phy,
11831 MDIO_REG_GPHY_SHADOW,
11832 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11833 /* Configure INTR based on link status change. */
11834 elink_cl22_write(sc, phy,
11835 MDIO_REG_INTR_MASK,
11836 ~MDIO_REG_INTR_MASK_LINK_STATUS);
11837 break;
11838 }
11839 }
11840
elink_54618se_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)11841 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
11842 struct elink_params *params,
11843 struct elink_vars *vars)
11844 {
11845 struct bxe_softc *sc = params->sc;
11846 uint8_t port;
11847 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11848 uint32_t cfg_pin;
11849
11850 ELINK_DEBUG_P0(sc, "54618SE cfg init\n");
11851 DELAY(1000 * 1);
11852
11853 /* This works with E3 only, no need to check the chip
11854 * before determining the port.
11855 */
11856 port = params->port;
11857
11858 cfg_pin = (REG_RD(sc, params->shmem_base +
11859 offsetof(struct shmem_region,
11860 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11861 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11862 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11863
11864 /* Drive pin high to bring the GPHY out of reset. */
11865 elink_set_cfg_pin(sc, cfg_pin, 1);
11866
11867 /* wait for GPHY to reset */
11868 DELAY(1000 * 50);
11869
11870 /* reset phy */
11871 elink_cl22_write(sc, phy,
11872 MDIO_PMA_REG_CTRL, 0x8000);
11873 elink_wait_reset_complete(sc, phy, params);
11874
11875 /* Wait for GPHY to reset */
11876 DELAY(1000 * 50);
11877
11878
11879 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
11880 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11881 elink_cl22_write(sc, phy,
11882 MDIO_REG_GPHY_SHADOW,
11883 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11884 elink_cl22_read(sc, phy,
11885 MDIO_REG_GPHY_SHADOW,
11886 &temp);
11887 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11888 elink_cl22_write(sc, phy,
11889 MDIO_REG_GPHY_SHADOW,
11890 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11891
11892 /* Set up fc */
11893 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11894 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11895 fc_val = 0;
11896 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11897 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11898 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11899
11900 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11901 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11902 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11903
11904 /* Read all advertisement */
11905 elink_cl22_read(sc, phy,
11906 0x09,
11907 &an_1000_val);
11908
11909 elink_cl22_read(sc, phy,
11910 0x04,
11911 &an_10_100_val);
11912
11913 elink_cl22_read(sc, phy,
11914 MDIO_PMA_REG_CTRL,
11915 &autoneg_val);
11916
11917 /* Disable forced speed */
11918 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11919 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11920 (1<<11));
11921
11922 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
11923 (phy->speed_cap_mask &
11924 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11925 (phy->req_line_speed == ELINK_SPEED_1000)) {
11926 an_1000_val |= (1<<8);
11927 autoneg_val |= (1<<9 | 1<<12);
11928 if (phy->req_duplex == DUPLEX_FULL)
11929 an_1000_val |= (1<<9);
11930 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
11931 } else
11932 an_1000_val &= ~((1<<8) | (1<<9));
11933
11934 elink_cl22_write(sc, phy,
11935 0x09,
11936 an_1000_val);
11937 elink_cl22_read(sc, phy,
11938 0x09,
11939 &an_1000_val);
11940
11941 /* Advertise 10/100 link speed */
11942 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
11943 if (phy->speed_cap_mask &
11944 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11945 an_10_100_val |= (1<<5);
11946 autoneg_val |= (1<<9 | 1<<12);
11947 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
11948 }
11949 if (phy->speed_cap_mask &
11950 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
11951 an_10_100_val |= (1<<6);
11952 autoneg_val |= (1<<9 | 1<<12);
11953 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
11954 }
11955 if (phy->speed_cap_mask &
11956 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11957 an_10_100_val |= (1<<7);
11958 autoneg_val |= (1<<9 | 1<<12);
11959 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
11960 }
11961 if (phy->speed_cap_mask &
11962 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11963 an_10_100_val |= (1<<8);
11964 autoneg_val |= (1<<9 | 1<<12);
11965 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
11966 }
11967 }
11968
11969 /* Only 10/100 are allowed to work in FORCE mode */
11970 if (phy->req_line_speed == ELINK_SPEED_100) {
11971 autoneg_val |= (1<<13);
11972 /* Enabled AUTO-MDIX when autoneg is disabled */
11973 elink_cl22_write(sc, phy,
11974 0x18,
11975 (1<<15 | 1<<9 | 7<<0));
11976 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
11977 }
11978 if (phy->req_line_speed == ELINK_SPEED_10) {
11979 /* Enabled AUTO-MDIX when autoneg is disabled */
11980 elink_cl22_write(sc, phy,
11981 0x18,
11982 (1<<15 | 1<<9 | 7<<0));
11983 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
11984 }
11985
11986 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
11987 elink_status_t rc;
11988
11989 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
11990 MDIO_REG_GPHY_EXP_ACCESS_TOP |
11991 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11992 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11993 temp &= 0xfffe;
11994 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11995
11996 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11997 if (rc != ELINK_STATUS_OK) {
11998 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11999 elink_eee_disable(phy, params, vars);
12000 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
12001 (phy->req_duplex == DUPLEX_FULL) &&
12002 (elink_eee_calc_timer(params) ||
12003 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
12004 /* Need to advertise EEE only when requested,
12005 * and either no LPI assertion was requested,
12006 * or it was requested and a valid timer was set.
12007 * Also notice full duplex is required for EEE.
12008 */
12009 elink_eee_advertise(phy, params, vars,
12010 SHMEM_EEE_1G_ADV);
12011 } else {
12012 ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE\n");
12013 elink_eee_disable(phy, params, vars);
12014 }
12015 } else {
12016 vars->eee_status &= ((uint32_t)(~SHMEM_EEE_1G_ADV) <<
12017 SHMEM_EEE_SUPPORTED_SHIFT);
12018
12019 if (phy->flags & ELINK_FLAGS_EEE) {
12020 /* Handle legacy auto-grEEEn */
12021 if (params->feature_config_flags &
12022 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
12023 temp = 6;
12024 ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn\n");
12025 } else {
12026 temp = 0;
12027 ELINK_DEBUG_P0(sc, "Don't Adv. EEE\n");
12028 }
12029 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
12030 MDIO_AN_REG_EEE_ADV, temp);
12031 }
12032 }
12033
12034 elink_cl22_write(sc, phy,
12035 0x04,
12036 an_10_100_val | fc_val);
12037
12038 if (phy->req_duplex == DUPLEX_FULL)
12039 autoneg_val |= (1<<8);
12040
12041 elink_cl22_write(sc, phy,
12042 MDIO_PMA_REG_CTRL, autoneg_val);
12043
12044 return ELINK_STATUS_OK;
12045 }
12046
12047
elink_5461x_set_link_led(struct elink_phy * phy,struct elink_params * params,uint8_t mode)12048 static void elink_5461x_set_link_led(struct elink_phy *phy,
12049 struct elink_params *params, uint8_t mode)
12050 {
12051 struct bxe_softc *sc = params->sc;
12052 uint16_t temp;
12053
12054 elink_cl22_write(sc, phy,
12055 MDIO_REG_GPHY_SHADOW,
12056 MDIO_REG_GPHY_SHADOW_LED_SEL1);
12057 elink_cl22_read(sc, phy,
12058 MDIO_REG_GPHY_SHADOW,
12059 &temp);
12060 temp &= 0xff00;
12061
12062 ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)\n", mode);
12063 switch (mode) {
12064 case ELINK_LED_MODE_FRONT_PANEL_OFF:
12065 case ELINK_LED_MODE_OFF:
12066 temp |= 0x00ee;
12067 break;
12068 case ELINK_LED_MODE_OPER:
12069 temp |= 0x0001;
12070 break;
12071 case ELINK_LED_MODE_ON:
12072 temp |= 0x00ff;
12073 break;
12074 default:
12075 break;
12076 }
12077 elink_cl22_write(sc, phy,
12078 MDIO_REG_GPHY_SHADOW,
12079 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
12080 return;
12081 }
12082
12083
elink_54618se_link_reset(struct elink_phy * phy,struct elink_params * params)12084 static void elink_54618se_link_reset(struct elink_phy *phy,
12085 struct elink_params *params)
12086 {
12087 struct bxe_softc *sc = params->sc;
12088 uint32_t cfg_pin;
12089 uint8_t port;
12090
12091 /* In case of no EPIO routed to reset the GPHY, put it
12092 * in low power mode.
12093 */
12094 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
12095 /* This works with E3 only, no need to check the chip
12096 * before determining the port.
12097 */
12098 port = params->port;
12099 cfg_pin = (REG_RD(sc, params->shmem_base +
12100 offsetof(struct shmem_region,
12101 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
12102 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
12103 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
12104
12105 /* Drive pin low to put GPHY in reset. */
12106 elink_set_cfg_pin(sc, cfg_pin, 0);
12107 }
12108
elink_54618se_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)12109 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
12110 struct elink_params *params,
12111 struct elink_vars *vars)
12112 {
12113 struct bxe_softc *sc = params->sc;
12114 uint16_t val;
12115 uint8_t link_up = 0;
12116 uint16_t legacy_status, legacy_speed;
12117
12118 /* Get speed operation status */
12119 elink_cl22_read(sc, phy,
12120 MDIO_REG_GPHY_AUX_STATUS,
12121 &legacy_status);
12122 ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x\n", legacy_status);
12123
12124 /* Read status to clear the PHY interrupt. */
12125 elink_cl22_read(sc, phy,
12126 MDIO_REG_INTR_STATUS,
12127 &val);
12128
12129 link_up = ((legacy_status & (1<<2)) == (1<<2));
12130
12131 if (link_up) {
12132 legacy_speed = (legacy_status & (7<<8));
12133 if (legacy_speed == (7<<8)) {
12134 vars->line_speed = ELINK_SPEED_1000;
12135 vars->duplex = DUPLEX_FULL;
12136 } else if (legacy_speed == (6<<8)) {
12137 vars->line_speed = ELINK_SPEED_1000;
12138 vars->duplex = DUPLEX_HALF;
12139 } else if (legacy_speed == (5<<8)) {
12140 vars->line_speed = ELINK_SPEED_100;
12141 vars->duplex = DUPLEX_FULL;
12142 }
12143 /* Omitting 100Base-T4 for now */
12144 else if (legacy_speed == (3<<8)) {
12145 vars->line_speed = ELINK_SPEED_100;
12146 vars->duplex = DUPLEX_HALF;
12147 } else if (legacy_speed == (2<<8)) {
12148 vars->line_speed = ELINK_SPEED_10;
12149 vars->duplex = DUPLEX_FULL;
12150 } else if (legacy_speed == (1<<8)) {
12151 vars->line_speed = ELINK_SPEED_10;
12152 vars->duplex = DUPLEX_HALF;
12153 } else /* Should not happen */
12154 vars->line_speed = 0;
12155
12156 ELINK_DEBUG_P2(sc,
12157 "Link is up in %dMbps, is_duplex_full= %d\n",
12158 vars->line_speed,
12159 (vars->duplex == DUPLEX_FULL));
12160
12161 /* Check legacy speed AN resolution */
12162 elink_cl22_read(sc, phy,
12163 0x01,
12164 &val);
12165 if (val & (1<<5))
12166 vars->link_status |=
12167 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
12168 elink_cl22_read(sc, phy,
12169 0x06,
12170 &val);
12171 if ((val & (1<<0)) == 0)
12172 vars->link_status |=
12173 LINK_STATUS_PARALLEL_DETECTION_USED;
12174
12175 ELINK_DEBUG_P1(sc, "BCM54618SE: link speed is %d\n",
12176 vars->line_speed);
12177
12178 elink_ext_phy_resolve_fc(phy, params, vars);
12179
12180 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
12181 /* Report LP advertised speeds */
12182 elink_cl22_read(sc, phy, 0x5, &val);
12183
12184 if (val & (1<<5))
12185 vars->link_status |=
12186 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
12187 if (val & (1<<6))
12188 vars->link_status |=
12189 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
12190 if (val & (1<<7))
12191 vars->link_status |=
12192 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
12193 if (val & (1<<8))
12194 vars->link_status |=
12195 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
12196 if (val & (1<<9))
12197 vars->link_status |=
12198 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
12199
12200 elink_cl22_read(sc, phy, 0xa, &val);
12201 if (val & (1<<10))
12202 vars->link_status |=
12203 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
12204 if (val & (1<<11))
12205 vars->link_status |=
12206 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
12207
12208 if ((phy->flags & ELINK_FLAGS_EEE) &&
12209 elink_eee_has_cap(params))
12210 elink_eee_an_resolve(phy, params, vars);
12211 }
12212 }
12213 return link_up;
12214 }
12215
elink_54618se_config_loopback(struct elink_phy * phy,struct elink_params * params)12216 static void elink_54618se_config_loopback(struct elink_phy *phy,
12217 struct elink_params *params)
12218 {
12219 struct bxe_softc *sc = params->sc;
12220 uint16_t val;
12221 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
12222
12223 ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se\n");
12224
12225 /* Enable master/slave manual mmode and set to master */
12226 /* mii write 9 [bits set 11 12] */
12227 elink_cl22_write(sc, phy, 0x09, 3<<11);
12228
12229 /* forced 1G and disable autoneg */
12230 /* set val [mii read 0] */
12231 /* set val [expr $val & [bits clear 6 12 13]] */
12232 /* set val [expr $val | [bits set 6 8]] */
12233 /* mii write 0 $val */
12234 elink_cl22_read(sc, phy, 0x00, &val);
12235 val &= ~((1<<6) | (1<<12) | (1<<13));
12236 val |= (1<<6) | (1<<8);
12237 elink_cl22_write(sc, phy, 0x00, val);
12238
12239 /* Set external loopback and Tx using 6dB coding */
12240 /* mii write 0x18 7 */
12241 /* set val [mii read 0x18] */
12242 /* mii write 0x18 [expr $val | [bits set 10 15]] */
12243 elink_cl22_write(sc, phy, 0x18, 7);
12244 elink_cl22_read(sc, phy, 0x18, &val);
12245 elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));
12246
12247 /* This register opens the gate for the UMAC despite its name */
12248 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
12249
12250 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
12251 * length used by the MAC receive logic to check frames.
12252 */
12253 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
12254 }
12255
12256 /******************************************************************/
12257 /* SFX7101 PHY SECTION */
12258 /******************************************************************/
elink_7101_config_loopback(struct elink_phy * phy,struct elink_params * params)12259 static void elink_7101_config_loopback(struct elink_phy *phy,
12260 struct elink_params *params)
12261 {
12262 struct bxe_softc *sc = params->sc;
12263 /* SFX7101_XGXS_TEST1 */
12264 elink_cl45_write(sc, phy,
12265 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
12266 }
12267
elink_7101_config_init(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)12268 static elink_status_t elink_7101_config_init(struct elink_phy *phy,
12269 struct elink_params *params,
12270 struct elink_vars *vars)
12271 {
12272 uint16_t fw_ver1, fw_ver2, val;
12273 struct bxe_softc *sc = params->sc;
12274 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication\n");
12275
12276 /* Restore normal power mode*/
12277 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12278 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
12279 /* HW reset */
12280 elink_ext_phy_hw_reset(sc, params->port);
12281 elink_wait_reset_complete(sc, phy, params);
12282
12283 elink_cl45_write(sc, phy,
12284 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
12285 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic\n");
12286 elink_cl45_write(sc, phy,
12287 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
12288
12289 elink_ext_phy_set_pause(params, phy, vars);
12290 /* Restart autoneg */
12291 elink_cl45_read(sc, phy,
12292 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
12293 val |= 0x200;
12294 elink_cl45_write(sc, phy,
12295 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
12296
12297 /* Save spirom version */
12298 elink_cl45_read(sc, phy,
12299 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
12300
12301 elink_cl45_read(sc, phy,
12302 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
12303 elink_save_spirom_version(sc, params->port,
12304 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
12305 return ELINK_STATUS_OK;
12306 }
12307
elink_7101_read_status(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)12308 static uint8_t elink_7101_read_status(struct elink_phy *phy,
12309 struct elink_params *params,
12310 struct elink_vars *vars)
12311 {
12312 struct bxe_softc *sc = params->sc;
12313 uint8_t link_up;
12314 uint16_t val1, val2;
12315 elink_cl45_read(sc, phy,
12316 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
12317 elink_cl45_read(sc, phy,
12318 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
12319 ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n",
12320 val2, val1);
12321 elink_cl45_read(sc, phy,
12322 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
12323 elink_cl45_read(sc, phy,
12324 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
12325 ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n",
12326 val2, val1);
12327 link_up = ((val1 & 4) == 4);
12328 /* If link is up print the AN outcome of the SFX7101 PHY */
12329 if (link_up) {
12330 elink_cl45_read(sc, phy,
12331 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
12332 &val2);
12333 vars->line_speed = ELINK_SPEED_10000;
12334 vars->duplex = DUPLEX_FULL;
12335 ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n",
12336 val2, (val2 & (1<<14)));
12337 elink_ext_phy_10G_an_resolve(sc, phy, vars);
12338 elink_ext_phy_resolve_fc(phy, params, vars);
12339
12340 /* Read LP advertised speeds */
12341 if (val2 & (1<<11))
12342 vars->link_status |=
12343 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
12344 }
12345 return link_up;
12346 }
12347
elink_7101_format_ver(uint32_t spirom_ver,uint8_t * str,uint16_t * len)12348 static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
12349 {
12350 if (*len < 5)
12351 return ELINK_STATUS_ERROR;
12352 str[0] = (spirom_ver & 0xFF);
12353 str[1] = (spirom_ver & 0xFF00) >> 8;
12354 str[2] = (spirom_ver & 0xFF0000) >> 16;
12355 str[3] = (spirom_ver & 0xFF000000) >> 24;
12356 str[4] = '\0';
12357 *len -= 5;
12358 return ELINK_STATUS_OK;
12359 }
12360
elink_sfx7101_sp_sw_reset(struct bxe_softc * sc,struct elink_phy * phy)12361 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)
12362 {
12363 uint16_t val, cnt;
12364
12365 elink_cl45_read(sc, phy,
12366 MDIO_PMA_DEVAD,
12367 MDIO_PMA_REG_7101_RESET, &val);
12368
12369 for (cnt = 0; cnt < 10; cnt++) {
12370 DELAY(1000 * 50);
12371 /* Writes a self-clearing reset */
12372 elink_cl45_write(sc, phy,
12373 MDIO_PMA_DEVAD,
12374 MDIO_PMA_REG_7101_RESET,
12375 (val | (1<<15)));
12376 /* Wait for clear */
12377 elink_cl45_read(sc, phy,
12378 MDIO_PMA_DEVAD,
12379 MDIO_PMA_REG_7101_RESET, &val);
12380
12381 if ((val & (1<<15)) == 0)
12382 break;
12383 }
12384 }
12385
elink_7101_hw_reset(struct elink_phy * phy,struct elink_params * params)12386 static void elink_7101_hw_reset(struct elink_phy *phy,
12387 struct elink_params *params) {
12388 /* Low power mode is controlled by GPIO 2 */
12389 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
12390 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12391 /* The PHY reset is controlled by GPIO 1 */
12392 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
12393 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12394 }
12395
elink_7101_set_link_led(struct elink_phy * phy,struct elink_params * params,uint8_t mode)12396 static void elink_7101_set_link_led(struct elink_phy *phy,
12397 struct elink_params *params, uint8_t mode)
12398 {
12399 uint16_t val = 0;
12400 struct bxe_softc *sc = params->sc;
12401 switch (mode) {
12402 case ELINK_LED_MODE_FRONT_PANEL_OFF:
12403 case ELINK_LED_MODE_OFF:
12404 val = 2;
12405 break;
12406 case ELINK_LED_MODE_ON:
12407 val = 1;
12408 break;
12409 case ELINK_LED_MODE_OPER:
12410 val = 0;
12411 break;
12412 }
12413 elink_cl45_write(sc, phy,
12414 MDIO_PMA_DEVAD,
12415 MDIO_PMA_REG_7107_LINK_LED_CNTL,
12416 val);
12417 }
12418
12419 /******************************************************************/
12420 /* STATIC PHY DECLARATION */
12421 /******************************************************************/
12422
12423 static const struct elink_phy phy_null = {
12424 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
12425 .addr = 0,
12426 .def_md_devad = 0,
12427 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12428 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12429 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12430 .mdio_ctrl = 0,
12431 .supported = 0,
12432 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12433 .ver_addr = 0,
12434 .req_flow_ctrl = 0,
12435 .req_line_speed = 0,
12436 .speed_cap_mask = 0,
12437 .req_duplex = 0,
12438 .rsrv = 0,
12439 .config_init = (config_init_t)NULL,
12440 .read_status = (read_status_t)NULL,
12441 .link_reset = (link_reset_t)NULL,
12442 .config_loopback = (config_loopback_t)NULL,
12443 .format_fw_ver = (format_fw_ver_t)NULL,
12444 .hw_reset = (hw_reset_t)NULL,
12445 .set_link_led = (set_link_led_t)NULL,
12446 .phy_specific_func = (phy_specific_func_t)NULL
12447 };
12448
12449 static const struct elink_phy phy_serdes = {
12450 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
12451 .addr = 0xff,
12452 .def_md_devad = 0,
12453 .flags = 0,
12454 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12455 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12456 .mdio_ctrl = 0,
12457 .supported = (ELINK_SUPPORTED_10baseT_Half |
12458 ELINK_SUPPORTED_10baseT_Full |
12459 ELINK_SUPPORTED_100baseT_Half |
12460 ELINK_SUPPORTED_100baseT_Full |
12461 ELINK_SUPPORTED_1000baseT_Full |
12462 ELINK_SUPPORTED_2500baseX_Full |
12463 ELINK_SUPPORTED_TP |
12464 ELINK_SUPPORTED_Autoneg |
12465 ELINK_SUPPORTED_Pause |
12466 ELINK_SUPPORTED_Asym_Pause),
12467 .media_type = ELINK_ETH_PHY_BASE_T,
12468 .ver_addr = 0,
12469 .req_flow_ctrl = 0,
12470 .req_line_speed = 0,
12471 .speed_cap_mask = 0,
12472 .req_duplex = 0,
12473 .rsrv = 0,
12474 .config_init = (config_init_t)elink_xgxs_config_init,
12475 .read_status = (read_status_t)elink_link_settings_status,
12476 .link_reset = (link_reset_t)elink_int_link_reset,
12477 .config_loopback = (config_loopback_t)NULL,
12478 .format_fw_ver = (format_fw_ver_t)NULL,
12479 .hw_reset = (hw_reset_t)NULL,
12480 .set_link_led = (set_link_led_t)NULL,
12481 .phy_specific_func = (phy_specific_func_t)NULL
12482 };
12483
12484 static const struct elink_phy phy_xgxs = {
12485 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12486 .addr = 0xff,
12487 .def_md_devad = 0,
12488 .flags = 0,
12489 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12490 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12491 .mdio_ctrl = 0,
12492 .supported = (ELINK_SUPPORTED_10baseT_Half |
12493 ELINK_SUPPORTED_10baseT_Full |
12494 ELINK_SUPPORTED_100baseT_Half |
12495 ELINK_SUPPORTED_100baseT_Full |
12496 ELINK_SUPPORTED_1000baseT_Full |
12497 ELINK_SUPPORTED_2500baseX_Full |
12498 ELINK_SUPPORTED_10000baseT_Full |
12499 ELINK_SUPPORTED_FIBRE |
12500 ELINK_SUPPORTED_Autoneg |
12501 ELINK_SUPPORTED_Pause |
12502 ELINK_SUPPORTED_Asym_Pause),
12503 .media_type = ELINK_ETH_PHY_CX4,
12504 .ver_addr = 0,
12505 .req_flow_ctrl = 0,
12506 .req_line_speed = 0,
12507 .speed_cap_mask = 0,
12508 .req_duplex = 0,
12509 .rsrv = 0,
12510 .config_init = (config_init_t)elink_xgxs_config_init,
12511 .read_status = (read_status_t)elink_link_settings_status,
12512 .link_reset = (link_reset_t)elink_int_link_reset,
12513 .config_loopback = (config_loopback_t)elink_set_xgxs_loopback,
12514 .format_fw_ver = (format_fw_ver_t)NULL,
12515 .hw_reset = (hw_reset_t)NULL,
12516 .set_link_led = (set_link_led_t)NULL,
12517 .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func
12518 };
12519 static const struct elink_phy phy_warpcore = {
12520 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12521 .addr = 0xff,
12522 .def_md_devad = 0,
12523 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
12524 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12525 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12526 .mdio_ctrl = 0,
12527 .supported = (ELINK_SUPPORTED_10baseT_Half |
12528 ELINK_SUPPORTED_10baseT_Full |
12529 ELINK_SUPPORTED_100baseT_Half |
12530 ELINK_SUPPORTED_100baseT_Full |
12531 ELINK_SUPPORTED_1000baseT_Full |
12532 ELINK_SUPPORTED_1000baseKX_Full |
12533 ELINK_SUPPORTED_10000baseT_Full |
12534 ELINK_SUPPORTED_10000baseKR_Full |
12535 ELINK_SUPPORTED_20000baseKR2_Full |
12536 ELINK_SUPPORTED_20000baseMLD2_Full |
12537 ELINK_SUPPORTED_FIBRE |
12538 ELINK_SUPPORTED_Autoneg |
12539 ELINK_SUPPORTED_Pause |
12540 ELINK_SUPPORTED_Asym_Pause),
12541 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
12542 .ver_addr = 0,
12543 .req_flow_ctrl = 0,
12544 .req_line_speed = 0,
12545 .speed_cap_mask = 0,
12546 /* req_duplex = */0,
12547 /* rsrv = */0,
12548 .config_init = (config_init_t)elink_warpcore_config_init,
12549 .read_status = (read_status_t)elink_warpcore_read_status,
12550 .link_reset = (link_reset_t)elink_warpcore_link_reset,
12551 .config_loopback = (config_loopback_t)elink_set_warpcore_loopback,
12552 .format_fw_ver = (format_fw_ver_t)NULL,
12553 .hw_reset = (hw_reset_t)elink_warpcore_hw_reset,
12554 .set_link_led = (set_link_led_t)NULL,
12555 .phy_specific_func = (phy_specific_func_t)NULL
12556 };
12557
12558
12559 static const struct elink_phy phy_7101 = {
12560 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
12561 .addr = 0xff,
12562 .def_md_devad = 0,
12563 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
12564 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12565 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12566 .mdio_ctrl = 0,
12567 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12568 ELINK_SUPPORTED_TP |
12569 ELINK_SUPPORTED_Autoneg |
12570 ELINK_SUPPORTED_Pause |
12571 ELINK_SUPPORTED_Asym_Pause),
12572 .media_type = ELINK_ETH_PHY_BASE_T,
12573 .ver_addr = 0,
12574 .req_flow_ctrl = 0,
12575 .req_line_speed = 0,
12576 .speed_cap_mask = 0,
12577 .req_duplex = 0,
12578 .rsrv = 0,
12579 .config_init = (config_init_t)elink_7101_config_init,
12580 .read_status = (read_status_t)elink_7101_read_status,
12581 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12582 .config_loopback = (config_loopback_t)elink_7101_config_loopback,
12583 .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver,
12584 .hw_reset = (hw_reset_t)elink_7101_hw_reset,
12585 .set_link_led = (set_link_led_t)elink_7101_set_link_led,
12586 .phy_specific_func = (phy_specific_func_t)NULL
12587 };
12588 static const struct elink_phy phy_8073 = {
12589 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
12590 .addr = 0xff,
12591 .def_md_devad = 0,
12592 .flags = 0,
12593 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12594 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12595 .mdio_ctrl = 0,
12596 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12597 ELINK_SUPPORTED_2500baseX_Full |
12598 ELINK_SUPPORTED_1000baseT_Full |
12599 ELINK_SUPPORTED_FIBRE |
12600 ELINK_SUPPORTED_Autoneg |
12601 ELINK_SUPPORTED_Pause |
12602 ELINK_SUPPORTED_Asym_Pause),
12603 .media_type = ELINK_ETH_PHY_KR,
12604 .ver_addr = 0,
12605 .req_flow_ctrl = 0,
12606 .req_line_speed = 0,
12607 .speed_cap_mask = 0,
12608 .req_duplex = 0,
12609 .rsrv = 0,
12610 .config_init = (config_init_t)elink_8073_config_init,
12611 .read_status = (read_status_t)elink_8073_read_status,
12612 .link_reset = (link_reset_t)elink_8073_link_reset,
12613 .config_loopback = (config_loopback_t)NULL,
12614 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12615 .hw_reset = (hw_reset_t)NULL,
12616 .set_link_led = (set_link_led_t)NULL,
12617 .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func
12618 };
12619 static const struct elink_phy phy_8705 = {
12620 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
12621 .addr = 0xff,
12622 .def_md_devad = 0,
12623 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12624 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12625 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12626 .mdio_ctrl = 0,
12627 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12628 ELINK_SUPPORTED_FIBRE |
12629 ELINK_SUPPORTED_Pause |
12630 ELINK_SUPPORTED_Asym_Pause),
12631 .media_type = ELINK_ETH_PHY_XFP_FIBER,
12632 .ver_addr = 0,
12633 .req_flow_ctrl = 0,
12634 .req_line_speed = 0,
12635 .speed_cap_mask = 0,
12636 .req_duplex = 0,
12637 .rsrv = 0,
12638 .config_init = (config_init_t)elink_8705_config_init,
12639 .read_status = (read_status_t)elink_8705_read_status,
12640 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12641 .config_loopback = (config_loopback_t)NULL,
12642 .format_fw_ver = (format_fw_ver_t)elink_null_format_ver,
12643 .hw_reset = (hw_reset_t)NULL,
12644 .set_link_led = (set_link_led_t)NULL,
12645 .phy_specific_func = (phy_specific_func_t)NULL
12646 };
12647 static const struct elink_phy phy_8706 = {
12648 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
12649 .addr = 0xff,
12650 .def_md_devad = 0,
12651 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12652 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12653 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12654 .mdio_ctrl = 0,
12655 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12656 ELINK_SUPPORTED_1000baseT_Full |
12657 ELINK_SUPPORTED_FIBRE |
12658 ELINK_SUPPORTED_Pause |
12659 ELINK_SUPPORTED_Asym_Pause),
12660 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
12661 .ver_addr = 0,
12662 .req_flow_ctrl = 0,
12663 .req_line_speed = 0,
12664 .speed_cap_mask = 0,
12665 .req_duplex = 0,
12666 .rsrv = 0,
12667 .config_init = (config_init_t)elink_8706_config_init,
12668 .read_status = (read_status_t)elink_8706_read_status,
12669 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12670 .config_loopback = (config_loopback_t)NULL,
12671 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12672 .hw_reset = (hw_reset_t)NULL,
12673 .set_link_led = (set_link_led_t)NULL,
12674 .phy_specific_func = (phy_specific_func_t)NULL
12675 };
12676
12677 static const struct elink_phy phy_8726 = {
12678 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
12679 .addr = 0xff,
12680 .def_md_devad = 0,
12681 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST |
12682 ELINK_FLAGS_TX_ERROR_CHECK),
12683 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12684 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12685 .mdio_ctrl = 0,
12686 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12687 ELINK_SUPPORTED_1000baseT_Full |
12688 ELINK_SUPPORTED_Autoneg |
12689 ELINK_SUPPORTED_FIBRE |
12690 ELINK_SUPPORTED_Pause |
12691 ELINK_SUPPORTED_Asym_Pause),
12692 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12693 .ver_addr = 0,
12694 .req_flow_ctrl = 0,
12695 .req_line_speed = 0,
12696 .speed_cap_mask = 0,
12697 .req_duplex = 0,
12698 .rsrv = 0,
12699 .config_init = (config_init_t)elink_8726_config_init,
12700 .read_status = (read_status_t)elink_8726_read_status,
12701 .link_reset = (link_reset_t)elink_8726_link_reset,
12702 .config_loopback = (config_loopback_t)elink_8726_config_loopback,
12703 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12704 .hw_reset = (hw_reset_t)NULL,
12705 .set_link_led = (set_link_led_t)NULL,
12706 .phy_specific_func = (phy_specific_func_t)NULL
12707 };
12708
12709 static const struct elink_phy phy_8727 = {
12710 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
12711 .addr = 0xff,
12712 .def_md_devad = 0,
12713 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12714 ELINK_FLAGS_TX_ERROR_CHECK),
12715 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12716 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12717 .mdio_ctrl = 0,
12718 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12719 ELINK_SUPPORTED_1000baseT_Full |
12720 ELINK_SUPPORTED_FIBRE |
12721 ELINK_SUPPORTED_Pause |
12722 ELINK_SUPPORTED_Asym_Pause),
12723 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12724 .ver_addr = 0,
12725 .req_flow_ctrl = 0,
12726 .req_line_speed = 0,
12727 .speed_cap_mask = 0,
12728 .req_duplex = 0,
12729 .rsrv = 0,
12730 .config_init = (config_init_t)elink_8727_config_init,
12731 .read_status = (read_status_t)elink_8727_read_status,
12732 .link_reset = (link_reset_t)elink_8727_link_reset,
12733 .config_loopback = (config_loopback_t)NULL,
12734 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12735 .hw_reset = (hw_reset_t)elink_8727_hw_reset,
12736 .set_link_led = (set_link_led_t)elink_8727_set_link_led,
12737 .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func
12738 };
12739 static const struct elink_phy phy_8481 = {
12740 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
12741 .addr = 0xff,
12742 .def_md_devad = 0,
12743 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12744 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12745 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12746 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12747 .mdio_ctrl = 0,
12748 .supported = (ELINK_SUPPORTED_10baseT_Half |
12749 ELINK_SUPPORTED_10baseT_Full |
12750 ELINK_SUPPORTED_100baseT_Half |
12751 ELINK_SUPPORTED_100baseT_Full |
12752 ELINK_SUPPORTED_1000baseT_Full |
12753 ELINK_SUPPORTED_10000baseT_Full |
12754 ELINK_SUPPORTED_TP |
12755 ELINK_SUPPORTED_Autoneg |
12756 ELINK_SUPPORTED_Pause |
12757 ELINK_SUPPORTED_Asym_Pause),
12758 .media_type = ELINK_ETH_PHY_BASE_T,
12759 .ver_addr = 0,
12760 .req_flow_ctrl = 0,
12761 .req_line_speed = 0,
12762 .speed_cap_mask = 0,
12763 .req_duplex = 0,
12764 .rsrv = 0,
12765 .config_init = (config_init_t)elink_8481_config_init,
12766 .read_status = (read_status_t)elink_848xx_read_status,
12767 .link_reset = (link_reset_t)elink_8481_link_reset,
12768 .config_loopback = (config_loopback_t)NULL,
12769 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12770 .hw_reset = (hw_reset_t)elink_8481_hw_reset,
12771 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12772 .phy_specific_func = (phy_specific_func_t)NULL
12773 };
12774
12775 static const struct elink_phy phy_84823 = {
12776 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
12777 .addr = 0xff,
12778 .def_md_devad = 0,
12779 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12780 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12781 ELINK_FLAGS_TX_ERROR_CHECK),
12782 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12783 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12784 .mdio_ctrl = 0,
12785 .supported = (ELINK_SUPPORTED_10baseT_Half |
12786 ELINK_SUPPORTED_10baseT_Full |
12787 ELINK_SUPPORTED_100baseT_Half |
12788 ELINK_SUPPORTED_100baseT_Full |
12789 ELINK_SUPPORTED_1000baseT_Full |
12790 ELINK_SUPPORTED_10000baseT_Full |
12791 ELINK_SUPPORTED_TP |
12792 ELINK_SUPPORTED_Autoneg |
12793 ELINK_SUPPORTED_Pause |
12794 ELINK_SUPPORTED_Asym_Pause),
12795 .media_type = ELINK_ETH_PHY_BASE_T,
12796 .ver_addr = 0,
12797 .req_flow_ctrl = 0,
12798 .req_line_speed = 0,
12799 .speed_cap_mask = 0,
12800 .req_duplex = 0,
12801 .rsrv = 0,
12802 .config_init = (config_init_t)elink_848x3_config_init,
12803 .read_status = (read_status_t)elink_848xx_read_status,
12804 .link_reset = (link_reset_t)elink_848x3_link_reset,
12805 .config_loopback = (config_loopback_t)NULL,
12806 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12807 .hw_reset = (hw_reset_t)NULL,
12808 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12809 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12810 };
12811
12812 static const struct elink_phy phy_84833 = {
12813 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12814 .addr = 0xff,
12815 .def_md_devad = 0,
12816 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12817 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12818 ELINK_FLAGS_TX_ERROR_CHECK |
12819 ELINK_FLAGS_TEMPERATURE),
12820 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12821 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12822 .mdio_ctrl = 0,
12823 .supported = (ELINK_SUPPORTED_100baseT_Half |
12824 ELINK_SUPPORTED_100baseT_Full |
12825 ELINK_SUPPORTED_1000baseT_Full |
12826 ELINK_SUPPORTED_10000baseT_Full |
12827 ELINK_SUPPORTED_TP |
12828 ELINK_SUPPORTED_Autoneg |
12829 ELINK_SUPPORTED_Pause |
12830 ELINK_SUPPORTED_Asym_Pause),
12831 .media_type = ELINK_ETH_PHY_BASE_T,
12832 .ver_addr = 0,
12833 .req_flow_ctrl = 0,
12834 .req_line_speed = 0,
12835 .speed_cap_mask = 0,
12836 .req_duplex = 0,
12837 .rsrv = 0,
12838 .config_init = (config_init_t)elink_848x3_config_init,
12839 .read_status = (read_status_t)elink_848xx_read_status,
12840 .link_reset = (link_reset_t)elink_848x3_link_reset,
12841 .config_loopback = (config_loopback_t)NULL,
12842 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12843 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12844 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12845 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12846 };
12847
12848 static const struct elink_phy phy_84834 = {
12849 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12850 .addr = 0xff,
12851 .def_md_devad = 0,
12852 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12853 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12854 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12855 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12856 .mdio_ctrl = 0,
12857 .supported = (ELINK_SUPPORTED_100baseT_Half |
12858 ELINK_SUPPORTED_100baseT_Full |
12859 ELINK_SUPPORTED_1000baseT_Full |
12860 ELINK_SUPPORTED_10000baseT_Full |
12861 ELINK_SUPPORTED_TP |
12862 ELINK_SUPPORTED_Autoneg |
12863 ELINK_SUPPORTED_Pause |
12864 ELINK_SUPPORTED_Asym_Pause),
12865 .media_type = ELINK_ETH_PHY_BASE_T,
12866 .ver_addr = 0,
12867 .req_flow_ctrl = 0,
12868 .req_line_speed = 0,
12869 .speed_cap_mask = 0,
12870 .req_duplex = 0,
12871 .rsrv = 0,
12872 .config_init = (config_init_t)elink_848x3_config_init,
12873 .read_status = (read_status_t)elink_848xx_read_status,
12874 .link_reset = (link_reset_t)elink_848x3_link_reset,
12875 .config_loopback = (config_loopback_t)NULL,
12876 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12877 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12878 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12879 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12880 };
12881
12882 static const struct elink_phy phy_84858 = {
12883 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
12884 .addr = 0xff,
12885 .def_md_devad = 0,
12886 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12887 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12888 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12889 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12890 .mdio_ctrl = 0,
12891 .supported = (ELINK_SUPPORTED_100baseT_Half |
12892 ELINK_SUPPORTED_100baseT_Full |
12893 ELINK_SUPPORTED_1000baseT_Full |
12894 ELINK_SUPPORTED_10000baseT_Full |
12895 ELINK_SUPPORTED_TP |
12896 ELINK_SUPPORTED_Autoneg |
12897 ELINK_SUPPORTED_Pause |
12898 ELINK_SUPPORTED_Asym_Pause),
12899 .media_type = ELINK_ETH_PHY_BASE_T,
12900 .ver_addr = 0,
12901 .req_flow_ctrl = 0,
12902 .req_line_speed = 0,
12903 .speed_cap_mask = 0,
12904 .req_duplex = 0,
12905 .rsrv = 0,
12906 .config_init = (config_init_t)elink_848x3_config_init,
12907 .read_status = (read_status_t)elink_848xx_read_status,
12908 .link_reset = (link_reset_t)elink_848x3_link_reset,
12909 .config_loopback = (config_loopback_t)NULL,
12910 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12911 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12912 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12913 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12914 };
12915
12916
12917 static const struct elink_phy phy_54618se = {
12918 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12919 .addr = 0xff,
12920 .def_md_devad = 0,
12921 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12922 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12923 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12924 .mdio_ctrl = 0,
12925 .supported = (ELINK_SUPPORTED_10baseT_Half |
12926 ELINK_SUPPORTED_10baseT_Full |
12927 ELINK_SUPPORTED_100baseT_Half |
12928 ELINK_SUPPORTED_100baseT_Full |
12929 ELINK_SUPPORTED_1000baseT_Full |
12930 ELINK_SUPPORTED_TP |
12931 ELINK_SUPPORTED_Autoneg |
12932 ELINK_SUPPORTED_Pause |
12933 ELINK_SUPPORTED_Asym_Pause),
12934 .media_type = ELINK_ETH_PHY_BASE_T,
12935 .ver_addr = 0,
12936 .req_flow_ctrl = 0,
12937 .req_line_speed = 0,
12938 .speed_cap_mask = 0,
12939 /* req_duplex = */0,
12940 /* rsrv = */0,
12941 .config_init = (config_init_t)elink_54618se_config_init,
12942 .read_status = (read_status_t)elink_54618se_read_status,
12943 .link_reset = (link_reset_t)elink_54618se_link_reset,
12944 .config_loopback = (config_loopback_t)elink_54618se_config_loopback,
12945 .format_fw_ver = (format_fw_ver_t)NULL,
12946 .hw_reset = (hw_reset_t)NULL,
12947 .set_link_led = (set_link_led_t)elink_5461x_set_link_led,
12948 .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func
12949 };
12950 /*****************************************************************/
12951 /* */
12952 /* Populate the phy according. Main function: elink_populate_phy */
12953 /* */
12954 /*****************************************************************/
12955
elink_populate_preemphasis(struct bxe_softc * sc,uint32_t shmem_base,struct elink_phy * phy,uint8_t port,uint8_t phy_index)12956 static void elink_populate_preemphasis(struct bxe_softc *sc, uint32_t shmem_base,
12957 struct elink_phy *phy, uint8_t port,
12958 uint8_t phy_index)
12959 {
12960 /* Get the 4 lanes xgxs config rx and tx */
12961 uint32_t rx = 0, tx = 0, i;
12962 for (i = 0; i < 2; i++) {
12963 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
12964 * the shmem. When num_phys is greater than 1, than this value
12965 * applies only to ELINK_EXT_PHY1
12966 */
12967 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
12968 rx = REG_RD(sc, shmem_base +
12969 offsetof(struct shmem_region,
12970 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12971
12972 tx = REG_RD(sc, shmem_base +
12973 offsetof(struct shmem_region,
12974 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12975 } else {
12976 rx = REG_RD(sc, shmem_base +
12977 offsetof(struct shmem_region,
12978 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12979
12980 tx = REG_RD(sc, shmem_base +
12981 offsetof(struct shmem_region,
12982 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12983 }
12984
12985 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12986 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12987
12988 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12989 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12990 ELINK_DEBUG_P2(sc,"phy->rx_preemphasis = %x, phy->tx_preemphasis = %x\n",
12991 phy->rx_preemphasis[i << 1], phy->tx_preemphasis[i << 1]);
12992 }
12993 }
12994
elink_get_ext_phy_config(struct bxe_softc * sc,uint32_t shmem_base,uint8_t phy_index,uint8_t port)12995 static uint32_t elink_get_ext_phy_config(struct bxe_softc *sc, uint32_t shmem_base,
12996 uint8_t phy_index, uint8_t port)
12997 {
12998 uint32_t ext_phy_config = 0;
12999 switch (phy_index) {
13000 case ELINK_EXT_PHY1:
13001 ext_phy_config = REG_RD(sc, shmem_base +
13002 offsetof(struct shmem_region,
13003 dev_info.port_hw_config[port].external_phy_config));
13004 break;
13005 case ELINK_EXT_PHY2:
13006 ext_phy_config = REG_RD(sc, shmem_base +
13007 offsetof(struct shmem_region,
13008 dev_info.port_hw_config[port].external_phy_config2));
13009 break;
13010 default:
13011 ELINK_DEBUG_P1(sc, "Invalid phy_index %d\n", phy_index);
13012 return ELINK_STATUS_ERROR;
13013 }
13014
13015 return ext_phy_config;
13016 }
elink_populate_int_phy(struct bxe_softc * sc,uint32_t shmem_base,uint8_t port,struct elink_phy * phy)13017 static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shmem_base, uint8_t port,
13018 struct elink_phy *phy)
13019 {
13020 uint32_t phy_addr;
13021 uint32_t chip_id;
13022 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
13023 offsetof(struct shmem_region,
13024 dev_info.port_feature_config[port].link_config)) &
13025 PORT_FEATURE_CONNECTED_SWITCH_MASK);
13026 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
13027 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
13028
13029 ELINK_DEBUG_P1(sc, ":chip_id = 0x%x\n", chip_id);
13030 if (USES_WARPCORE(sc)) {
13031 uint32_t serdes_net_if;
13032 phy_addr = REG_RD(sc,
13033 MISC_REG_WC0_CTRL_PHY_ADDR);
13034 *phy = phy_warpcore;
13035 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
13036 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
13037 else
13038 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
13039 /* Check Dual mode */
13040 serdes_net_if = (REG_RD(sc, shmem_base +
13041 offsetof(struct shmem_region, dev_info.
13042 port_hw_config[port].default_cfg)) &
13043 PORT_HW_CFG_NET_SERDES_IF_MASK);
13044 /* Set the appropriate supported and flags indications per
13045 * interface type of the chip
13046 */
13047 switch (serdes_net_if) {
13048 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
13049 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
13050 ELINK_SUPPORTED_10baseT_Full |
13051 ELINK_SUPPORTED_100baseT_Half |
13052 ELINK_SUPPORTED_100baseT_Full |
13053 ELINK_SUPPORTED_1000baseT_Full |
13054 ELINK_SUPPORTED_FIBRE |
13055 ELINK_SUPPORTED_Autoneg |
13056 ELINK_SUPPORTED_Pause |
13057 ELINK_SUPPORTED_Asym_Pause);
13058 phy->media_type = ELINK_ETH_PHY_BASE_T;
13059 break;
13060 case PORT_HW_CFG_NET_SERDES_IF_XFI:
13061 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
13062 ELINK_SUPPORTED_10000baseT_Full |
13063 ELINK_SUPPORTED_FIBRE |
13064 ELINK_SUPPORTED_Pause |
13065 ELINK_SUPPORTED_Asym_Pause);
13066 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
13067 break;
13068 case PORT_HW_CFG_NET_SERDES_IF_SFI:
13069 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
13070 ELINK_SUPPORTED_10000baseT_Full |
13071 ELINK_SUPPORTED_FIBRE |
13072 ELINK_SUPPORTED_Pause |
13073 ELINK_SUPPORTED_Asym_Pause);
13074 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
13075 break;
13076 case PORT_HW_CFG_NET_SERDES_IF_KR:
13077 phy->media_type = ELINK_ETH_PHY_KR;
13078 phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |
13079 ELINK_SUPPORTED_10000baseKR_Full |
13080 ELINK_SUPPORTED_FIBRE |
13081 ELINK_SUPPORTED_Autoneg |
13082 ELINK_SUPPORTED_Pause |
13083 ELINK_SUPPORTED_Asym_Pause);
13084 break;
13085 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
13086 phy->media_type = ELINK_ETH_PHY_KR;
13087 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
13088 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
13089 ELINK_SUPPORTED_FIBRE |
13090 ELINK_SUPPORTED_Pause |
13091 ELINK_SUPPORTED_Asym_Pause);
13092 break;
13093 case PORT_HW_CFG_NET_SERDES_IF_KR2:
13094 phy->media_type = ELINK_ETH_PHY_KR;
13095 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
13096 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
13097 ELINK_SUPPORTED_10000baseKR_Full |
13098 ELINK_SUPPORTED_1000baseKX_Full |
13099 ELINK_SUPPORTED_Autoneg |
13100 ELINK_SUPPORTED_FIBRE |
13101 ELINK_SUPPORTED_Pause |
13102 ELINK_SUPPORTED_Asym_Pause);
13103 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13104 break;
13105 default:
13106 ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x\n",
13107 serdes_net_if);
13108 break;
13109 }
13110
13111 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
13112 * was not set as expected. For B0, ECO will be enabled so there
13113 * won't be an issue there
13114 */
13115 if (CHIP_REV(sc) == CHIP_REV_Ax)
13116 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
13117 else
13118 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
13119 ELINK_DEBUG_P3(sc, "media_type = %x, flags = %x, supported = %x\n",
13120 phy->media_type, phy->flags, phy->supported);
13121 } else
13122 {
13123 switch (switch_cfg) {
13124 case ELINK_SWITCH_CFG_1G:
13125 phy_addr = REG_RD(sc,
13126 NIG_REG_SERDES0_CTRL_PHY_ADDR +
13127 port * 0x10);
13128 *phy = phy_serdes;
13129 break;
13130 case ELINK_SWITCH_CFG_10G:
13131 phy_addr = REG_RD(sc,
13132 NIG_REG_XGXS0_CTRL_PHY_ADDR +
13133 port * 0x18);
13134 *phy = phy_xgxs;
13135 break;
13136 default:
13137 ELINK_DEBUG_P0(sc, "Invalid switch_cfg\n");
13138 return ELINK_STATUS_ERROR;
13139 }
13140 }
13141 phy->addr = (uint8_t)phy_addr;
13142 phy->mdio_ctrl = elink_get_emac_base(sc,
13143 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
13144 port);
13145 if (CHIP_IS_E2(sc))
13146 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
13147 else
13148 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
13149
13150 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
13151 port, phy->addr, phy->mdio_ctrl);
13152
13153 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
13154 return ELINK_STATUS_OK;
13155 }
13156
elink_populate_ext_phy(struct bxe_softc * sc,uint8_t phy_index,uint32_t shmem_base,uint32_t shmem2_base,uint8_t port,struct elink_phy * phy)13157 static elink_status_t elink_populate_ext_phy(struct bxe_softc *sc,
13158 uint8_t phy_index,
13159 uint32_t shmem_base,
13160 uint32_t shmem2_base,
13161 uint8_t port,
13162 struct elink_phy *phy)
13163 {
13164 uint32_t ext_phy_config, phy_type, config2;
13165 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
13166 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
13167 phy_index, port);
13168 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
13169 /* Select the phy type */
13170 switch (phy_type) {
13171 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13172 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
13173 *phy = phy_8073;
13174 break;
13175 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
13176 *phy = phy_8705;
13177 break;
13178 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
13179 *phy = phy_8706;
13180 break;
13181 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13182 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
13183 *phy = phy_8726;
13184 break;
13185 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13186 /* BCM8727_NOC => BCM8727 no over current */
13187 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
13188 *phy = phy_8727;
13189 phy->flags |= ELINK_FLAGS_NOC;
13190 break;
13191 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13193 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
13194 *phy = phy_8727;
13195 break;
13196 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
13197 *phy = phy_8481;
13198 break;
13199 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
13200 *phy = phy_84823;
13201 break;
13202 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13203 *phy = phy_84833;
13204 break;
13205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13206 *phy = phy_84834;
13207 break;
13208 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
13209 *phy = phy_84858;
13210 break;
13211 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
13212 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
13213 *phy = phy_54618se;
13214 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
13215 phy->flags |= ELINK_FLAGS_EEE;
13216 break;
13217 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
13218 *phy = phy_7101;
13219 break;
13220 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13221 *phy = phy_null;
13222 return ELINK_STATUS_ERROR;
13223 default:
13224 *phy = phy_null;
13225 /* In case external PHY wasn't found */
13226 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
13227 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
13228 return ELINK_STATUS_ERROR;
13229 return ELINK_STATUS_OK;
13230 }
13231
13232 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
13233 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
13234
13235 /* The shmem address of the phy version is located on different
13236 * structures. In case this structure is too old, do not set
13237 * the address
13238 */
13239 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
13240 dev_info.shared_hw_config.config2));
13241 if (phy_index == ELINK_EXT_PHY1) {
13242 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
13243 port_mb[port].ext_phy_fw_version);
13244
13245 /* Check specific mdc mdio settings */
13246 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
13247 mdc_mdio_access = config2 &
13248 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
13249 } else {
13250 uint32_t size = REG_RD(sc, shmem2_base);
13251
13252 if (size >
13253 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
13254 phy->ver_addr = shmem2_base +
13255 offsetof(struct shmem2_region,
13256 ext_phy_fw_version2[port]);
13257 }
13258 /* Check specific mdc mdio settings */
13259 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
13260 mdc_mdio_access = (config2 &
13261 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
13262 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
13263 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
13264 }
13265 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
13266
13267 if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {
13268 /* Remove 100Mb link supported for BCM84833/4 when phy fw
13269 * version lower than or equal to 1.39
13270 */
13271 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
13272 if (((raw_ver & 0x7F) <= 39) &&
13273 (((raw_ver & 0xF80) >> 7) <= 1))
13274 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
13275 ELINK_SUPPORTED_100baseT_Full);
13276 }
13277
13278 ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n",
13279 phy_type, port, phy_index);
13280 ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x\n",
13281 phy->addr, phy->mdio_ctrl);
13282 return ELINK_STATUS_OK;
13283 }
13284
elink_populate_phy(struct bxe_softc * sc,uint8_t phy_index,uint32_t shmem_base,uint32_t shmem2_base,uint8_t port,struct elink_phy * phy)13285 static elink_status_t elink_populate_phy(struct bxe_softc *sc, uint8_t phy_index, uint32_t shmem_base,
13286 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)
13287 {
13288 elink_status_t status = ELINK_STATUS_OK;
13289 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
13290 if (phy_index == ELINK_INT_PHY)
13291 return elink_populate_int_phy(sc, shmem_base, port, phy);
13292 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
13293 port, phy);
13294 return status;
13295 }
13296
elink_phy_def_cfg(struct elink_params * params,struct elink_phy * phy,uint8_t phy_index)13297 static void elink_phy_def_cfg(struct elink_params *params,
13298 struct elink_phy *phy,
13299 uint8_t phy_index)
13300 {
13301 struct bxe_softc *sc = params->sc;
13302 uint32_t link_config;
13303 /* Populate the default phy configuration for MF mode */
13304 if (phy_index == ELINK_EXT_PHY2) {
13305 link_config = REG_RD(sc, params->shmem_base +
13306 offsetof(struct shmem_region, dev_info.
13307 port_feature_config[params->port].link_config2));
13308 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
13309 offsetof(struct shmem_region,
13310 dev_info.
13311 port_hw_config[params->port].speed_capability_mask2));
13312 } else {
13313 link_config = REG_RD(sc, params->shmem_base +
13314 offsetof(struct shmem_region, dev_info.
13315 port_feature_config[params->port].link_config));
13316 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
13317 offsetof(struct shmem_region,
13318 dev_info.
13319 port_hw_config[params->port].speed_capability_mask));
13320 }
13321 ELINK_DEBUG_P3(sc,
13322 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
13323 phy_index, link_config, phy->speed_cap_mask);
13324
13325 phy->req_duplex = DUPLEX_FULL;
13326 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
13327 case PORT_FEATURE_LINK_SPEED_10M_HALF:
13328 phy->req_duplex = DUPLEX_HALF;
13329 case PORT_FEATURE_LINK_SPEED_10M_FULL:
13330 phy->req_line_speed = ELINK_SPEED_10;
13331 break;
13332 case PORT_FEATURE_LINK_SPEED_100M_HALF:
13333 phy->req_duplex = DUPLEX_HALF;
13334 case PORT_FEATURE_LINK_SPEED_100M_FULL:
13335 phy->req_line_speed = ELINK_SPEED_100;
13336 break;
13337 case PORT_FEATURE_LINK_SPEED_1G:
13338 phy->req_line_speed = ELINK_SPEED_1000;
13339 break;
13340 case PORT_FEATURE_LINK_SPEED_2_5G:
13341 phy->req_line_speed = ELINK_SPEED_2500;
13342 break;
13343 case PORT_FEATURE_LINK_SPEED_10G_CX4:
13344 phy->req_line_speed = ELINK_SPEED_10000;
13345 break;
13346 default:
13347 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
13348 break;
13349 }
13350
13351 ELINK_DEBUG_P2(sc, "Default config phy idx %x, req_duplex config %x\n",
13352 phy_index, phy->req_duplex);
13353
13354 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
13355 case PORT_FEATURE_FLOW_CONTROL_AUTO:
13356 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
13357 break;
13358 case PORT_FEATURE_FLOW_CONTROL_TX:
13359 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
13360 break;
13361 case PORT_FEATURE_FLOW_CONTROL_RX:
13362 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
13363 break;
13364 case PORT_FEATURE_FLOW_CONTROL_BOTH:
13365 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
13366 break;
13367 default:
13368 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
13369 break;
13370 }
13371 ELINK_DEBUG_P3(sc, "Requested Duplex = %x, line_speed = %x, flow_ctrl = %x\n",
13372 phy->req_duplex, phy->req_line_speed, phy->req_flow_ctrl);
13373 }
13374
elink_phy_selection(struct elink_params * params)13375 uint32_t elink_phy_selection(struct elink_params *params)
13376 {
13377 uint32_t phy_config_swapped, prio_cfg;
13378 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
13379
13380 phy_config_swapped = params->multi_phy_config &
13381 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13382
13383 prio_cfg = params->multi_phy_config &
13384 PORT_HW_CFG_PHY_SELECTION_MASK;
13385
13386 if (phy_config_swapped) {
13387 switch (prio_cfg) {
13388 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
13389 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
13390 break;
13391 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
13392 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
13393 break;
13394 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
13395 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
13396 break;
13397 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
13398 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
13399 break;
13400 }
13401 } else
13402 return_cfg = prio_cfg;
13403
13404 return return_cfg;
13405 }
13406
elink_phy_probe(struct elink_params * params)13407 elink_status_t elink_phy_probe(struct elink_params *params)
13408 {
13409 uint8_t phy_index, actual_phy_idx;
13410 uint32_t phy_config_swapped, sync_offset, media_types;
13411 struct bxe_softc *sc = params->sc;
13412 struct elink_phy *phy;
13413 params->num_phys = 0;
13414 ELINK_DEBUG_P0(sc, "Begin phy probe\n");
13415 #ifdef ELINK_INCLUDE_EMUL
13416 if (CHIP_REV_IS_EMUL(sc))
13417 return ELINK_STATUS_OK;
13418 #endif
13419 phy_config_swapped = params->multi_phy_config &
13420 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13421
13422 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
13423 phy_index++) {
13424 actual_phy_idx = phy_index;
13425 if (phy_config_swapped) {
13426 if (phy_index == ELINK_EXT_PHY1)
13427 actual_phy_idx = ELINK_EXT_PHY2;
13428 else if (phy_index == ELINK_EXT_PHY2)
13429 actual_phy_idx = ELINK_EXT_PHY1;
13430 }
13431 ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x,"
13432 " actual_phy_idx %x\n", phy_config_swapped,
13433 phy_index, actual_phy_idx);
13434 phy = ¶ms->phy[actual_phy_idx];
13435 if (elink_populate_phy(sc, phy_index, params->shmem_base,
13436 params->shmem2_base, params->port,
13437 phy) != ELINK_STATUS_OK) {
13438 params->num_phys = 0;
13439 ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d\n",
13440 phy_index);
13441 for (phy_index = ELINK_INT_PHY;
13442 phy_index < ELINK_MAX_PHYS;
13443 phy_index++)
13444 *phy = phy_null;
13445 return ELINK_STATUS_ERROR;
13446 }
13447 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
13448 break;
13449
13450 if (params->feature_config_flags &
13451 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
13452 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13453
13454 if (!(params->feature_config_flags &
13455 ELINK_FEATURE_CONFIG_MT_SUPPORT))
13456 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
13457
13458 sync_offset = params->shmem_base +
13459 offsetof(struct shmem_region,
13460 dev_info.port_hw_config[params->port].media_type);
13461 media_types = REG_RD(sc, sync_offset);
13462
13463 /* Update media type for non-PMF sync only for the first time
13464 * In case the media type changes afterwards, it will be updated
13465 * using the update_status function
13466 */
13467 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
13468 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13469 actual_phy_idx))) == 0) {
13470 media_types |= ((phy->media_type &
13471 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
13472 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13473 actual_phy_idx));
13474 }
13475 REG_WR(sc, sync_offset, media_types);
13476
13477 elink_phy_def_cfg(params, phy, phy_index);
13478 params->num_phys++;
13479 }
13480
13481 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys);
13482 return ELINK_STATUS_OK;
13483 }
13484
13485 #ifdef ELINK_INCLUDE_EMUL
elink_init_e3_emul_mac(struct elink_params * params,struct elink_vars * vars)13486 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
13487 struct elink_vars *vars)
13488 {
13489 struct bxe_softc *sc = params->sc;
13490 vars->line_speed = params->req_line_speed[0];
13491 /* In case link speed is auto, set speed the highest as possible */
13492 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
13493 if (params->feature_config_flags &
13494 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
13495 vars->line_speed = ELINK_SPEED_2500;
13496 else if (elink_is_4_port_mode(sc))
13497 vars->line_speed = ELINK_SPEED_10000;
13498 else
13499 vars->line_speed = ELINK_SPEED_20000;
13500 }
13501 if (vars->line_speed < ELINK_SPEED_10000) {
13502 if ((params->feature_config_flags &
13503 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
13504 ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is"
13505 " disabled!\n", params->req_line_speed[0]);
13506 return ELINK_STATUS_ERROR;
13507 }
13508 switch (vars->line_speed) {
13509 case ELINK_SPEED_10:
13510 vars->link_status = ELINK_LINK_10TFD;
13511 break;
13512 case ELINK_SPEED_100:
13513 vars->link_status = ELINK_LINK_100TXFD;
13514 break;
13515 case ELINK_SPEED_1000:
13516 vars->link_status = ELINK_LINK_1000TFD;
13517 break;
13518 case ELINK_SPEED_2500:
13519 vars->link_status = ELINK_LINK_2500TFD;
13520 break;
13521 default:
13522 ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC\n",
13523 vars->line_speed);
13524 return ELINK_STATUS_ERROR;
13525 }
13526 vars->link_status |= LINK_STATUS_LINK_UP;
13527
13528 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13529 elink_umac_enable(params, vars, 1);
13530 else
13531 elink_umac_enable(params, vars, 0);
13532 } else {
13533 /* Link speed >= 10000 requires XMAC enabled */
13534 if (params->feature_config_flags &
13535 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
13536 ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is"
13537 " disabled!\n", params->req_line_speed[0]);
13538 return ELINK_STATUS_ERROR;
13539 }
13540 /* Check link speed */
13541 switch (vars->line_speed) {
13542 case ELINK_SPEED_10000:
13543 vars->link_status = ELINK_LINK_10GTFD;
13544 break;
13545 case ELINK_SPEED_20000:
13546 vars->link_status = ELINK_LINK_20GTFD;
13547 break;
13548 default:
13549 ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC\n",
13550 vars->line_speed);
13551 return ELINK_STATUS_ERROR;
13552 }
13553 vars->link_status |= LINK_STATUS_LINK_UP;
13554 if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
13555 elink_xmac_enable(params, vars, 1);
13556 else
13557 elink_xmac_enable(params, vars, 0);
13558 }
13559 return ELINK_STATUS_OK;
13560 }
13561
elink_init_emul(struct elink_params * params,struct elink_vars * vars)13562 static elink_status_t elink_init_emul(struct elink_params *params,
13563 struct elink_vars *vars)
13564 {
13565 struct bxe_softc *sc = params->sc;
13566 if (CHIP_IS_E3(sc)) {
13567 if (elink_init_e3_emul_mac(params, vars) !=
13568 ELINK_STATUS_OK)
13569 return ELINK_STATUS_ERROR;
13570 } else {
13571 if (params->feature_config_flags &
13572 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
13573 vars->line_speed = ELINK_SPEED_1000;
13574 vars->link_status = (LINK_STATUS_LINK_UP |
13575 ELINK_LINK_1000XFD);
13576 if (params->loopback_mode ==
13577 ELINK_LOOPBACK_EMAC)
13578 elink_emac_enable(params, vars, 1);
13579 else
13580 elink_emac_enable(params, vars, 0);
13581 } else {
13582 vars->line_speed = ELINK_SPEED_10000;
13583 vars->link_status = (LINK_STATUS_LINK_UP |
13584 ELINK_LINK_10GTFD);
13585 if (params->loopback_mode ==
13586 ELINK_LOOPBACK_BMAC)
13587 elink_bmac_enable(params, vars, 1, 1);
13588 else
13589 elink_bmac_enable(params, vars, 0, 1);
13590 }
13591 }
13592 vars->link_up = 1;
13593 vars->duplex = DUPLEX_FULL;
13594 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13595
13596 if (CHIP_IS_E1x(sc))
13597 elink_pbf_update(params, vars->flow_ctrl,
13598 vars->line_speed);
13599 /* Disable drain */
13600 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13601
13602 /* update shared memory */
13603 elink_update_mng(params, vars->link_status);
13604 return ELINK_STATUS_OK;
13605 }
13606 #endif
13607 #ifdef ELINK_INCLUDE_FPGA
elink_init_fpga(struct elink_params * params,struct elink_vars * vars)13608 static elink_status_t elink_init_fpga(struct elink_params *params,
13609 struct elink_vars *vars)
13610 {
13611 /* Enable on E1.5 FPGA */
13612 struct bxe_softc *sc = params->sc;
13613 vars->duplex = DUPLEX_FULL;
13614 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13615 if (!(CHIP_IS_E1(sc))) {
13616 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX |
13617 ELINK_FLOW_CTRL_RX);
13618 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
13619 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
13620 }
13621 if (CHIP_IS_E3(sc)) {
13622 vars->line_speed = params->req_line_speed[0];
13623 switch (vars->line_speed) {
13624 case ELINK_SPEED_AUTO_NEG:
13625 vars->line_speed = ELINK_SPEED_2500;
13626 case ELINK_SPEED_2500:
13627 vars->link_status = ELINK_LINK_2500TFD;
13628 break;
13629 case ELINK_SPEED_1000:
13630 vars->link_status = ELINK_LINK_1000XFD;
13631 break;
13632 case ELINK_SPEED_100:
13633 vars->link_status = ELINK_LINK_100TXFD;
13634 break;
13635 case ELINK_SPEED_10:
13636 vars->link_status = ELINK_LINK_10TFD;
13637 break;
13638 default:
13639 ELINK_DEBUG_P1(sc, "Invalid link speed %d\n",
13640 params->req_line_speed[0]);
13641 return ELINK_STATUS_ERROR;
13642 }
13643 vars->link_status |= LINK_STATUS_LINK_UP;
13644 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13645 elink_umac_enable(params, vars, 1);
13646 else
13647 elink_umac_enable(params, vars, 0);
13648 } else {
13649 vars->line_speed = ELINK_SPEED_10000;
13650 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
13651 if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
13652 elink_emac_enable(params, vars, 1);
13653 else
13654 elink_emac_enable(params, vars, 0);
13655 }
13656 vars->link_up = 1;
13657
13658 if (CHIP_IS_E1x(sc))
13659 elink_pbf_update(params, vars->flow_ctrl,
13660 vars->line_speed);
13661 /* Disable drain */
13662 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13663
13664 /* Update shared memory */
13665 elink_update_mng(params, vars->link_status);
13666 return ELINK_STATUS_OK;
13667 }
13668 #endif
elink_init_bmac_loopback(struct elink_params * params,struct elink_vars * vars)13669 static void elink_init_bmac_loopback(struct elink_params *params,
13670 struct elink_vars *vars)
13671 {
13672 struct bxe_softc *sc = params->sc;
13673 vars->link_up = 1;
13674 vars->line_speed = ELINK_SPEED_10000;
13675 vars->duplex = DUPLEX_FULL;
13676 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13677 vars->mac_type = ELINK_MAC_TYPE_BMAC;
13678
13679 vars->phy_flags = PHY_XGXS_FLAG;
13680
13681 elink_xgxs_deassert(params);
13682
13683 /* Set bmac loopback */
13684 elink_bmac_enable(params, vars, 1, 1);
13685
13686 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13687 }
13688
elink_init_emac_loopback(struct elink_params * params,struct elink_vars * vars)13689 static void elink_init_emac_loopback(struct elink_params *params,
13690 struct elink_vars *vars)
13691 {
13692 struct bxe_softc *sc = params->sc;
13693 vars->link_up = 1;
13694 vars->line_speed = ELINK_SPEED_1000;
13695 vars->duplex = DUPLEX_FULL;
13696 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13697 vars->mac_type = ELINK_MAC_TYPE_EMAC;
13698
13699 vars->phy_flags = PHY_XGXS_FLAG;
13700
13701 elink_xgxs_deassert(params);
13702 /* Set bmac loopback */
13703 elink_emac_enable(params, vars, 1);
13704 elink_emac_program(params, vars);
13705 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13706 }
13707
elink_init_xmac_loopback(struct elink_params * params,struct elink_vars * vars)13708 static void elink_init_xmac_loopback(struct elink_params *params,
13709 struct elink_vars *vars)
13710 {
13711 struct bxe_softc *sc = params->sc;
13712 vars->link_up = 1;
13713 if (!params->req_line_speed[0])
13714 vars->line_speed = ELINK_SPEED_10000;
13715 else
13716 vars->line_speed = params->req_line_speed[0];
13717 vars->duplex = DUPLEX_FULL;
13718 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13719 vars->mac_type = ELINK_MAC_TYPE_XMAC;
13720 vars->phy_flags = PHY_XGXS_FLAG;
13721 /* Set WC to loopback mode since link is required to provide clock
13722 * to the XMAC in 20G mode
13723 */
13724 elink_set_aer_mmd(params, ¶ms->phy[0]);
13725 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
13726 params->phy[ELINK_INT_PHY].config_loopback(
13727 ¶ms->phy[ELINK_INT_PHY],
13728 params);
13729
13730 elink_xmac_enable(params, vars, 1);
13731 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13732 }
13733
elink_init_umac_loopback(struct elink_params * params,struct elink_vars * vars)13734 static void elink_init_umac_loopback(struct elink_params *params,
13735 struct elink_vars *vars)
13736 {
13737 struct bxe_softc *sc = params->sc;
13738 vars->link_up = 1;
13739 vars->line_speed = ELINK_SPEED_1000;
13740 vars->duplex = DUPLEX_FULL;
13741 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13742 vars->mac_type = ELINK_MAC_TYPE_UMAC;
13743 vars->phy_flags = PHY_XGXS_FLAG;
13744 elink_umac_enable(params, vars, 1);
13745
13746 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13747 }
13748
elink_init_xgxs_loopback(struct elink_params * params,struct elink_vars * vars)13749 static void elink_init_xgxs_loopback(struct elink_params *params,
13750 struct elink_vars *vars)
13751 {
13752 struct bxe_softc *sc = params->sc;
13753 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
13754 vars->link_up = 1;
13755 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13756 vars->duplex = DUPLEX_FULL;
13757 if (params->req_line_speed[0] == ELINK_SPEED_1000)
13758 vars->line_speed = ELINK_SPEED_1000;
13759 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
13760 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
13761 vars->line_speed = ELINK_SPEED_20000;
13762 else
13763 vars->line_speed = ELINK_SPEED_10000;
13764
13765 if (!USES_WARPCORE(sc))
13766 elink_xgxs_deassert(params);
13767 elink_link_initialize(params, vars);
13768
13769 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
13770 if (USES_WARPCORE(sc))
13771 elink_umac_enable(params, vars, 0);
13772 else {
13773 elink_emac_program(params, vars);
13774 elink_emac_enable(params, vars, 0);
13775 }
13776 } else {
13777 if (USES_WARPCORE(sc))
13778 elink_xmac_enable(params, vars, 0);
13779 else
13780 elink_bmac_enable(params, vars, 0, 1);
13781 }
13782
13783 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
13784 /* Set 10G XGXS loopback */
13785 int_phy->config_loopback(int_phy, params);
13786 } else {
13787 /* Set external phy loopback */
13788 uint8_t phy_index;
13789 for (phy_index = ELINK_EXT_PHY1;
13790 phy_index < params->num_phys; phy_index++)
13791 if (params->phy[phy_index].config_loopback)
13792 params->phy[phy_index].config_loopback(
13793 ¶ms->phy[phy_index],
13794 params);
13795 }
13796 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13797
13798 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
13799 }
13800
elink_set_rx_filter(struct elink_params * params,uint8_t en)13801 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
13802 {
13803 struct bxe_softc *sc = params->sc;
13804 uint8_t val = en * 0x1F;
13805
13806 /* Open / close the gate between the NIG and the BRB */
13807 if (!CHIP_IS_E1x(sc))
13808 val |= en * 0x20;
13809 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13810
13811 if (!CHIP_IS_E1(sc)) {
13812 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13813 en*0x3);
13814 }
13815
13816 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13817 NIG_REG_LLH0_BRB1_NOT_MCP), en);
13818 }
elink_avoid_link_flap(struct elink_params * params,struct elink_vars * vars)13819 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
13820 struct elink_vars *vars)
13821 {
13822 uint32_t phy_idx;
13823 uint32_t dont_clear_stat, lfa_sts;
13824 struct bxe_softc *sc = params->sc;
13825
13826 elink_set_mdio_emac_per_phy(sc, params);
13827 /* Sync the link parameters */
13828 elink_link_status_update(params, vars);
13829
13830 /*
13831 * The module verification was already done by previous link owner,
13832 * so this call is meant only to get warning message
13833 */
13834
13835 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
13836 struct elink_phy *phy = ¶ms->phy[phy_idx];
13837 if (phy->phy_specific_func) {
13838 ELINK_DEBUG_P0(sc, "Calling PHY specific func\n");
13839 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
13840 }
13841 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
13842 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
13843 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
13844 elink_verify_sfp_module(phy, params);
13845 }
13846 lfa_sts = REG_RD(sc, params->lfa_base +
13847 offsetof(struct shmem_lfa,
13848 lfa_sts));
13849
13850 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
13851
13852 /* Re-enable the NIG/MAC */
13853 if (CHIP_IS_E3(sc)) {
13854 if (!dont_clear_stat) {
13855 REG_WR(sc, GRCBASE_MISC +
13856 MISC_REGISTERS_RESET_REG_2_CLEAR,
13857 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13858 params->port));
13859 REG_WR(sc, GRCBASE_MISC +
13860 MISC_REGISTERS_RESET_REG_2_SET,
13861 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13862 params->port));
13863 }
13864 if (vars->line_speed < ELINK_SPEED_10000)
13865 elink_umac_enable(params, vars, 0);
13866 else
13867 elink_xmac_enable(params, vars, 0);
13868 } else {
13869 if (vars->line_speed < ELINK_SPEED_10000)
13870 elink_emac_enable(params, vars, 0);
13871 else
13872 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
13873 }
13874
13875 /* Increment LFA count */
13876 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
13877 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
13878 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
13879 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
13880 /* Clear link flap reason */
13881 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13882
13883 REG_WR(sc, params->lfa_base +
13884 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13885
13886 /* Disable NIG DRAIN */
13887 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13888
13889 /* Enable interrupts */
13890 elink_link_int_enable(params);
13891 return ELINK_STATUS_OK;
13892 }
13893
elink_cannot_avoid_link_flap(struct elink_params * params,struct elink_vars * vars,int lfa_status)13894 static void elink_cannot_avoid_link_flap(struct elink_params *params,
13895 struct elink_vars *vars,
13896 int lfa_status)
13897 {
13898 uint32_t lfa_sts, cfg_idx, tmp_val;
13899 struct bxe_softc *sc = params->sc;
13900
13901 elink_link_reset(params, vars, 1);
13902
13903 if (!params->lfa_base)
13904 return;
13905 /* Store the new link parameters */
13906 REG_WR(sc, params->lfa_base +
13907 offsetof(struct shmem_lfa, req_duplex),
13908 params->req_duplex[0] | (params->req_duplex[1] << 16));
13909
13910 REG_WR(sc, params->lfa_base +
13911 offsetof(struct shmem_lfa, req_flow_ctrl),
13912 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
13913
13914 REG_WR(sc, params->lfa_base +
13915 offsetof(struct shmem_lfa, req_line_speed),
13916 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
13917
13918 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
13919 REG_WR(sc, params->lfa_base +
13920 offsetof(struct shmem_lfa,
13921 speed_cap_mask[cfg_idx]),
13922 params->speed_cap_mask[cfg_idx]);
13923 }
13924
13925 tmp_val = REG_RD(sc, params->lfa_base +
13926 offsetof(struct shmem_lfa, additional_config));
13927 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
13928 tmp_val |= params->req_fc_auto_adv;
13929
13930 REG_WR(sc, params->lfa_base +
13931 offsetof(struct shmem_lfa, additional_config), tmp_val);
13932
13933 lfa_sts = REG_RD(sc, params->lfa_base +
13934 offsetof(struct shmem_lfa, lfa_sts));
13935
13936 /* Clear the "Don't Clear Statistics" bit, and set reason */
13937 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
13938
13939 /* Set link flap reason */
13940 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13941 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
13942 LFA_LINK_FLAP_REASON_OFFSET);
13943
13944 /* Increment link flap counter */
13945 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
13946 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
13947 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
13948 << LINK_FLAP_COUNT_OFFSET));
13949 REG_WR(sc, params->lfa_base +
13950 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13951 /* Proceed with regular link initialization */
13952 }
13953
elink_phy_init(struct elink_params * params,struct elink_vars * vars)13954 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars)
13955 {
13956 int lfa_status;
13957 struct bxe_softc *sc = params->sc;
13958 ELINK_DEBUG_P0(sc, "Phy Initialization started\n");
13959 ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d\n",
13960 params->req_line_speed[0], params->req_flow_ctrl[0]);
13961 ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d\n",
13962 params->req_line_speed[1], params->req_flow_ctrl[1]);
13963 ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
13964 vars->link_status = 0;
13965 vars->phy_link_up = 0;
13966 vars->link_up = 0;
13967 vars->line_speed = 0;
13968 vars->duplex = DUPLEX_FULL;
13969 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13970 vars->mac_type = ELINK_MAC_TYPE_NONE;
13971 vars->phy_flags = 0;
13972 vars->check_kr2_recovery_cnt = 0;
13973 params->link_flags = ELINK_PHY_INITIALIZED;
13974 /* Driver opens NIG-BRB filters */
13975 elink_set_rx_filter(params, 1);
13976 elink_chng_link_count(params, 1);
13977 /* Check if link flap can be avoided */
13978 lfa_status = elink_check_lfa(params);
13979
13980 ELINK_DEBUG_P3(sc, " params : port = %x, loopback_mode = %x req_duplex = %x\n",
13981 params->port, params->loopback_mode, params->req_duplex[0]);
13982 ELINK_DEBUG_P3(sc, " params : switch_cfg = %x, lane_config = %x req_duplex[1] = %x\n",
13983 params->switch_cfg, params->lane_config, params->req_duplex[1]);
13984 ELINK_DEBUG_P3(sc, " params : chip_id = %x, feature_config_flags = %x, num_phys = %x\n",
13985 params->chip_id, params->feature_config_flags, params->num_phys);
13986 ELINK_DEBUG_P3(sc, " params : rsrv = %x, eee_mode = %x, hw_led_mode = x\n",
13987 params->rsrv, params->eee_mode, params->hw_led_mode);
13988 ELINK_DEBUG_P3(sc, " params : multi_phy = %x, req_fc_auto_adv = %x, link_flags = %x\n",
13989 params->multi_phy_config, params->req_fc_auto_adv, params->link_flags);
13990 ELINK_DEBUG_P2(sc, " params : lfa_base = %x, link_attr = %x\n",
13991 params->lfa_base, params->link_attr_sync);
13992 if (lfa_status == 0) {
13993 ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress\n");
13994 return elink_avoid_link_flap(params, vars);
13995 }
13996
13997 ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x\n",
13998 lfa_status);
13999 elink_cannot_avoid_link_flap(params, vars, lfa_status);
14000
14001 /* Disable attentions */
14002 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14003 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14004 ELINK_NIG_MASK_XGXS0_LINK10G |
14005 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14006 ELINK_NIG_MASK_MI_INT));
14007 #ifdef ELINK_INCLUDE_EMUL
14008 if (!(params->feature_config_flags &
14009 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
14010 #endif
14011
14012 elink_emac_init(params, vars);
14013
14014 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
14015 vars->link_status |= LINK_STATUS_PFC_ENABLED;
14016
14017 if ((params->num_phys == 0) &&
14018 !CHIP_REV_IS_SLOW(sc)) {
14019 ELINK_DEBUG_P0(sc, "No phy found for initialization !!\n");
14020 return ELINK_STATUS_ERROR;
14021 }
14022 set_phy_vars(params, vars);
14023
14024 ELINK_DEBUG_P1(sc, "Num of phys on board: %d\n", params->num_phys);
14025 #ifdef ELINK_INCLUDE_FPGA
14026 if (CHIP_REV_IS_FPGA(sc)) {
14027 return elink_init_fpga(params, vars);
14028 } else
14029 #endif
14030 #ifdef ELINK_INCLUDE_EMUL
14031 if (CHIP_REV_IS_EMUL(sc)) {
14032 return elink_init_emul(params, vars);
14033 } else
14034 #endif
14035 switch (params->loopback_mode) {
14036 case ELINK_LOOPBACK_BMAC:
14037 elink_init_bmac_loopback(params, vars);
14038 break;
14039 case ELINK_LOOPBACK_EMAC:
14040 elink_init_emac_loopback(params, vars);
14041 break;
14042 case ELINK_LOOPBACK_XMAC:
14043 elink_init_xmac_loopback(params, vars);
14044 break;
14045 case ELINK_LOOPBACK_UMAC:
14046 elink_init_umac_loopback(params, vars);
14047 break;
14048 case ELINK_LOOPBACK_XGXS:
14049 case ELINK_LOOPBACK_EXT_PHY:
14050 elink_init_xgxs_loopback(params, vars);
14051 break;
14052 default:
14053 if (!CHIP_IS_E3(sc)) {
14054 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
14055 elink_xgxs_deassert(params);
14056 else
14057 elink_serdes_deassert(sc, params->port);
14058 }
14059 elink_link_initialize(params, vars);
14060 DELAY(1000 * 30);
14061 elink_link_int_enable(params);
14062 break;
14063 }
14064 elink_update_mng(params, vars->link_status);
14065
14066 elink_update_mng_eee(params, vars->eee_status);
14067 return ELINK_STATUS_OK;
14068 }
14069
elink_link_reset(struct elink_params * params,struct elink_vars * vars,uint8_t reset_ext_phy)14070 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
14071 uint8_t reset_ext_phy)
14072 {
14073 struct bxe_softc *sc = params->sc;
14074 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
14075 ELINK_DEBUG_P1(sc, "Resetting the link of port %d\n", port);
14076 /* Disable attentions */
14077 vars->link_status = 0;
14078 elink_chng_link_count(params, 1);
14079 elink_update_mng(params, vars->link_status);
14080 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
14081 SHMEM_EEE_ACTIVE_BIT);
14082 elink_update_mng_eee(params, vars->eee_status);
14083 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
14084 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14085 ELINK_NIG_MASK_XGXS0_LINK10G |
14086 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14087 ELINK_NIG_MASK_MI_INT));
14088
14089 /* Activate nig drain */
14090 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
14091
14092 /* Disable nig egress interface */
14093 if (!CHIP_IS_E3(sc)) {
14094 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);
14095 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
14096 }
14097
14098 #ifdef ELINK_INCLUDE_EMUL
14099 /* Stop BigMac rx */
14100 if (!(params->feature_config_flags &
14101 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
14102 #endif
14103 if (!CHIP_IS_E3(sc))
14104 elink_set_bmac_rx(sc, params->chip_id, port, 0);
14105 #ifdef ELINK_INCLUDE_EMUL
14106 /* Stop XMAC/UMAC rx */
14107 if (!(params->feature_config_flags &
14108 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
14109 #endif
14110 if (CHIP_IS_E3(sc) &&
14111 !CHIP_REV_IS_FPGA(sc)) {
14112 elink_set_xmac_rxtx(params, 0);
14113 elink_set_umac_rxtx(params, 0);
14114 }
14115 /* Disable emac */
14116 if (!CHIP_IS_E3(sc))
14117 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
14118
14119 DELAY(1000 * 10);
14120 /* The PHY reset is controlled by GPIO 1
14121 * Hold it as vars low
14122 */
14123 /* Clear link led */
14124 elink_set_mdio_emac_per_phy(sc, params);
14125 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
14126
14127 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
14128 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
14129 phy_index++) {
14130 if (params->phy[phy_index].link_reset) {
14131 elink_set_aer_mmd(params,
14132 ¶ms->phy[phy_index]);
14133 params->phy[phy_index].link_reset(
14134 ¶ms->phy[phy_index],
14135 params);
14136 }
14137 if (params->phy[phy_index].flags &
14138 ELINK_FLAGS_REARM_LATCH_SIGNAL)
14139 clear_latch_ind = 1;
14140 }
14141 }
14142
14143 if (clear_latch_ind) {
14144 /* Clear latching indication */
14145 elink_rearm_latch_signal(sc, port, 0);
14146 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port*4,
14147 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
14148 }
14149 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
14150 if (!CHIP_REV_IS_SLOW(sc))
14151 #endif
14152 if (params->phy[ELINK_INT_PHY].link_reset)
14153 params->phy[ELINK_INT_PHY].link_reset(
14154 ¶ms->phy[ELINK_INT_PHY], params);
14155
14156 /* Disable nig ingress interface */
14157 if (!CHIP_IS_E3(sc)) {
14158 /* Reset BigMac */
14159 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
14160 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
14161 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);
14162 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);
14163 } else {
14164 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14165 elink_set_xumac_nig(params, 0, 0);
14166 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14167 MISC_REGISTERS_RESET_REG_2_XMAC)
14168 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
14169 XMAC_CTRL_REG_SOFT_RESET);
14170 }
14171 vars->link_up = 0;
14172 vars->phy_flags = 0;
14173 return ELINK_STATUS_OK;
14174 }
elink_lfa_reset(struct elink_params * params,struct elink_vars * vars)14175 elink_status_t elink_lfa_reset(struct elink_params *params,
14176 struct elink_vars *vars)
14177 {
14178 struct bxe_softc *sc = params->sc;
14179 vars->link_up = 0;
14180 vars->phy_flags = 0;
14181 params->link_flags &= ~ELINK_PHY_INITIALIZED;
14182 if (!params->lfa_base)
14183 return elink_link_reset(params, vars, 1);
14184 /*
14185 * Activate NIG drain so that during this time the device won't send
14186 * anything while it is unable to response.
14187 */
14188 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14189
14190 /*
14191 * Close gracefully the gate from BMAC to NIG such that no half packets
14192 * are passed.
14193 */
14194 if (!CHIP_IS_E3(sc))
14195 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
14196
14197 if (CHIP_IS_E3(sc)) {
14198 elink_set_xmac_rxtx(params, 0);
14199 elink_set_umac_rxtx(params, 0);
14200 }
14201 /* Wait 10ms for the pipe to clean up*/
14202 DELAY(1000 * 10);
14203
14204 /* Clean the NIG-BRB using the network filters in a way that will
14205 * not cut a packet in the middle.
14206 */
14207 elink_set_rx_filter(params, 0);
14208
14209 /*
14210 * Re-open the gate between the BMAC and the NIG, after verifying the
14211 * gate to the BRB is closed, otherwise packets may arrive to the
14212 * firmware before driver had initialized it. The target is to achieve
14213 * minimum management protocol down time.
14214 */
14215 if (!CHIP_IS_E3(sc))
14216 elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
14217
14218 if (CHIP_IS_E3(sc)) {
14219 elink_set_xmac_rxtx(params, 1);
14220 elink_set_umac_rxtx(params, 1);
14221 }
14222 /* Disable NIG drain */
14223 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14224 return ELINK_STATUS_OK;
14225 }
14226
14227 /****************************************************************************/
14228 /* Common function */
14229 /****************************************************************************/
elink_8073_common_init_phy(struct bxe_softc * sc,uint32_t shmem_base_path[],uint32_t shmem2_base_path[],uint8_t phy_index,uint32_t chip_id)14230 static elink_status_t elink_8073_common_init_phy(struct bxe_softc *sc,
14231 uint32_t shmem_base_path[],
14232 uint32_t shmem2_base_path[], uint8_t phy_index,
14233 uint32_t chip_id)
14234 {
14235 struct elink_phy phy[PORT_MAX];
14236 struct elink_phy *phy_blk[PORT_MAX];
14237 uint16_t val;
14238 int8_t port = 0;
14239 int8_t port_of_path = 0;
14240 uint32_t swap_val, swap_override;
14241 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14242 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14243 port ^= (swap_val && swap_override);
14244 elink_ext_phy_hw_reset(sc, port);
14245 /* PART1 - Reset both phys */
14246 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14247 uint32_t shmem_base, shmem2_base;
14248 /* In E2, same phy is using for port0 of the two paths */
14249 if (CHIP_IS_E1x(sc)) {
14250 shmem_base = shmem_base_path[0];
14251 shmem2_base = shmem2_base_path[0];
14252 port_of_path = port;
14253 } else {
14254 shmem_base = shmem_base_path[port];
14255 shmem2_base = shmem2_base_path[port];
14256 port_of_path = 0;
14257 }
14258
14259 /* Extract the ext phy address for the port */
14260 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14261 port_of_path, &phy[port]) !=
14262 ELINK_STATUS_OK) {
14263 ELINK_DEBUG_P0(sc, "populate_phy failed\n");
14264 return ELINK_STATUS_ERROR;
14265 }
14266 /* Disable attentions */
14267 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
14268 port_of_path*4,
14269 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14270 ELINK_NIG_MASK_XGXS0_LINK10G |
14271 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14272 ELINK_NIG_MASK_MI_INT));
14273
14274 /* Need to take the phy out of low power mode in order
14275 * to write to access its registers
14276 */
14277 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
14278 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14279 port);
14280
14281 /* Reset the phy */
14282 elink_cl45_write(sc, &phy[port],
14283 MDIO_PMA_DEVAD,
14284 MDIO_PMA_REG_CTRL,
14285 1<<15);
14286 }
14287
14288 /* Add delay of 150ms after reset */
14289 DELAY(1000 * 150);
14290
14291 if (phy[PORT_0].addr & 0x1) {
14292 phy_blk[PORT_0] = &(phy[PORT_1]);
14293 phy_blk[PORT_1] = &(phy[PORT_0]);
14294 } else {
14295 phy_blk[PORT_0] = &(phy[PORT_0]);
14296 phy_blk[PORT_1] = &(phy[PORT_1]);
14297 }
14298
14299 /* PART2 - Download firmware to both phys */
14300 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14301 if (CHIP_IS_E1x(sc))
14302 port_of_path = port;
14303 else
14304 port_of_path = 0;
14305
14306 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14307 phy_blk[port]->addr);
14308 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14309 port_of_path))
14310 return ELINK_STATUS_ERROR;
14311
14312 /* Only set bit 10 = 1 (Tx power down) */
14313 elink_cl45_read(sc, phy_blk[port],
14314 MDIO_PMA_DEVAD,
14315 MDIO_PMA_REG_TX_POWER_DOWN, &val);
14316
14317 /* Phase1 of TX_POWER_DOWN reset */
14318 elink_cl45_write(sc, phy_blk[port],
14319 MDIO_PMA_DEVAD,
14320 MDIO_PMA_REG_TX_POWER_DOWN,
14321 (val | 1<<10));
14322 }
14323
14324 /* Toggle Transmitter: Power down and then up with 600ms delay
14325 * between
14326 */
14327 DELAY(1000 * 600);
14328
14329 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
14330 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14331 /* Phase2 of POWER_DOWN_RESET */
14332 /* Release bit 10 (Release Tx power down) */
14333 elink_cl45_read(sc, phy_blk[port],
14334 MDIO_PMA_DEVAD,
14335 MDIO_PMA_REG_TX_POWER_DOWN, &val);
14336
14337 elink_cl45_write(sc, phy_blk[port],
14338 MDIO_PMA_DEVAD,
14339 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
14340 DELAY(1000 * 15);
14341
14342 /* Read modify write the SPI-ROM version select register */
14343 elink_cl45_read(sc, phy_blk[port],
14344 MDIO_PMA_DEVAD,
14345 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
14346 elink_cl45_write(sc, phy_blk[port],
14347 MDIO_PMA_DEVAD,
14348 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
14349
14350 /* set GPIO2 back to LOW */
14351 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
14352 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
14353 }
14354 return ELINK_STATUS_OK;
14355 }
elink_8726_common_init_phy(struct bxe_softc * sc,uint32_t shmem_base_path[],uint32_t shmem2_base_path[],uint8_t phy_index,uint32_t chip_id)14356 static elink_status_t elink_8726_common_init_phy(struct bxe_softc *sc,
14357 uint32_t shmem_base_path[],
14358 uint32_t shmem2_base_path[], uint8_t phy_index,
14359 uint32_t chip_id)
14360 {
14361 uint32_t val;
14362 int8_t port;
14363 struct elink_phy phy;
14364 /* Use port1 because of the static port-swap */
14365 /* Enable the module detection interrupt */
14366 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14367 val |= ((1<<MISC_REGISTERS_GPIO_3)|
14368 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
14369 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
14370
14371 elink_ext_phy_hw_reset(sc, 0);
14372 DELAY(1000 * 5);
14373 for (port = 0; port < PORT_MAX; port++) {
14374 uint32_t shmem_base, shmem2_base;
14375
14376 /* In E2, same phy is using for port0 of the two paths */
14377 if (CHIP_IS_E1x(sc)) {
14378 shmem_base = shmem_base_path[0];
14379 shmem2_base = shmem2_base_path[0];
14380 } else {
14381 shmem_base = shmem_base_path[port];
14382 shmem2_base = shmem2_base_path[port];
14383 }
14384 /* Extract the ext phy address for the port */
14385 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14386 port, &phy) !=
14387 ELINK_STATUS_OK) {
14388 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14389 return ELINK_STATUS_ERROR;
14390 }
14391
14392 /* Reset phy*/
14393 elink_cl45_write(sc, &phy,
14394 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
14395
14396
14397 /* Set fault module detected LED on */
14398 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
14399 MISC_REGISTERS_GPIO_HIGH,
14400 port);
14401 }
14402
14403 return ELINK_STATUS_OK;
14404 }
elink_get_ext_phy_reset_gpio(struct bxe_softc * sc,uint32_t shmem_base,uint8_t * io_gpio,uint8_t * io_port)14405 static void elink_get_ext_phy_reset_gpio(struct bxe_softc *sc, uint32_t shmem_base,
14406 uint8_t *io_gpio, uint8_t *io_port)
14407 {
14408
14409 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
14410 offsetof(struct shmem_region,
14411 dev_info.port_hw_config[PORT_0].default_cfg));
14412 switch (phy_gpio_reset) {
14413 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
14414 *io_gpio = 0;
14415 *io_port = 0;
14416 break;
14417 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
14418 *io_gpio = 1;
14419 *io_port = 0;
14420 break;
14421 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
14422 *io_gpio = 2;
14423 *io_port = 0;
14424 break;
14425 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
14426 *io_gpio = 3;
14427 *io_port = 0;
14428 break;
14429 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
14430 *io_gpio = 0;
14431 *io_port = 1;
14432 break;
14433 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
14434 *io_gpio = 1;
14435 *io_port = 1;
14436 break;
14437 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
14438 *io_gpio = 2;
14439 *io_port = 1;
14440 break;
14441 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
14442 *io_gpio = 3;
14443 *io_port = 1;
14444 break;
14445 default:
14446 /* Don't override the io_gpio and io_port */
14447 break;
14448 }
14449 }
14450
elink_8727_common_init_phy(struct bxe_softc * sc,uint32_t shmem_base_path[],uint32_t shmem2_base_path[],uint8_t phy_index,uint32_t chip_id)14451 static elink_status_t elink_8727_common_init_phy(struct bxe_softc *sc,
14452 uint32_t shmem_base_path[],
14453 uint32_t shmem2_base_path[], uint8_t phy_index,
14454 uint32_t chip_id)
14455 {
14456 int8_t port, reset_gpio;
14457 uint32_t swap_val, swap_override;
14458 struct elink_phy phy[PORT_MAX];
14459 struct elink_phy *phy_blk[PORT_MAX];
14460 int8_t port_of_path;
14461 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14462 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14463
14464 reset_gpio = MISC_REGISTERS_GPIO_1;
14465 port = 1;
14466
14467 /* Retrieve the reset gpio/port which control the reset.
14468 * Default is GPIO1, PORT1
14469 */
14470 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
14471 (uint8_t *)&reset_gpio, (uint8_t *)&port);
14472
14473 /* Calculate the port based on port swap */
14474 port ^= (swap_val && swap_override);
14475
14476 /* Initiate PHY reset*/
14477 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
14478 port);
14479 DELAY(1000 * 1);
14480 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14481 port);
14482
14483 DELAY(1000 * 5);
14484
14485 /* PART1 - Reset both phys */
14486 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14487 uint32_t shmem_base, shmem2_base;
14488
14489 /* In E2, same phy is using for port0 of the two paths */
14490 if (CHIP_IS_E1x(sc)) {
14491 shmem_base = shmem_base_path[0];
14492 shmem2_base = shmem2_base_path[0];
14493 port_of_path = port;
14494 } else {
14495 shmem_base = shmem_base_path[port];
14496 shmem2_base = shmem2_base_path[port];
14497 port_of_path = 0;
14498 }
14499
14500 /* Extract the ext phy address for the port */
14501 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14502 port_of_path, &phy[port]) !=
14503 ELINK_STATUS_OK) {
14504 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14505 return ELINK_STATUS_ERROR;
14506 }
14507 /* disable attentions */
14508 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
14509 port_of_path*4,
14510 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14511 ELINK_NIG_MASK_XGXS0_LINK10G |
14512 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14513 ELINK_NIG_MASK_MI_INT));
14514
14515
14516 /* Reset the phy */
14517 elink_cl45_write(sc, &phy[port],
14518 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
14519 }
14520
14521 /* Add delay of 150ms after reset */
14522 DELAY(1000 * 150);
14523 if (phy[PORT_0].addr & 0x1) {
14524 phy_blk[PORT_0] = &(phy[PORT_1]);
14525 phy_blk[PORT_1] = &(phy[PORT_0]);
14526 } else {
14527 phy_blk[PORT_0] = &(phy[PORT_0]);
14528 phy_blk[PORT_1] = &(phy[PORT_1]);
14529 }
14530 /* PART2 - Download firmware to both phys */
14531 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14532 if (CHIP_IS_E1x(sc))
14533 port_of_path = port;
14534 else
14535 port_of_path = 0;
14536 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14537 phy_blk[port]->addr);
14538 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14539 port_of_path))
14540 return ELINK_STATUS_ERROR;
14541 /* Disable PHY transmitter output */
14542 elink_cl45_write(sc, phy_blk[port],
14543 MDIO_PMA_DEVAD,
14544 MDIO_PMA_REG_TX_DISABLE, 1);
14545
14546 }
14547 return ELINK_STATUS_OK;
14548 }
14549
elink_84833_common_init_phy(struct bxe_softc * sc,uint32_t shmem_base_path[],uint32_t shmem2_base_path[],uint8_t phy_index,uint32_t chip_id)14550 static elink_status_t elink_84833_common_init_phy(struct bxe_softc *sc,
14551 uint32_t shmem_base_path[],
14552 uint32_t shmem2_base_path[],
14553 uint8_t phy_index,
14554 uint32_t chip_id)
14555 {
14556 uint8_t reset_gpios;
14557 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
14558 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
14559 DELAY(10);
14560 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
14561 ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x\n",
14562 reset_gpios);
14563 return ELINK_STATUS_OK;
14564 }
elink_ext_phy_common_init(struct bxe_softc * sc,uint32_t shmem_base_path[],uint32_t shmem2_base_path[],uint8_t phy_index,uint32_t ext_phy_type,uint32_t chip_id)14565 static elink_status_t elink_ext_phy_common_init(struct bxe_softc *sc, uint32_t shmem_base_path[],
14566 uint32_t shmem2_base_path[], uint8_t phy_index,
14567 uint32_t ext_phy_type, uint32_t chip_id)
14568 {
14569 elink_status_t rc = ELINK_STATUS_OK;
14570
14571 switch (ext_phy_type) {
14572 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
14573 rc = elink_8073_common_init_phy(sc, shmem_base_path,
14574 shmem2_base_path,
14575 phy_index, chip_id);
14576 break;
14577 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
14578 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
14579 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
14580 rc = elink_8727_common_init_phy(sc, shmem_base_path,
14581 shmem2_base_path,
14582 phy_index, chip_id);
14583 break;
14584
14585 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
14586 /* GPIO1 affects both ports, so there's need to pull
14587 * it for single port alone
14588 */
14589 rc = elink_8726_common_init_phy(sc, shmem_base_path,
14590 shmem2_base_path,
14591 phy_index, chip_id);
14592 break;
14593 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
14594 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
14595 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
14596 /* GPIO3's are linked, and so both need to be toggled
14597 * to obtain required 2us pulse.
14598 */
14599 rc = elink_84833_common_init_phy(sc, shmem_base_path,
14600 shmem2_base_path,
14601 phy_index, chip_id);
14602 break;
14603 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
14604 rc = ELINK_STATUS_ERROR;
14605 break;
14606 default:
14607 ELINK_DEBUG_P1(sc,
14608 "ext_phy 0x%x common init not required\n",
14609 ext_phy_type);
14610 break;
14611 }
14612
14613 if (rc != ELINK_STATUS_OK)
14614 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
14615 // " Port %d\n",
14616
14617 return rc;
14618 }
14619
elink_common_init_phy(struct bxe_softc * sc,uint32_t shmem_base_path[],uint32_t shmem2_base_path[],uint32_t chip_id,uint8_t one_port_enabled)14620 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
14621 uint32_t shmem2_base_path[], uint32_t chip_id,
14622 uint8_t one_port_enabled)
14623 {
14624 elink_status_t rc = ELINK_STATUS_OK;
14625 uint32_t phy_ver, val;
14626 uint8_t phy_index = 0;
14627 uint32_t ext_phy_type, ext_phy_config;
14628 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
14629 if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
14630 return ELINK_STATUS_OK;
14631 #endif
14632
14633 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);
14634 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);
14635 ELINK_DEBUG_P0(sc, "Begin common phy init\n");
14636 if (CHIP_IS_E3(sc)) {
14637 /* Enable EPIO */
14638 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
14639 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
14640 }
14641 /* Check if common init was already done */
14642 phy_ver = REG_RD(sc, shmem_base_path[0] +
14643 offsetof(struct shmem_region,
14644 port_mb[PORT_0].ext_phy_fw_version));
14645 if (phy_ver) {
14646 ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n",
14647 phy_ver);
14648 return ELINK_STATUS_OK;
14649 }
14650
14651 /* Read the ext_phy_type for arbitrary port(0) */
14652 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14653 phy_index++) {
14654 ext_phy_config = elink_get_ext_phy_config(sc,
14655 shmem_base_path[0],
14656 phy_index, 0);
14657 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
14658 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
14659 shmem2_base_path,
14660 phy_index, ext_phy_type,
14661 chip_id);
14662 }
14663 return rc;
14664 }
14665
elink_check_over_curr(struct elink_params * params,struct elink_vars * vars)14666 static void elink_check_over_curr(struct elink_params *params,
14667 struct elink_vars *vars)
14668 {
14669 struct bxe_softc *sc = params->sc;
14670 uint32_t cfg_pin;
14671 uint8_t port = params->port;
14672 uint32_t pin_val;
14673
14674 cfg_pin = (REG_RD(sc, params->shmem_base +
14675 offsetof(struct shmem_region,
14676 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
14677 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
14678 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
14679
14680 /* Ignore check if no external input PIN available */
14681 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
14682 return;
14683
14684 if (!pin_val) {
14685 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
14686 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
14687 // " been detected and the power to "
14688 // "that SFP+ module has been removed"
14689 // " to prevent failure of the card."
14690 // " Please remove the SFP+ module and"
14691 // " restart the system to clear this"
14692 // " error.\n",
14693 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
14694 elink_warpcore_power_module(params, 0);
14695 }
14696 } else
14697 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
14698 }
14699
14700 /* Returns 0 if no change occurred since last check; 1 otherwise. */
elink_analyze_link_error(struct elink_params * params,struct elink_vars * vars,uint32_t status,uint32_t phy_flag,uint32_t link_flag,uint8_t notify)14701 static uint8_t elink_analyze_link_error(struct elink_params *params,
14702 struct elink_vars *vars, uint32_t status,
14703 uint32_t phy_flag, uint32_t link_flag, uint8_t notify)
14704 {
14705 struct bxe_softc *sc = params->sc;
14706 /* Compare new value with previous value */
14707 uint8_t led_mode;
14708 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
14709
14710 if ((status ^ old_status) == 0)
14711 return 0;
14712
14713 /* If values differ */
14714 switch (phy_flag) {
14715 case PHY_HALF_OPEN_CONN_FLAG:
14716 ELINK_DEBUG_P0(sc, "Analyze Remote Fault\n");
14717 break;
14718 case PHY_SFP_TX_FAULT_FLAG:
14719 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n");
14720 break;
14721 default:
14722 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n");
14723 }
14724 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up,
14725 old_status, status);
14726
14727 /* Do not touch the link in case physical link down */
14728 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
14729 return 1;
14730
14731 /* a. Update shmem->link_status accordingly
14732 * b. Update elink_vars->link_up
14733 */
14734 if (status) {
14735 vars->link_status &= ~LINK_STATUS_LINK_UP;
14736 vars->link_status |= link_flag;
14737 vars->link_up = 0;
14738 vars->phy_flags |= phy_flag;
14739
14740 /* activate nig drain */
14741 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14742 /* Set LED mode to off since the PHY doesn't know about these
14743 * errors
14744 */
14745 led_mode = ELINK_LED_MODE_OFF;
14746 } else {
14747 vars->link_status |= LINK_STATUS_LINK_UP;
14748 vars->link_status &= ~link_flag;
14749 vars->link_up = 1;
14750 vars->phy_flags &= ~phy_flag;
14751 led_mode = ELINK_LED_MODE_OPER;
14752
14753 /* Clear nig drain */
14754 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14755 }
14756 elink_sync_link(params, vars);
14757 /* Update the LED according to the link state */
14758 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
14759
14760 /* Update link status in the shared memory */
14761 elink_update_mng(params, vars->link_status);
14762
14763 /* C. Trigger General Attention */
14764 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
14765 if (notify)
14766 elink_cb_notify_link_changed(sc);
14767
14768 return 1;
14769 }
14770
14771 /******************************************************************************
14772 * Description:
14773 * This function checks for half opened connection change indication.
14774 * When such change occurs, it calls the elink_analyze_link_error
14775 * to check if Remote Fault is set or cleared. Reception of remote fault
14776 * status message in the MAC indicates that the peer's MAC has detected
14777 * a fault, for example, due to break in the TX side of fiber.
14778 *
14779 ******************************************************************************/
14780 static
elink_check_half_open_conn(struct elink_params * params,struct elink_vars * vars,uint8_t notify)14781 elink_status_t elink_check_half_open_conn(struct elink_params *params,
14782 struct elink_vars *vars,
14783 uint8_t notify)
14784 {
14785 struct bxe_softc *sc = params->sc;
14786 uint32_t lss_status = 0;
14787 uint32_t mac_base;
14788 /* In case link status is physically up @ 10G do */
14789 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
14790 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
14791 return ELINK_STATUS_OK;
14792
14793 if (CHIP_IS_E3(sc) &&
14794 (REG_RD(sc, MISC_REG_RESET_REG_2) &
14795 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
14796 /* Check E3 XMAC */
14797 /* Note that link speed cannot be queried here, since it may be
14798 * zero while link is down. In case UMAC is active, LSS will
14799 * simply not be set
14800 */
14801 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14802
14803 /* Clear stick bits (Requires rising edge) */
14804 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
14805 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
14806 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
14807 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
14808 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
14809 lss_status = 1;
14810
14811 elink_analyze_link_error(params, vars, lss_status,
14812 PHY_HALF_OPEN_CONN_FLAG,
14813 LINK_STATUS_NONE, notify);
14814 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14815 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
14816 /* Check E1X / E2 BMAC */
14817 uint32_t lss_status_reg;
14818 uint32_t wb_data[2];
14819 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
14820 NIG_REG_INGRESS_BMAC0_MEM;
14821 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
14822 if (CHIP_IS_E2(sc))
14823 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
14824 else
14825 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
14826
14827 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
14828 lss_status = (wb_data[0] > 0);
14829
14830 elink_analyze_link_error(params, vars, lss_status,
14831 PHY_HALF_OPEN_CONN_FLAG,
14832 LINK_STATUS_NONE, notify);
14833 }
14834 return ELINK_STATUS_OK;
14835 }
elink_sfp_tx_fault_detection(struct elink_phy * phy,struct elink_params * params,struct elink_vars * vars)14836 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
14837 struct elink_params *params,
14838 struct elink_vars *vars)
14839 {
14840 struct bxe_softc *sc = params->sc;
14841 uint32_t cfg_pin, value = 0;
14842 uint8_t led_change, port = params->port;
14843
14844 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
14845 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
14846 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
14847 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
14848 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
14849
14850 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
14851 ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x\n", cfg_pin);
14852 return;
14853 }
14854
14855 led_change = elink_analyze_link_error(params, vars, value,
14856 PHY_SFP_TX_FAULT_FLAG,
14857 LINK_STATUS_SFP_TX_FAULT, 1);
14858
14859 if (led_change) {
14860 /* Change TX_Fault led, set link status for further syncs */
14861 uint8_t led_mode;
14862
14863 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
14864 led_mode = MISC_REGISTERS_GPIO_HIGH;
14865 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
14866 } else {
14867 led_mode = MISC_REGISTERS_GPIO_LOW;
14868 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14869 }
14870
14871 /* If module is unapproved, led should be on regardless */
14872 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
14873 ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x\n",
14874 led_mode);
14875 elink_set_e3_module_fault_led(params, led_mode);
14876 }
14877 }
14878 }
elink_kr2_recovery(struct elink_params * params,struct elink_vars * vars,struct elink_phy * phy)14879 static void elink_kr2_recovery(struct elink_params *params,
14880 struct elink_vars *vars,
14881 struct elink_phy *phy)
14882 {
14883 struct bxe_softc *sc = params->sc;
14884 ELINK_DEBUG_P0(sc, "KR2 recovery\n");
14885 elink_warpcore_enable_AN_KR2(phy, params, vars);
14886 elink_warpcore_restart_AN_KR(phy, params);
14887 }
14888
elink_check_kr2_wa(struct elink_params * params,struct elink_vars * vars,struct elink_phy * phy)14889 static void elink_check_kr2_wa(struct elink_params *params,
14890 struct elink_vars *vars,
14891 struct elink_phy *phy)
14892 {
14893 struct bxe_softc *sc = params->sc;
14894 uint16_t base_page, next_page, not_kr2_device, lane;
14895 int sigdet;
14896
14897 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
14898 * Since some switches tend to reinit the AN process and clear the
14899 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
14900 * and recovered many times
14901 */
14902 if (vars->check_kr2_recovery_cnt > 0) {
14903 vars->check_kr2_recovery_cnt--;
14904 return;
14905 }
14906
14907 sigdet = elink_warpcore_get_sigdet(phy, params);
14908 if (!sigdet) {
14909 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14910 elink_kr2_recovery(params, vars, phy);
14911 ELINK_DEBUG_P0(sc, "No sigdet\n");
14912 }
14913 return;
14914 }
14915
14916 lane = elink_get_warpcore_lane(phy, params);
14917 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
14918 MDIO_AER_BLOCK_AER_REG, lane);
14919 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14920 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
14921 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14922 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
14923 elink_set_aer_mmd(params, phy);
14924
14925 /* CL73 has not begun yet */
14926 if (base_page == 0) {
14927 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14928 elink_kr2_recovery(params, vars, phy);
14929 ELINK_DEBUG_P0(sc, "No BP\n");
14930 }
14931 return;
14932 }
14933
14934 /* In case NP bit is not set in the BasePage, or it is set,
14935 * but only KX is advertised, declare this link partner as non-KR2
14936 * device.
14937 */
14938 not_kr2_device = (((base_page & 0x8000) == 0) ||
14939 (((base_page & 0x8000) &&
14940 ((next_page & 0xe0) == 0x20))));
14941
14942 /* In case KR2 is already disabled, check if we need to re-enable it */
14943 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14944 if (!not_kr2_device) {
14945 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page,
14946 next_page);
14947 elink_kr2_recovery(params, vars, phy);
14948 }
14949 return;
14950 }
14951 /* KR2 is enabled, but not KR2 device */
14952 if (not_kr2_device) {
14953 /* Disable KR2 on both lanes */
14954 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, next_page);
14955 elink_disable_kr2(params, vars, phy);
14956 /* Restart AN on leading lane */
14957 elink_warpcore_restart_AN_KR(phy, params);
14958 return;
14959 }
14960 }
14961
elink_period_func(struct elink_params * params,struct elink_vars * vars)14962 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
14963 {
14964 uint16_t phy_idx;
14965 struct bxe_softc *sc = params->sc;
14966 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
14967 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
14968 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
14969 if (elink_check_half_open_conn(params, vars, 1) !=
14970 ELINK_STATUS_OK)
14971 ELINK_DEBUG_P0(sc, "Fault detection failed\n");
14972 break;
14973 }
14974 }
14975
14976 if (CHIP_IS_E3(sc)) {
14977 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
14978 elink_set_aer_mmd(params, phy);
14979 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
14980 (phy->speed_cap_mask &
14981 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
14982 (phy->req_line_speed == ELINK_SPEED_20000))
14983 elink_check_kr2_wa(params, vars, phy);
14984 elink_check_over_curr(params, vars);
14985 if (vars->rx_tx_asic_rst)
14986 elink_warpcore_config_runtime(phy, params, vars);
14987
14988 if ((REG_RD(sc, params->shmem_base +
14989 offsetof(struct shmem_region, dev_info.
14990 port_hw_config[params->port].default_cfg))
14991 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
14992 PORT_HW_CFG_NET_SERDES_IF_SFI) {
14993 if (elink_is_sfp_module_plugged(phy, params)) {
14994 elink_sfp_tx_fault_detection(phy, params, vars);
14995 } else if (vars->link_status &
14996 LINK_STATUS_SFP_TX_FAULT) {
14997 /* Clean trail, interrupt corrects the leds */
14998 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14999 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
15000 /* Update link status in the shared memory */
15001 elink_update_mng(params, vars->link_status);
15002 }
15003 }
15004 }
15005 }
15006
elink_fan_failure_det_req(struct bxe_softc * sc,uint32_t shmem_base,uint32_t shmem2_base,uint8_t port)15007 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc,
15008 uint32_t shmem_base,
15009 uint32_t shmem2_base,
15010 uint8_t port)
15011 {
15012 uint8_t phy_index, fan_failure_det_req = 0;
15013 struct elink_phy phy;
15014 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
15015 phy_index++) {
15016 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
15017 port, &phy)
15018 != ELINK_STATUS_OK) {
15019 ELINK_DEBUG_P0(sc, "populate phy failed\n");
15020 return 0;
15021 }
15022 fan_failure_det_req |= (phy.flags &
15023 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
15024 }
15025 return fan_failure_det_req;
15026 }
15027
elink_hw_reset_phy(struct elink_params * params)15028 void elink_hw_reset_phy(struct elink_params *params)
15029 {
15030 uint8_t phy_index;
15031 struct bxe_softc *sc = params->sc;
15032 elink_update_mng(params, 0);
15033 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
15034 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
15035 ELINK_NIG_MASK_XGXS0_LINK10G |
15036 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
15037 ELINK_NIG_MASK_MI_INT));
15038
15039 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
15040 phy_index++) {
15041 if (params->phy[phy_index].hw_reset) {
15042 params->phy[phy_index].hw_reset(
15043 ¶ms->phy[phy_index],
15044 params);
15045 params->phy[phy_index] = phy_null;
15046 }
15047 }
15048 }
15049
elink_init_mod_abs_int(struct bxe_softc * sc,struct elink_vars * vars,uint32_t chip_id,uint32_t shmem_base,uint32_t shmem2_base,uint8_t port)15050 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
15051 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
15052 uint8_t port)
15053 {
15054 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
15055 uint32_t val;
15056 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
15057 if (CHIP_IS_E3(sc)) {
15058 if (elink_get_mod_abs_int_cfg(sc, chip_id,
15059 shmem_base,
15060 port,
15061 &gpio_num,
15062 &gpio_port) != ELINK_STATUS_OK)
15063 return;
15064 } else {
15065 struct elink_phy phy;
15066 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
15067 phy_index++) {
15068 if (elink_populate_phy(sc, phy_index, shmem_base,
15069 shmem2_base, port, &phy)
15070 != ELINK_STATUS_OK) {
15071 ELINK_DEBUG_P0(sc, "populate phy failed\n");
15072 return;
15073 }
15074 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
15075 gpio_num = MISC_REGISTERS_GPIO_3;
15076 gpio_port = port;
15077 break;
15078 }
15079 }
15080 }
15081
15082 if (gpio_num == 0xff)
15083 return;
15084
15085 /* Set GPIO3 to trigger SFP+ module insertion/removal */
15086 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
15087
15088 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
15089 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
15090 gpio_port ^= (swap_val && swap_override);
15091
15092 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
15093 (gpio_num + (gpio_port << 2));
15094
15095 sync_offset = shmem_base +
15096 offsetof(struct shmem_region,
15097 dev_info.port_hw_config[port].aeu_int_mask);
15098 REG_WR(sc, sync_offset, vars->aeu_int_mask);
15099
15100 ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
15101 gpio_num, gpio_port, vars->aeu_int_mask);
15102
15103 if (port == 0)
15104 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
15105 else
15106 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
15107
15108 /* Open appropriate AEU for interrupts */
15109 aeu_mask = REG_RD(sc, offset);
15110 aeu_mask |= vars->aeu_int_mask;
15111 REG_WR(sc, offset, aeu_mask);
15112
15113 /* Enable the GPIO to trigger interrupt */
15114 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
15115 val |= 1 << (gpio_num + (gpio_port << 2));
15116 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
15117 }
15118
15119