xref: /linux/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Samsung S5P Multi Format Codec v 5.0
4  *
5  * This file contains definitions of enums and structs used by the codec
6  * driver.
7  *
8  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
9  * Kamil Debski, <k.debski@samsung.com>
10  */
11 
12 #ifndef S5P_MFC_COMMON_H_
13 #define S5P_MFC_COMMON_H_
14 
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-ioctl.h>
20 #include <media/videobuf2-v4l2.h>
21 #include "regs-mfc.h"
22 #include "regs-mfc-v12.h"
23 
24 #define S5P_MFC_NAME		"s5p-mfc"
25 
26 /* Definitions related to MFC memory */
27 
28 /* Offset base used to differentiate between CAPTURE and OUTPUT
29 *  while mmaping */
30 #define DST_QUEUE_OFF_BASE	(1 << 30)
31 
32 #define BANK_L_CTX	0
33 #define BANK_R_CTX	1
34 #define BANK_CTX_NUM	2
35 
36 #define MFC_BANK1_ALIGN_ORDER	13
37 #define MFC_BANK2_ALIGN_ORDER	13
38 #define MFC_BASE_ALIGN_ORDER	17
39 
40 #define MFC_FW_MAX_VERSIONS	2
41 
42 #include <media/videobuf2-dma-contig.h>
43 
44 /* MFC definitions */
45 #define MFC_MAX_EXTRA_DPB       5
46 #define MFC_MAX_BUFFERS		32
47 #define MFC_NUM_CONTEXTS	4
48 /* Interrupt timeout */
49 #define MFC_INT_TIMEOUT		2000
50 /* Busy wait timeout */
51 #define MFC_BW_TIMEOUT		500
52 /* Watchdog interval */
53 #define MFC_WATCHDOG_INTERVAL   1000
54 /* After how many executions watchdog should assume lock up */
55 #define MFC_WATCHDOG_CNT        10
56 #define MFC_NO_INSTANCE_SET	-1
57 #define MFC_ENC_CAP_PLANE_COUNT	1
58 #define MFC_ENC_OUT_PLANE_COUNT	2
59 #define VB2_MAX_PLANE_COUNT	3
60 #define STUFF_BYTE		4
61 #define MFC_MAX_CTRLS		128
62 
63 #define S5P_MFC_CODEC_NONE		-1
64 #define S5P_MFC_CODEC_H264_DEC		0
65 #define S5P_MFC_CODEC_H264_MVC_DEC	1
66 #define S5P_MFC_CODEC_VC1_DEC		2
67 #define S5P_MFC_CODEC_MPEG4_DEC		3
68 #define S5P_MFC_CODEC_MPEG2_DEC		4
69 #define S5P_MFC_CODEC_H263_DEC		5
70 #define S5P_MFC_CODEC_VC1RCV_DEC	6
71 #define S5P_MFC_CODEC_VP8_DEC		7
72 #define S5P_MFC_CODEC_HEVC_DEC		17
73 #define S5P_MFC_CODEC_VP9_DEC		18
74 
75 #define S5P_MFC_CODEC_H264_ENC		20
76 #define S5P_MFC_CODEC_H264_MVC_ENC	21
77 #define S5P_MFC_CODEC_MPEG4_ENC		22
78 #define S5P_MFC_CODEC_H263_ENC		23
79 #define S5P_MFC_CODEC_VP8_ENC		24
80 #define S5P_MFC_CODEC_HEVC_ENC		26
81 
82 #define S5P_MFC_R2H_CMD_EMPTY			0
83 #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
84 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET	2
85 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET		3
86 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET	4
87 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET	6
88 #define S5P_MFC_R2H_CMD_SLEEP_RET		7
89 #define S5P_MFC_R2H_CMD_WAKEUP_RET		8
90 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET	9
91 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET		10
92 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET		11
93 #define S5P_MFC_R2H_CMD_FW_STATUS_RET		12
94 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET		13
95 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET		14
96 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET		15
97 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET	16
98 #define S5P_MFC_R2H_CMD_ERR_RET			32
99 
100 #define MFC_MAX_CLOCKS		4
101 
102 #define mfc_read(dev, offset)		readl(dev->regs_base + (offset))
103 #define mfc_write(dev, data, offset)	writel((data), dev->regs_base + \
104 								(offset))
105 
106 /*
107  * enum s5p_mfc_fmt_type - type of the pixelformat
108  */
109 enum s5p_mfc_fmt_type {
110 	MFC_FMT_DEC,
111 	MFC_FMT_ENC,
112 	MFC_FMT_RAW,
113 };
114 
115 /*
116  * enum s5p_mfc_inst_type - The type of an MFC instance.
117  */
118 enum s5p_mfc_inst_type {
119 	MFCINST_INVALID,
120 	MFCINST_DECODER,
121 	MFCINST_ENCODER,
122 };
123 
124 /*
125  * enum s5p_mfc_inst_state - The state of an MFC instance.
126  */
127 enum s5p_mfc_inst_state {
128 	MFCINST_FREE = 0,
129 	MFCINST_INIT = 100,
130 	MFCINST_GOT_INST,
131 	MFCINST_HEAD_PARSED,
132 	MFCINST_HEAD_PRODUCED,
133 	MFCINST_BUFS_SET,
134 	MFCINST_RUNNING,
135 	MFCINST_FINISHING,
136 	MFCINST_FINISHED,
137 	MFCINST_RETURN_INST,
138 	MFCINST_ERROR,
139 	MFCINST_ABORT,
140 	MFCINST_FLUSH,
141 	MFCINST_RES_CHANGE_INIT,
142 	MFCINST_RES_CHANGE_FLUSH,
143 	MFCINST_RES_CHANGE_END,
144 };
145 
146 /*
147  * enum s5p_mfc_queue_state - The state of buffer queue.
148  */
149 enum s5p_mfc_queue_state {
150 	QUEUE_FREE,
151 	QUEUE_BUFS_REQUESTED,
152 	QUEUE_BUFS_QUERIED,
153 	QUEUE_BUFS_MMAPED,
154 };
155 
156 /*
157  * enum s5p_mfc_decode_arg - type of frame decoding
158  */
159 enum s5p_mfc_decode_arg {
160 	MFC_DEC_FRAME,
161 	MFC_DEC_LAST_FRAME,
162 	MFC_DEC_RES_CHANGE,
163 };
164 
165 enum s5p_mfc_fw_ver {
166 	MFC_FW_V1,
167 	MFC_FW_V2,
168 };
169 
170 #define MFC_BUF_FLAG_USED	(1 << 0)
171 #define MFC_BUF_FLAG_EOS	(1 << 1)
172 
173 struct s5p_mfc_ctx;
174 
175 /*
176  * struct s5p_mfc_buf - MFC buffer
177  */
178 struct s5p_mfc_buf {
179 	struct vb2_v4l2_buffer *b;
180 	struct list_head list;
181 	union {
182 		struct {
183 			size_t luma;
184 			size_t chroma;
185 			size_t chroma_1;
186 		} raw;
187 		size_t stream;
188 	} cookie;
189 	int flags;
190 };
191 
192 /*
193  * struct s5p_mfc_pm - power management data structure
194  */
195 struct s5p_mfc_pm {
196 	struct clk	*clock_gate;
197 	const char * const *clk_names;
198 	struct clk	*clocks[MFC_MAX_CLOCKS];
199 	int		num_clocks;
200 	bool		use_clock_gating;
201 
202 	struct device	*device;
203 };
204 
205 struct s5p_mfc_buf_size_v5 {
206 	unsigned int h264_ctx;
207 	unsigned int non_h264_ctx;
208 	unsigned int dsc;
209 	unsigned int shm;
210 };
211 
212 struct s5p_mfc_buf_size_v6 {
213 	unsigned int dev_ctx;
214 	unsigned int h264_dec_ctx;
215 	unsigned int other_dec_ctx;
216 	unsigned int h264_enc_ctx;
217 	unsigned int hevc_enc_ctx;
218 	unsigned int other_enc_ctx;
219 };
220 
221 struct s5p_mfc_buf_size {
222 	unsigned int fw;
223 	unsigned int cpb;
224 	const void *priv;
225 };
226 
227 struct s5p_mfc_variant {
228 	unsigned int version;
229 	unsigned int port_num;
230 	u32 version_bit;
231 	const struct s5p_mfc_buf_size *buf_size;
232 	const char	*fw_name[MFC_FW_MAX_VERSIONS];
233 	const char	*clk_names[MFC_MAX_CLOCKS];
234 	int		num_clocks;
235 	bool		use_clock_gating;
236 };
237 
238 /**
239  * struct s5p_mfc_priv_buf - represents internal used buffer
240  * @ofs:		offset of each buffer, will be used for MFC
241  * @virt:		kernel virtual address, only valid when the
242  *			buffer accessed by driver
243  * @dma:		DMA address, only valid when kernel DMA API used
244  * @size:		size of the buffer
245  * @ctx:		memory context (bank) used for this allocation
246  */
247 struct s5p_mfc_priv_buf {
248 	unsigned long	ofs;
249 	void		*virt;
250 	dma_addr_t	dma;
251 	size_t		size;
252 	unsigned int	ctx;
253 };
254 
255 /**
256  * struct s5p_mfc_dev - The struct containing driver internal parameters.
257  *
258  * @v4l2_dev:		v4l2_device
259  * @vfd_dec:		video device for decoding
260  * @vfd_enc:		video device for encoding
261  * @plat_dev:		platform device
262  * @mem_dev:		child devices of the memory banks
263  * @regs_base:		base address of the MFC hw registers
264  * @irq:		irq resource
265  * @dec_ctrl_handler:	control framework handler for decoding
266  * @enc_ctrl_handler:	control framework handler for encoding
267  * @pm:			power management control
268  * @variant:		MFC hardware variant information
269  * @num_inst:		counter of active MFC instances
270  * @irqlock:		lock for operations on videobuf2 queues
271  * @condlock:		lock for changing/checking if a context is ready to be
272  *			processed
273  * @mfc_mutex:		lock for video_device
274  * @int_cond:		variable used by the waitqueue
275  * @int_type:		type of last interrupt
276  * @int_err:		error number for last interrupt
277  * @queue:		waitqueue for waiting for completion of device commands
278  * @fw_buf:		the firmware buffer data structure
279  * @mem_size:		size of the firmware operation memory
280  * @mem_base:		base DMA address of the firmware operation memory
281  * @mem_bitmap:		bitmap for managing MFC internal buffer allocations
282  * @mem_virt:		virtual address of the firmware operation memory
283  * @dma_base:		address of the beginning of memory banks
284  * @hw_lock:		used for hardware locking
285  * @ctx:		array of driver contexts
286  * @curr_ctx:		number of the currently running context
287  * @ctx_work_bits:	used to mark which contexts are waiting for hardware
288  * @watchdog_cnt:	counter for the watchdog
289  * @watchdog_timer:	timer for the watchdog
290  * @watchdog_workqueue:	workqueue for the watchdog
291  * @watchdog_work:	worker for the watchdog
292  * @enter_suspend:	flag set when entering suspend
293  * @ctx_buf:		common context memory (MFCv6)
294  * @warn_start:		hardware error code from which warnings start
295  * @mfc_ops:		ops structure holding HW operation function pointers
296  * @mfc_cmds:		cmd structure holding HW commands function pointers
297  * @mfc_regs:		structure holding MFC registers
298  * @fw_ver:		loaded firmware sub-version
299  * @fw_get_done:	flag set when request_firmware() is complete and
300  *			copied into fw_buf
301  * @risc_on:		flag indicates RISC is on or off
302  *
303  */
304 struct s5p_mfc_dev {
305 	struct v4l2_device	v4l2_dev;
306 	struct video_device	*vfd_dec;
307 	struct video_device	*vfd_enc;
308 	struct platform_device	*plat_dev;
309 	struct device		*mem_dev[BANK_CTX_NUM];
310 	void __iomem		*regs_base;
311 	int			irq;
312 	struct v4l2_ctrl_handler dec_ctrl_handler;
313 	struct v4l2_ctrl_handler enc_ctrl_handler;
314 	struct s5p_mfc_pm	pm;
315 	const struct s5p_mfc_variant	*variant;
316 	int num_inst;
317 	spinlock_t irqlock;	/* lock when operating on context */
318 	spinlock_t condlock;	/* lock when changing/checking if a context is
319 					ready to be processed */
320 	struct mutex mfc_mutex; /* video_device lock */
321 	int int_cond;
322 	int int_type;
323 	unsigned int int_err;
324 	wait_queue_head_t queue;
325 	struct s5p_mfc_priv_buf fw_buf;
326 	size_t mem_size;
327 	dma_addr_t mem_base;
328 	unsigned long *mem_bitmap;
329 	void *mem_virt;
330 	dma_addr_t dma_base[BANK_CTX_NUM];
331 	unsigned long hw_lock;
332 	struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
333 	int curr_ctx;
334 	unsigned long ctx_work_bits;
335 	atomic_t watchdog_cnt;
336 	struct timer_list watchdog_timer;
337 	struct workqueue_struct *watchdog_workqueue;
338 	struct work_struct watchdog_work;
339 	unsigned long enter_suspend;
340 
341 	struct s5p_mfc_priv_buf ctx_buf;
342 	int warn_start;
343 	const struct s5p_mfc_hw_ops *mfc_ops;
344 	const struct s5p_mfc_hw_cmds *mfc_cmds;
345 	const struct s5p_mfc_regs *mfc_regs;
346 	enum s5p_mfc_fw_ver fw_ver;
347 	bool fw_get_done;
348 	bool risc_on; /* indicates if RISC is on or off */
349 };
350 
351 /*
352  * struct s5p_mfc_h264_enc_params - encoding parameters for h264
353  */
354 struct s5p_mfc_h264_enc_params {
355 	enum v4l2_mpeg_video_h264_profile profile;
356 	enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
357 	s8 loop_filter_alpha;
358 	s8 loop_filter_beta;
359 	enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
360 	u8 max_ref_pic;
361 	u8 num_ref_pic_4p;
362 	int _8x8_transform;
363 	int rc_mb_dark;
364 	int rc_mb_smooth;
365 	int rc_mb_static;
366 	int rc_mb_activity;
367 	int vui_sar;
368 	u8 vui_sar_idc;
369 	u16 vui_ext_sar_width;
370 	u16 vui_ext_sar_height;
371 	int open_gop;
372 	u16 open_gop_size;
373 	u8 rc_frame_qp;
374 	u8 rc_min_qp;
375 	u8 rc_max_qp;
376 	u8 rc_p_frame_qp;
377 	u8 rc_b_frame_qp;
378 	enum v4l2_mpeg_video_h264_level level_v4l2;
379 	int level;
380 	u16 cpb_size;
381 	int interlace;
382 	u8 hier_qp;
383 	u8 hier_qp_type;
384 	u8 hier_qp_layer;
385 	u8 hier_qp_layer_qp[7];
386 	u8 sei_frame_packing;
387 	u8 sei_fp_curr_frame_0;
388 	u8 sei_fp_arrangement_type;
389 
390 	u8 fmo;
391 	u8 fmo_map_type;
392 	u8 fmo_slice_grp;
393 	u8 fmo_chg_dir;
394 	u32 fmo_chg_rate;
395 	u32 fmo_run_len[4];
396 	u8 aso;
397 	u32 aso_slice_order[8];
398 };
399 
400 /*
401  * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
402  */
403 struct s5p_mfc_mpeg4_enc_params {
404 	/* MPEG4 Only */
405 	enum v4l2_mpeg_video_mpeg4_profile profile;
406 	int quarter_pixel;
407 	/* Common for MPEG4, H263 */
408 	u16 vop_time_res;
409 	u16 vop_frm_delta;
410 	u8 rc_frame_qp;
411 	u8 rc_min_qp;
412 	u8 rc_max_qp;
413 	u8 rc_p_frame_qp;
414 	u8 rc_b_frame_qp;
415 	enum v4l2_mpeg_video_mpeg4_level level_v4l2;
416 	int level;
417 };
418 
419 /*
420  * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
421  */
422 struct s5p_mfc_vp8_enc_params {
423 	u8 imd_4x4;
424 	enum v4l2_vp8_num_partitions num_partitions;
425 	enum v4l2_vp8_num_ref_frames num_ref;
426 	u8 filter_level;
427 	u8 filter_sharpness;
428 	u32 golden_frame_ref_period;
429 	enum v4l2_vp8_golden_frame_sel golden_frame_sel;
430 	u8 hier_layer;
431 	u8 hier_layer_qp[3];
432 	u8 rc_min_qp;
433 	u8 rc_max_qp;
434 	u8 rc_frame_qp;
435 	u8 rc_p_frame_qp;
436 	u8 profile;
437 };
438 
439 struct s5p_mfc_hevc_enc_params {
440 	enum v4l2_mpeg_video_hevc_profile profile;
441 	int level;
442 	enum v4l2_mpeg_video_h264_level level_v4l2;
443 	u8 tier;
444 	u32 rc_framerate;
445 	u8 rc_min_qp;
446 	u8 rc_max_qp;
447 	u8 rc_lcu_dark;
448 	u8 rc_lcu_smooth;
449 	u8 rc_lcu_static;
450 	u8 rc_lcu_activity;
451 	u8 rc_frame_qp;
452 	u8 rc_p_frame_qp;
453 	u8 rc_b_frame_qp;
454 	u8 max_partition_depth;
455 	u8 num_refs_for_p;
456 	u8 refreshtype;
457 	u16 refreshperiod;
458 	s32 lf_beta_offset_div2;
459 	s32 lf_tc_offset_div2;
460 	u8 loopfilter;
461 	u8 loopfilter_disable;
462 	u8 loopfilter_across;
463 	u8 nal_control_length_filed;
464 	u8 nal_control_user_ref;
465 	u8 nal_control_store_ref;
466 	u8 const_intra_period_enable;
467 	u8 lossless_cu_enable;
468 	u8 wavefront_enable;
469 	u8 enable_ltr;
470 	u8 hier_qp_enable;
471 	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
472 	u8 num_hier_layer;
473 	u8 hier_qp_layer[7];
474 	u32 hier_bit_layer[7];
475 	u8 sign_data_hiding;
476 	u8 general_pb_enable;
477 	u8 temporal_id_enable;
478 	u8 strong_intra_smooth;
479 	u8 intra_pu_split_disable;
480 	u8 tmv_prediction_disable;
481 	u8 max_num_merge_mv;
482 	u8 eco_mode_enable;
483 	u8 encoding_nostartcode_enable;
484 	u8 size_of_length_field;
485 	u8 prepend_sps_pps_to_idr;
486 };
487 
488 /*
489  * struct s5p_mfc_enc_params - general encoding parameters
490  */
491 struct s5p_mfc_enc_params {
492 	u16 width;
493 	u16 height;
494 	u32 mv_h_range;
495 	u32 mv_v_range;
496 
497 	u16 gop_size;
498 	enum v4l2_mpeg_video_multi_slice_mode slice_mode;
499 	u16 slice_mb;
500 	u32 slice_bit;
501 	u16 intra_refresh_mb;
502 	int pad;
503 	u8 pad_luma;
504 	u8 pad_cb;
505 	u8 pad_cr;
506 	int rc_frame;
507 	int rc_mb;
508 	u32 rc_bitrate;
509 	u16 rc_reaction_coeff;
510 	u16 vbv_size;
511 	u32 vbv_delay;
512 
513 	enum v4l2_mpeg_video_header_mode seq_hdr_mode;
514 	enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
515 	int fixed_target_bit;
516 
517 	u8 num_b_frame;
518 	u32 rc_framerate_num;
519 	u32 rc_framerate_denom;
520 
521 	struct {
522 		struct s5p_mfc_h264_enc_params h264;
523 		struct s5p_mfc_mpeg4_enc_params mpeg4;
524 		struct s5p_mfc_vp8_enc_params vp8;
525 		struct s5p_mfc_hevc_enc_params hevc;
526 	} codec;
527 
528 };
529 
530 /*
531  * struct s5p_mfc_codec_ops - codec ops, used by encoding
532  */
533 struct s5p_mfc_codec_ops {
534 	/* initialization routines */
535 	int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
536 	int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
537 	/* execution routines */
538 	int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
539 	int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
540 };
541 
542 #define call_cop(c, op, args...)				\
543 	(((c)->c_ops->op) ?					\
544 		((c)->c_ops->op(args)) : 0)
545 
546 /**
547  * struct s5p_mfc_ctx - This struct contains the instance context
548  *
549  * @dev:		pointer to the s5p_mfc_dev of the device
550  * @fh:			struct v4l2_fh
551  * @num:		number of the context that this structure describes
552  * @int_cond:		variable used by the waitqueue
553  * @int_type:		type of the last interrupt
554  * @int_err:		error number received from MFC hw in the interrupt
555  * @queue:		waitqueue that can be used to wait for this context to
556  *			finish
557  * @src_fmt:		source pixelformat information
558  * @dst_fmt:		destination pixelformat information
559  * @vq_src:		vb2 queue for source buffers
560  * @vq_dst:		vb2 queue for destination buffers
561  * @src_queue:		driver internal queue for source buffers
562  * @dst_queue:		driver internal queue for destination buffers
563  * @src_queue_cnt:	number of buffers queued on the source internal queue
564  * @dst_queue_cnt:	number of buffers queued on the dest internal queue
565  * @type:		type of the instance - decoder or encoder
566  * @state:		state of the context
567  * @inst_no:		number of hw instance associated with the context
568  * @img_width:		width of the image that is decoded or encoded
569  * @img_height:		height of the image that is decoded or encoded
570  * @buf_width:		width of the buffer for processed image
571  * @buf_height:		height of the buffer for processed image
572  * @luma_size:		size of a luma plane
573  * @chroma_size:	size of a chroma plane
574  * @mv_size:		size of a motion vectors buffer
575  * @consumed_stream:	number of bytes that have been used so far from the
576  *			decoding buffer
577  * @dpb_flush_flag:	flag used to indicate that a DPB buffers are being
578  *			flushed
579  * @head_processed:	flag mentioning whether the header data is processed
580  *			completely or not
581  * @bank1:		handle to memory allocated for temporary buffers from
582  *			memory bank 1
583  * @bank2:		handle to memory allocated for temporary buffers from
584  *			memory bank 2
585  * @capture_state:	state of the capture buffers queue
586  * @output_state:	state of the output buffers queue
587  * @src_bufs:		information on allocated source buffers
588  * @src_bufs_cnt:	number of allocated source buffers
589  * @dst_bufs:		information on allocated destination buffers
590  * @dst_bufs_cnt:	number of allocated destination buffers
591  * @sequence:		counter for the sequence number for v4l2
592  * @dec_dst_flag:	flags for buffers queued in the hardware
593  * @dec_src_buf_size:	size of the buffer for source buffers in decoding
594  * @codec_mode:		number of codec mode used by MFC hw
595  * @slice_interface:	slice interface flag
596  * @loop_filter_mpeg4:	loop filter for MPEG4 flag
597  * @display_delay:	value of the display delay for H264
598  * @display_delay_enable:	display delay for H264 enable flag
599  * @after_packed_pb:	flag used to track buffer when stream is in
600  *			Packed PB format
601  * @sei_fp_parse:	enable/disable parsing of frame packing SEI information
602  * @pb_count:		count of the DPB buffers required by MFC hw
603  * @total_dpb_count:	count of DPB buffers with additional buffers
604  *			requested by the application
605  * @ctx:		context buffer information
606  * @dsc:		descriptor buffer information
607  * @shm:		shared memory buffer information
608  * @mv_count:		number of MV buffers allocated for decoding
609  * @enc_params:		encoding parameters for MFC
610  * @enc_dst_buf_size:	size of the buffers for encoder output
611  * @luma_dpb_size:	dpb buffer size for luma
612  * @chroma_dpb_size:	dpb buffer size for chroma
613  * @me_buffer_size:	size of the motion estimation buffer
614  * @tmv_buffer_size:	size of temporal predictor motion vector buffer
615  * @ref_queue:		list of the reference buffers for encoding
616  * @force_frame_type:	encoder's frame type forcing control
617  * @ref_queue_cnt:	number of the buffers in the reference list
618  * @slice_size:		slice size
619  * @slice_mode:		mode of dividing frames into slices
620  * @c_ops:		ops for encoding
621  * @ctrls:		array of controls, used when adding controls to the
622  *			v4l2 control framework
623  * @ctrl_handler:	handler for v4l2 framework
624  * @scratch_buf_size:	scratch buffer size
625  * @is_10bit:		state to check 10bit support
626  * @is_422:		state to check YUV422 10bit format
627  * @chroma_size_1:	size of a chroma third plane
628  * @stride:		size of stride for all planes
629  */
630 struct s5p_mfc_ctx {
631 	struct s5p_mfc_dev *dev;
632 	struct v4l2_fh fh;
633 
634 	int num;
635 
636 	int int_cond;
637 	int int_type;
638 	unsigned int int_err;
639 	wait_queue_head_t queue;
640 
641 	const struct s5p_mfc_fmt *src_fmt;
642 	const struct s5p_mfc_fmt *dst_fmt;
643 
644 	struct vb2_queue vq_src;
645 	struct vb2_queue vq_dst;
646 
647 	struct list_head src_queue;
648 	struct list_head dst_queue;
649 
650 	unsigned int src_queue_cnt;
651 	unsigned int dst_queue_cnt;
652 
653 	enum s5p_mfc_inst_type type;
654 	enum s5p_mfc_inst_state state;
655 	int inst_no;
656 
657 	/* Image parameters */
658 	int img_width;
659 	int img_height;
660 	int buf_width;
661 	int buf_height;
662 
663 	int luma_size;
664 	int chroma_size;
665 	int chroma_size_1;
666 	int mv_size;
667 
668 	unsigned long consumed_stream;
669 
670 	unsigned int dpb_flush_flag;
671 	unsigned int head_processed;
672 
673 	struct s5p_mfc_priv_buf bank1;
674 	struct s5p_mfc_priv_buf bank2;
675 
676 	enum s5p_mfc_queue_state capture_state;
677 	enum s5p_mfc_queue_state output_state;
678 
679 	struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
680 	int src_bufs_cnt;
681 	struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
682 	int dst_bufs_cnt;
683 
684 	unsigned int sequence;
685 	unsigned long dec_dst_flag;
686 	size_t dec_src_buf_size;
687 
688 	/* Control values */
689 	int codec_mode;
690 	int slice_interface;
691 	int loop_filter_mpeg4;
692 	int display_delay;
693 	int display_delay_enable;
694 	int after_packed_pb;
695 	int sei_fp_parse;
696 
697 	int pb_count;
698 	int total_dpb_count;
699 	int mv_count;
700 	/* Buffers */
701 	struct s5p_mfc_priv_buf ctx;
702 	struct s5p_mfc_priv_buf dsc;
703 	struct s5p_mfc_priv_buf shm;
704 
705 	struct s5p_mfc_enc_params enc_params;
706 
707 	size_t enc_dst_buf_size;
708 	size_t luma_dpb_size;
709 	size_t chroma_dpb_size;
710 	size_t me_buffer_size;
711 	size_t tmv_buffer_size;
712 
713 	enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
714 
715 	struct list_head ref_queue;
716 	unsigned int ref_queue_cnt;
717 
718 	enum v4l2_mpeg_video_multi_slice_mode slice_mode;
719 	union {
720 		unsigned int mb;
721 		unsigned int bits;
722 	} slice_size;
723 
724 	const struct s5p_mfc_codec_ops *c_ops;
725 
726 	struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
727 	struct v4l2_ctrl_handler ctrl_handler;
728 	size_t scratch_buf_size;
729 	int is_10bit;
730 	int is_422;
731 	int stride[VB2_MAX_PLANE_COUNT];
732 };
733 
734 /*
735  * struct s5p_mfc_fmt -	structure used to store information about pixelformats
736  *			used by the MFC
737  */
738 struct s5p_mfc_fmt {
739 	u32 fourcc;
740 	u32 codec_mode;
741 	enum s5p_mfc_fmt_type type;
742 	u32 num_planes;
743 	u32 versions;
744 	u32 flags;
745 };
746 
747 /*
748  * struct mfc_control -	structure used to store information about MFC controls
749  *			it is used to initialize the control framework.
750  */
751 struct mfc_control {
752 	__u32			id;
753 	enum v4l2_ctrl_type	type;
754 	__u8			name[32];  /* Whatever */
755 	__s32			minimum;   /* Note signedness */
756 	__s32			maximum;
757 	__s32			step;
758 	__u32			menu_skip_mask;
759 	__s32			default_value;
760 	__u32			flags;
761 	__u32			reserved[2];
762 	__u8			is_volatile;
763 };
764 
765 /* Macro for making hardware specific calls */
766 #define s5p_mfc_hw_call(f, op, args...) \
767 	((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
768 
769 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
770 #define ctrl_to_ctx(__ctrl) \
771 	container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
772 
773 void clear_work_bit(struct s5p_mfc_ctx *ctx);
774 void set_work_bit(struct s5p_mfc_ctx *ctx);
775 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
776 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
777 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
778 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
779 
780 #define HAS_PORTNUM(dev)	(dev ? (dev->variant ? \
781 				(dev->variant->port_num ? 1 : 0) : 0) : 0)
782 #define IS_TWOPORT(dev)		(dev->variant->port_num == 2 ? 1 : 0)
783 #define IS_MFCV6_PLUS(dev)	((dev)->variant->version >= 0x60)
784 #define IS_MFCV7_PLUS(dev)	((dev)->variant->version >= 0x70)
785 #define IS_MFCV8_PLUS(dev)	((dev)->variant->version >= 0x80)
786 #define IS_MFCV10_PLUS(dev)	((dev)->variant->version >= 0xA0)
787 #define IS_MFCV12(dev)		((dev)->variant->version >= 0xC0)
788 #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev))
789 
790 #define MFC_V5_BIT	BIT(0)
791 #define MFC_V6_BIT	BIT(1)
792 #define MFC_V7_BIT	BIT(2)
793 #define MFC_V8_BIT	BIT(3)
794 #define MFC_V10_BIT	BIT(5)
795 #define MFC_V12_BIT	BIT(7)
796 
797 #define MFC_V5PLUS_BITS		(MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
798 					MFC_V8_BIT | MFC_V10_BIT | MFC_V12_BIT)
799 #define MFC_V6PLUS_BITS		(MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
800 					MFC_V10_BIT | MFC_V12_BIT)
801 #define MFC_V7PLUS_BITS		(MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT | \
802 					MFC_V12_BIT)
803 
804 #define MFC_V10PLUS_BITS	(MFC_V10_BIT | MFC_V12_BIT)
805 
806 #endif /* S5P_MFC_COMMON_H_ */
807