1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/drm_cache.h>
29 #include "amdgpu.h"
30 #include "gmc_v6_0.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_gem.h"
33
34 #include "bif/bif_3_0_d.h"
35 #include "bif/bif_3_0_sh_mask.h"
36 #include "oss/oss_1_0_d.h"
37 #include "oss/oss_1_0_sh_mask.h"
38 #include "gmc/gmc_6_0_d.h"
39 #include "gmc/gmc_6_0_sh_mask.h"
40 #include "dce/dce_6_0_d.h"
41 #include "dce/dce_6_0_sh_mask.h"
42 #include "si_enums.h"
43
44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
46 static int gmc_v6_0_wait_for_idle(void *handle);
47
48 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
49 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
50 MODULE_FIRMWARE("amdgpu/verde_mc.bin");
51 MODULE_FIRMWARE("amdgpu/oland_mc.bin");
52 MODULE_FIRMWARE("amdgpu/hainan_mc.bin");
53 MODULE_FIRMWARE("amdgpu/si58_mc.bin");
54
55 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
56 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
57 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
58 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
59 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
60 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
61 #define MC_SEQ_MISC0__MT__HBM 0x60000000
62 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
63
gmc_v6_0_mc_stop(struct amdgpu_device * adev)64 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
65 {
66 u32 blackout;
67
68 gmc_v6_0_wait_for_idle((void *)adev);
69
70 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
71 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
72 /* Block CPU access */
73 WREG32(mmBIF_FB_EN, 0);
74 /* blackout the MC */
75 blackout = REG_SET_FIELD(blackout,
76 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
77 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
78 }
79 /* wait for the MC to settle */
80 udelay(100);
81
82 }
83
gmc_v6_0_mc_resume(struct amdgpu_device * adev)84 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
85 {
86 u32 tmp;
87
88 /* unblackout the MC */
89 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
90 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
91 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
92 /* allow CPU access */
93 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
94 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
95 WREG32(mmBIF_FB_EN, tmp);
96 }
97
gmc_v6_0_init_microcode(struct amdgpu_device * adev)98 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
99 {
100 const char *chip_name;
101 int err;
102
103 DRM_DEBUG("\n");
104
105 switch (adev->asic_type) {
106 case CHIP_TAHITI:
107 chip_name = "tahiti";
108 break;
109 case CHIP_PITCAIRN:
110 chip_name = "pitcairn";
111 break;
112 case CHIP_VERDE:
113 chip_name = "verde";
114 break;
115 case CHIP_OLAND:
116 chip_name = "oland";
117 break;
118 case CHIP_HAINAN:
119 chip_name = "hainan";
120 break;
121 default:
122 BUG();
123 }
124
125 /* this memory configuration requires special firmware */
126 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
127 chip_name = "si58";
128
129 err = amdgpu_ucode_request(adev, &adev->gmc.fw, "amdgpu/%s_mc.bin", chip_name);
130 if (err) {
131 dev_err(adev->dev,
132 "si_mc: Failed to load firmware \"%s_mc.bin\"\n",
133 chip_name);
134 amdgpu_ucode_release(&adev->gmc.fw);
135 }
136 return err;
137 }
138
gmc_v6_0_mc_load_microcode(struct amdgpu_device * adev)139 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
140 {
141 const __le32 *new_fw_data = NULL;
142 u32 running;
143 const __le32 *new_io_mc_regs = NULL;
144 int i, regs_size, ucode_size;
145 const struct mc_firmware_header_v1_0 *hdr;
146
147 if (!adev->gmc.fw)
148 return -EINVAL;
149
150 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
151
152 amdgpu_ucode_print_mc_hdr(&hdr->header);
153
154 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
155 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
156 new_io_mc_regs = (const __le32 *)
157 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
158 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
159 new_fw_data = (const __le32 *)
160 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
161
162 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
163
164 if (running == 0) {
165
166 /* reset the engine and set to writable */
167 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
168 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
169
170 /* load mc io regs */
171 for (i = 0; i < regs_size; i++) {
172 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
173 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
174 }
175 /* load the MC ucode */
176 for (i = 0; i < ucode_size; i++)
177 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
178
179 /* put the engine back into the active state */
180 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
181 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
182 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
183
184 /* wait for training to complete */
185 for (i = 0; i < adev->usec_timeout; i++) {
186 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
187 break;
188 udelay(1);
189 }
190 for (i = 0; i < adev->usec_timeout; i++) {
191 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
192 break;
193 udelay(1);
194 }
195
196 }
197
198 return 0;
199 }
200
gmc_v6_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)201 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
202 struct amdgpu_gmc *mc)
203 {
204 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
205
206 base <<= 24;
207
208 amdgpu_gmc_set_agp_default(adev, mc);
209 amdgpu_gmc_vram_location(adev, mc, base);
210 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
211 }
212
gmc_v6_0_mc_program(struct amdgpu_device * adev)213 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
214 {
215 int i, j;
216
217 /* Initialize HDP */
218 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
219 WREG32((0xb05 + j), 0x00000000);
220 WREG32((0xb06 + j), 0x00000000);
221 WREG32((0xb07 + j), 0x00000000);
222 WREG32((0xb08 + j), 0x00000000);
223 WREG32((0xb09 + j), 0x00000000);
224 }
225 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
226
227 if (gmc_v6_0_wait_for_idle((void *)adev))
228 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
229
230 if (adev->mode_info.num_crtc) {
231 u32 tmp;
232
233 /* Lockout access through VGA aperture*/
234 tmp = RREG32(mmVGA_HDP_CONTROL);
235 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
236 WREG32(mmVGA_HDP_CONTROL, tmp);
237
238 /* disable VGA render */
239 tmp = RREG32(mmVGA_RENDER_CONTROL);
240 tmp &= ~VGA_VSTATUS_CNTL;
241 WREG32(mmVGA_RENDER_CONTROL, tmp);
242 }
243 /* Update configuration */
244 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
245 adev->gmc.vram_start >> 12);
246 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
247 adev->gmc.vram_end >> 12);
248 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
249 adev->mem_scratch.gpu_addr >> 12);
250 WREG32(mmMC_VM_AGP_BASE, 0);
251 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
252 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
253
254 if (gmc_v6_0_wait_for_idle((void *)adev))
255 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
256 }
257
gmc_v6_0_mc_init(struct amdgpu_device * adev)258 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
259 {
260
261 u32 tmp;
262 int chansize, numchan;
263 int r;
264
265 tmp = RREG32(mmMC_ARB_RAMCFG);
266 if (tmp & (1 << 11))
267 chansize = 16;
268 else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK)
269 chansize = 64;
270 else
271 chansize = 32;
272
273 tmp = RREG32(mmMC_SHARED_CHMAP);
274 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
275 case 0:
276 default:
277 numchan = 1;
278 break;
279 case 1:
280 numchan = 2;
281 break;
282 case 2:
283 numchan = 4;
284 break;
285 case 3:
286 numchan = 8;
287 break;
288 case 4:
289 numchan = 3;
290 break;
291 case 5:
292 numchan = 6;
293 break;
294 case 6:
295 numchan = 10;
296 break;
297 case 7:
298 numchan = 12;
299 break;
300 case 8:
301 numchan = 16;
302 break;
303 }
304 adev->gmc.vram_width = numchan * chansize;
305 /* size in MB on si */
306 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
307 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
308
309 if (!(adev->flags & AMD_IS_APU)) {
310 r = amdgpu_device_resize_fb_bar(adev);
311 if (r)
312 return r;
313 }
314 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
315 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
316 adev->gmc.visible_vram_size = adev->gmc.aper_size;
317
318 /* set the gart size */
319 if (amdgpu_gart_size == -1) {
320 switch (adev->asic_type) {
321 case CHIP_HAINAN: /* no MM engines */
322 default:
323 adev->gmc.gart_size = 256ULL << 20;
324 break;
325 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
326 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
327 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
328 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
329 adev->gmc.gart_size = 1024ULL << 20;
330 break;
331 }
332 } else {
333 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
334 }
335
336 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
337 gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
338
339 return 0;
340 }
341
gmc_v6_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)342 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
343 uint32_t vmhub, uint32_t flush_type)
344 {
345 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
346 }
347
gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)348 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
349 unsigned int vmid, uint64_t pd_addr)
350 {
351 uint32_t reg;
352
353 /* write new base address */
354 if (vmid < 8)
355 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
356 else
357 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
358 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
359
360 /* bits 0-15 are the VM contexts0-15 */
361 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
362
363 return pd_addr;
364 }
365
gmc_v6_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)366 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
367 uint64_t *addr, uint64_t *flags)
368 {
369 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
370 }
371
gmc_v6_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)372 static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev,
373 struct amdgpu_bo_va_mapping *mapping,
374 uint64_t *flags)
375 {
376 *flags &= ~AMDGPU_PTE_EXECUTABLE;
377 *flags &= ~AMDGPU_PTE_PRT;
378 }
379
gmc_v6_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)380 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
381 bool value)
382 {
383 u32 tmp;
384
385 tmp = RREG32(mmVM_CONTEXT1_CNTL);
386 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
387 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
388 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
389 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
390 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
391 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
392 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
393 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
394 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
395 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
396 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
397 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
398 WREG32(mmVM_CONTEXT1_CNTL, tmp);
399 }
400
401 /**
402 * gmc_v8_0_set_prt() - set PRT VM fault
403 *
404 * @adev: amdgpu_device pointer
405 * @enable: enable/disable VM fault handling for PRT
406 */
gmc_v6_0_set_prt(struct amdgpu_device * adev,bool enable)407 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
408 {
409 u32 tmp;
410
411 if (enable && !adev->gmc.prt_warning) {
412 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
413 adev->gmc.prt_warning = true;
414 }
415
416 tmp = RREG32(mmVM_PRT_CNTL);
417 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
418 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
419 enable);
420 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
421 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
422 enable);
423 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
424 L2_CACHE_STORE_INVALID_ENTRIES,
425 enable);
426 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
427 L1_TLB_STORE_INVALID_ENTRIES,
428 enable);
429 WREG32(mmVM_PRT_CNTL, tmp);
430
431 if (enable) {
432 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>
433 AMDGPU_GPU_PAGE_SHIFT;
434 uint32_t high = adev->vm_manager.max_pfn -
435 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT);
436
437 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
438 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
439 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
440 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
441 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
442 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
443 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
444 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
445 } else {
446 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
447 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
448 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
449 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
450 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
451 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
452 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
453 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
454 }
455 }
456
gmc_v6_0_gart_enable(struct amdgpu_device * adev)457 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
458 {
459 uint64_t table_addr;
460 u32 field;
461 int i;
462
463 if (adev->gart.bo == NULL) {
464 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
465 return -EINVAL;
466 }
467 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
468
469 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
470
471 /* Setup TLB control */
472 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
473 (0xA << 7) |
474 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
475 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
476 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
477 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
478 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
479 /* Setup L2 cache */
480 WREG32(mmVM_L2_CNTL,
481 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
482 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
483 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
484 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
485 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
486 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
487 WREG32(mmVM_L2_CNTL2,
488 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
489 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
490
491 field = adev->vm_manager.fragment_size;
492 WREG32(mmVM_L2_CNTL3,
493 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
494 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
495 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
496 /* setup context0 */
497 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
498 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
499 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
500 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
501 (u32)(adev->dummy_page_addr >> 12));
502 WREG32(mmVM_CONTEXT0_CNTL2, 0);
503 WREG32(mmVM_CONTEXT0_CNTL,
504 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
505 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
506 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
507
508 WREG32(0x575, 0);
509 WREG32(0x576, 0);
510 WREG32(0x577, 0);
511
512 /* empty context1-15 */
513 /* set vm size, must be a multiple of 4 */
514 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
515 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
516 /* Assign the pt base to something valid for now; the pts used for
517 * the VMs are determined by the application and setup and assigned
518 * on the fly in the vm part of radeon_gart.c
519 */
520 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
521 if (i < 8)
522 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
523 table_addr >> 12);
524 else
525 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
526 table_addr >> 12);
527 }
528
529 /* enable context1-15 */
530 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
531 (u32)(adev->dummy_page_addr >> 12));
532 WREG32(mmVM_CONTEXT1_CNTL2, 4);
533 WREG32(mmVM_CONTEXT1_CNTL,
534 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
535 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
536 ((adev->vm_manager.block_size - 9)
537 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
538 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
539 gmc_v6_0_set_fault_enable_default(adev, false);
540 else
541 gmc_v6_0_set_fault_enable_default(adev, true);
542
543 gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
544 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
545 (unsigned int)(adev->gmc.gart_size >> 20),
546 (unsigned long long)table_addr);
547 return 0;
548 }
549
gmc_v6_0_gart_init(struct amdgpu_device * adev)550 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
551 {
552 int r;
553
554 if (adev->gart.bo) {
555 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
556 return 0;
557 }
558 r = amdgpu_gart_init(adev);
559 if (r)
560 return r;
561 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
562 adev->gart.gart_pte_flags = 0;
563 return amdgpu_gart_table_vram_alloc(adev);
564 }
565
gmc_v6_0_gart_disable(struct amdgpu_device * adev)566 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
567 {
568 /*unsigned i;
569
570 for (i = 1; i < 16; ++i) {
571 uint32_t reg;
572 if (i < 8)
573 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
574 else
575 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
576 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
577 }*/
578
579 /* Disable all tables */
580 WREG32(mmVM_CONTEXT0_CNTL, 0);
581 WREG32(mmVM_CONTEXT1_CNTL, 0);
582 /* Setup TLB control */
583 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
584 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
585 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
586 /* Setup L2 cache */
587 WREG32(mmVM_L2_CNTL,
588 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
589 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
590 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
591 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
592 WREG32(mmVM_L2_CNTL2, 0);
593 WREG32(mmVM_L2_CNTL3,
594 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
595 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
596 }
597
gmc_v6_0_vm_decode_fault(struct amdgpu_device * adev,u32 status,u32 addr,u32 mc_client)598 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
599 u32 status, u32 addr, u32 mc_client)
600 {
601 u32 mc_id;
602 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
603 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
604 PROTECTIONS);
605 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
606 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
607
608 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
609 MEMORY_CLIENT_ID);
610
611 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
612 protections, vmid, addr,
613 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
614 MEMORY_CLIENT_RW) ?
615 "write" : "read", block, mc_client, mc_id);
616 }
617
618 /*
619 static const u32 mc_cg_registers[] = {
620 MC_HUB_MISC_HUB_CG,
621 MC_HUB_MISC_SIP_CG,
622 MC_HUB_MISC_VM_CG,
623 MC_XPB_CLK_GAT,
624 ATC_MISC_CG,
625 MC_CITF_MISC_WR_CG,
626 MC_CITF_MISC_RD_CG,
627 MC_CITF_MISC_VM_CG,
628 VM_L2_CG,
629 };
630
631 static const u32 mc_cg_ls_en[] = {
632 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
633 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
634 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
635 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
636 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
637 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
638 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
639 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
640 VM_L2_CG__MEM_LS_ENABLE_MASK,
641 };
642
643 static const u32 mc_cg_en[] = {
644 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
645 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
646 MC_HUB_MISC_VM_CG__ENABLE_MASK,
647 MC_XPB_CLK_GAT__ENABLE_MASK,
648 ATC_MISC_CG__ENABLE_MASK,
649 MC_CITF_MISC_WR_CG__ENABLE_MASK,
650 MC_CITF_MISC_RD_CG__ENABLE_MASK,
651 MC_CITF_MISC_VM_CG__ENABLE_MASK,
652 VM_L2_CG__ENABLE_MASK,
653 };
654
655 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
656 bool enable)
657 {
658 int i;
659 u32 orig, data;
660
661 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
662 orig = data = RREG32(mc_cg_registers[i]);
663 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
664 data |= mc_cg_ls_en[i];
665 else
666 data &= ~mc_cg_ls_en[i];
667 if (data != orig)
668 WREG32(mc_cg_registers[i], data);
669 }
670 }
671
672 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
673 bool enable)
674 {
675 int i;
676 u32 orig, data;
677
678 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
679 orig = data = RREG32(mc_cg_registers[i]);
680 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
681 data |= mc_cg_en[i];
682 else
683 data &= ~mc_cg_en[i];
684 if (data != orig)
685 WREG32(mc_cg_registers[i], data);
686 }
687 }
688
689 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
690 bool enable)
691 {
692 u32 orig, data;
693
694 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
695
696 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
697 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
698 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
699 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
700 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
701 } else {
702 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
703 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
704 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
705 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
706 }
707
708 if (orig != data)
709 WREG32_PCIE(ixPCIE_CNTL2, data);
710 }
711
712 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
713 bool enable)
714 {
715 u32 orig, data;
716
717 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
718
719 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
720 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
721 else
722 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
723
724 if (orig != data)
725 WREG32(mmHDP_HOST_PATH_CNTL, data);
726 }
727
728 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
729 bool enable)
730 {
731 u32 orig, data;
732
733 orig = data = RREG32(mmHDP_MEM_POWER_LS);
734
735 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
736 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
737 else
738 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
739
740 if (orig != data)
741 WREG32(mmHDP_MEM_POWER_LS, data);
742 }
743 */
744
gmc_v6_0_convert_vram_type(int mc_seq_vram_type)745 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
746 {
747 switch (mc_seq_vram_type) {
748 case MC_SEQ_MISC0__MT__GDDR1:
749 return AMDGPU_VRAM_TYPE_GDDR1;
750 case MC_SEQ_MISC0__MT__DDR2:
751 return AMDGPU_VRAM_TYPE_DDR2;
752 case MC_SEQ_MISC0__MT__GDDR3:
753 return AMDGPU_VRAM_TYPE_GDDR3;
754 case MC_SEQ_MISC0__MT__GDDR4:
755 return AMDGPU_VRAM_TYPE_GDDR4;
756 case MC_SEQ_MISC0__MT__GDDR5:
757 return AMDGPU_VRAM_TYPE_GDDR5;
758 case MC_SEQ_MISC0__MT__DDR3:
759 return AMDGPU_VRAM_TYPE_DDR3;
760 default:
761 return AMDGPU_VRAM_TYPE_UNKNOWN;
762 }
763 }
764
gmc_v6_0_early_init(void * handle)765 static int gmc_v6_0_early_init(void *handle)
766 {
767 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
768
769 gmc_v6_0_set_gmc_funcs(adev);
770 gmc_v6_0_set_irq_funcs(adev);
771
772 return 0;
773 }
774
gmc_v6_0_late_init(void * handle)775 static int gmc_v6_0_late_init(void *handle)
776 {
777 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
778
779 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
780 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
781 else
782 return 0;
783 }
784
gmc_v6_0_get_vbios_fb_size(struct amdgpu_device * adev)785 static unsigned int gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
786 {
787 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
788 unsigned int size;
789
790 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
791 size = AMDGPU_VBIOS_VGA_ALLOCATION;
792 } else {
793 u32 viewport = RREG32(mmVIEWPORT_SIZE);
794
795 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
796 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
797 4);
798 }
799 return size;
800 }
801
gmc_v6_0_sw_init(void * handle)802 static int gmc_v6_0_sw_init(void *handle)
803 {
804 int r;
805 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
806
807 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
808
809 if (adev->flags & AMD_IS_APU) {
810 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
811 } else {
812 u32 tmp = RREG32(mmMC_SEQ_MISC0);
813
814 tmp &= MC_SEQ_MISC0__MT__MASK;
815 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
816 }
817
818 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
819 if (r)
820 return r;
821
822 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
823 if (r)
824 return r;
825
826 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
827
828 adev->gmc.mc_mask = 0xffffffffffULL;
829
830 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
831 if (r) {
832 dev_warn(adev->dev, "No suitable DMA available.\n");
833 return r;
834 }
835 adev->need_swiotlb = drm_need_swiotlb(40);
836
837 r = gmc_v6_0_init_microcode(adev);
838 if (r) {
839 dev_err(adev->dev, "Failed to load mc firmware!\n");
840 return r;
841 }
842
843 r = gmc_v6_0_mc_init(adev);
844 if (r)
845 return r;
846
847 amdgpu_gmc_get_vbios_allocations(adev);
848
849 r = amdgpu_bo_init(adev);
850 if (r)
851 return r;
852
853 r = gmc_v6_0_gart_init(adev);
854 if (r)
855 return r;
856
857 /*
858 * number of VMs
859 * VMID 0 is reserved for System
860 * amdgpu graphics/compute will use VMIDs 1-7
861 * amdkfd will use VMIDs 8-15
862 */
863 adev->vm_manager.first_kfd_vmid = 8;
864 amdgpu_vm_manager_init(adev);
865
866 /* base offset of vram pages */
867 if (adev->flags & AMD_IS_APU) {
868 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
869
870 tmp <<= 22;
871 adev->vm_manager.vram_base_offset = tmp;
872 } else {
873 adev->vm_manager.vram_base_offset = 0;
874 }
875
876 return 0;
877 }
878
gmc_v6_0_sw_fini(void * handle)879 static int gmc_v6_0_sw_fini(void *handle)
880 {
881 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
882
883 amdgpu_gem_force_release(adev);
884 amdgpu_vm_manager_fini(adev);
885 amdgpu_gart_table_vram_free(adev);
886 amdgpu_bo_fini(adev);
887 amdgpu_ucode_release(&adev->gmc.fw);
888
889 return 0;
890 }
891
gmc_v6_0_hw_init(void * handle)892 static int gmc_v6_0_hw_init(void *handle)
893 {
894 int r;
895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
896
897 gmc_v6_0_mc_program(adev);
898
899 if (!(adev->flags & AMD_IS_APU)) {
900 r = gmc_v6_0_mc_load_microcode(adev);
901 if (r) {
902 dev_err(adev->dev, "Failed to load MC firmware!\n");
903 return r;
904 }
905 }
906
907 r = gmc_v6_0_gart_enable(adev);
908 if (r)
909 return r;
910
911 if (amdgpu_emu_mode == 1)
912 return amdgpu_gmc_vram_checking(adev);
913
914 return 0;
915 }
916
gmc_v6_0_hw_fini(void * handle)917 static int gmc_v6_0_hw_fini(void *handle)
918 {
919 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
920
921 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
922 gmc_v6_0_gart_disable(adev);
923
924 return 0;
925 }
926
gmc_v6_0_suspend(void * handle)927 static int gmc_v6_0_suspend(void *handle)
928 {
929 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
930
931 gmc_v6_0_hw_fini(adev);
932
933 return 0;
934 }
935
gmc_v6_0_resume(void * handle)936 static int gmc_v6_0_resume(void *handle)
937 {
938 int r;
939 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
940
941 r = gmc_v6_0_hw_init(adev);
942 if (r)
943 return r;
944
945 amdgpu_vmid_reset_all(adev);
946
947 return 0;
948 }
949
gmc_v6_0_is_idle(void * handle)950 static bool gmc_v6_0_is_idle(void *handle)
951 {
952 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
953 u32 tmp = RREG32(mmSRBM_STATUS);
954
955 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
956 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
957 return false;
958
959 return true;
960 }
961
gmc_v6_0_wait_for_idle(void * handle)962 static int gmc_v6_0_wait_for_idle(void *handle)
963 {
964 unsigned int i;
965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
966
967 for (i = 0; i < adev->usec_timeout; i++) {
968 if (gmc_v6_0_is_idle(handle))
969 return 0;
970 udelay(1);
971 }
972 return -ETIMEDOUT;
973
974 }
975
gmc_v6_0_soft_reset(void * handle)976 static int gmc_v6_0_soft_reset(void *handle)
977 {
978 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
979 u32 srbm_soft_reset = 0;
980 u32 tmp = RREG32(mmSRBM_STATUS);
981
982 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
983 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
984 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
985
986 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
987 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
988 if (!(adev->flags & AMD_IS_APU))
989 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
990 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
991 }
992
993 if (srbm_soft_reset) {
994 gmc_v6_0_mc_stop(adev);
995 if (gmc_v6_0_wait_for_idle(adev))
996 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
997
998 tmp = RREG32(mmSRBM_SOFT_RESET);
999 tmp |= srbm_soft_reset;
1000 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1001 WREG32(mmSRBM_SOFT_RESET, tmp);
1002 tmp = RREG32(mmSRBM_SOFT_RESET);
1003
1004 udelay(50);
1005
1006 tmp &= ~srbm_soft_reset;
1007 WREG32(mmSRBM_SOFT_RESET, tmp);
1008 tmp = RREG32(mmSRBM_SOFT_RESET);
1009
1010 udelay(50);
1011
1012 gmc_v6_0_mc_resume(adev);
1013 udelay(50);
1014 }
1015
1016 return 0;
1017 }
1018
gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)1019 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1020 struct amdgpu_irq_src *src,
1021 unsigned int type,
1022 enum amdgpu_interrupt_state state)
1023 {
1024 u32 tmp;
1025 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1026 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1027 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1028 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1029 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1030 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1031
1032 switch (state) {
1033 case AMDGPU_IRQ_STATE_DISABLE:
1034 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1035 tmp &= ~bits;
1036 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1037 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1038 tmp &= ~bits;
1039 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1040 break;
1041 case AMDGPU_IRQ_STATE_ENABLE:
1042 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1043 tmp |= bits;
1044 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1045 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1046 tmp |= bits;
1047 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1048 break;
1049 default:
1050 break;
1051 }
1052
1053 return 0;
1054 }
1055
gmc_v6_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1056 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1057 struct amdgpu_irq_src *source,
1058 struct amdgpu_iv_entry *entry)
1059 {
1060 u32 addr, status;
1061
1062 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1063 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1064 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1065
1066 if (!addr && !status)
1067 return 0;
1068
1069 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1070 gmc_v6_0_set_fault_enable_default(adev, false);
1071
1072 if (printk_ratelimit()) {
1073 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1074 entry->src_id, entry->src_data[0]);
1075 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1076 addr);
1077 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1078 status);
1079 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1080 }
1081
1082 return 0;
1083 }
1084
gmc_v6_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1085 static int gmc_v6_0_set_clockgating_state(void *handle,
1086 enum amd_clockgating_state state)
1087 {
1088 return 0;
1089 }
1090
gmc_v6_0_set_powergating_state(void * handle,enum amd_powergating_state state)1091 static int gmc_v6_0_set_powergating_state(void *handle,
1092 enum amd_powergating_state state)
1093 {
1094 return 0;
1095 }
1096
1097 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1098 .name = "gmc_v6_0",
1099 .early_init = gmc_v6_0_early_init,
1100 .late_init = gmc_v6_0_late_init,
1101 .sw_init = gmc_v6_0_sw_init,
1102 .sw_fini = gmc_v6_0_sw_fini,
1103 .hw_init = gmc_v6_0_hw_init,
1104 .hw_fini = gmc_v6_0_hw_fini,
1105 .suspend = gmc_v6_0_suspend,
1106 .resume = gmc_v6_0_resume,
1107 .is_idle = gmc_v6_0_is_idle,
1108 .wait_for_idle = gmc_v6_0_wait_for_idle,
1109 .soft_reset = gmc_v6_0_soft_reset,
1110 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1111 .set_powergating_state = gmc_v6_0_set_powergating_state,
1112 .dump_ip_state = NULL,
1113 .print_ip_state = NULL,
1114 };
1115
1116 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1117 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1118 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1119 .set_prt = gmc_v6_0_set_prt,
1120 .get_vm_pde = gmc_v6_0_get_vm_pde,
1121 .get_vm_pte = gmc_v6_0_get_vm_pte,
1122 .get_vbios_fb_size = gmc_v6_0_get_vbios_fb_size,
1123 };
1124
1125 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1126 .set = gmc_v6_0_vm_fault_interrupt_state,
1127 .process = gmc_v6_0_process_interrupt,
1128 };
1129
gmc_v6_0_set_gmc_funcs(struct amdgpu_device * adev)1130 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1131 {
1132 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1133 }
1134
gmc_v6_0_set_irq_funcs(struct amdgpu_device * adev)1135 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1136 {
1137 adev->gmc.vm_fault.num_types = 1;
1138 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1139 }
1140
1141 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = {
1142 .type = AMD_IP_BLOCK_TYPE_GMC,
1143 .major = 6,
1144 .minor = 0,
1145 .rev = 0,
1146 .funcs = &gmc_v6_0_ip_funcs,
1147 };
1148