1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 /*
30 * AMD Geode LX CS5536 System Management Bus controller.
31 *
32 * Although AMD refers to this device as an SMBus controller, it
33 * really is an I2C controller (It lacks SMBus ALERT# and Alert
34 * Response support).
35 *
36 * The driver is implemented as an interrupt-driven state machine,
37 * supporting both master and slave mode.
38 */
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/bus.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/lock.h>
45 #include <sys/mutex.h>
46 #include <sys/sysctl.h>
47 #ifdef GLXIIC_DEBUG
48 #include <sys/syslog.h>
49 #endif
50
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
53
54 #include <machine/bus.h>
55 #include <sys/rman.h>
56 #include <machine/resource.h>
57
58 #include <dev/iicbus/iiconf.h>
59 #include <dev/iicbus/iicbus.h>
60
61 #include "iicbus_if.h"
62
63 /* CS5536 PCI-ISA ID. */
64 #define GLXIIC_CS5536_DEV_ID 0x20901022
65
66 /* MSRs. */
67 #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021
68
69 /* Bus speeds. */
70 #define GLXIIC_SLOW 0x0258 /* 10 kHz. */
71 #define GLXIIC_FAST 0x0078 /* 50 kHz. */
72 #define GLXIIC_FASTEST 0x003c /* 100 kHz. */
73
74 /* Default bus activity timeout in milliseconds. */
75 #define GLXIIC_DEFAULT_TIMEOUT 35
76
77 /* GPIO register offsets. */
78 #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10
79 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34
80
81 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */
82 #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000
83 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000
84
85 /* SMB register offsets. */
86 #define GLXIIC_SMB_SDA 0x00
87 #define GLXIIC_SMB_STS 0x01
88 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7)
89 #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6)
90 #define GLXIIC_SMB_STS_BER_BIT (1 << 5)
91 #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4)
92 #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3)
93 #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2)
94 #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1)
95 #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0)
96 #define GLXIIC_SMB_CTRL_STS 0x02
97 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5)
98 #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4)
99 #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3)
100 #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2)
101 #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1)
102 #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0)
103 #define GLXIIC_SMB_CTRL1 0x03
104 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7)
105 #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6)
106 #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5)
107 #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4)
108 #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2)
109 #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1)
110 #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0)
111 #define GLXIIC_SMB_ADDR 0x04
112 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7)
113 #define GLXIIC_SMB_CTRL2 0x05
114 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0)
115 #define GLXIIC_SMB_CTRL3 0x06
116
117 typedef enum {
118 GLXIIC_STATE_IDLE,
119 GLXIIC_STATE_SLAVE_TX,
120 GLXIIC_STATE_SLAVE_RX,
121 GLXIIC_STATE_MASTER_ADDR,
122 GLXIIC_STATE_MASTER_TX,
123 GLXIIC_STATE_MASTER_RX,
124 GLXIIC_STATE_MASTER_STOP,
125 GLXIIC_STATE_MAX,
126 } glxiic_state_t;
127
128 struct glxiic_softc {
129 device_t dev; /* Myself. */
130 device_t iicbus; /* IIC bus. */
131 struct mtx mtx; /* Lock. */
132 glxiic_state_t state; /* Driver state. */
133 struct callout callout; /* Driver state timeout callout. */
134 int timeout; /* Driver state timeout (ms). */
135
136 int smb_rid; /* SMB controller resource ID. */
137 struct resource *smb_res; /* SMB controller resource. */
138 int gpio_rid; /* GPIO resource ID. */
139 struct resource *gpio_res; /* GPIO resource. */
140
141 int irq_rid; /* IRQ resource ID. */
142 struct resource *irq_res; /* IRQ resource. */
143 void *irq_handler; /* IRQ handler cookie. */
144 int old_irq; /* IRQ mapped by board firmware. */
145
146 struct iic_msg *msg; /* Current master mode message. */
147 uint32_t nmsgs; /* Number of messages remaining. */
148 uint8_t *data; /* Current master mode data byte. */
149 uint16_t ndata; /* Number of data bytes remaining. */
150 int error; /* Last master mode error. */
151
152 uint8_t addr; /* Own address. */
153 uint16_t sclfrq; /* Bus frequency. */
154 };
155
156 #ifdef GLXIIC_DEBUG
157 #define GLXIIC_DEBUG_LOG(fmt, args...) \
158 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args)
159 #else
160 #define GLXIIC_DEBUG_LOG(fmt, args...)
161 #endif
162
163 #define GLXIIC_SCLFRQ(n) ((n << 1))
164 #define GLXIIC_SMBADDR(n) ((n >> 1))
165 #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16))
166 #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf)
167
168 #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx)
169 #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx)
170 #define GLXIIC_LOCK_INIT(_sc) \
171 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF)
172 #define GLXIIC_SLEEP(_sc) \
173 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0)
174 #define GLXIIC_WAKEUP(_sc) wakeup(_sc);
175 #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
176 #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
177
178 typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc,
179 uint8_t status);
180
181 static glxiic_state_callback_t glxiic_state_idle_callback;
182 static glxiic_state_callback_t glxiic_state_slave_tx_callback;
183 static glxiic_state_callback_t glxiic_state_slave_rx_callback;
184 static glxiic_state_callback_t glxiic_state_master_addr_callback;
185 static glxiic_state_callback_t glxiic_state_master_tx_callback;
186 static glxiic_state_callback_t glxiic_state_master_rx_callback;
187 static glxiic_state_callback_t glxiic_state_master_stop_callback;
188
189 struct glxiic_state_table_entry {
190 glxiic_state_callback_t *callback;
191 boolean_t master;
192 };
193 typedef struct glxiic_state_table_entry glxiic_state_table_entry_t;
194
195 static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = {
196 [GLXIIC_STATE_IDLE] = {
197 .callback = &glxiic_state_idle_callback,
198 .master = FALSE,
199 },
200
201 [GLXIIC_STATE_SLAVE_TX] = {
202 .callback = &glxiic_state_slave_tx_callback,
203 .master = FALSE,
204 },
205
206 [GLXIIC_STATE_SLAVE_RX] = {
207 .callback = &glxiic_state_slave_rx_callback,
208 .master = FALSE,
209 },
210
211 [GLXIIC_STATE_MASTER_ADDR] = {
212 .callback = &glxiic_state_master_addr_callback,
213 .master = TRUE,
214 },
215
216 [GLXIIC_STATE_MASTER_TX] = {
217 .callback = &glxiic_state_master_tx_callback,
218 .master = TRUE,
219 },
220
221 [GLXIIC_STATE_MASTER_RX] = {
222 .callback = &glxiic_state_master_rx_callback,
223 .master = TRUE,
224 },
225
226 [GLXIIC_STATE_MASTER_STOP] = {
227 .callback = &glxiic_state_master_stop_callback,
228 .master = TRUE,
229 },
230 };
231
232 static void glxiic_identify(driver_t *driver, device_t parent);
233 static int glxiic_probe(device_t dev);
234 static int glxiic_attach(device_t dev);
235 static int glxiic_detach(device_t dev);
236
237 static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc);
238 static void glxiic_stop_locked(struct glxiic_softc *sc);
239 static void glxiic_timeout(void *arg);
240 static void glxiic_start_timeout_locked(struct glxiic_softc *sc);
241 static void glxiic_set_state_locked(struct glxiic_softc *sc,
242 glxiic_state_t state);
243 static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc,
244 uint8_t status);
245 static void glxiic_intr(void *arg);
246
247 static int glxiic_reset(device_t dev, u_char speed, u_char addr,
248 u_char *oldaddr);
249 static int glxiic_transfer(device_t dev, struct iic_msg *msgs,
250 uint32_t nmsgs);
251
252 static void glxiic_smb_map_interrupt(int irq);
253 static void glxiic_gpio_enable(struct glxiic_softc *sc);
254 static void glxiic_gpio_disable(struct glxiic_softc *sc);
255 static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed,
256 uint8_t addr);
257 static void glxiic_smb_disable(struct glxiic_softc *sc);
258
259 static device_method_t glxiic_methods[] = {
260 DEVMETHOD(device_identify, glxiic_identify),
261 DEVMETHOD(device_probe, glxiic_probe),
262 DEVMETHOD(device_attach, glxiic_attach),
263 DEVMETHOD(device_detach, glxiic_detach),
264
265 DEVMETHOD(iicbus_reset, glxiic_reset),
266 DEVMETHOD(iicbus_transfer, glxiic_transfer),
267 DEVMETHOD(iicbus_callback, iicbus_null_callback),
268
269 { 0, 0 }
270 };
271
272 static driver_t glxiic_driver = {
273 "glxiic",
274 glxiic_methods,
275 sizeof(struct glxiic_softc),
276 };
277
278 DRIVER_MODULE(glxiic, isab, glxiic_driver, 0, 0);
279 DRIVER_MODULE(iicbus, glxiic, iicbus_driver, 0, 0);
280 MODULE_DEPEND(glxiic, iicbus, 1, 1, 1);
281
282 static void
glxiic_identify(driver_t * driver,device_t parent)283 glxiic_identify(driver_t *driver, device_t parent)
284 {
285
286 /* Prevent child from being added more than once. */
287 if (device_find_child(parent, driver->name, -1) != NULL)
288 return;
289
290 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) {
291 if (device_add_child(parent, driver->name, -1) == NULL)
292 device_printf(parent, "Could not add glxiic child\n");
293 }
294 }
295
296 static int
glxiic_probe(device_t dev)297 glxiic_probe(device_t dev)
298 {
299
300 if (resource_disabled("glxiic", device_get_unit(dev)))
301 return (ENXIO);
302
303 device_set_desc(dev, "AMD Geode CS5536 SMBus controller");
304
305 return (BUS_PROBE_DEFAULT);
306 }
307
308 static int
glxiic_attach(device_t dev)309 glxiic_attach(device_t dev)
310 {
311 struct glxiic_softc *sc;
312 struct sysctl_ctx_list *ctx;
313 struct sysctl_oid *tree;
314 int error, irq, unit;
315 uint32_t irq_map;
316
317 sc = device_get_softc(dev);
318 sc->dev = dev;
319 sc->state = GLXIIC_STATE_IDLE;
320 error = 0;
321
322 GLXIIC_LOCK_INIT(sc);
323 callout_init_mtx(&sc->callout, &sc->mtx, 0);
324
325 sc->smb_rid = PCIR_BAR(0);
326 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid,
327 RF_ACTIVE);
328 if (sc->smb_res == NULL) {
329 device_printf(dev, "Could not allocate SMBus I/O port\n");
330 error = ENXIO;
331 goto out;
332 }
333
334 sc->gpio_rid = PCIR_BAR(1);
335 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
336 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE);
337 if (sc->gpio_res == NULL) {
338 device_printf(dev, "Could not allocate GPIO I/O port\n");
339 error = ENXIO;
340 goto out;
341 }
342
343 /* Ensure the controller is not enabled by firmware. */
344 glxiic_smb_disable(sc);
345
346 /* Read the existing IRQ map. */
347 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
348 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
349
350 unit = device_get_unit(dev);
351 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) {
352 if (irq < 1 || irq > 15) {
353 device_printf(dev, "Bad value %d for glxiic.%d.irq\n",
354 irq, unit);
355 error = ENXIO;
356 goto out;
357 }
358
359 if (bootverbose)
360 device_printf(dev, "Using irq %d set by hint\n", irq);
361 } else if (sc->old_irq != 0) {
362 if (bootverbose)
363 device_printf(dev, "Using irq %d set by firmware\n",
364 irq);
365 irq = sc->old_irq;
366 } else {
367 device_printf(dev, "No irq mapped by firmware");
368 printf(" and no glxiic.%d.irq hint provided\n", unit);
369 error = ENXIO;
370 goto out;
371 }
372
373 /* Map the SMBus interrupt to the requested legacy IRQ. */
374 glxiic_smb_map_interrupt(irq);
375
376 sc->irq_rid = 0;
377 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
378 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE);
379 if (sc->irq_res == NULL) {
380 device_printf(dev, "Could not allocate IRQ %d\n", irq);
381 error = ENXIO;
382 goto out;
383 }
384
385 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
386 NULL, glxiic_intr, sc, &(sc->irq_handler));
387 if (error != 0) {
388 device_printf(dev, "Could not setup IRQ handler\n");
389 error = ENXIO;
390 goto out;
391 }
392
393 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
394 device_printf(dev, "Could not allocate iicbus instance\n");
395 error = ENXIO;
396 goto out;
397 }
398
399 ctx = device_get_sysctl_ctx(dev);
400 tree = device_get_sysctl_tree(dev);
401
402 sc->timeout = GLXIIC_DEFAULT_TIMEOUT;
403 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
404 "timeout", CTLFLAG_RWTUN, &sc->timeout, 0,
405 "activity timeout in ms");
406
407 glxiic_gpio_enable(sc);
408 glxiic_smb_enable(sc, IIC_FASTEST, 0);
409
410 /* Probe and attach the iicbus when interrupts are available. */
411 error = bus_delayed_attach_children(dev);
412
413 out:
414 if (error != 0) {
415 callout_drain(&sc->callout);
416
417 if (sc->iicbus != NULL)
418 device_delete_child(dev, sc->iicbus);
419 if (sc->smb_res != NULL) {
420 glxiic_smb_disable(sc);
421 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
422 sc->smb_res);
423 }
424 if (sc->gpio_res != NULL) {
425 glxiic_gpio_disable(sc);
426 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
427 sc->gpio_res);
428 }
429 if (sc->irq_handler != NULL)
430 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
431 if (sc->irq_res != NULL)
432 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
433 sc->irq_res);
434
435 /* Restore the old SMBus interrupt mapping. */
436 glxiic_smb_map_interrupt(sc->old_irq);
437
438 GLXIIC_LOCK_DESTROY(sc);
439 }
440
441 return (error);
442 }
443
444 static int
glxiic_detach(device_t dev)445 glxiic_detach(device_t dev)
446 {
447 struct glxiic_softc *sc;
448 int error;
449
450 sc = device_get_softc(dev);
451
452 error = bus_generic_detach(dev);
453 if (error != 0)
454 goto out;
455 if (sc->iicbus != NULL)
456 error = device_delete_child(dev, sc->iicbus);
457
458 out:
459 callout_drain(&sc->callout);
460
461 if (sc->smb_res != NULL) {
462 glxiic_smb_disable(sc);
463 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
464 sc->smb_res);
465 }
466 if (sc->gpio_res != NULL) {
467 glxiic_gpio_disable(sc);
468 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
469 sc->gpio_res);
470 }
471 if (sc->irq_handler != NULL)
472 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
473 if (sc->irq_res != NULL)
474 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
475 sc->irq_res);
476
477 /* Restore the old SMBus interrupt mapping. */
478 glxiic_smb_map_interrupt(sc->old_irq);
479
480 GLXIIC_LOCK_DESTROY(sc);
481
482 return (error);
483 }
484
485 static uint8_t
glxiic_read_status_locked(struct glxiic_softc * sc)486 glxiic_read_status_locked(struct glxiic_softc *sc)
487 {
488 uint8_t status;
489
490 GLXIIC_ASSERT_LOCKED(sc);
491
492 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS);
493
494 /* Clear all status flags except SDAST and STASTR after reading. */
495 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT |
496 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT |
497 GLXIIC_SMB_STS_NMATCH_BIT));
498
499 return (status);
500 }
501
502 static void
glxiic_stop_locked(struct glxiic_softc * sc)503 glxiic_stop_locked(struct glxiic_softc *sc)
504 {
505 uint8_t status, ctrl1;
506
507 GLXIIC_ASSERT_LOCKED(sc);
508
509 status = glxiic_read_status_locked(sc);
510
511 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
512 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
513 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT);
514
515 /*
516 * Perform a dummy read of SDA in master receive mode to clear
517 * SDAST if set.
518 */
519 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 &&
520 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0)
521 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
522
523 /* Check stall after start bit and clear if needed */
524 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
525 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
526 GLXIIC_SMB_STS_STASTR_BIT);
527 }
528 }
529
530 static void
glxiic_timeout(void * arg)531 glxiic_timeout(void *arg)
532 {
533 struct glxiic_softc *sc;
534 uint8_t error;
535
536 sc = (struct glxiic_softc *)arg;
537
538 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state);
539
540 if (glxiic_state_table[sc->state].master) {
541 sc->error = IIC_ETIMEOUT;
542 GLXIIC_WAKEUP(sc);
543 } else {
544 error = IIC_ETIMEOUT;
545 iicbus_intr(sc->iicbus, INTR_ERROR, &error);
546 }
547
548 glxiic_smb_disable(sc);
549 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr);
550 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
551 }
552
553 static void
glxiic_start_timeout_locked(struct glxiic_softc * sc)554 glxiic_start_timeout_locked(struct glxiic_softc *sc)
555 {
556
557 GLXIIC_ASSERT_LOCKED(sc);
558
559 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0,
560 glxiic_timeout, sc, 0);
561 }
562
563 static void
glxiic_set_state_locked(struct glxiic_softc * sc,glxiic_state_t state)564 glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state)
565 {
566
567 GLXIIC_ASSERT_LOCKED(sc);
568
569 if (state == GLXIIC_STATE_IDLE)
570 callout_stop(&sc->callout);
571 else if (sc->timeout > 0)
572 glxiic_start_timeout_locked(sc);
573
574 sc->state = state;
575 }
576
577 static int
glxiic_handle_slave_match_locked(struct glxiic_softc * sc,uint8_t status)578 glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status)
579 {
580 uint8_t ctrl_sts, addr;
581
582 GLXIIC_ASSERT_LOCKED(sc);
583
584 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS);
585
586 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) {
587 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) {
588 addr = sc->addr | LSB;
589 glxiic_set_state_locked(sc,
590 GLXIIC_STATE_SLAVE_TX);
591 } else {
592 addr = sc->addr & ~LSB;
593 glxiic_set_state_locked(sc,
594 GLXIIC_STATE_SLAVE_RX);
595 }
596 iicbus_intr(sc->iicbus, INTR_START, &addr);
597 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) {
598 addr = 0;
599 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX);
600 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr);
601 } else {
602 GLXIIC_DEBUG_LOG("unknown slave match");
603 return (IIC_ESTATUS);
604 }
605
606 return (IIC_NOERR);
607 }
608
609 static int
glxiic_state_idle_callback(struct glxiic_softc * sc,uint8_t status)610 glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status)
611 {
612
613 GLXIIC_ASSERT_LOCKED(sc);
614
615 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
616 GLXIIC_DEBUG_LOG("bus error in idle");
617 return (IIC_EBUSERR);
618 }
619
620 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
621 return (glxiic_handle_slave_match_locked(sc, status));
622 }
623
624 return (IIC_NOERR);
625 }
626
627 static int
glxiic_state_slave_tx_callback(struct glxiic_softc * sc,uint8_t status)628 glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status)
629 {
630 uint8_t data;
631
632 GLXIIC_ASSERT_LOCKED(sc);
633
634 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
635 GLXIIC_DEBUG_LOG("bus error in slave tx");
636 return (IIC_EBUSERR);
637 }
638
639 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
640 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
641 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
642 return (IIC_NOERR);
643 }
644
645 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
646 iicbus_intr(sc->iicbus, INTR_NOACK, NULL);
647 return (IIC_NOERR);
648 }
649
650 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
651 /* Handle repeated start in slave mode. */
652 return (glxiic_handle_slave_match_locked(sc, status));
653 }
654
655 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
656 GLXIIC_DEBUG_LOG("not awaiting data in slave tx");
657 return (IIC_ESTATUS);
658 }
659
660 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data);
661 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data);
662
663 glxiic_start_timeout_locked(sc);
664
665 return (IIC_NOERR);
666 }
667
668 static int
glxiic_state_slave_rx_callback(struct glxiic_softc * sc,uint8_t status)669 glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status)
670 {
671 uint8_t data;
672
673 GLXIIC_ASSERT_LOCKED(sc);
674
675 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
676 GLXIIC_DEBUG_LOG("bus error in slave rx");
677 return (IIC_EBUSERR);
678 }
679
680 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
681 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
682 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
683 return (IIC_NOERR);
684 }
685
686 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
687 /* Handle repeated start in slave mode. */
688 return (glxiic_handle_slave_match_locked(sc, status));
689 }
690
691 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
692 GLXIIC_DEBUG_LOG("no pending data in slave rx");
693 return (IIC_ESTATUS);
694 }
695
696 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
697 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data);
698
699 glxiic_start_timeout_locked(sc);
700
701 return (IIC_NOERR);
702 }
703
704 static int
glxiic_state_master_addr_callback(struct glxiic_softc * sc,uint8_t status)705 glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status)
706 {
707 uint8_t slave;
708 uint8_t ctrl1;
709
710 GLXIIC_ASSERT_LOCKED(sc);
711
712 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
713 GLXIIC_DEBUG_LOG("bus error after master start");
714 return (IIC_EBUSERR);
715 }
716
717 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
718 GLXIIC_DEBUG_LOG("not bus master after master start");
719 return (IIC_ESTATUS);
720 }
721
722 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
723 GLXIIC_DEBUG_LOG("not awaiting address in master addr");
724 return (IIC_ESTATUS);
725 }
726
727 if ((sc->msg->flags & IIC_M_RD) != 0) {
728 slave = sc->msg->slave | LSB;
729 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX);
730 } else {
731 slave = sc->msg->slave & ~LSB;
732 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX);
733 }
734
735 sc->data = sc->msg->buf;
736 sc->ndata = sc->msg->len;
737
738 /* Handle address-only transfer. */
739 if (sc->ndata == 0)
740 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
741
742 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave);
743
744 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) {
745 /* Last byte from slave, set NACK. */
746 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
747 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
748 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
749 }
750
751 return (IIC_NOERR);
752 }
753
754 static int
glxiic_state_master_tx_callback(struct glxiic_softc * sc,uint8_t status)755 glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status)
756 {
757
758 GLXIIC_ASSERT_LOCKED(sc);
759
760 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
761 GLXIIC_DEBUG_LOG("bus error in master tx");
762 return (IIC_EBUSERR);
763 }
764
765 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
766 GLXIIC_DEBUG_LOG("not bus master in master tx");
767 return (IIC_ESTATUS);
768 }
769
770 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
771 GLXIIC_DEBUG_LOG("slave nack in master tx");
772 return (IIC_ENOACK);
773 }
774
775 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
776 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
777 GLXIIC_SMB_STS_STASTR_BIT);
778 }
779
780 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
781 GLXIIC_DEBUG_LOG("not awaiting data in master tx");
782 return (IIC_ESTATUS);
783 }
784
785 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++);
786 if (--sc->ndata == 0)
787 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
788 else
789 glxiic_start_timeout_locked(sc);
790
791 return (IIC_NOERR);
792 }
793
794 static int
glxiic_state_master_rx_callback(struct glxiic_softc * sc,uint8_t status)795 glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status)
796 {
797 uint8_t ctrl1;
798
799 GLXIIC_ASSERT_LOCKED(sc);
800
801 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
802 GLXIIC_DEBUG_LOG("bus error in master rx");
803 return (IIC_EBUSERR);
804 }
805
806 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
807 GLXIIC_DEBUG_LOG("not bus master in master rx");
808 return (IIC_ESTATUS);
809 }
810
811 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
812 GLXIIC_DEBUG_LOG("slave nack in rx");
813 return (IIC_ENOACK);
814 }
815
816 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
817 /* Bus is stalled, clear and wait for data. */
818 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
819 GLXIIC_SMB_STS_STASTR_BIT);
820 return (IIC_NOERR);
821 }
822
823 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
824 GLXIIC_DEBUG_LOG("no pending data in master rx");
825 return (IIC_ESTATUS);
826 }
827
828 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
829 if (--sc->ndata == 0) {
830 /* Proceed with stop on reading last byte. */
831 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
832 return (glxiic_state_table[sc->state].callback(sc, status));
833 }
834
835 if (sc->ndata == 1) {
836 /* Last byte from slave, set NACK. */
837 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
838 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
839 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
840 }
841
842 glxiic_start_timeout_locked(sc);
843
844 return (IIC_NOERR);
845 }
846
847 static int
glxiic_state_master_stop_callback(struct glxiic_softc * sc,uint8_t status)848 glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status)
849 {
850 uint8_t ctrl1;
851
852 GLXIIC_ASSERT_LOCKED(sc);
853
854 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
855 GLXIIC_DEBUG_LOG("bus error in master stop");
856 return (IIC_EBUSERR);
857 }
858
859 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
860 GLXIIC_DEBUG_LOG("not bus master in master stop");
861 return (IIC_ESTATUS);
862 }
863
864 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
865 GLXIIC_DEBUG_LOG("slave nack in master stop");
866 return (IIC_ENOACK);
867 }
868
869 if (--sc->nmsgs > 0) {
870 /* Start transfer of next message. */
871 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) {
872 glxiic_stop_locked(sc);
873 }
874
875 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
876 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
877 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
878
879 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
880 sc->msg++;
881 } else {
882 /* Last message. */
883 glxiic_stop_locked(sc);
884 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
885 sc->error = IIC_NOERR;
886 GLXIIC_WAKEUP(sc);
887 }
888
889 return (IIC_NOERR);
890 }
891
892 static void
glxiic_intr(void * arg)893 glxiic_intr(void *arg)
894 {
895 struct glxiic_softc *sc;
896 int error;
897 uint8_t status, data;
898
899 sc = (struct glxiic_softc *)arg;
900
901 GLXIIC_LOCK(sc);
902
903 status = glxiic_read_status_locked(sc);
904
905 /* Check if this interrupt originated from the SMBus. */
906 if ((status &
907 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) {
908
909 error = glxiic_state_table[sc->state].callback(sc, status);
910
911 if (error != IIC_NOERR) {
912 if (glxiic_state_table[sc->state].master) {
913 glxiic_stop_locked(sc);
914 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
915 sc->error = error;
916 GLXIIC_WAKEUP(sc);
917 } else {
918 data = error & 0xff;
919 iicbus_intr(sc->iicbus, INTR_ERROR, &data);
920 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
921 }
922 }
923 }
924
925 GLXIIC_UNLOCK(sc);
926 }
927
928 static int
glxiic_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)929 glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
930 {
931 struct glxiic_softc *sc;
932
933 sc = device_get_softc(dev);
934
935 GLXIIC_LOCK(sc);
936
937 if (oldaddr != NULL)
938 *oldaddr = sc->addr;
939 sc->addr = addr;
940
941 /* A disable/enable cycle resets the controller. */
942 glxiic_smb_disable(sc);
943 glxiic_smb_enable(sc, speed, addr);
944
945 if (glxiic_state_table[sc->state].master) {
946 sc->error = IIC_ESTATUS;
947 GLXIIC_WAKEUP(sc);
948 }
949 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
950
951 GLXIIC_UNLOCK(sc);
952
953 return (IIC_NOERR);
954 }
955
956 static int
glxiic_transfer(device_t dev,struct iic_msg * msgs,uint32_t nmsgs)957 glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
958 {
959 struct glxiic_softc *sc;
960 int error;
961 uint8_t ctrl1;
962
963 sc = device_get_softc(dev);
964
965 GLXIIC_LOCK(sc);
966
967 if (sc->state != GLXIIC_STATE_IDLE) {
968 error = IIC_EBUSBSY;
969 goto out;
970 }
971
972 sc->msg = msgs;
973 sc->nmsgs = nmsgs;
974 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
975
976 /* Set start bit and let glxiic_intr() handle the transfer. */
977 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
978 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
979 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
980
981 GLXIIC_SLEEP(sc);
982 error = sc->error;
983 out:
984 GLXIIC_UNLOCK(sc);
985
986 return (error);
987 }
988
989 static void
glxiic_smb_map_interrupt(int irq)990 glxiic_smb_map_interrupt(int irq)
991 {
992 uint32_t irq_map;
993 int old_irq;
994
995 /* Protect the read-modify-write operation. */
996 critical_enter();
997
998 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
999 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
1000
1001 if (irq != old_irq) {
1002 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq);
1003 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq);
1004 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map);
1005 }
1006
1007 critical_exit();
1008 }
1009
1010 static void
glxiic_gpio_enable(struct glxiic_softc * sc)1011 glxiic_gpio_enable(struct glxiic_softc *sc)
1012 {
1013
1014 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1015 GLXIIC_GPIO_14_15_ENABLE);
1016 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1017 GLXIIC_GPIO_14_15_ENABLE);
1018 }
1019
1020 static void
glxiic_gpio_disable(struct glxiic_softc * sc)1021 glxiic_gpio_disable(struct glxiic_softc *sc)
1022 {
1023
1024 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1025 GLXIIC_GPIO_14_15_DISABLE);
1026 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1027 GLXIIC_GPIO_14_15_DISABLE);
1028 }
1029
1030 static void
glxiic_smb_enable(struct glxiic_softc * sc,uint8_t speed,uint8_t addr)1031 glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr)
1032 {
1033 uint8_t ctrl1;
1034
1035 ctrl1 = 0;
1036
1037 switch (speed) {
1038 case IIC_SLOW:
1039 sc->sclfrq = GLXIIC_SLOW;
1040 break;
1041 case IIC_FAST:
1042 sc->sclfrq = GLXIIC_FAST;
1043 break;
1044 case IIC_FASTEST:
1045 sc->sclfrq = GLXIIC_FASTEST;
1046 break;
1047 case IIC_UNKNOWN:
1048 default:
1049 /* Reuse last frequency. */
1050 break;
1051 }
1052
1053 /* Set bus speed and enable controller. */
1054 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1055 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT);
1056
1057 if (addr != 0) {
1058 /* Enable new match and global call match interrupts. */
1059 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT |
1060 GLXIIC_SMB_CTRL1_GCMEN_BIT;
1061 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR,
1062 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr));
1063 } else {
1064 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0);
1065 }
1066
1067 /* Enable stall after start and interrupt. */
1068 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
1069 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT);
1070 }
1071
1072 static void
glxiic_smb_disable(struct glxiic_softc * sc)1073 glxiic_smb_disable(struct glxiic_softc *sc)
1074 {
1075 uint16_t sclfrq;
1076
1077 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2);
1078 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1079 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT);
1080 }
1081