1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _GIC_V3_VAR_H_ 30 #define _GIC_V3_VAR_H_ 31 32 #include <arm/arm/gic_common.h> 33 34 #define GIC_V3_DEVSTR "ARM Generic Interrupt Controller v3.0" 35 36 DECLARE_CLASS(gic_v3_driver); 37 38 struct gic_v3_irqsrc; 39 40 struct redist_pcpu { 41 struct resource *res; /* mem resource for redist */ 42 vm_offset_t pend_base; 43 bus_size_t offset; 44 bool lpi_enabled; /* redist LPI configured? */ 45 }; 46 47 struct gic_redists { 48 /* 49 * Re-Distributor region description. 50 * We will have few of those depending 51 * on the #redistributor-regions property in FDT. 52 */ 53 struct resource ** regions; 54 /* Number of Re-Distributor regions */ 55 u_int nregions; 56 /* 57 * Whether to treat each region as a single Re-Distributor page or a 58 * series of contiguous pages (i.e. from each ACPI MADT GICC's GICR 59 * Base Address field) 60 */ 61 bool single; 62 /* Per-CPU Re-Distributor data */ 63 struct redist_pcpu *pcpu; 64 }; 65 66 struct gic_v3_softc { 67 device_t dev; 68 struct resource ** gic_res; 69 struct mtx gic_mtx; 70 /* Distributor */ 71 struct resource * gic_dist; 72 /* Re-Distributors */ 73 struct gic_redists gic_redists; 74 75 /* Message Based Interrupts */ 76 u_int gic_mbi_start; 77 u_int gic_mbi_end; 78 struct mtx gic_mbi_mtx; 79 80 uint32_t gic_pidr2; 81 u_int gic_bus; 82 83 u_int gic_nirqs; 84 u_int gic_idbits; 85 86 boolean_t gic_registered; 87 88 int gic_nchildren; 89 device_t *gic_children; 90 struct intr_pic *gic_pic; 91 struct gic_v3_irqsrc *gic_irqs; 92 93 int nranges; 94 struct arm_gic_range * ranges; 95 }; 96 97 struct gic_v3_devinfo { 98 int gic_domain; 99 int msi_xref; 100 int is_vgic; 101 }; 102 103 #define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc) 104 105 MALLOC_DECLARE(M_GIC_V3); 106 107 /* ivars */ 108 #define GICV3_IVAR_NIRQS 1000 109 /* 1001 was GICV3_IVAR_REDIST_VADDR */ 110 #define GICV3_IVAR_REDIST 1002 111 #define GICV3_IVAR_SUPPORT_LPIS 1003 112 113 __BUS_ACCESSOR(gicv3, nirqs, GICV3, NIRQS, u_int); 114 __BUS_ACCESSOR(gicv3, redist, GICV3, REDIST, void *); 115 __BUS_ACCESSOR(gicv3, support_lpis, GICV3, SUPPORT_LPIS, bool); 116 117 /* Device methods */ 118 int gic_v3_attach(device_t dev); 119 int gic_v3_detach(device_t dev); 120 int arm_gic_v3_intr(void *); 121 122 uint32_t gic_r_read_4(device_t, bus_size_t); 123 uint64_t gic_r_read_8(device_t, bus_size_t); 124 void gic_r_write_4(device_t, bus_size_t, uint32_t var); 125 void gic_r_write_8(device_t, bus_size_t, uint64_t var); 126 127 /* 128 * GIC Distributor accessors. 129 * Notice that only GIC sofc can be passed. 130 */ 131 #define gic_d_read(sc, len, reg) \ 132 ({ \ 133 bus_read_##len(sc->gic_dist, reg); \ 134 }) 135 136 #define gic_d_write(sc, len, reg, val) \ 137 ({ \ 138 bus_write_##len(sc->gic_dist, reg, val);\ 139 }) 140 141 /* GIC Re-Distributor accessors (per-CPU) */ 142 #define gic_r_read(sc, len, reg) \ 143 ({ \ 144 u_int cpu = PCPU_GET(cpuid); \ 145 \ 146 bus_read_##len( \ 147 (sc)->gic_redists.pcpu[cpu].res, \ 148 (sc)->gic_redists.pcpu[cpu].offset + (reg)); \ 149 }) 150 151 #define gic_r_write(sc, len, reg, val) \ 152 ({ \ 153 u_int cpu = PCPU_GET(cpuid); \ 154 \ 155 bus_write_##len( \ 156 (sc)->gic_redists.pcpu[cpu].res, \ 157 (sc)->gic_redists.pcpu[cpu].offset + (reg), \ 158 (val)); \ 159 }) 160 161 #endif /* _GIC_V3_VAR_H_ */ 162