1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42 #include "soc15.h"
43 #include "soc15_common.h"
44 #include "clearstate_gfx10.h"
45 #include "v10_structs.h"
46 #include "gfx_v10_0.h"
47 #include "gfx_v10_0_cleaner_shader.h"
48 #include "nbio_v2_3.h"
49
50 /*
51 * Navi10 has two graphic rings to share each graphic pipe.
52 * 1. Primary ring
53 * 2. Async ring
54 */
55 #define GFX10_NUM_GFX_RINGS_NV1X 1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2
57 #define GFX10_MEC_HPD_SIZE 2048
58
59 #define F32_CE_PROGRAM_RAM_SIZE 65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61
62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
71
72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
76
77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
104
105 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish 0x0105
106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX 1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish 0x0106
108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX 1
109
110 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
112 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
114
115 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
117 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
119
120 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
121 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
122 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
124 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
126 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e
127 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
128 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
129 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
130 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
131 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
132 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
133 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
134 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440
135 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
136 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
137 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
138 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
139
140 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
141 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
142 #define mmCP_HYP_PFP_UCODE_DATA 0x5815
143 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
144 #define mmCP_HYP_CE_UCODE_ADDR 0x5818
145 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
146 #define mmCP_HYP_CE_UCODE_DATA 0x5819
147 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
148 #define mmCP_HYP_ME_UCODE_ADDR 0x5816
149 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
150 #define mmCP_HYP_ME_UCODE_DATA 0x5817
151 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
152
153 #define mmCPG_PSP_DEBUG 0x5c10
154 #define mmCPG_PSP_DEBUG_BASE_IDX 1
155 #define mmCPC_PSP_DEBUG 0x5c11
156 #define mmCPC_PSP_DEBUG_BASE_IDX 1
157 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
158 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
159
160 //CC_GC_SA_UNIT_DISABLE
161 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
162 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
163 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
165 //GC_USER_SA_UNIT_DISABLE
166 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea
167 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
168 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
170 //PA_SC_ENHANCE_3
171 #define mmPA_SC_ENHANCE_3 0x1085
172 #define mmPA_SC_ENHANCE_3_BASE_IDX 0
173 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
175
176 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c
177 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
178
179 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3
180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
181 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
183
184 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
186
187 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
189
190 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
191 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
192 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
193 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
194 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
195 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
196
197 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
203 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
204 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
205 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
206 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
207 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
208
209 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
210 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
211 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
212 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
213 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
214 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
215
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
222
223 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
224 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
225 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
226 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
228 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
229
230 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
231 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
232 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
233 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
234 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
235 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
236
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
243
244 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
245 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
246 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
247 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
248 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
249 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
250
251 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
252 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
253 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
254 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
256 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
257
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
264
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
271
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
278
279 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
280 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
281 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
282 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
283 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
284 SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
285 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
286 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
287 SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
288 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
289 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
290 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
291 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
292 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
293 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
294 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
295 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
296 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
297 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
298 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
299 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
301 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
302 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
303 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
304 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
307 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
308 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
309 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
310 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
311 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
312 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
313 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
314 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
315 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
316 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
317 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
318 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
319 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
320 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
321 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
322 SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
323 SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
324 SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
325 SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
326 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
327 SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
328 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
329 SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
330 SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
331 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
332 SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
333 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
334 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
335 SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
336 SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
337 SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
338 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
339 SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
340 SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
341 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
342 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
343 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
344 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
345 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
346 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
347 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
348 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
349 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
350 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
351 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
352 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
353 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
354 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
355 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
356 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
357 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
358 SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
359 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
360 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
361 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
362 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
363 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
364 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
365 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
366 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
367 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
368 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
369 SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
370 /* cp header registers */
371 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
372 /* SE status registers */
373 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
374 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
375 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
376 SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
377 };
378
379 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
380 /* compute registers */
381 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
382 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
383 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
384 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
385 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
386 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
387 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
388 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
389 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
390 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
391 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
392 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
393 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
394 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
395 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
396 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
397 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
398 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
399 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
400 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
401 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
402 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
403 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
404 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
405 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
406 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
407 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
408 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
409 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
410 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
411 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
412 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
413 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
414 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
415 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
416 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
417 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
418 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
419 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS),
420 /* cp header registers */
421 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
422 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
423 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
424 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
425 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
426 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
427 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
428 SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
429 };
430
431 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
432 /* gfx queue registers */
433 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
434 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
435 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
436 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
437 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
438 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
439 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
440 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
442 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
443 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
444 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
445 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
446 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
447 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
448 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
449 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
450 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
451 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
452 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
453 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
454 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
455 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI),
456 /* gfx header registers */
457 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
458 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
459 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
460 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
461 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
462 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
463 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
464 SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
465 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
466 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
467 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
468 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
469 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
470 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
471 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
472 SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
473 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
474 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
475 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
476 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
477 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
478 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
479 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
480 SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
481 };
482
483 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
524 };
525
526 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
527 /* Pending on emulation bring up */
528 };
529
530 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1583 };
1584
1585 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1624 };
1625
1626 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1669 };
1670
1671 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1672 /* Pending on emulation bring up */
1673 };
1674
1675 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2296 };
2297
2298 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2299 /* Pending on emulation bring up */
2300 };
2301
2302 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3355 };
3356
3357 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3401 };
3402
3403 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3404 /* Pending on emulation bring up */
3405 };
3406
3407 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3449
3450 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3452 };
3453
3454 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3479
3480 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3482 };
3483
3484 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3505 };
3506
3507 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
3544 };
3545
3546 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3579 };
3580
3581 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3616 };
3617
3618 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3641 };
3642
3643 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3666 };
3667
3668 #define DEFAULT_SH_MEM_CONFIG \
3669 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3670 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3671 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3672 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3673
3674 /* TODO: pending on golden setting value of gb address config */
3675 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3676
3677 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3678 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3679 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3680 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3681 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3682 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3683 struct amdgpu_cu_info *cu_info);
3684 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3685 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3686 u32 sh_num, u32 instance, int xcc_id);
3687 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3688
3689 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3690 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3691 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3692 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3693 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3694 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3695 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3696 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3697 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3698 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3699 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3700 uint16_t pasid, uint32_t flush_type,
3701 bool all_hub, uint8_t dst_sel);
3702 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3703 unsigned int vmid);
3704
3705 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3706 enum amd_powergating_state state);
gfx10_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)3707 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3708 {
3709 struct amdgpu_device *adev = kiq_ring->adev;
3710 u64 shader_mc_addr;
3711
3712 /* Cleaner shader MC address */
3713 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
3714
3715 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3716 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3717 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3718 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3719 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3720 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
3721 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
3722 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3723 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3724 }
3725
gfx10_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)3726 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3727 struct amdgpu_ring *ring)
3728 {
3729 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3730 uint64_t wptr_addr = ring->wptr_gpu_addr;
3731 uint32_t eng_sel = 0;
3732
3733 switch (ring->funcs->type) {
3734 case AMDGPU_RING_TYPE_COMPUTE:
3735 eng_sel = 0;
3736 break;
3737 case AMDGPU_RING_TYPE_GFX:
3738 eng_sel = 4;
3739 break;
3740 case AMDGPU_RING_TYPE_MES:
3741 eng_sel = 5;
3742 break;
3743 default:
3744 WARN_ON(1);
3745 }
3746
3747 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3748 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3749 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3750 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3751 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3752 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3753 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3754 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3755 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3756 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3757 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3758 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3759 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3760 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3761 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3762 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3763 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3764 }
3765
gfx10_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)3766 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3767 struct amdgpu_ring *ring,
3768 enum amdgpu_unmap_queues_action action,
3769 u64 gpu_addr, u64 seq)
3770 {
3771 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3772
3773 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3774 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3775 PACKET3_UNMAP_QUEUES_ACTION(action) |
3776 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3777 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3778 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3779 amdgpu_ring_write(kiq_ring,
3780 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3781
3782 if (action == PREEMPT_QUEUES_NO_UNMAP) {
3783 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3784 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3785 amdgpu_ring_write(kiq_ring, seq);
3786 } else {
3787 amdgpu_ring_write(kiq_ring, 0);
3788 amdgpu_ring_write(kiq_ring, 0);
3789 amdgpu_ring_write(kiq_ring, 0);
3790 }
3791 }
3792
gfx10_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)3793 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3794 struct amdgpu_ring *ring,
3795 u64 addr,
3796 u64 seq)
3797 {
3798 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3799
3800 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3801 amdgpu_ring_write(kiq_ring,
3802 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3803 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3804 PACKET3_QUERY_STATUS_COMMAND(2));
3805 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3806 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3807 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3808 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3809 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3810 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3811 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3812 }
3813
gfx10_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)3814 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3815 uint16_t pasid, uint32_t flush_type,
3816 bool all_hub)
3817 {
3818 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3819 }
3820
gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring * kiq_ring,uint32_t queue_type,uint32_t me_id,uint32_t pipe_id,uint32_t queue_id,uint32_t xcc_id,uint32_t vmid)3821 static void gfx_v10_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type,
3822 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id,
3823 uint32_t xcc_id, uint32_t vmid)
3824 {
3825 struct amdgpu_device *adev = kiq_ring->adev;
3826 unsigned i;
3827 uint32_t tmp;
3828
3829 /* enter save mode */
3830 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
3831 mutex_lock(&adev->srbm_mutex);
3832 nv_grbm_select(adev, me_id, pipe_id, queue_id, 0);
3833
3834 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) {
3835 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2);
3836 WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1);
3837 /* wait till dequeue take effects */
3838 for (i = 0; i < adev->usec_timeout; i++) {
3839 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3840 break;
3841 udelay(1);
3842 }
3843 if (i >= adev->usec_timeout)
3844 dev_err(adev->dev, "fail to wait on hqd deactive\n");
3845 } else if (queue_type == AMDGPU_RING_TYPE_GFX) {
3846 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
3847 (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
3848 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
3849 if (pipe_id == 0)
3850 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);
3851 else
3852 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);
3853 WREG32_SOC15(GC, 0, mmCP_VMID_RESET, tmp);
3854
3855 /* wait till dequeue take effects */
3856 for (i = 0; i < adev->usec_timeout; i++) {
3857 if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1))
3858 break;
3859 udelay(1);
3860 }
3861 if (i >= adev->usec_timeout)
3862 dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n");
3863 } else {
3864 dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type);
3865 }
3866
3867 nv_grbm_select(adev, 0, 0, 0, 0);
3868 mutex_unlock(&adev->srbm_mutex);
3869 /* exit safe mode */
3870 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
3871 }
3872
3873 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3874 .kiq_set_resources = gfx10_kiq_set_resources,
3875 .kiq_map_queues = gfx10_kiq_map_queues,
3876 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3877 .kiq_query_status = gfx10_kiq_query_status,
3878 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3879 .kiq_reset_hw_queue = gfx_v10_0_kiq_reset_hw_queue,
3880 .set_resources_size = 8,
3881 .map_queues_size = 7,
3882 .unmap_queues_size = 6,
3883 .query_status_size = 7,
3884 .invalidate_tlbs_size = 2,
3885 };
3886
gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)3887 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3888 {
3889 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3890 }
3891
gfx_v10_0_init_spm_golden_registers(struct amdgpu_device * adev)3892 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3893 {
3894 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3895 case IP_VERSION(10, 1, 10):
3896 soc15_program_register_sequence(adev,
3897 golden_settings_gc_rlc_spm_10_0_nv10,
3898 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3899 break;
3900 case IP_VERSION(10, 1, 1):
3901 soc15_program_register_sequence(adev,
3902 golden_settings_gc_rlc_spm_10_1_nv14,
3903 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3904 break;
3905 case IP_VERSION(10, 1, 2):
3906 soc15_program_register_sequence(adev,
3907 golden_settings_gc_rlc_spm_10_1_2_nv12,
3908 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3909 break;
3910 default:
3911 break;
3912 }
3913 }
3914
gfx_v10_0_init_golden_registers(struct amdgpu_device * adev)3915 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3916 {
3917 if (amdgpu_sriov_vf(adev))
3918 return;
3919
3920 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3921 case IP_VERSION(10, 1, 10):
3922 soc15_program_register_sequence(adev,
3923 golden_settings_gc_10_1,
3924 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3925 soc15_program_register_sequence(adev,
3926 golden_settings_gc_10_0_nv10,
3927 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3928 break;
3929 case IP_VERSION(10, 1, 1):
3930 soc15_program_register_sequence(adev,
3931 golden_settings_gc_10_1_1,
3932 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3933 soc15_program_register_sequence(adev,
3934 golden_settings_gc_10_1_nv14,
3935 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3936 break;
3937 case IP_VERSION(10, 1, 2):
3938 soc15_program_register_sequence(adev,
3939 golden_settings_gc_10_1_2,
3940 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3941 soc15_program_register_sequence(adev,
3942 golden_settings_gc_10_1_2_nv12,
3943 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3944 break;
3945 case IP_VERSION(10, 3, 0):
3946 soc15_program_register_sequence(adev,
3947 golden_settings_gc_10_3,
3948 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3949 soc15_program_register_sequence(adev,
3950 golden_settings_gc_10_3_sienna_cichlid,
3951 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3952 break;
3953 case IP_VERSION(10, 3, 2):
3954 soc15_program_register_sequence(adev,
3955 golden_settings_gc_10_3_2,
3956 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3957 break;
3958 case IP_VERSION(10, 3, 1):
3959 soc15_program_register_sequence(adev,
3960 golden_settings_gc_10_3_vangogh,
3961 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3962 break;
3963 case IP_VERSION(10, 3, 3):
3964 soc15_program_register_sequence(adev,
3965 golden_settings_gc_10_3_3,
3966 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3967 break;
3968 case IP_VERSION(10, 3, 4):
3969 soc15_program_register_sequence(adev,
3970 golden_settings_gc_10_3_4,
3971 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3972 break;
3973 case IP_VERSION(10, 3, 5):
3974 soc15_program_register_sequence(adev,
3975 golden_settings_gc_10_3_5,
3976 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3977 break;
3978 case IP_VERSION(10, 1, 3):
3979 case IP_VERSION(10, 1, 4):
3980 soc15_program_register_sequence(adev,
3981 golden_settings_gc_10_0_cyan_skillfish,
3982 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3983 break;
3984 case IP_VERSION(10, 3, 6):
3985 soc15_program_register_sequence(adev,
3986 golden_settings_gc_10_3_6,
3987 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3988 break;
3989 case IP_VERSION(10, 3, 7):
3990 soc15_program_register_sequence(adev,
3991 golden_settings_gc_10_3_7,
3992 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3993 break;
3994 default:
3995 break;
3996 }
3997 gfx_v10_0_init_spm_golden_registers(adev);
3998 }
3999
gfx_v10_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)4000 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
4001 bool wc, uint32_t reg, uint32_t val)
4002 {
4003 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4004 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
4005 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
4006 amdgpu_ring_write(ring, reg);
4007 amdgpu_ring_write(ring, 0);
4008 amdgpu_ring_write(ring, val);
4009 }
4010
gfx_v10_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)4011 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
4012 int mem_space, int opt, uint32_t addr0,
4013 uint32_t addr1, uint32_t ref, uint32_t mask,
4014 uint32_t inv)
4015 {
4016 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4017 amdgpu_ring_write(ring,
4018 /* memory (1) or register (0) */
4019 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
4020 WAIT_REG_MEM_OPERATION(opt) | /* wait */
4021 WAIT_REG_MEM_FUNCTION(3) | /* equal */
4022 WAIT_REG_MEM_ENGINE(eng_sel)));
4023
4024 if (mem_space)
4025 BUG_ON(addr0 & 0x3); /* Dword align */
4026 amdgpu_ring_write(ring, addr0);
4027 amdgpu_ring_write(ring, addr1);
4028 amdgpu_ring_write(ring, ref);
4029 amdgpu_ring_write(ring, mask);
4030 amdgpu_ring_write(ring, inv); /* poll interval */
4031 }
4032
gfx_v10_0_ring_test_ring(struct amdgpu_ring * ring)4033 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
4034 {
4035 struct amdgpu_device *adev = ring->adev;
4036 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4037 uint32_t tmp = 0;
4038 unsigned int i;
4039 int r;
4040
4041 WREG32(scratch, 0xCAFEDEAD);
4042 r = amdgpu_ring_alloc(ring, 3);
4043 if (r) {
4044 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
4045 ring->idx, r);
4046 return r;
4047 }
4048
4049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
4050 amdgpu_ring_write(ring, scratch -
4051 PACKET3_SET_UCONFIG_REG_START);
4052 amdgpu_ring_write(ring, 0xDEADBEEF);
4053 amdgpu_ring_commit(ring);
4054
4055 for (i = 0; i < adev->usec_timeout; i++) {
4056 tmp = RREG32(scratch);
4057 if (tmp == 0xDEADBEEF)
4058 break;
4059 if (amdgpu_emu_mode == 1)
4060 msleep(1);
4061 else
4062 udelay(1);
4063 }
4064
4065 if (i >= adev->usec_timeout)
4066 r = -ETIMEDOUT;
4067
4068 return r;
4069 }
4070
gfx_v10_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)4071 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
4072 {
4073 struct amdgpu_device *adev = ring->adev;
4074 struct amdgpu_ib ib;
4075 struct dma_fence *f = NULL;
4076 unsigned int index;
4077 uint64_t gpu_addr;
4078 volatile uint32_t *cpu_ptr;
4079 long r;
4080
4081 memset(&ib, 0, sizeof(ib));
4082
4083 r = amdgpu_device_wb_get(adev, &index);
4084 if (r)
4085 return r;
4086
4087 gpu_addr = adev->wb.gpu_addr + (index * 4);
4088 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
4089 cpu_ptr = &adev->wb.wb[index];
4090
4091 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
4092 if (r) {
4093 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
4094 goto err1;
4095 }
4096
4097 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
4098 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
4099 ib.ptr[2] = lower_32_bits(gpu_addr);
4100 ib.ptr[3] = upper_32_bits(gpu_addr);
4101 ib.ptr[4] = 0xDEADBEEF;
4102 ib.length_dw = 5;
4103
4104 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4105 if (r)
4106 goto err2;
4107
4108 r = dma_fence_wait_timeout(f, false, timeout);
4109 if (r == 0) {
4110 r = -ETIMEDOUT;
4111 goto err2;
4112 } else if (r < 0) {
4113 goto err2;
4114 }
4115
4116 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
4117 r = 0;
4118 else
4119 r = -EINVAL;
4120 err2:
4121 amdgpu_ib_free(&ib, NULL);
4122 dma_fence_put(f);
4123 err1:
4124 amdgpu_device_wb_free(adev, index);
4125 return r;
4126 }
4127
gfx_v10_0_free_microcode(struct amdgpu_device * adev)4128 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
4129 {
4130 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4131 amdgpu_ucode_release(&adev->gfx.me_fw);
4132 amdgpu_ucode_release(&adev->gfx.ce_fw);
4133 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4134 amdgpu_ucode_release(&adev->gfx.mec_fw);
4135 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4136
4137 kfree(adev->gfx.rlc.register_list_format);
4138 }
4139
gfx_v10_0_check_fw_write_wait(struct amdgpu_device * adev)4140 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
4141 {
4142 adev->gfx.cp_fw_write_wait = false;
4143
4144 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4145 case IP_VERSION(10, 1, 10):
4146 case IP_VERSION(10, 1, 2):
4147 case IP_VERSION(10, 1, 1):
4148 case IP_VERSION(10, 1, 3):
4149 case IP_VERSION(10, 1, 4):
4150 if ((adev->gfx.me_fw_version >= 0x00000046) &&
4151 (adev->gfx.me_feature_version >= 27) &&
4152 (adev->gfx.pfp_fw_version >= 0x00000068) &&
4153 (adev->gfx.pfp_feature_version >= 27) &&
4154 (adev->gfx.mec_fw_version >= 0x0000005b) &&
4155 (adev->gfx.mec_feature_version >= 27))
4156 adev->gfx.cp_fw_write_wait = true;
4157 break;
4158 case IP_VERSION(10, 3, 0):
4159 case IP_VERSION(10, 3, 2):
4160 case IP_VERSION(10, 3, 1):
4161 case IP_VERSION(10, 3, 4):
4162 case IP_VERSION(10, 3, 5):
4163 case IP_VERSION(10, 3, 6):
4164 case IP_VERSION(10, 3, 3):
4165 case IP_VERSION(10, 3, 7):
4166 adev->gfx.cp_fw_write_wait = true;
4167 break;
4168 default:
4169 break;
4170 }
4171
4172 if (!adev->gfx.cp_fw_write_wait)
4173 DRM_WARN_ONCE("CP firmware version too old, please update!");
4174 }
4175
gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device * adev)4176 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4177 {
4178 bool ret = false;
4179
4180 switch (adev->pdev->revision) {
4181 case 0xc2:
4182 case 0xc3:
4183 ret = true;
4184 break;
4185 default:
4186 ret = false;
4187 break;
4188 }
4189
4190 return ret;
4191 }
4192
gfx_v10_0_check_gfxoff_flag(struct amdgpu_device * adev)4193 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4194 {
4195 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4196 case IP_VERSION(10, 1, 10):
4197 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4198 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4199 break;
4200 default:
4201 break;
4202 }
4203 }
4204
gfx_v10_0_init_microcode(struct amdgpu_device * adev)4205 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4206 {
4207 char fw_name[53];
4208 char ucode_prefix[30];
4209 const char *wks = "";
4210 int err;
4211 const struct rlc_firmware_header_v2_0 *rlc_hdr;
4212 uint16_t version_major;
4213 uint16_t version_minor;
4214
4215 DRM_DEBUG("\n");
4216
4217 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4218 (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4219 wks = "_wks";
4220 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4221
4222 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
4223 AMDGPU_UCODE_REQUIRED,
4224 "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4225 if (err)
4226 goto out;
4227 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4228
4229 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
4230 AMDGPU_UCODE_REQUIRED,
4231 "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4232 if (err)
4233 goto out;
4234 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4235
4236 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
4237 AMDGPU_UCODE_REQUIRED,
4238 "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4239 if (err)
4240 goto out;
4241 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4242
4243 if (!amdgpu_sriov_vf(adev)) {
4244 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4245 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4246 if (err)
4247 goto out;
4248
4249 /* don't validate this firmware. There are apparently firmwares
4250 * in the wild with incorrect size in the header
4251 */
4252 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4253 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4254 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4255 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4256 if (err)
4257 goto out;
4258 }
4259
4260 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
4261 AMDGPU_UCODE_REQUIRED,
4262 "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4263 if (err)
4264 goto out;
4265 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4266 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4267
4268 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
4269 AMDGPU_UCODE_REQUIRED,
4270 "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4271 if (!err) {
4272 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4273 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4274 } else {
4275 err = 0;
4276 adev->gfx.mec2_fw = NULL;
4277 }
4278
4279 gfx_v10_0_check_fw_write_wait(adev);
4280 out:
4281 if (err) {
4282 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4283 amdgpu_ucode_release(&adev->gfx.me_fw);
4284 amdgpu_ucode_release(&adev->gfx.ce_fw);
4285 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4286 amdgpu_ucode_release(&adev->gfx.mec_fw);
4287 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4288 }
4289
4290 gfx_v10_0_check_gfxoff_flag(adev);
4291
4292 return err;
4293 }
4294
gfx_v10_0_get_csb_size(struct amdgpu_device * adev)4295 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4296 {
4297 u32 count = 0;
4298 const struct cs_section_def *sect = NULL;
4299 const struct cs_extent_def *ext = NULL;
4300
4301 /* begin clear state */
4302 count += 2;
4303 /* context control state */
4304 count += 3;
4305
4306 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4307 for (ext = sect->section; ext->extent != NULL; ++ext) {
4308 if (sect->id == SECT_CONTEXT)
4309 count += 2 + ext->reg_count;
4310 else
4311 return 0;
4312 }
4313 }
4314
4315 /* set PA_SC_TILE_STEERING_OVERRIDE */
4316 count += 3;
4317 /* end clear state */
4318 count += 2;
4319 /* clear state */
4320 count += 2;
4321
4322 return count;
4323 }
4324
gfx_v10_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)4325 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4326 volatile u32 *buffer)
4327 {
4328 u32 count = 0;
4329 int ctx_reg_offset;
4330
4331 if (adev->gfx.rlc.cs_data == NULL)
4332 return;
4333 if (buffer == NULL)
4334 return;
4335
4336 count = amdgpu_gfx_csb_preamble_start(buffer);
4337 count = amdgpu_gfx_csb_data_parser(adev, buffer, count);
4338
4339 ctx_reg_offset = SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4340 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4341 buffer[count++] = cpu_to_le32(ctx_reg_offset);
4342 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4343
4344 amdgpu_gfx_csb_preamble_end(buffer, count);
4345 }
4346
gfx_v10_0_rlc_fini(struct amdgpu_device * adev)4347 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4348 {
4349 /* clear state block */
4350 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4351 &adev->gfx.rlc.clear_state_gpu_addr,
4352 (void **)&adev->gfx.rlc.cs_ptr);
4353
4354 /* jump table block */
4355 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4356 &adev->gfx.rlc.cp_table_gpu_addr,
4357 (void **)&adev->gfx.rlc.cp_table_ptr);
4358 }
4359
gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)4360 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4361 {
4362 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4363
4364 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4365 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4366 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4367 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4368 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4369 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4370 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4371 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4372 case IP_VERSION(10, 3, 0):
4373 reg_access_ctrl->spare_int =
4374 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4375 break;
4376 default:
4377 reg_access_ctrl->spare_int =
4378 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4379 break;
4380 }
4381 adev->gfx.rlc.rlcg_reg_access_supported = true;
4382 }
4383
gfx_v10_0_rlc_init(struct amdgpu_device * adev)4384 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4385 {
4386 const struct cs_section_def *cs_data;
4387 int r;
4388
4389 adev->gfx.rlc.cs_data = gfx10_cs_data;
4390
4391 cs_data = adev->gfx.rlc.cs_data;
4392
4393 if (cs_data) {
4394 /* init clear state block */
4395 r = amdgpu_gfx_rlc_init_csb(adev);
4396 if (r)
4397 return r;
4398 }
4399
4400 return 0;
4401 }
4402
gfx_v10_0_mec_fini(struct amdgpu_device * adev)4403 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4404 {
4405 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4406 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4407 }
4408
gfx_v10_0_me_init(struct amdgpu_device * adev)4409 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4410 {
4411 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4412
4413 amdgpu_gfx_graphics_queue_acquire(adev);
4414 }
4415
gfx_v10_0_mec_init(struct amdgpu_device * adev)4416 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4417 {
4418 int r;
4419 u32 *hpd;
4420 const __le32 *fw_data = NULL;
4421 unsigned int fw_size;
4422 u32 *fw = NULL;
4423 size_t mec_hpd_size;
4424
4425 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4426
4427 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4428
4429 /* take ownership of the relevant compute queues */
4430 amdgpu_gfx_compute_queue_acquire(adev);
4431 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4432
4433 if (mec_hpd_size) {
4434 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4435 AMDGPU_GEM_DOMAIN_GTT,
4436 &adev->gfx.mec.hpd_eop_obj,
4437 &adev->gfx.mec.hpd_eop_gpu_addr,
4438 (void **)&hpd);
4439 if (r) {
4440 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4441 gfx_v10_0_mec_fini(adev);
4442 return r;
4443 }
4444
4445 memset(hpd, 0, mec_hpd_size);
4446
4447 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4448 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4449 }
4450
4451 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4452 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4453
4454 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4455 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4456 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4457
4458 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4459 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4460 &adev->gfx.mec.mec_fw_obj,
4461 &adev->gfx.mec.mec_fw_gpu_addr,
4462 (void **)&fw);
4463 if (r) {
4464 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4465 gfx_v10_0_mec_fini(adev);
4466 return r;
4467 }
4468
4469 memcpy(fw, fw_data, fw_size);
4470
4471 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4472 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4473 }
4474
4475 return 0;
4476 }
4477
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)4478 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4479 {
4480 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4481 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4482 (address << SQ_IND_INDEX__INDEX__SHIFT));
4483 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4484 }
4485
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)4486 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4487 uint32_t thread, uint32_t regno,
4488 uint32_t num, uint32_t *out)
4489 {
4490 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4491 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4492 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4493 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4494 (SQ_IND_INDEX__AUTO_INCR_MASK));
4495 while (num--)
4496 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4497 }
4498
gfx_v10_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)4499 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4500 {
4501 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4502 * field when performing a select_se_sh so it should be
4503 * zero here
4504 */
4505 WARN_ON(simd != 0);
4506
4507 /* type 2 wave data */
4508 dst[(*no_fields)++] = 2;
4509 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4510 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4511 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4512 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4513 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4514 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4515 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4516 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4517 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4518 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4519 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4520 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4521 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4522 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4523 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4524 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4525 }
4526
gfx_v10_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)4527 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4528 uint32_t wave, uint32_t start,
4529 uint32_t size, uint32_t *dst)
4530 {
4531 WARN_ON(simd != 0);
4532
4533 wave_read_regs(
4534 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4535 dst);
4536 }
4537
gfx_v10_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)4538 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4539 uint32_t wave, uint32_t thread,
4540 uint32_t start, uint32_t size,
4541 uint32_t *dst)
4542 {
4543 wave_read_regs(
4544 adev, wave, thread,
4545 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4546 }
4547
gfx_v10_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)4548 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4549 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4550 {
4551 nv_grbm_select(adev, me, pipe, q, vm);
4552 }
4553
gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device * adev,bool enable)4554 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4555 bool enable)
4556 {
4557 uint32_t data, def;
4558
4559 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4560
4561 if (enable)
4562 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4563 else
4564 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4565
4566 if (data != def)
4567 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4568 }
4569
4570 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4571 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4572 .select_se_sh = &gfx_v10_0_select_se_sh,
4573 .read_wave_data = &gfx_v10_0_read_wave_data,
4574 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4575 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4576 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4577 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4578 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4579 };
4580
gfx_v10_0_gpu_early_init(struct amdgpu_device * adev)4581 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4582 {
4583 u32 gb_addr_config;
4584
4585 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4586 case IP_VERSION(10, 1, 10):
4587 case IP_VERSION(10, 1, 1):
4588 case IP_VERSION(10, 1, 2):
4589 adev->gfx.config.max_hw_contexts = 8;
4590 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4591 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4592 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4593 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4594 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4595 break;
4596 case IP_VERSION(10, 3, 0):
4597 case IP_VERSION(10, 3, 2):
4598 case IP_VERSION(10, 3, 1):
4599 case IP_VERSION(10, 3, 4):
4600 case IP_VERSION(10, 3, 5):
4601 case IP_VERSION(10, 3, 6):
4602 case IP_VERSION(10, 3, 3):
4603 case IP_VERSION(10, 3, 7):
4604 adev->gfx.config.max_hw_contexts = 8;
4605 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4606 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4607 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4608 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4609 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4610 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4611 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4612 break;
4613 case IP_VERSION(10, 1, 3):
4614 case IP_VERSION(10, 1, 4):
4615 adev->gfx.config.max_hw_contexts = 8;
4616 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4617 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4618 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4619 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4620 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4621 break;
4622 default:
4623 BUG();
4624 break;
4625 }
4626
4627 adev->gfx.config.gb_addr_config = gb_addr_config;
4628
4629 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4630 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4631 GB_ADDR_CONFIG, NUM_PIPES);
4632
4633 adev->gfx.config.max_tile_pipes =
4634 adev->gfx.config.gb_addr_config_fields.num_pipes;
4635
4636 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4637 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4638 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4639 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4640 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4641 GB_ADDR_CONFIG, NUM_RB_PER_SE);
4642 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4643 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4644 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4645 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4646 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4647 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4648 }
4649
gfx_v10_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)4650 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4651 int me, int pipe, int queue)
4652 {
4653 struct amdgpu_ring *ring;
4654 unsigned int irq_type;
4655 unsigned int hw_prio;
4656
4657 ring = &adev->gfx.gfx_ring[ring_id];
4658
4659 ring->me = me;
4660 ring->pipe = pipe;
4661 ring->queue = queue;
4662
4663 ring->ring_obj = NULL;
4664 ring->use_doorbell = true;
4665
4666 if (!ring_id)
4667 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4668 else
4669 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4670 ring->vm_hub = AMDGPU_GFXHUB(0);
4671 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4672
4673 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4674 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4675 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4676 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4677 hw_prio, NULL);
4678 }
4679
gfx_v10_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)4680 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4681 int mec, int pipe, int queue)
4682 {
4683 unsigned int irq_type;
4684 struct amdgpu_ring *ring;
4685 unsigned int hw_prio;
4686
4687 ring = &adev->gfx.compute_ring[ring_id];
4688
4689 /* mec0 is me1 */
4690 ring->me = mec + 1;
4691 ring->pipe = pipe;
4692 ring->queue = queue;
4693
4694 ring->ring_obj = NULL;
4695 ring->use_doorbell = true;
4696 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4697 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4698 + (ring_id * GFX10_MEC_HPD_SIZE);
4699 ring->vm_hub = AMDGPU_GFXHUB(0);
4700 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4701
4702 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4703 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4704 + ring->pipe;
4705 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4706 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4707 /* type-2 packets are deprecated on MEC, use type-3 instead */
4708 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4709 hw_prio, NULL);
4710 }
4711
gfx_v10_0_alloc_ip_dump(struct amdgpu_device * adev)4712 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
4713 {
4714 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4715 uint32_t *ptr;
4716 uint32_t inst;
4717
4718 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4719 if (!ptr) {
4720 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
4721 adev->gfx.ip_dump_core = NULL;
4722 } else {
4723 adev->gfx.ip_dump_core = ptr;
4724 }
4725
4726 /* Allocate memory for compute queue registers for all the instances */
4727 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
4728 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
4729 adev->gfx.mec.num_queue_per_pipe;
4730
4731 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4732 if (!ptr) {
4733 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
4734 adev->gfx.ip_dump_compute_queues = NULL;
4735 } else {
4736 adev->gfx.ip_dump_compute_queues = ptr;
4737 }
4738
4739 /* Allocate memory for gfx queue registers for all the instances */
4740 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
4741 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
4742 adev->gfx.me.num_queue_per_pipe;
4743
4744 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4745 if (!ptr) {
4746 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
4747 adev->gfx.ip_dump_gfx_queues = NULL;
4748 } else {
4749 adev->gfx.ip_dump_gfx_queues = ptr;
4750 }
4751 }
4752
gfx_v10_0_sw_init(struct amdgpu_ip_block * ip_block)4753 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
4754 {
4755 int i, j, k, r, ring_id = 0;
4756 int xcc_id = 0;
4757 struct amdgpu_device *adev = ip_block->adev;
4758 int num_queue_per_pipe = 1; /* we only enable 1 KGQ per pipe */
4759
4760 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
4761
4762 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4763 case IP_VERSION(10, 1, 10):
4764 case IP_VERSION(10, 1, 1):
4765 case IP_VERSION(10, 1, 2):
4766 case IP_VERSION(10, 1, 3):
4767 case IP_VERSION(10, 1, 4):
4768 adev->gfx.me.num_me = 1;
4769 adev->gfx.me.num_pipe_per_me = 1;
4770 adev->gfx.me.num_queue_per_pipe = 8;
4771 adev->gfx.mec.num_mec = 2;
4772 adev->gfx.mec.num_pipe_per_mec = 4;
4773 adev->gfx.mec.num_queue_per_pipe = 8;
4774 break;
4775 case IP_VERSION(10, 3, 0):
4776 case IP_VERSION(10, 3, 2):
4777 case IP_VERSION(10, 3, 1):
4778 case IP_VERSION(10, 3, 4):
4779 case IP_VERSION(10, 3, 5):
4780 case IP_VERSION(10, 3, 6):
4781 case IP_VERSION(10, 3, 3):
4782 case IP_VERSION(10, 3, 7):
4783 adev->gfx.me.num_me = 1;
4784 adev->gfx.me.num_pipe_per_me = 2;
4785 adev->gfx.me.num_queue_per_pipe = 2;
4786 adev->gfx.mec.num_mec = 2;
4787 adev->gfx.mec.num_pipe_per_mec = 4;
4788 adev->gfx.mec.num_queue_per_pipe = 4;
4789 break;
4790 default:
4791 adev->gfx.me.num_me = 1;
4792 adev->gfx.me.num_pipe_per_me = 1;
4793 adev->gfx.me.num_queue_per_pipe = 1;
4794 adev->gfx.mec.num_mec = 1;
4795 adev->gfx.mec.num_pipe_per_mec = 4;
4796 adev->gfx.mec.num_queue_per_pipe = 8;
4797 break;
4798 }
4799 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4800 case IP_VERSION(10, 1, 10):
4801 case IP_VERSION(10, 1, 1):
4802 case IP_VERSION(10, 1, 2):
4803 adev->gfx.cleaner_shader_ptr = gfx_10_1_10_cleaner_shader_hex;
4804 adev->gfx.cleaner_shader_size = sizeof(gfx_10_1_10_cleaner_shader_hex);
4805 if (adev->gfx.me_fw_version >= 101 &&
4806 adev->gfx.pfp_fw_version >= 158 &&
4807 adev->gfx.mec_fw_version >= 151) {
4808 adev->gfx.enable_cleaner_shader = true;
4809 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4810 if (r) {
4811 adev->gfx.enable_cleaner_shader = false;
4812 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4813 }
4814 }
4815 break;
4816 case IP_VERSION(10, 3, 0):
4817 case IP_VERSION(10, 3, 1):
4818 case IP_VERSION(10, 3, 2):
4819 case IP_VERSION(10, 3, 3):
4820 case IP_VERSION(10, 3, 4):
4821 case IP_VERSION(10, 3, 5):
4822 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4823 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4824 if (adev->gfx.me_fw_version >= 64 &&
4825 adev->gfx.pfp_fw_version >= 100 &&
4826 adev->gfx.mec_fw_version >= 122) {
4827 adev->gfx.enable_cleaner_shader = true;
4828 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4829 if (r) {
4830 adev->gfx.enable_cleaner_shader = false;
4831 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4832 }
4833 }
4834 break;
4835 case IP_VERSION(10, 3, 6):
4836 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4837 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4838 if (adev->gfx.me_fw_version >= 14 &&
4839 adev->gfx.pfp_fw_version >= 17 &&
4840 adev->gfx.mec_fw_version >= 24) {
4841 adev->gfx.enable_cleaner_shader = true;
4842 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4843 if (r) {
4844 adev->gfx.enable_cleaner_shader = false;
4845 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4846 }
4847 }
4848 break;
4849 case IP_VERSION(10, 3, 7):
4850 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4851 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4852 if (adev->gfx.me_fw_version >= 4 &&
4853 adev->gfx.pfp_fw_version >= 9 &&
4854 adev->gfx.mec_fw_version >= 12) {
4855 adev->gfx.enable_cleaner_shader = true;
4856 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4857 if (r) {
4858 adev->gfx.enable_cleaner_shader = false;
4859 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4860 }
4861 }
4862 break;
4863 default:
4864 adev->gfx.enable_cleaner_shader = false;
4865 break;
4866 }
4867
4868 /* KIQ event */
4869 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4870 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4871 &adev->gfx.kiq[0].irq);
4872 if (r)
4873 return r;
4874
4875 /* EOP Event */
4876 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4877 GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4878 &adev->gfx.eop_irq);
4879 if (r)
4880 return r;
4881
4882 /* Bad opcode Event */
4883 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4884 GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
4885 &adev->gfx.bad_op_irq);
4886 if (r)
4887 return r;
4888
4889 /* Privileged reg */
4890 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4891 &adev->gfx.priv_reg_irq);
4892 if (r)
4893 return r;
4894
4895 /* Privileged inst */
4896 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4897 &adev->gfx.priv_inst_irq);
4898 if (r)
4899 return r;
4900
4901 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4902
4903 gfx_v10_0_me_init(adev);
4904
4905 if (adev->gfx.rlc.funcs) {
4906 if (adev->gfx.rlc.funcs->init) {
4907 r = adev->gfx.rlc.funcs->init(adev);
4908 if (r) {
4909 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4910 return r;
4911 }
4912 }
4913 }
4914
4915 r = gfx_v10_0_mec_init(adev);
4916 if (r) {
4917 DRM_ERROR("Failed to init MEC BOs!\n");
4918 return r;
4919 }
4920
4921 /* set up the gfx ring */
4922 for (i = 0; i < adev->gfx.me.num_me; i++) {
4923 for (j = 0; j < num_queue_per_pipe; j++) {
4924 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4925 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4926 continue;
4927
4928 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4929 i, k, j);
4930 if (r)
4931 return r;
4932 ring_id++;
4933 }
4934 }
4935 }
4936
4937 ring_id = 0;
4938 /* set up the compute queues - allocate horizontally across pipes */
4939 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4940 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4941 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4942 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4943 k, j))
4944 continue;
4945
4946 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4947 i, k, j);
4948 if (r)
4949 return r;
4950
4951 ring_id++;
4952 }
4953 }
4954 }
4955 /* TODO: Add queue reset mask when FW fully supports it */
4956 adev->gfx.gfx_supported_reset =
4957 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
4958 adev->gfx.compute_supported_reset =
4959 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4960
4961 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4962 if (r) {
4963 DRM_ERROR("Failed to init KIQ BOs!\n");
4964 return r;
4965 }
4966
4967 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4968 if (r)
4969 return r;
4970
4971 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4972 if (r)
4973 return r;
4974
4975 /* allocate visible FB for rlc auto-loading fw */
4976 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4977 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4978 if (r)
4979 return r;
4980 }
4981
4982 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4983
4984 gfx_v10_0_gpu_early_init(adev);
4985
4986 gfx_v10_0_alloc_ip_dump(adev);
4987
4988 r = amdgpu_gfx_sysfs_init(adev);
4989 if (r)
4990 return r;
4991
4992 return 0;
4993 }
4994
gfx_v10_0_pfp_fini(struct amdgpu_device * adev)4995 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4996 {
4997 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4998 &adev->gfx.pfp.pfp_fw_gpu_addr,
4999 (void **)&adev->gfx.pfp.pfp_fw_ptr);
5000 }
5001
gfx_v10_0_ce_fini(struct amdgpu_device * adev)5002 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
5003 {
5004 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
5005 &adev->gfx.ce.ce_fw_gpu_addr,
5006 (void **)&adev->gfx.ce.ce_fw_ptr);
5007 }
5008
gfx_v10_0_me_fini(struct amdgpu_device * adev)5009 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
5010 {
5011 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
5012 &adev->gfx.me.me_fw_gpu_addr,
5013 (void **)&adev->gfx.me.me_fw_ptr);
5014 }
5015
gfx_v10_0_sw_fini(struct amdgpu_ip_block * ip_block)5016 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
5017 {
5018 int i;
5019 struct amdgpu_device *adev = ip_block->adev;
5020
5021 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5022 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
5023 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5024 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
5025
5026 amdgpu_gfx_mqd_sw_fini(adev, 0);
5027
5028 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
5029 amdgpu_gfx_kiq_fini(adev, 0);
5030
5031 amdgpu_gfx_cleaner_shader_sw_fini(adev);
5032
5033 gfx_v10_0_pfp_fini(adev);
5034 gfx_v10_0_ce_fini(adev);
5035 gfx_v10_0_me_fini(adev);
5036 gfx_v10_0_rlc_fini(adev);
5037 gfx_v10_0_mec_fini(adev);
5038
5039 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5040 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5041
5042 gfx_v10_0_free_microcode(adev);
5043 amdgpu_gfx_sysfs_fini(adev);
5044
5045 kfree(adev->gfx.ip_dump_core);
5046 kfree(adev->gfx.ip_dump_compute_queues);
5047 kfree(adev->gfx.ip_dump_gfx_queues);
5048
5049 return 0;
5050 }
5051
gfx_v10_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)5052 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5053 u32 sh_num, u32 instance, int xcc_id)
5054 {
5055 u32 data;
5056
5057 if (instance == 0xffffffff)
5058 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5059 INSTANCE_BROADCAST_WRITES, 1);
5060 else
5061 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5062 instance);
5063
5064 if (se_num == 0xffffffff)
5065 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5066 1);
5067 else
5068 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5069
5070 if (sh_num == 0xffffffff)
5071 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5072 1);
5073 else
5074 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5075
5076 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5077 }
5078
gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device * adev)5079 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5080 {
5081 u32 data, mask;
5082
5083 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5084 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5085
5086 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5087 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5088
5089 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5090 adev->gfx.config.max_sh_per_se);
5091
5092 return (~data) & mask;
5093 }
5094
gfx_v10_0_setup_rb(struct amdgpu_device * adev)5095 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5096 {
5097 int i, j;
5098 u32 data;
5099 u32 active_rbs = 0;
5100 u32 bitmap;
5101 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5102 adev->gfx.config.max_sh_per_se;
5103
5104 mutex_lock(&adev->grbm_idx_mutex);
5105 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5106 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5107 bitmap = i * adev->gfx.config.max_sh_per_se + j;
5108 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
5109 IP_VERSION(10, 3, 0)) ||
5110 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5111 IP_VERSION(10, 3, 3)) ||
5112 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5113 IP_VERSION(10, 3, 6))) &&
5114 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5115 continue;
5116 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5117 data = gfx_v10_0_get_rb_active_bitmap(adev);
5118 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5119 rb_bitmap_width_per_sh);
5120 }
5121 }
5122 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5123 mutex_unlock(&adev->grbm_idx_mutex);
5124
5125 adev->gfx.config.backend_enable_mask = active_rbs;
5126 adev->gfx.config.num_rbs = hweight32(active_rbs);
5127 }
5128
gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device * adev)5129 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5130 {
5131 uint32_t num_sc;
5132 uint32_t enabled_rb_per_sh;
5133 uint32_t active_rb_bitmap;
5134 uint32_t num_rb_per_sc;
5135 uint32_t num_packer_per_sc;
5136 uint32_t pa_sc_tile_steering_override;
5137
5138 /* for ASICs that integrates GFX v10.3
5139 * pa_sc_tile_steering_override should be set to 0
5140 */
5141 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
5142 return 0;
5143
5144 /* init num_sc */
5145 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5146 adev->gfx.config.num_sc_per_sh;
5147 /* init num_rb_per_sc */
5148 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5149 enabled_rb_per_sh = hweight32(active_rb_bitmap);
5150 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5151 /* init num_packer_per_sc */
5152 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5153
5154 pa_sc_tile_steering_override = 0;
5155 pa_sc_tile_steering_override |=
5156 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5157 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5158 pa_sc_tile_steering_override |=
5159 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5160 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5161 pa_sc_tile_steering_override |=
5162 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5163 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5164
5165 return pa_sc_tile_steering_override;
5166 }
5167
5168 #define DEFAULT_SH_MEM_BASES (0x6000)
5169
gfx_v10_0_debug_trap_config_init(struct amdgpu_device * adev,uint32_t first_vmid,uint32_t last_vmid)5170 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
5171 uint32_t first_vmid,
5172 uint32_t last_vmid)
5173 {
5174 uint32_t data;
5175 uint32_t trap_config_vmid_mask = 0;
5176 int i;
5177
5178 /* Calculate trap config vmid mask */
5179 for (i = first_vmid; i < last_vmid; i++)
5180 trap_config_vmid_mask |= (1 << i);
5181
5182 data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
5183 VMID_SEL, trap_config_vmid_mask);
5184 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
5185 TRAP_EN, 1);
5186 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
5187 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
5188
5189 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
5190 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
5191 }
5192
gfx_v10_0_init_compute_vmid(struct amdgpu_device * adev)5193 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5194 {
5195 int i;
5196 uint32_t sh_mem_bases;
5197
5198 /*
5199 * Configure apertures:
5200 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
5201 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
5202 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
5203 */
5204 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5205
5206 mutex_lock(&adev->srbm_mutex);
5207 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5208 nv_grbm_select(adev, 0, 0, 0, i);
5209 /* CP and shaders */
5210 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5211 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5212 }
5213 nv_grbm_select(adev, 0, 0, 0, 0);
5214 mutex_unlock(&adev->srbm_mutex);
5215
5216 /*
5217 * Initialize all compute VMIDs to have no GDS, GWS, or OA
5218 * access. These should be enabled by FW for target VMIDs.
5219 */
5220 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5221 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5222 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5223 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5224 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5225 }
5226
5227 gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
5228 AMDGPU_NUM_VMID);
5229 }
5230
gfx_v10_0_init_gds_vmid(struct amdgpu_device * adev)5231 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5232 {
5233 int vmid;
5234
5235 /*
5236 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5237 * access. Compute VMIDs should be enabled by FW for target VMIDs,
5238 * the driver can enable them for graphics. VMID0 should maintain
5239 * access so that HWS firmware can save/restore entries.
5240 */
5241 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5242 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5243 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5244 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5245 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5246 }
5247 }
5248
5249
gfx_v10_0_tcp_harvest(struct amdgpu_device * adev)5250 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5251 {
5252 int i, j, k;
5253 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5254 u32 tmp, wgp_active_bitmap = 0;
5255 u32 gcrd_targets_disable_tcp = 0;
5256 u32 utcl_invreq_disable = 0;
5257 /*
5258 * GCRD_TARGETS_DISABLE field contains
5259 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5260 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5261 */
5262 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5263 2 * max_wgp_per_sh + /* TCP */
5264 max_wgp_per_sh + /* SQC */
5265 4); /* GL1C */
5266 /*
5267 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5268 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5269 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5270 */
5271 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5272 2 * max_wgp_per_sh + /* TCP */
5273 2 * max_wgp_per_sh + /* SQC */
5274 4 + /* RMI */
5275 1); /* SQG */
5276
5277 mutex_lock(&adev->grbm_idx_mutex);
5278 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5279 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5280 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5281 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5282 /*
5283 * Set corresponding TCP bits for the inactive WGPs in
5284 * GCRD_SA_TARGETS_DISABLE
5285 */
5286 gcrd_targets_disable_tcp = 0;
5287 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5288 utcl_invreq_disable = 0;
5289
5290 for (k = 0; k < max_wgp_per_sh; k++) {
5291 if (!(wgp_active_bitmap & (1 << k))) {
5292 gcrd_targets_disable_tcp |= 3 << (2 * k);
5293 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5294 utcl_invreq_disable |= (3 << (2 * k)) |
5295 (3 << (2 * (max_wgp_per_sh + k)));
5296 }
5297 }
5298
5299 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5300 /* only override TCP & SQC bits */
5301 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5302 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5303 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5304
5305 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5306 /* only override TCP & SQC bits */
5307 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5308 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5309 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5310 }
5311 }
5312
5313 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5314 mutex_unlock(&adev->grbm_idx_mutex);
5315 }
5316
gfx_v10_0_get_tcc_info(struct amdgpu_device * adev)5317 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5318 {
5319 /* TCCs are global (not instanced). */
5320 uint32_t tcc_disable;
5321
5322 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5323 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5324 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5325 } else {
5326 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5327 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5328 }
5329
5330 adev->gfx.config.tcc_disabled_mask =
5331 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5332 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5333 }
5334
gfx_v10_0_constants_init(struct amdgpu_device * adev)5335 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5336 {
5337 u32 tmp;
5338 int i;
5339
5340 if (!amdgpu_sriov_vf(adev))
5341 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5342
5343 gfx_v10_0_setup_rb(adev);
5344 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5345 gfx_v10_0_get_tcc_info(adev);
5346 adev->gfx.config.pa_sc_tile_steering_override =
5347 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5348
5349 /* XXX SH_MEM regs */
5350 /* where to put LDS, scratch, GPUVM in FSA64 space */
5351 mutex_lock(&adev->srbm_mutex);
5352 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5353 nv_grbm_select(adev, 0, 0, 0, i);
5354 /* CP and shaders */
5355 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5356 if (i != 0) {
5357 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5358 (adev->gmc.private_aperture_start >> 48));
5359 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5360 (adev->gmc.shared_aperture_start >> 48));
5361 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5362 }
5363 }
5364 nv_grbm_select(adev, 0, 0, 0, 0);
5365
5366 mutex_unlock(&adev->srbm_mutex);
5367
5368 gfx_v10_0_init_compute_vmid(adev);
5369 gfx_v10_0_init_gds_vmid(adev);
5370
5371 }
5372
gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device * adev,int me,int pipe)5373 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
5374 int me, int pipe)
5375 {
5376 if (me != 0)
5377 return 0;
5378
5379 switch (pipe) {
5380 case 0:
5381 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
5382 case 1:
5383 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
5384 default:
5385 return 0;
5386 }
5387 }
5388
gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device * adev,int me,int pipe)5389 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
5390 int me, int pipe)
5391 {
5392 /*
5393 * amdgpu controls only the first MEC. That's why this function only
5394 * handles the setting of interrupts for this specific MEC. All other
5395 * pipes' interrupts are set by amdkfd.
5396 */
5397 if (me != 1)
5398 return 0;
5399
5400 switch (pipe) {
5401 case 0:
5402 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5403 case 1:
5404 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5405 case 2:
5406 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5407 case 3:
5408 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5409 default:
5410 return 0;
5411 }
5412 }
5413
gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)5414 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5415 bool enable)
5416 {
5417 u32 tmp, cp_int_cntl_reg;
5418 int i, j;
5419
5420 if (amdgpu_sriov_vf(adev))
5421 return;
5422
5423 for (i = 0; i < adev->gfx.me.num_me; i++) {
5424 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5425 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
5426
5427 if (cp_int_cntl_reg) {
5428 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5429 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5430 enable ? 1 : 0);
5431 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5432 enable ? 1 : 0);
5433 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5434 enable ? 1 : 0);
5435 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5436 enable ? 1 : 0);
5437 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
5438 }
5439 }
5440 }
5441 }
5442
gfx_v10_0_init_csb(struct amdgpu_device * adev)5443 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5444 {
5445 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5446
5447 /* csib */
5448 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5449 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5450 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5451 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5452 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5453 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5454 } else {
5455 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5456 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5457 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5458 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5459 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5460 }
5461 return 0;
5462 }
5463
gfx_v10_0_rlc_stop(struct amdgpu_device * adev)5464 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5465 {
5466 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5467
5468 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5469 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5470 }
5471
gfx_v10_0_rlc_reset(struct amdgpu_device * adev)5472 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5473 {
5474 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5475 udelay(50);
5476 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5477 udelay(50);
5478 }
5479
gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)5480 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5481 bool enable)
5482 {
5483 uint32_t rlc_pg_cntl;
5484
5485 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5486
5487 if (!enable) {
5488 /* RLC_PG_CNTL[23] = 0 (default)
5489 * RLC will wait for handshake acks with SMU
5490 * GFXOFF will be enabled
5491 * RLC_PG_CNTL[23] = 1
5492 * RLC will not issue any message to SMU
5493 * hence no handshake between SMU & RLC
5494 * GFXOFF will be disabled
5495 */
5496 rlc_pg_cntl |= 0x800000;
5497 } else
5498 rlc_pg_cntl &= ~0x800000;
5499 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5500 }
5501
gfx_v10_0_rlc_start(struct amdgpu_device * adev)5502 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5503 {
5504 /*
5505 * TODO: enable rlc & smu handshake until smu
5506 * and gfxoff feature works as expected
5507 */
5508 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5509 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5510
5511 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5512 udelay(50);
5513 }
5514
gfx_v10_0_rlc_enable_srm(struct amdgpu_device * adev)5515 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5516 {
5517 uint32_t tmp;
5518
5519 /* enable Save Restore Machine */
5520 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5521 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5522 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5523 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5524 }
5525
gfx_v10_0_rlc_load_microcode(struct amdgpu_device * adev)5526 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5527 {
5528 const struct rlc_firmware_header_v2_0 *hdr;
5529 const __le32 *fw_data;
5530 unsigned int i, fw_size;
5531
5532 if (!adev->gfx.rlc_fw)
5533 return -EINVAL;
5534
5535 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5536 amdgpu_ucode_print_rlc_hdr(&hdr->header);
5537
5538 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5539 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5540 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5541
5542 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5543 RLCG_UCODE_LOADING_START_ADDRESS);
5544
5545 for (i = 0; i < fw_size; i++)
5546 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5547 le32_to_cpup(fw_data++));
5548
5549 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5550
5551 return 0;
5552 }
5553
gfx_v10_0_rlc_resume(struct amdgpu_device * adev)5554 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5555 {
5556 int r;
5557
5558 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5559 adev->psp.autoload_supported) {
5560
5561 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5562 if (r)
5563 return r;
5564
5565 gfx_v10_0_init_csb(adev);
5566
5567 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5568
5569 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5570 gfx_v10_0_rlc_enable_srm(adev);
5571 } else {
5572 if (amdgpu_sriov_vf(adev)) {
5573 gfx_v10_0_init_csb(adev);
5574 return 0;
5575 }
5576
5577 adev->gfx.rlc.funcs->stop(adev);
5578
5579 /* disable CG */
5580 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5581
5582 /* disable PG */
5583 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5584
5585 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5586 /* legacy rlc firmware loading */
5587 r = gfx_v10_0_rlc_load_microcode(adev);
5588 if (r)
5589 return r;
5590 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5591 /* rlc backdoor autoload firmware */
5592 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5593 if (r)
5594 return r;
5595 }
5596
5597 gfx_v10_0_init_csb(adev);
5598
5599 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5600
5601 adev->gfx.rlc.funcs->start(adev);
5602
5603 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5604 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5605 if (r)
5606 return r;
5607 }
5608 }
5609
5610 return 0;
5611 }
5612
5613 static struct {
5614 FIRMWARE_ID id;
5615 unsigned int offset;
5616 unsigned int size;
5617 } rlc_autoload_info[FIRMWARE_ID_MAX];
5618
gfx_v10_0_parse_rlc_toc(struct amdgpu_device * adev)5619 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5620 {
5621 int ret;
5622 RLC_TABLE_OF_CONTENT *rlc_toc;
5623
5624 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5625 AMDGPU_GEM_DOMAIN_GTT,
5626 &adev->gfx.rlc.rlc_toc_bo,
5627 &adev->gfx.rlc.rlc_toc_gpu_addr,
5628 (void **)&adev->gfx.rlc.rlc_toc_buf);
5629 if (ret) {
5630 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5631 return ret;
5632 }
5633
5634 /* Copy toc from psp sos fw to rlc toc buffer */
5635 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5636
5637 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5638 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5639 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5640 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5641 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5642 /* Offset needs 4KB alignment */
5643 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5644 }
5645
5646 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5647 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5648 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5649
5650 rlc_toc++;
5651 }
5652
5653 return 0;
5654 }
5655
gfx_v10_0_calc_toc_total_size(struct amdgpu_device * adev)5656 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5657 {
5658 uint32_t total_size = 0;
5659 FIRMWARE_ID id;
5660 int ret;
5661
5662 ret = gfx_v10_0_parse_rlc_toc(adev);
5663 if (ret) {
5664 dev_err(adev->dev, "failed to parse rlc toc\n");
5665 return 0;
5666 }
5667
5668 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5669 total_size += rlc_autoload_info[id].size;
5670
5671 /* In case the offset in rlc toc ucode is aligned */
5672 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5673 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5674 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5675
5676 return total_size;
5677 }
5678
gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device * adev)5679 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5680 {
5681 int r;
5682 uint32_t total_size;
5683
5684 total_size = gfx_v10_0_calc_toc_total_size(adev);
5685
5686 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5687 AMDGPU_GEM_DOMAIN_GTT,
5688 &adev->gfx.rlc.rlc_autoload_bo,
5689 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5690 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5691 if (r) {
5692 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5693 return r;
5694 }
5695
5696 return 0;
5697 }
5698
gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device * adev)5699 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5700 {
5701 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5702 &adev->gfx.rlc.rlc_toc_gpu_addr,
5703 (void **)&adev->gfx.rlc.rlc_toc_buf);
5704 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5705 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5706 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5707 }
5708
gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)5709 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5710 FIRMWARE_ID id,
5711 const void *fw_data,
5712 uint32_t fw_size)
5713 {
5714 uint32_t toc_offset;
5715 uint32_t toc_fw_size;
5716 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5717
5718 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5719 return;
5720
5721 toc_offset = rlc_autoload_info[id].offset;
5722 toc_fw_size = rlc_autoload_info[id].size;
5723
5724 if (fw_size == 0)
5725 fw_size = toc_fw_size;
5726
5727 if (fw_size > toc_fw_size)
5728 fw_size = toc_fw_size;
5729
5730 memcpy(ptr + toc_offset, fw_data, fw_size);
5731
5732 if (fw_size < toc_fw_size)
5733 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5734 }
5735
gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)5736 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5737 {
5738 void *data;
5739 uint32_t size;
5740
5741 data = adev->gfx.rlc.rlc_toc_buf;
5742 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5743
5744 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5745 FIRMWARE_ID_RLC_TOC,
5746 data, size);
5747 }
5748
gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)5749 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5750 {
5751 const __le32 *fw_data;
5752 uint32_t fw_size;
5753 const struct gfx_firmware_header_v1_0 *cp_hdr;
5754 const struct rlc_firmware_header_v2_0 *rlc_hdr;
5755
5756 /* pfp ucode */
5757 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5758 adev->gfx.pfp_fw->data;
5759 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5760 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5761 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5762 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5763 FIRMWARE_ID_CP_PFP,
5764 fw_data, fw_size);
5765
5766 /* ce ucode */
5767 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5768 adev->gfx.ce_fw->data;
5769 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5770 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5771 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5772 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5773 FIRMWARE_ID_CP_CE,
5774 fw_data, fw_size);
5775
5776 /* me ucode */
5777 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5778 adev->gfx.me_fw->data;
5779 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5780 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5781 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5782 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5783 FIRMWARE_ID_CP_ME,
5784 fw_data, fw_size);
5785
5786 /* rlc ucode */
5787 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5788 adev->gfx.rlc_fw->data;
5789 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5790 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5791 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5792 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5793 FIRMWARE_ID_RLC_G_UCODE,
5794 fw_data, fw_size);
5795
5796 /* mec1 ucode */
5797 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5798 adev->gfx.mec_fw->data;
5799 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5800 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5801 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5802 cp_hdr->jt_size * 4;
5803 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5804 FIRMWARE_ID_CP_MEC,
5805 fw_data, fw_size);
5806 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5807 }
5808
5809 /* Temporarily put sdma part here */
gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)5810 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5811 {
5812 const __le32 *fw_data;
5813 uint32_t fw_size;
5814 const struct sdma_firmware_header_v1_0 *sdma_hdr;
5815 int i;
5816
5817 for (i = 0; i < adev->sdma.num_instances; i++) {
5818 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5819 adev->sdma.instance[i].fw->data;
5820 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5821 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5822 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5823
5824 if (i == 0) {
5825 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5826 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5827 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5828 FIRMWARE_ID_SDMA0_JT,
5829 (uint32_t *)fw_data +
5830 sdma_hdr->jt_offset,
5831 sdma_hdr->jt_size * 4);
5832 } else if (i == 1) {
5833 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5834 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5835 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5836 FIRMWARE_ID_SDMA1_JT,
5837 (uint32_t *)fw_data +
5838 sdma_hdr->jt_offset,
5839 sdma_hdr->jt_size * 4);
5840 }
5841 }
5842 }
5843
gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)5844 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5845 {
5846 uint32_t rlc_g_offset, rlc_g_size, tmp;
5847 uint64_t gpu_addr;
5848
5849 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5850 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5851 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5852
5853 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5854 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5855 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5856
5857 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5858 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5859 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5860
5861 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5862 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5863 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5864 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5865 return -EINVAL;
5866 }
5867
5868 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5869 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5870 DRM_ERROR("RLC ROM should halt itself\n");
5871 return -EINVAL;
5872 }
5873
5874 return 0;
5875 }
5876
gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device * adev)5877 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5878 {
5879 uint32_t usec_timeout = 50000; /* wait for 50ms */
5880 uint32_t tmp;
5881 int i;
5882 uint64_t addr;
5883
5884 /* Trigger an invalidation of the L1 instruction caches */
5885 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5886 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5887 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5888
5889 /* Wait for invalidation complete */
5890 for (i = 0; i < usec_timeout; i++) {
5891 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5892 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5893 INVALIDATE_CACHE_COMPLETE))
5894 break;
5895 udelay(1);
5896 }
5897
5898 if (i >= usec_timeout) {
5899 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5900 return -EINVAL;
5901 }
5902
5903 /* Program me ucode address into intruction cache address register */
5904 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5905 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5906 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5907 lower_32_bits(addr) & 0xFFFFF000);
5908 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5909 upper_32_bits(addr));
5910
5911 return 0;
5912 }
5913
gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device * adev)5914 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5915 {
5916 uint32_t usec_timeout = 50000; /* wait for 50ms */
5917 uint32_t tmp;
5918 int i;
5919 uint64_t addr;
5920
5921 /* Trigger an invalidation of the L1 instruction caches */
5922 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5923 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5924 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5925
5926 /* Wait for invalidation complete */
5927 for (i = 0; i < usec_timeout; i++) {
5928 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5929 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5930 INVALIDATE_CACHE_COMPLETE))
5931 break;
5932 udelay(1);
5933 }
5934
5935 if (i >= usec_timeout) {
5936 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5937 return -EINVAL;
5938 }
5939
5940 /* Program ce ucode address into intruction cache address register */
5941 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5942 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5943 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5944 lower_32_bits(addr) & 0xFFFFF000);
5945 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5946 upper_32_bits(addr));
5947
5948 return 0;
5949 }
5950
gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device * adev)5951 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5952 {
5953 uint32_t usec_timeout = 50000; /* wait for 50ms */
5954 uint32_t tmp;
5955 int i;
5956 uint64_t addr;
5957
5958 /* Trigger an invalidation of the L1 instruction caches */
5959 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5960 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5961 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5962
5963 /* Wait for invalidation complete */
5964 for (i = 0; i < usec_timeout; i++) {
5965 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5966 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5967 INVALIDATE_CACHE_COMPLETE))
5968 break;
5969 udelay(1);
5970 }
5971
5972 if (i >= usec_timeout) {
5973 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5974 return -EINVAL;
5975 }
5976
5977 /* Program pfp ucode address into intruction cache address register */
5978 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5979 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5980 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5981 lower_32_bits(addr) & 0xFFFFF000);
5982 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5983 upper_32_bits(addr));
5984
5985 return 0;
5986 }
5987
gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device * adev)5988 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5989 {
5990 uint32_t usec_timeout = 50000; /* wait for 50ms */
5991 uint32_t tmp;
5992 int i;
5993 uint64_t addr;
5994
5995 /* Trigger an invalidation of the L1 instruction caches */
5996 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5997 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5998 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5999
6000 /* Wait for invalidation complete */
6001 for (i = 0; i < usec_timeout; i++) {
6002 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6003 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6004 INVALIDATE_CACHE_COMPLETE))
6005 break;
6006 udelay(1);
6007 }
6008
6009 if (i >= usec_timeout) {
6010 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6011 return -EINVAL;
6012 }
6013
6014 /* Program mec1 ucode address into intruction cache address register */
6015 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
6016 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
6017 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
6018 lower_32_bits(addr) & 0xFFFFF000);
6019 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6020 upper_32_bits(addr));
6021
6022 return 0;
6023 }
6024
gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)6025 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
6026 {
6027 uint32_t cp_status;
6028 uint32_t bootload_status;
6029 int i, r;
6030
6031 for (i = 0; i < adev->usec_timeout; i++) {
6032 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
6033 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
6034 if ((cp_status == 0) &&
6035 (REG_GET_FIELD(bootload_status,
6036 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
6037 break;
6038 }
6039 udelay(1);
6040 }
6041
6042 if (i >= adev->usec_timeout) {
6043 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
6044 return -ETIMEDOUT;
6045 }
6046
6047 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
6048 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
6049 if (r)
6050 return r;
6051
6052 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
6053 if (r)
6054 return r;
6055
6056 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
6057 if (r)
6058 return r;
6059
6060 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
6061 if (r)
6062 return r;
6063 }
6064
6065 return 0;
6066 }
6067
gfx_v10_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)6068 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
6069 {
6070 int i;
6071 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
6072
6073 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
6074 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
6075 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
6076
6077 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
6078 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
6079 else
6080 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
6081
6082 if (amdgpu_in_reset(adev) && !enable)
6083 return 0;
6084
6085 for (i = 0; i < adev->usec_timeout; i++) {
6086 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
6087 break;
6088 udelay(1);
6089 }
6090
6091 if (i >= adev->usec_timeout)
6092 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
6093
6094 return 0;
6095 }
6096
gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device * adev)6097 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
6098 {
6099 int r;
6100 const struct gfx_firmware_header_v1_0 *pfp_hdr;
6101 const __le32 *fw_data;
6102 unsigned int i, fw_size;
6103 uint32_t tmp;
6104 uint32_t usec_timeout = 50000; /* wait for 50ms */
6105
6106 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
6107 adev->gfx.pfp_fw->data;
6108
6109 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
6110
6111 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6112 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6113 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6114
6115 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6116 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6117 &adev->gfx.pfp.pfp_fw_obj,
6118 &adev->gfx.pfp.pfp_fw_gpu_addr,
6119 (void **)&adev->gfx.pfp.pfp_fw_ptr);
6120 if (r) {
6121 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6122 gfx_v10_0_pfp_fini(adev);
6123 return r;
6124 }
6125
6126 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6127
6128 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6129 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6130
6131 /* Trigger an invalidation of the L1 instruction caches */
6132 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6133 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6134 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6135
6136 /* Wait for invalidation complete */
6137 for (i = 0; i < usec_timeout; i++) {
6138 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6139 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6140 INVALIDATE_CACHE_COMPLETE))
6141 break;
6142 udelay(1);
6143 }
6144
6145 if (i >= usec_timeout) {
6146 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6147 return -EINVAL;
6148 }
6149
6150 if (amdgpu_emu_mode == 1)
6151 amdgpu_device_flush_hdp(adev, NULL);
6152
6153 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6154 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6155 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6156 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6157 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6158 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6159 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6160 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6161 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6162 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6163
6164 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6165
6166 for (i = 0; i < pfp_hdr->jt_size; i++)
6167 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6168 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6169
6170 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6171
6172 return 0;
6173 }
6174
gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device * adev)6175 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6176 {
6177 int r;
6178 const struct gfx_firmware_header_v1_0 *ce_hdr;
6179 const __le32 *fw_data;
6180 unsigned int i, fw_size;
6181 uint32_t tmp;
6182 uint32_t usec_timeout = 50000; /* wait for 50ms */
6183
6184 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6185 adev->gfx.ce_fw->data;
6186
6187 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6188
6189 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6190 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6191 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6192
6193 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6194 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6195 &adev->gfx.ce.ce_fw_obj,
6196 &adev->gfx.ce.ce_fw_gpu_addr,
6197 (void **)&adev->gfx.ce.ce_fw_ptr);
6198 if (r) {
6199 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6200 gfx_v10_0_ce_fini(adev);
6201 return r;
6202 }
6203
6204 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6205
6206 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6207 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6208
6209 /* Trigger an invalidation of the L1 instruction caches */
6210 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6211 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6212 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6213
6214 /* Wait for invalidation complete */
6215 for (i = 0; i < usec_timeout; i++) {
6216 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6217 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6218 INVALIDATE_CACHE_COMPLETE))
6219 break;
6220 udelay(1);
6221 }
6222
6223 if (i >= usec_timeout) {
6224 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6225 return -EINVAL;
6226 }
6227
6228 if (amdgpu_emu_mode == 1)
6229 amdgpu_device_flush_hdp(adev, NULL);
6230
6231 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6232 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6233 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6234 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6235 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6236 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6237 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6238 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6239 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6240
6241 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6242
6243 for (i = 0; i < ce_hdr->jt_size; i++)
6244 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6245 le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6246
6247 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6248
6249 return 0;
6250 }
6251
gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device * adev)6252 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6253 {
6254 int r;
6255 const struct gfx_firmware_header_v1_0 *me_hdr;
6256 const __le32 *fw_data;
6257 unsigned int i, fw_size;
6258 uint32_t tmp;
6259 uint32_t usec_timeout = 50000; /* wait for 50ms */
6260
6261 me_hdr = (const struct gfx_firmware_header_v1_0 *)
6262 adev->gfx.me_fw->data;
6263
6264 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6265
6266 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6267 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6268 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6269
6270 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6271 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6272 &adev->gfx.me.me_fw_obj,
6273 &adev->gfx.me.me_fw_gpu_addr,
6274 (void **)&adev->gfx.me.me_fw_ptr);
6275 if (r) {
6276 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6277 gfx_v10_0_me_fini(adev);
6278 return r;
6279 }
6280
6281 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6282
6283 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6284 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6285
6286 /* Trigger an invalidation of the L1 instruction caches */
6287 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6288 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6289 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6290
6291 /* Wait for invalidation complete */
6292 for (i = 0; i < usec_timeout; i++) {
6293 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6294 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6295 INVALIDATE_CACHE_COMPLETE))
6296 break;
6297 udelay(1);
6298 }
6299
6300 if (i >= usec_timeout) {
6301 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6302 return -EINVAL;
6303 }
6304
6305 if (amdgpu_emu_mode == 1)
6306 amdgpu_device_flush_hdp(adev, NULL);
6307
6308 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6309 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6310 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6311 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6312 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6313 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6314 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6315 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6316 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6317
6318 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6319
6320 for (i = 0; i < me_hdr->jt_size; i++)
6321 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6322 le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6323
6324 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6325
6326 return 0;
6327 }
6328
gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device * adev)6329 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6330 {
6331 int r;
6332
6333 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6334 return -EINVAL;
6335
6336 gfx_v10_0_cp_gfx_enable(adev, false);
6337
6338 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6339 if (r) {
6340 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6341 return r;
6342 }
6343
6344 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6345 if (r) {
6346 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6347 return r;
6348 }
6349
6350 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6351 if (r) {
6352 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6353 return r;
6354 }
6355
6356 return 0;
6357 }
6358
gfx_v10_0_cp_gfx_start(struct amdgpu_device * adev)6359 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6360 {
6361 struct amdgpu_ring *ring;
6362 const struct cs_section_def *sect = NULL;
6363 const struct cs_extent_def *ext = NULL;
6364 int r, i;
6365 int ctx_reg_offset;
6366
6367 /* init the CP */
6368 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6369 adev->gfx.config.max_hw_contexts - 1);
6370 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6371
6372 gfx_v10_0_cp_gfx_enable(adev, true);
6373
6374 ring = &adev->gfx.gfx_ring[0];
6375 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6376 if (r) {
6377 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6378 return r;
6379 }
6380
6381 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6382 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6383
6384 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6385 amdgpu_ring_write(ring, 0x80000000);
6386 amdgpu_ring_write(ring, 0x80000000);
6387
6388 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6389 for (ext = sect->section; ext->extent != NULL; ++ext) {
6390 if (sect->id == SECT_CONTEXT) {
6391 amdgpu_ring_write(ring,
6392 PACKET3(PACKET3_SET_CONTEXT_REG,
6393 ext->reg_count));
6394 amdgpu_ring_write(ring, ext->reg_index -
6395 PACKET3_SET_CONTEXT_REG_START);
6396 for (i = 0; i < ext->reg_count; i++)
6397 amdgpu_ring_write(ring, ext->extent[i]);
6398 }
6399 }
6400 }
6401
6402 ctx_reg_offset =
6403 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6404 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6405 amdgpu_ring_write(ring, ctx_reg_offset);
6406 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6407
6408 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6409 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6410
6411 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6412 amdgpu_ring_write(ring, 0);
6413
6414 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6415 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6416 amdgpu_ring_write(ring, 0x8000);
6417 amdgpu_ring_write(ring, 0x8000);
6418
6419 amdgpu_ring_commit(ring);
6420
6421 /* submit cs packet to copy state 0 to next available state */
6422 if (adev->gfx.num_gfx_rings > 1) {
6423 /* maximum supported gfx ring is 2 */
6424 ring = &adev->gfx.gfx_ring[1];
6425 r = amdgpu_ring_alloc(ring, 2);
6426 if (r) {
6427 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6428 return r;
6429 }
6430
6431 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6432 amdgpu_ring_write(ring, 0);
6433
6434 amdgpu_ring_commit(ring);
6435 }
6436 return 0;
6437 }
6438
gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)6439 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6440 CP_PIPE_ID pipe)
6441 {
6442 u32 tmp;
6443
6444 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6445 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6446
6447 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6448 }
6449
gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)6450 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6451 struct amdgpu_ring *ring)
6452 {
6453 u32 tmp;
6454
6455 if (!amdgpu_async_gfx_ring) {
6456 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6457 if (ring->use_doorbell) {
6458 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6459 DOORBELL_OFFSET, ring->doorbell_index);
6460 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6461 DOORBELL_EN, 1);
6462 } else {
6463 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6464 DOORBELL_EN, 0);
6465 }
6466 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6467 }
6468 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6469 case IP_VERSION(10, 3, 0):
6470 case IP_VERSION(10, 3, 2):
6471 case IP_VERSION(10, 3, 1):
6472 case IP_VERSION(10, 3, 4):
6473 case IP_VERSION(10, 3, 5):
6474 case IP_VERSION(10, 3, 6):
6475 case IP_VERSION(10, 3, 3):
6476 case IP_VERSION(10, 3, 7):
6477 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6478 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6479 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6480
6481 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6482 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6483 break;
6484 default:
6485 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6486 DOORBELL_RANGE_LOWER, ring->doorbell_index);
6487 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6488
6489 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6490 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6491 break;
6492 }
6493 }
6494
gfx_v10_0_cp_gfx_resume(struct amdgpu_device * adev)6495 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6496 {
6497 struct amdgpu_ring *ring;
6498 u32 tmp;
6499 u32 rb_bufsz;
6500 u64 rb_addr, rptr_addr, wptr_gpu_addr;
6501
6502 /* Set the write pointer delay */
6503 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6504
6505 /* set the RB to use vmid 0 */
6506 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6507
6508 /* Init gfx ring 0 for pipe 0 */
6509 mutex_lock(&adev->srbm_mutex);
6510 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6511
6512 /* Set ring buffer size */
6513 ring = &adev->gfx.gfx_ring[0];
6514 rb_bufsz = order_base_2(ring->ring_size / 8);
6515 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6516 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6517 #ifdef __BIG_ENDIAN
6518 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6519 #endif
6520 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6521
6522 /* Initialize the ring buffer's write pointers */
6523 ring->wptr = 0;
6524 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6525 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6526
6527 /* set the wb address whether it's enabled or not */
6528 rptr_addr = ring->rptr_gpu_addr;
6529 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6530 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6531 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6532
6533 wptr_gpu_addr = ring->wptr_gpu_addr;
6534 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6535 lower_32_bits(wptr_gpu_addr));
6536 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6537 upper_32_bits(wptr_gpu_addr));
6538
6539 mdelay(1);
6540 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6541
6542 rb_addr = ring->gpu_addr >> 8;
6543 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6544 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6545
6546 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6547
6548 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6549 mutex_unlock(&adev->srbm_mutex);
6550
6551 /* Init gfx ring 1 for pipe 1 */
6552 if (adev->gfx.num_gfx_rings > 1) {
6553 mutex_lock(&adev->srbm_mutex);
6554 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6555 /* maximum supported gfx ring is 2 */
6556 ring = &adev->gfx.gfx_ring[1];
6557 rb_bufsz = order_base_2(ring->ring_size / 8);
6558 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6559 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6560 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6561 /* Initialize the ring buffer's write pointers */
6562 ring->wptr = 0;
6563 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6564 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6565 /* Set the wb address whether it's enabled or not */
6566 rptr_addr = ring->rptr_gpu_addr;
6567 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6568 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6569 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6570 wptr_gpu_addr = ring->wptr_gpu_addr;
6571 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6572 lower_32_bits(wptr_gpu_addr));
6573 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6574 upper_32_bits(wptr_gpu_addr));
6575
6576 mdelay(1);
6577 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6578
6579 rb_addr = ring->gpu_addr >> 8;
6580 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6581 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6582 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6583
6584 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6585 mutex_unlock(&adev->srbm_mutex);
6586 }
6587 /* Switch to pipe 0 */
6588 mutex_lock(&adev->srbm_mutex);
6589 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6590 mutex_unlock(&adev->srbm_mutex);
6591
6592 /* start the ring */
6593 gfx_v10_0_cp_gfx_start(adev);
6594
6595 return 0;
6596 }
6597
gfx_v10_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)6598 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6599 {
6600 if (enable) {
6601 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6602 case IP_VERSION(10, 3, 0):
6603 case IP_VERSION(10, 3, 2):
6604 case IP_VERSION(10, 3, 1):
6605 case IP_VERSION(10, 3, 4):
6606 case IP_VERSION(10, 3, 5):
6607 case IP_VERSION(10, 3, 6):
6608 case IP_VERSION(10, 3, 3):
6609 case IP_VERSION(10, 3, 7):
6610 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6611 break;
6612 default:
6613 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6614 break;
6615 }
6616 } else {
6617 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6618 case IP_VERSION(10, 3, 0):
6619 case IP_VERSION(10, 3, 2):
6620 case IP_VERSION(10, 3, 1):
6621 case IP_VERSION(10, 3, 4):
6622 case IP_VERSION(10, 3, 5):
6623 case IP_VERSION(10, 3, 6):
6624 case IP_VERSION(10, 3, 3):
6625 case IP_VERSION(10, 3, 7):
6626 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6627 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6628 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6629 break;
6630 default:
6631 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6632 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6633 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6634 break;
6635 }
6636 adev->gfx.kiq[0].ring.sched.ready = false;
6637 }
6638 udelay(50);
6639 }
6640
gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device * adev)6641 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6642 {
6643 const struct gfx_firmware_header_v1_0 *mec_hdr;
6644 const __le32 *fw_data;
6645 unsigned int i;
6646 u32 tmp;
6647 u32 usec_timeout = 50000; /* Wait for 50 ms */
6648
6649 if (!adev->gfx.mec_fw)
6650 return -EINVAL;
6651
6652 gfx_v10_0_cp_compute_enable(adev, false);
6653
6654 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6655 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6656
6657 fw_data = (const __le32 *)
6658 (adev->gfx.mec_fw->data +
6659 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6660
6661 /* Trigger an invalidation of the L1 instruction caches */
6662 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6663 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6664 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6665
6666 /* Wait for invalidation complete */
6667 for (i = 0; i < usec_timeout; i++) {
6668 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6669 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6670 INVALIDATE_CACHE_COMPLETE))
6671 break;
6672 udelay(1);
6673 }
6674
6675 if (i >= usec_timeout) {
6676 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6677 return -EINVAL;
6678 }
6679
6680 if (amdgpu_emu_mode == 1)
6681 amdgpu_device_flush_hdp(adev, NULL);
6682
6683 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6684 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6685 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6686 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6687 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6688
6689 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6690 0xFFFFF000);
6691 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6692 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6693
6694 /* MEC1 */
6695 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6696
6697 for (i = 0; i < mec_hdr->jt_size; i++)
6698 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6699 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6700
6701 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6702
6703 /*
6704 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6705 * different microcode than MEC1.
6706 */
6707
6708 return 0;
6709 }
6710
gfx_v10_0_kiq_setting(struct amdgpu_ring * ring)6711 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6712 {
6713 uint32_t tmp;
6714 struct amdgpu_device *adev = ring->adev;
6715
6716 /* tell RLC which is KIQ queue */
6717 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6718 case IP_VERSION(10, 3, 0):
6719 case IP_VERSION(10, 3, 2):
6720 case IP_VERSION(10, 3, 1):
6721 case IP_VERSION(10, 3, 4):
6722 case IP_VERSION(10, 3, 5):
6723 case IP_VERSION(10, 3, 6):
6724 case IP_VERSION(10, 3, 3):
6725 case IP_VERSION(10, 3, 7):
6726 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6727 tmp &= 0xffffff00;
6728 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6729 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
6730 break;
6731 default:
6732 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6733 tmp &= 0xffffff00;
6734 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6735 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
6736 break;
6737 }
6738 }
6739
gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device * adev,struct v10_gfx_mqd * mqd,struct amdgpu_mqd_prop * prop)6740 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6741 struct v10_gfx_mqd *mqd,
6742 struct amdgpu_mqd_prop *prop)
6743 {
6744 bool priority = 0;
6745 u32 tmp;
6746
6747 /* set up default queue priority level
6748 * 0x0 = low priority, 0x1 = high priority
6749 */
6750 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6751 priority = 1;
6752
6753 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6754 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6755 mqd->cp_gfx_hqd_queue_priority = tmp;
6756 }
6757
gfx_v10_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6758 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6759 struct amdgpu_mqd_prop *prop)
6760 {
6761 struct v10_gfx_mqd *mqd = m;
6762 uint64_t hqd_gpu_addr, wb_gpu_addr;
6763 uint32_t tmp;
6764 uint32_t rb_bufsz;
6765
6766 /* set up gfx hqd wptr */
6767 mqd->cp_gfx_hqd_wptr = 0;
6768 mqd->cp_gfx_hqd_wptr_hi = 0;
6769
6770 /* set the pointer to the MQD */
6771 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6772 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6773
6774 /* set up mqd control */
6775 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6776 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6777 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6778 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6779 mqd->cp_gfx_mqd_control = tmp;
6780
6781 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6782 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6783 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6784 mqd->cp_gfx_hqd_vmid = 0;
6785
6786 /* set up gfx queue priority */
6787 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6788
6789 /* set up time quantum */
6790 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6791 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6792 mqd->cp_gfx_hqd_quantum = tmp;
6793
6794 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6795 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6796 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6797 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6798
6799 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6800 wb_gpu_addr = prop->rptr_gpu_addr;
6801 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6802 mqd->cp_gfx_hqd_rptr_addr_hi =
6803 upper_32_bits(wb_gpu_addr) & 0xffff;
6804
6805 /* set up rb_wptr_poll addr */
6806 wb_gpu_addr = prop->wptr_gpu_addr;
6807 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6808 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6809
6810 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6811 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6812 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6813 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6814 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6815 #ifdef __BIG_ENDIAN
6816 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6817 #endif
6818 mqd->cp_gfx_hqd_cntl = tmp;
6819
6820 /* set up cp_doorbell_control */
6821 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6822 if (prop->use_doorbell) {
6823 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6824 DOORBELL_OFFSET, prop->doorbell_index);
6825 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6826 DOORBELL_EN, 1);
6827 } else
6828 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6829 DOORBELL_EN, 0);
6830 mqd->cp_rb_doorbell_control = tmp;
6831
6832 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6833 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6834
6835 /* active the queue */
6836 mqd->cp_gfx_hqd_active = 1;
6837
6838 return 0;
6839 }
6840
gfx_v10_0_kgq_init_queue(struct amdgpu_ring * ring,bool reset)6841 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
6842 {
6843 struct amdgpu_device *adev = ring->adev;
6844 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6845 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6846
6847 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
6848 memset((void *)mqd, 0, sizeof(*mqd));
6849 mutex_lock(&adev->srbm_mutex);
6850 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6851 amdgpu_ring_init_mqd(ring);
6852
6853 /*
6854 * if there are 2 gfx rings, set the lower doorbell
6855 * range of the first ring, otherwise the range of
6856 * the second ring will override the first ring
6857 */
6858 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6859 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6860
6861 nv_grbm_select(adev, 0, 0, 0, 0);
6862 mutex_unlock(&adev->srbm_mutex);
6863 if (adev->gfx.me.mqd_backup[mqd_idx])
6864 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6865 } else {
6866 mutex_lock(&adev->srbm_mutex);
6867 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6868 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6869 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6870
6871 nv_grbm_select(adev, 0, 0, 0, 0);
6872 mutex_unlock(&adev->srbm_mutex);
6873 /* restore mqd with the backup copy */
6874 if (adev->gfx.me.mqd_backup[mqd_idx])
6875 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6876 /* reset the ring */
6877 ring->wptr = 0;
6878 *ring->wptr_cpu_addr = 0;
6879 amdgpu_ring_clear_ring(ring);
6880 }
6881
6882 return 0;
6883 }
6884
gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)6885 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6886 {
6887 int r, i;
6888
6889 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6890 r = gfx_v10_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
6891 if (r)
6892 return r;
6893 }
6894
6895 r = amdgpu_gfx_enable_kgq(adev, 0);
6896 if (r)
6897 return r;
6898
6899 return gfx_v10_0_cp_gfx_start(adev);
6900 }
6901
gfx_v10_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6902 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6903 struct amdgpu_mqd_prop *prop)
6904 {
6905 struct v10_compute_mqd *mqd = m;
6906 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6907 uint32_t tmp;
6908
6909 mqd->header = 0xC0310800;
6910 mqd->compute_pipelinestat_enable = 0x00000001;
6911 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6912 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6913 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6914 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6915 mqd->compute_misc_reserved = 0x00000003;
6916
6917 eop_base_addr = prop->eop_gpu_addr >> 8;
6918 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6919 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6920
6921 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6922 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6923 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6924 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6925
6926 mqd->cp_hqd_eop_control = tmp;
6927
6928 /* enable doorbell? */
6929 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6930
6931 if (prop->use_doorbell) {
6932 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6933 DOORBELL_OFFSET, prop->doorbell_index);
6934 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6935 DOORBELL_EN, 1);
6936 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6937 DOORBELL_SOURCE, 0);
6938 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6939 DOORBELL_HIT, 0);
6940 } else {
6941 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6942 DOORBELL_EN, 0);
6943 }
6944
6945 mqd->cp_hqd_pq_doorbell_control = tmp;
6946
6947 /* disable the queue if it's active */
6948 mqd->cp_hqd_dequeue_request = 0;
6949 mqd->cp_hqd_pq_rptr = 0;
6950 mqd->cp_hqd_pq_wptr_lo = 0;
6951 mqd->cp_hqd_pq_wptr_hi = 0;
6952
6953 /* set the pointer to the MQD */
6954 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6955 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6956
6957 /* set MQD vmid to 0 */
6958 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6959 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6960 mqd->cp_mqd_control = tmp;
6961
6962 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6963 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6964 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6965 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6966
6967 /* set up the HQD, this is similar to CP_RB0_CNTL */
6968 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6969 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6970 (order_base_2(prop->queue_size / 4) - 1));
6971 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6972 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6973 #ifdef __BIG_ENDIAN
6974 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6975 #endif
6976 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6977 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6978 prop->allow_tunneling);
6979 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6980 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6981 mqd->cp_hqd_pq_control = tmp;
6982
6983 /* set the wb address whether it's enabled or not */
6984 wb_gpu_addr = prop->rptr_gpu_addr;
6985 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6986 mqd->cp_hqd_pq_rptr_report_addr_hi =
6987 upper_32_bits(wb_gpu_addr) & 0xffff;
6988
6989 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6990 wb_gpu_addr = prop->wptr_gpu_addr;
6991 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6992 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6993
6994 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6995 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6996
6997 /* set the vmid for the queue */
6998 mqd->cp_hqd_vmid = 0;
6999
7000 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
7001 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
7002 mqd->cp_hqd_persistent_state = tmp;
7003
7004 /* set MIN_IB_AVAIL_SIZE */
7005 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
7006 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
7007 mqd->cp_hqd_ib_control = tmp;
7008
7009 /* set static priority for a compute queue/ring */
7010 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
7011 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
7012
7013 mqd->cp_hqd_active = prop->hqd_active;
7014
7015 return 0;
7016 }
7017
gfx_v10_0_kiq_init_register(struct amdgpu_ring * ring)7018 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
7019 {
7020 struct amdgpu_device *adev = ring->adev;
7021 struct v10_compute_mqd *mqd = ring->mqd_ptr;
7022 int j;
7023
7024 /* inactivate the queue */
7025 if (amdgpu_sriov_vf(adev))
7026 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
7027
7028 /* disable wptr polling */
7029 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
7030
7031 /* disable the queue if it's active */
7032 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
7033 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7034 for (j = 0; j < adev->usec_timeout; j++) {
7035 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7036 break;
7037 udelay(1);
7038 }
7039 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7040 mqd->cp_hqd_dequeue_request);
7041 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7042 mqd->cp_hqd_pq_rptr);
7043 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7044 mqd->cp_hqd_pq_wptr_lo);
7045 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7046 mqd->cp_hqd_pq_wptr_hi);
7047 }
7048
7049 /* disable doorbells */
7050 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
7051
7052 /* write the EOP addr */
7053 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7054 mqd->cp_hqd_eop_base_addr_lo);
7055 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7056 mqd->cp_hqd_eop_base_addr_hi);
7057
7058 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7059 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7060 mqd->cp_hqd_eop_control);
7061
7062 /* set the pointer to the MQD */
7063 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7064 mqd->cp_mqd_base_addr_lo);
7065 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7066 mqd->cp_mqd_base_addr_hi);
7067
7068 /* set MQD vmid to 0 */
7069 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7070 mqd->cp_mqd_control);
7071
7072 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7073 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7074 mqd->cp_hqd_pq_base_lo);
7075 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7076 mqd->cp_hqd_pq_base_hi);
7077
7078 /* set up the HQD, this is similar to CP_RB0_CNTL */
7079 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7080 mqd->cp_hqd_pq_control);
7081
7082 /* set the wb address whether it's enabled or not */
7083 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7084 mqd->cp_hqd_pq_rptr_report_addr_lo);
7085 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7086 mqd->cp_hqd_pq_rptr_report_addr_hi);
7087
7088 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7089 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7090 mqd->cp_hqd_pq_wptr_poll_addr_lo);
7091 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7092 mqd->cp_hqd_pq_wptr_poll_addr_hi);
7093
7094 /* enable the doorbell if requested */
7095 if (ring->use_doorbell) {
7096 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7097 (adev->doorbell_index.kiq * 2) << 2);
7098 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7099 (adev->doorbell_index.userqueue_end * 2) << 2);
7100 }
7101
7102 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7103 mqd->cp_hqd_pq_doorbell_control);
7104
7105 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7106 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7107 mqd->cp_hqd_pq_wptr_lo);
7108 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7109 mqd->cp_hqd_pq_wptr_hi);
7110
7111 /* set the vmid for the queue */
7112 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7113
7114 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7115 mqd->cp_hqd_persistent_state);
7116
7117 /* activate the queue */
7118 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7119 mqd->cp_hqd_active);
7120
7121 if (ring->use_doorbell)
7122 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7123
7124 return 0;
7125 }
7126
gfx_v10_0_kiq_init_queue(struct amdgpu_ring * ring)7127 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7128 {
7129 struct amdgpu_device *adev = ring->adev;
7130 struct v10_compute_mqd *mqd = ring->mqd_ptr;
7131
7132 gfx_v10_0_kiq_setting(ring);
7133
7134 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7135 /* reset MQD to a clean status */
7136 if (adev->gfx.kiq[0].mqd_backup)
7137 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
7138
7139 /* reset ring buffer */
7140 ring->wptr = 0;
7141 amdgpu_ring_clear_ring(ring);
7142
7143 mutex_lock(&adev->srbm_mutex);
7144 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7145 gfx_v10_0_kiq_init_register(ring);
7146 nv_grbm_select(adev, 0, 0, 0, 0);
7147 mutex_unlock(&adev->srbm_mutex);
7148 } else {
7149 memset((void *)mqd, 0, sizeof(*mqd));
7150 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
7151 amdgpu_ring_clear_ring(ring);
7152 mutex_lock(&adev->srbm_mutex);
7153 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7154 amdgpu_ring_init_mqd(ring);
7155 gfx_v10_0_kiq_init_register(ring);
7156 nv_grbm_select(adev, 0, 0, 0, 0);
7157 mutex_unlock(&adev->srbm_mutex);
7158
7159 if (adev->gfx.kiq[0].mqd_backup)
7160 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
7161 }
7162
7163 return 0;
7164 }
7165
gfx_v10_0_kcq_init_queue(struct amdgpu_ring * ring,bool restore)7166 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
7167 {
7168 struct amdgpu_device *adev = ring->adev;
7169 struct v10_compute_mqd *mqd = ring->mqd_ptr;
7170 int mqd_idx = ring - &adev->gfx.compute_ring[0];
7171
7172 if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {
7173 memset((void *)mqd, 0, sizeof(*mqd));
7174 mutex_lock(&adev->srbm_mutex);
7175 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7176 amdgpu_ring_init_mqd(ring);
7177 nv_grbm_select(adev, 0, 0, 0, 0);
7178 mutex_unlock(&adev->srbm_mutex);
7179
7180 if (adev->gfx.mec.mqd_backup[mqd_idx])
7181 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7182 } else {
7183 /* restore MQD to a clean status */
7184 if (adev->gfx.mec.mqd_backup[mqd_idx])
7185 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7186 /* reset ring buffer */
7187 ring->wptr = 0;
7188 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7189 amdgpu_ring_clear_ring(ring);
7190 }
7191
7192 return 0;
7193 }
7194
gfx_v10_0_kiq_resume(struct amdgpu_device * adev)7195 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7196 {
7197 gfx_v10_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
7198 return 0;
7199 }
7200
gfx_v10_0_kcq_resume(struct amdgpu_device * adev)7201 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7202 {
7203 int i, r;
7204
7205 gfx_v10_0_cp_compute_enable(adev, true);
7206
7207 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7208 r = gfx_v10_0_kcq_init_queue(&adev->gfx.compute_ring[i],
7209 false);
7210 if (r)
7211 return r;
7212 }
7213
7214 return amdgpu_gfx_enable_kcq(adev, 0);
7215 }
7216
gfx_v10_0_cp_resume(struct amdgpu_device * adev)7217 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7218 {
7219 int r, i;
7220 struct amdgpu_ring *ring;
7221
7222 if (!(adev->flags & AMD_IS_APU))
7223 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7224
7225 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7226 /* legacy firmware loading */
7227 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7228 if (r)
7229 return r;
7230
7231 r = gfx_v10_0_cp_compute_load_microcode(adev);
7232 if (r)
7233 return r;
7234 }
7235
7236 r = gfx_v10_0_kiq_resume(adev);
7237 if (r)
7238 return r;
7239
7240 r = gfx_v10_0_kcq_resume(adev);
7241 if (r)
7242 return r;
7243
7244 if (!amdgpu_async_gfx_ring) {
7245 r = gfx_v10_0_cp_gfx_resume(adev);
7246 if (r)
7247 return r;
7248 } else {
7249 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7250 if (r)
7251 return r;
7252 }
7253
7254 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7255 ring = &adev->gfx.gfx_ring[i];
7256 r = amdgpu_ring_test_helper(ring);
7257 if (r)
7258 return r;
7259 }
7260
7261 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7262 ring = &adev->gfx.compute_ring[i];
7263 r = amdgpu_ring_test_helper(ring);
7264 if (r)
7265 return r;
7266 }
7267
7268 return 0;
7269 }
7270
gfx_v10_0_cp_enable(struct amdgpu_device * adev,bool enable)7271 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7272 {
7273 gfx_v10_0_cp_gfx_enable(adev, enable);
7274 gfx_v10_0_cp_compute_enable(adev, enable);
7275 }
7276
gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device * adev)7277 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7278 {
7279 uint32_t data, pattern = 0xDEADBEEF;
7280
7281 /*
7282 * check if mmVGT_ESGS_RING_SIZE_UMD
7283 * has been remapped to mmVGT_ESGS_RING_SIZE
7284 */
7285 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7286 case IP_VERSION(10, 3, 0):
7287 case IP_VERSION(10, 3, 2):
7288 case IP_VERSION(10, 3, 4):
7289 case IP_VERSION(10, 3, 5):
7290 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7291 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7292 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7293
7294 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7295 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7296 return true;
7297 }
7298 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7299 break;
7300 case IP_VERSION(10, 3, 1):
7301 case IP_VERSION(10, 3, 3):
7302 case IP_VERSION(10, 3, 6):
7303 case IP_VERSION(10, 3, 7):
7304 return true;
7305 default:
7306 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7307 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7308 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7309
7310 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7311 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7312 return true;
7313 }
7314 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7315 break;
7316 }
7317
7318 return false;
7319 }
7320
gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device * adev)7321 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7322 {
7323 uint32_t data;
7324
7325 if (amdgpu_sriov_vf(adev))
7326 return;
7327
7328 /*
7329 * Initialize cam_index to 0
7330 * index will auto-inc after each data writing
7331 */
7332 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7333
7334 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7335 case IP_VERSION(10, 3, 0):
7336 case IP_VERSION(10, 3, 2):
7337 case IP_VERSION(10, 3, 1):
7338 case IP_VERSION(10, 3, 4):
7339 case IP_VERSION(10, 3, 5):
7340 case IP_VERSION(10, 3, 6):
7341 case IP_VERSION(10, 3, 3):
7342 case IP_VERSION(10, 3, 7):
7343 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7344 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7345 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7346 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7347 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7348 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7349 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7350
7351 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7352 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7353 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7354 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7355 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7356 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7357 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7358
7359 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7360 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7361 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7362 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7363 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7364 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7365 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7366
7367 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7368 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7369 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7370 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7371 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7372 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7373 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7374
7375 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7376 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7377 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7378 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7379 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7380 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7381 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7382
7383 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7384 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7385 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7386 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7387 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7388 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7389 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7390
7391 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7392 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7393 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7394 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7395 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7396 break;
7397 default:
7398 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7399 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7400 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7401 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7402 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7403 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7404 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7405
7406 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7407 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7408 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7409 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7410 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7411 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7412 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7413
7414 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7415 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7416 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7417 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7418 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7419 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7420 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7421
7422 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7423 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7424 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7425 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7426 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7427 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7428 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7429
7430 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7431 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7432 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7433 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7434 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7435 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7436 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7437
7438 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7439 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7440 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7441 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7442 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7443 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7444 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7445
7446 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7447 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7448 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7449 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7450 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7451 break;
7452 }
7453
7454 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7455 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7456 }
7457
gfx_v10_0_disable_gpa_mode(struct amdgpu_device * adev)7458 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7459 {
7460 uint32_t data;
7461
7462 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7463 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7464 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7465
7466 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7467 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7468 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7469 }
7470
gfx_v10_0_hw_init(struct amdgpu_ip_block * ip_block)7471 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
7472 {
7473 int r;
7474 struct amdgpu_device *adev = ip_block->adev;
7475
7476 if (!amdgpu_emu_mode)
7477 gfx_v10_0_init_golden_registers(adev);
7478
7479 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
7480 adev->gfx.cleaner_shader_ptr);
7481
7482 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7483 /**
7484 * For gfx 10, rlc firmware loading relies on smu firmware is
7485 * loaded firstly, so in direct type, it has to load smc ucode
7486 * here before rlc.
7487 */
7488 r = amdgpu_pm_load_smu_firmware(adev, NULL);
7489 if (r)
7490 return r;
7491 gfx_v10_0_disable_gpa_mode(adev);
7492 }
7493
7494 /* if GRBM CAM not remapped, set up the remapping */
7495 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7496 gfx_v10_0_setup_grbm_cam_remapping(adev);
7497
7498 gfx_v10_0_constants_init(adev);
7499
7500 r = gfx_v10_0_rlc_resume(adev);
7501 if (r)
7502 return r;
7503
7504 /*
7505 * init golden registers and rlc resume may override some registers,
7506 * reconfig them here
7507 */
7508 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7509 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7510 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7511 gfx_v10_0_tcp_harvest(adev);
7512
7513 r = gfx_v10_0_cp_resume(adev);
7514 if (r)
7515 return r;
7516
7517 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7518 gfx_v10_3_program_pbb_mode(adev);
7519
7520 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7521 gfx_v10_3_set_power_brake_sequence(adev);
7522
7523 return r;
7524 }
7525
gfx_v10_0_hw_fini(struct amdgpu_ip_block * ip_block)7526 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
7527 {
7528 struct amdgpu_device *adev = ip_block->adev;
7529
7530 cancel_delayed_work_sync(&adev->gfx.idle_work);
7531
7532 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7533 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7534 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
7535
7536 /* WA added for Vangogh asic fixing the SMU suspend failure
7537 * It needs to set power gating again during gfxoff control
7538 * otherwise the gfxoff disallowing will be failed to set.
7539 */
7540 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7541 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
7542
7543 if (!adev->no_hw_access) {
7544 if (amdgpu_async_gfx_ring) {
7545 if (amdgpu_gfx_disable_kgq(adev, 0))
7546 DRM_ERROR("KGQ disable failed\n");
7547 }
7548
7549 if (amdgpu_gfx_disable_kcq(adev, 0))
7550 DRM_ERROR("KCQ disable failed\n");
7551 }
7552
7553 if (amdgpu_sriov_vf(adev)) {
7554 gfx_v10_0_cp_gfx_enable(adev, false);
7555 /* Remove the steps of clearing KIQ position.
7556 * It causes GFX hang when another Win guest is rendering.
7557 */
7558 return 0;
7559 }
7560 gfx_v10_0_cp_enable(adev, false);
7561 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7562
7563 return 0;
7564 }
7565
gfx_v10_0_suspend(struct amdgpu_ip_block * ip_block)7566 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)
7567 {
7568 return gfx_v10_0_hw_fini(ip_block);
7569 }
7570
gfx_v10_0_resume(struct amdgpu_ip_block * ip_block)7571 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
7572 {
7573 return gfx_v10_0_hw_init(ip_block);
7574 }
7575
gfx_v10_0_is_idle(struct amdgpu_ip_block * ip_block)7576 static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
7577 {
7578 struct amdgpu_device *adev = ip_block->adev;
7579
7580 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7581 GRBM_STATUS, GUI_ACTIVE))
7582 return false;
7583 else
7584 return true;
7585 }
7586
gfx_v10_0_wait_for_idle(struct amdgpu_ip_block * ip_block)7587 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
7588 {
7589 unsigned int i;
7590 u32 tmp;
7591 struct amdgpu_device *adev = ip_block->adev;
7592
7593 for (i = 0; i < adev->usec_timeout; i++) {
7594 /* read MC_STATUS */
7595 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7596 GRBM_STATUS__GUI_ACTIVE_MASK;
7597
7598 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7599 return 0;
7600 udelay(1);
7601 }
7602 return -ETIMEDOUT;
7603 }
7604
gfx_v10_0_soft_reset(struct amdgpu_ip_block * ip_block)7605 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
7606 {
7607 u32 grbm_soft_reset = 0;
7608 u32 tmp;
7609 struct amdgpu_device *adev = ip_block->adev;
7610
7611 /* GRBM_STATUS */
7612 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7613 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7614 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7615 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7616 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7617 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7618 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7619 GRBM_SOFT_RESET, SOFT_RESET_CP,
7620 1);
7621 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7622 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7623 1);
7624 }
7625
7626 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7627 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7628 GRBM_SOFT_RESET, SOFT_RESET_CP,
7629 1);
7630 }
7631
7632 /* GRBM_STATUS2 */
7633 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7634 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7635 case IP_VERSION(10, 3, 0):
7636 case IP_VERSION(10, 3, 2):
7637 case IP_VERSION(10, 3, 1):
7638 case IP_VERSION(10, 3, 4):
7639 case IP_VERSION(10, 3, 5):
7640 case IP_VERSION(10, 3, 6):
7641 case IP_VERSION(10, 3, 3):
7642 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7643 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7644 GRBM_SOFT_RESET,
7645 SOFT_RESET_RLC,
7646 1);
7647 break;
7648 default:
7649 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7650 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7651 GRBM_SOFT_RESET,
7652 SOFT_RESET_RLC,
7653 1);
7654 break;
7655 }
7656
7657 if (grbm_soft_reset) {
7658 /* stop the rlc */
7659 gfx_v10_0_rlc_stop(adev);
7660
7661 /* Disable GFX parsing/prefetching */
7662 gfx_v10_0_cp_gfx_enable(adev, false);
7663
7664 /* Disable MEC parsing/prefetching */
7665 gfx_v10_0_cp_compute_enable(adev, false);
7666
7667 if (grbm_soft_reset) {
7668 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7669 tmp |= grbm_soft_reset;
7670 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7671 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7672 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7673
7674 udelay(50);
7675
7676 tmp &= ~grbm_soft_reset;
7677 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7678 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7679 }
7680
7681 /* Wait a little for things to settle down */
7682 udelay(50);
7683 }
7684 return 0;
7685 }
7686
gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device * adev)7687 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7688 {
7689 uint64_t clock, clock_lo, clock_hi, hi_check;
7690
7691 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7692 case IP_VERSION(10, 1, 3):
7693 case IP_VERSION(10, 1, 4):
7694 preempt_disable();
7695 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7696 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7697 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7698 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7699 * roughly every 42 seconds.
7700 */
7701 if (hi_check != clock_hi) {
7702 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7703 clock_hi = hi_check;
7704 }
7705 preempt_enable();
7706 clock = clock_lo | (clock_hi << 32ULL);
7707 break;
7708 case IP_VERSION(10, 3, 1):
7709 case IP_VERSION(10, 3, 3):
7710 case IP_VERSION(10, 3, 7):
7711 preempt_disable();
7712 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7713 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7714 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7715 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7716 * roughly every 42 seconds.
7717 */
7718 if (hi_check != clock_hi) {
7719 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7720 clock_hi = hi_check;
7721 }
7722 preempt_enable();
7723 clock = clock_lo | (clock_hi << 32ULL);
7724 break;
7725 case IP_VERSION(10, 3, 6):
7726 preempt_disable();
7727 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7728 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7729 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7730 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7731 * roughly every 42 seconds.
7732 */
7733 if (hi_check != clock_hi) {
7734 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7735 clock_hi = hi_check;
7736 }
7737 preempt_enable();
7738 clock = clock_lo | (clock_hi << 32ULL);
7739 break;
7740 default:
7741 preempt_disable();
7742 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7743 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7744 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7745 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7746 * roughly every 42 seconds.
7747 */
7748 if (hi_check != clock_hi) {
7749 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7750 clock_hi = hi_check;
7751 }
7752 preempt_enable();
7753 clock = clock_lo | (clock_hi << 32ULL);
7754 break;
7755 }
7756 return clock;
7757 }
7758
gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)7759 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7760 uint32_t vmid,
7761 uint32_t gds_base, uint32_t gds_size,
7762 uint32_t gws_base, uint32_t gws_size,
7763 uint32_t oa_base, uint32_t oa_size)
7764 {
7765 struct amdgpu_device *adev = ring->adev;
7766
7767 /* GDS Base */
7768 gfx_v10_0_write_data_to_reg(ring, 0, false,
7769 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7770 gds_base);
7771
7772 /* GDS Size */
7773 gfx_v10_0_write_data_to_reg(ring, 0, false,
7774 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7775 gds_size);
7776
7777 /* GWS */
7778 gfx_v10_0_write_data_to_reg(ring, 0, false,
7779 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7780 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7781
7782 /* OA */
7783 gfx_v10_0_write_data_to_reg(ring, 0, false,
7784 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7785 (1 << (oa_size + oa_base)) - (1 << oa_base));
7786 }
7787
gfx_v10_0_early_init(struct amdgpu_ip_block * ip_block)7788 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)
7789 {
7790 struct amdgpu_device *adev = ip_block->adev;
7791
7792 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7793
7794 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7795 case IP_VERSION(10, 1, 10):
7796 case IP_VERSION(10, 1, 1):
7797 case IP_VERSION(10, 1, 2):
7798 case IP_VERSION(10, 1, 3):
7799 case IP_VERSION(10, 1, 4):
7800 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7801 break;
7802 case IP_VERSION(10, 3, 0):
7803 case IP_VERSION(10, 3, 2):
7804 case IP_VERSION(10, 3, 1):
7805 case IP_VERSION(10, 3, 4):
7806 case IP_VERSION(10, 3, 5):
7807 case IP_VERSION(10, 3, 6):
7808 case IP_VERSION(10, 3, 3):
7809 case IP_VERSION(10, 3, 7):
7810 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7811 break;
7812 default:
7813 break;
7814 }
7815
7816 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7817 AMDGPU_MAX_COMPUTE_RINGS);
7818
7819 gfx_v10_0_set_kiq_pm4_funcs(adev);
7820 gfx_v10_0_set_ring_funcs(adev);
7821 gfx_v10_0_set_irq_funcs(adev);
7822 gfx_v10_0_set_gds_init(adev);
7823 gfx_v10_0_set_rlc_funcs(adev);
7824 gfx_v10_0_set_mqd_funcs(adev);
7825
7826 /* init rlcg reg access ctrl */
7827 gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7828
7829 return gfx_v10_0_init_microcode(adev);
7830 }
7831
gfx_v10_0_late_init(struct amdgpu_ip_block * ip_block)7832 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)
7833 {
7834 struct amdgpu_device *adev = ip_block->adev;
7835 int r;
7836
7837 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7838 if (r)
7839 return r;
7840
7841 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7842 if (r)
7843 return r;
7844
7845 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
7846 if (r)
7847 return r;
7848
7849 return 0;
7850 }
7851
gfx_v10_0_is_rlc_enabled(struct amdgpu_device * adev)7852 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7853 {
7854 uint32_t rlc_cntl;
7855
7856 /* if RLC is not enabled, do nothing */
7857 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7858 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7859 }
7860
gfx_v10_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)7861 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7862 {
7863 uint32_t data;
7864 unsigned int i;
7865
7866 data = RLC_SAFE_MODE__CMD_MASK;
7867 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7868
7869 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7870 case IP_VERSION(10, 3, 0):
7871 case IP_VERSION(10, 3, 2):
7872 case IP_VERSION(10, 3, 1):
7873 case IP_VERSION(10, 3, 4):
7874 case IP_VERSION(10, 3, 5):
7875 case IP_VERSION(10, 3, 6):
7876 case IP_VERSION(10, 3, 3):
7877 case IP_VERSION(10, 3, 7):
7878 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7879
7880 /* wait for RLC_SAFE_MODE */
7881 for (i = 0; i < adev->usec_timeout; i++) {
7882 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7883 RLC_SAFE_MODE, CMD))
7884 break;
7885 udelay(1);
7886 }
7887 break;
7888 default:
7889 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7890
7891 /* wait for RLC_SAFE_MODE */
7892 for (i = 0; i < adev->usec_timeout; i++) {
7893 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7894 RLC_SAFE_MODE, CMD))
7895 break;
7896 udelay(1);
7897 }
7898 break;
7899 }
7900 }
7901
gfx_v10_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)7902 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7903 {
7904 uint32_t data;
7905
7906 data = RLC_SAFE_MODE__CMD_MASK;
7907 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7908 case IP_VERSION(10, 3, 0):
7909 case IP_VERSION(10, 3, 2):
7910 case IP_VERSION(10, 3, 1):
7911 case IP_VERSION(10, 3, 4):
7912 case IP_VERSION(10, 3, 5):
7913 case IP_VERSION(10, 3, 6):
7914 case IP_VERSION(10, 3, 3):
7915 case IP_VERSION(10, 3, 7):
7916 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7917 break;
7918 default:
7919 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7920 break;
7921 }
7922 }
7923
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)7924 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7925 bool enable)
7926 {
7927 uint32_t data, def;
7928
7929 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7930 return;
7931
7932 /* It is disabled by HW by default */
7933 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7934 /* 0 - Disable some blocks' MGCG */
7935 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7936 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7937 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7938 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7939
7940 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7941 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7942 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7943 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7944 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7945 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7946 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7947 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7948
7949 if (def != data)
7950 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7951
7952 /* MGLS is a global flag to control all MGLS in GFX */
7953 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7954 /* 2 - RLC memory Light sleep */
7955 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7956 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7957 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7958 if (def != data)
7959 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7960 }
7961 /* 3 - CP memory Light sleep */
7962 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7963 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7964 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7965 if (def != data)
7966 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7967 }
7968 }
7969 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7970 /* 1 - MGCG_OVERRIDE */
7971 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7972 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7973 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7974 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7975 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7976 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7977 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7978 if (def != data)
7979 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7980
7981 /* 2 - disable MGLS in CP */
7982 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7983 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7984 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7985 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7986 }
7987
7988 /* 3 - disable MGLS in RLC */
7989 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7990 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7991 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7992 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7993 }
7994
7995 }
7996 }
7997
gfx_v10_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)7998 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7999 bool enable)
8000 {
8001 uint32_t data, def;
8002
8003 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
8004 return;
8005
8006 /* Enable 3D CGCG/CGLS */
8007 if (enable) {
8008 /* write cmd to clear cgcg/cgls ov */
8009 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8010
8011 /* unset CGCG override */
8012 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8013 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
8014
8015 /* update CGCG and CGLS override bits */
8016 if (def != data)
8017 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8018
8019 /* enable 3Dcgcg FSM(0x0000363f) */
8020 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8021 data = 0;
8022
8023 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8024 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8025 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8026
8027 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8028 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8029 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8030
8031 if (def != data)
8032 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8033
8034 /* set IDLE_POLL_COUNT(0x00900100) */
8035 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8036 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8037 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8038 if (def != data)
8039 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8040 } else {
8041 /* Disable CGCG/CGLS */
8042 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8043
8044 /* disable cgcg, cgls should be disabled */
8045 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8046 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8047
8048 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8049 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8050
8051 /* disable cgcg and cgls in FSM */
8052 if (def != data)
8053 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8054 }
8055 }
8056
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)8057 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8058 bool enable)
8059 {
8060 uint32_t def, data;
8061
8062 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8063 return;
8064
8065 if (enable) {
8066 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8067
8068 /* unset CGCG override */
8069 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8070 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8071
8072 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8073 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8074
8075 /* update CGCG and CGLS override bits */
8076 if (def != data)
8077 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8078
8079 /* enable cgcg FSM(0x0000363F) */
8080 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8081 data = 0;
8082
8083 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8084 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8085 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8086
8087 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8088 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8089 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8090
8091 if (def != data)
8092 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8093
8094 /* set IDLE_POLL_COUNT(0x00900100) */
8095 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8096 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8097 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8098 if (def != data)
8099 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8100 } else {
8101 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8102
8103 /* reset CGCG/CGLS bits */
8104 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8105 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8106
8107 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8108 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8109
8110 /* disable cgcg and cgls in FSM */
8111 if (def != data)
8112 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8113 }
8114 }
8115
gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device * adev,bool enable)8116 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8117 bool enable)
8118 {
8119 uint32_t def, data;
8120
8121 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8122 return;
8123
8124 if (enable) {
8125 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8126 /* unset FGCG override */
8127 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8128 /* update FGCG override bits */
8129 if (def != data)
8130 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8131
8132 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8133 /* unset RLC SRAM CLK GATER override */
8134 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8135 /* update RLC SRAM CLK GATER override bits */
8136 if (def != data)
8137 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8138 } else {
8139 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8140 /* reset FGCG bits */
8141 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8142 /* disable FGCG*/
8143 if (def != data)
8144 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8145
8146 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8147 /* reset RLC SRAM CLK GATER bits */
8148 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8149 /* disable RLC SRAM CLK*/
8150 if (def != data)
8151 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8152 }
8153 }
8154
gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device * adev)8155 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8156 {
8157 uint32_t reg_data = 0;
8158 uint32_t reg_idx = 0;
8159 uint32_t i;
8160
8161 const uint32_t tcp_ctrl_regs[] = {
8162 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8163 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8164 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8165 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8166 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8167 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8168 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8169 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8170 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8171 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8172 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8173 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8174 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8175 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8176 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8177 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8178 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8179 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8180 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8181 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8182 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8183 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8184 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8185 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8186 };
8187
8188 const uint32_t tcp_ctrl_regs_nv12[] = {
8189 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8190 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8191 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8192 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8193 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8194 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8195 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8196 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8197 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8198 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8199 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8200 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8201 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8202 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8203 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8204 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8205 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8206 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8207 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8208 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8209 };
8210
8211 const uint32_t sm_ctlr_regs[] = {
8212 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8213 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8214 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8215 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8216 };
8217
8218 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
8219 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8220 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8221 tcp_ctrl_regs_nv12[i];
8222 reg_data = RREG32(reg_idx);
8223 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8224 WREG32(reg_idx, reg_data);
8225 }
8226 } else {
8227 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8228 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8229 tcp_ctrl_regs[i];
8230 reg_data = RREG32(reg_idx);
8231 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8232 WREG32(reg_idx, reg_data);
8233 }
8234 }
8235
8236 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8237 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8238 sm_ctlr_regs[i];
8239 reg_data = RREG32(reg_idx);
8240 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8241 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8242 WREG32(reg_idx, reg_data);
8243 }
8244 }
8245
gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)8246 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8247 bool enable)
8248 {
8249 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8250
8251 if (enable) {
8252 /* enable FGCG firstly*/
8253 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8254 /* CGCG/CGLS should be enabled after MGCG/MGLS
8255 * === MGCG + MGLS ===
8256 */
8257 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8258 /* === CGCG /CGLS for GFX 3D Only === */
8259 gfx_v10_0_update_3d_clock_gating(adev, enable);
8260 /* === CGCG + CGLS === */
8261 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8262
8263 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8264 IP_VERSION(10, 1, 10)) ||
8265 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8266 IP_VERSION(10, 1, 1)) ||
8267 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8268 IP_VERSION(10, 1, 2)))
8269 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8270 } else {
8271 /* CGCG/CGLS should be disabled before MGCG/MGLS
8272 * === CGCG + CGLS ===
8273 */
8274 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8275 /* === CGCG /CGLS for GFX 3D Only === */
8276 gfx_v10_0_update_3d_clock_gating(adev, enable);
8277 /* === MGCG + MGLS === */
8278 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8279 /* disable fgcg at last*/
8280 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8281 }
8282
8283 if (adev->cg_flags &
8284 (AMD_CG_SUPPORT_GFX_MGCG |
8285 AMD_CG_SUPPORT_GFX_CGLS |
8286 AMD_CG_SUPPORT_GFX_CGCG |
8287 AMD_CG_SUPPORT_GFX_3D_CGCG |
8288 AMD_CG_SUPPORT_GFX_3D_CGLS))
8289 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8290
8291 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8292
8293 return 0;
8294 }
8295
gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device * adev,unsigned int vmid)8296 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8297 unsigned int vmid)
8298 {
8299 u32 reg, pre_data, data;
8300
8301 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8302 /* not for *_SOC15 */
8303 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
8304 pre_data = RREG32_NO_KIQ(reg);
8305 else
8306 pre_data = RREG32(reg);
8307
8308 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
8309 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8310
8311 if (pre_data != data) {
8312 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
8313 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8314 } else
8315 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8316 }
8317 }
8318
gfx_v10_0_update_spm_vmid(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned int vmid)8319 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8320 {
8321 amdgpu_gfx_off_ctrl(adev, false);
8322
8323 gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8324
8325 amdgpu_gfx_off_ctrl(adev, true);
8326 }
8327
gfx_v10_0_check_rlcg_range(struct amdgpu_device * adev,uint32_t offset,struct soc15_reg_rlcg * entries,int arr_size)8328 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8329 uint32_t offset,
8330 struct soc15_reg_rlcg *entries, int arr_size)
8331 {
8332 int i;
8333 uint32_t reg;
8334
8335 if (!entries)
8336 return false;
8337
8338 for (i = 0; i < arr_size; i++) {
8339 const struct soc15_reg_rlcg *entry;
8340
8341 entry = &entries[i];
8342 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8343 if (offset == reg)
8344 return true;
8345 }
8346
8347 return false;
8348 }
8349
gfx_v10_0_is_rlcg_access_range(struct amdgpu_device * adev,u32 offset)8350 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8351 {
8352 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8353 }
8354
gfx_v10_cntl_power_gating(struct amdgpu_device * adev,bool enable)8355 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8356 {
8357 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8358
8359 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8360 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8361 else
8362 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8363
8364 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8365
8366 /*
8367 * CGPG enablement required and the register to program the hysteresis value
8368 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8369 * in refclk count. Note that RLC FW is modified to take 16 bits from
8370 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8371 *
8372 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8373 * of CGPG enablement starting point.
8374 * Power/performance team will optimize it and might give a new value later.
8375 */
8376 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8377 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8378 case IP_VERSION(10, 3, 1):
8379 case IP_VERSION(10, 3, 3):
8380 case IP_VERSION(10, 3, 6):
8381 case IP_VERSION(10, 3, 7):
8382 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8383 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8384 break;
8385 default:
8386 break;
8387 }
8388 }
8389 }
8390
gfx_v10_cntl_pg(struct amdgpu_device * adev,bool enable)8391 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8392 {
8393 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8394
8395 gfx_v10_cntl_power_gating(adev, enable);
8396
8397 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8398 }
8399
8400 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8401 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8402 .set_safe_mode = gfx_v10_0_set_safe_mode,
8403 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8404 .init = gfx_v10_0_rlc_init,
8405 .get_csb_size = gfx_v10_0_get_csb_size,
8406 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8407 .resume = gfx_v10_0_rlc_resume,
8408 .stop = gfx_v10_0_rlc_stop,
8409 .reset = gfx_v10_0_rlc_reset,
8410 .start = gfx_v10_0_rlc_start,
8411 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8412 };
8413
8414 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8415 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8416 .set_safe_mode = gfx_v10_0_set_safe_mode,
8417 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8418 .init = gfx_v10_0_rlc_init,
8419 .get_csb_size = gfx_v10_0_get_csb_size,
8420 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8421 .resume = gfx_v10_0_rlc_resume,
8422 .stop = gfx_v10_0_rlc_stop,
8423 .reset = gfx_v10_0_rlc_reset,
8424 .start = gfx_v10_0_rlc_start,
8425 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8426 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8427 };
8428
gfx_v10_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)8429 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
8430 enum amd_powergating_state state)
8431 {
8432 struct amdgpu_device *adev = ip_block->adev;
8433 bool enable = (state == AMD_PG_STATE_GATE);
8434
8435 if (amdgpu_sriov_vf(adev))
8436 return 0;
8437
8438 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8439 case IP_VERSION(10, 1, 10):
8440 case IP_VERSION(10, 1, 1):
8441 case IP_VERSION(10, 1, 2):
8442 case IP_VERSION(10, 3, 0):
8443 case IP_VERSION(10, 3, 2):
8444 case IP_VERSION(10, 3, 4):
8445 case IP_VERSION(10, 3, 5):
8446 amdgpu_gfx_off_ctrl(adev, enable);
8447 break;
8448 case IP_VERSION(10, 3, 1):
8449 case IP_VERSION(10, 3, 3):
8450 case IP_VERSION(10, 3, 6):
8451 case IP_VERSION(10, 3, 7):
8452 if (!enable)
8453 amdgpu_gfx_off_ctrl(adev, false);
8454
8455 gfx_v10_cntl_pg(adev, enable);
8456
8457 if (enable)
8458 amdgpu_gfx_off_ctrl(adev, true);
8459
8460 break;
8461 default:
8462 break;
8463 }
8464 return 0;
8465 }
8466
gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)8467 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
8468 enum amd_clockgating_state state)
8469 {
8470 struct amdgpu_device *adev = ip_block->adev;
8471
8472 if (amdgpu_sriov_vf(adev))
8473 return 0;
8474
8475 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8476 case IP_VERSION(10, 1, 10):
8477 case IP_VERSION(10, 1, 1):
8478 case IP_VERSION(10, 1, 2):
8479 case IP_VERSION(10, 3, 0):
8480 case IP_VERSION(10, 3, 2):
8481 case IP_VERSION(10, 3, 1):
8482 case IP_VERSION(10, 3, 4):
8483 case IP_VERSION(10, 3, 5):
8484 case IP_VERSION(10, 3, 6):
8485 case IP_VERSION(10, 3, 3):
8486 case IP_VERSION(10, 3, 7):
8487 gfx_v10_0_update_gfx_clock_gating(adev,
8488 state == AMD_CG_STATE_GATE);
8489 break;
8490 default:
8491 break;
8492 }
8493 return 0;
8494 }
8495
gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)8496 static void gfx_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
8497 {
8498 struct amdgpu_device *adev = ip_block->adev;
8499 int data;
8500
8501 /* AMD_CG_SUPPORT_GFX_FGCG */
8502 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8503 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8504 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8505
8506 /* AMD_CG_SUPPORT_GFX_MGCG */
8507 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8508 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8509 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8510
8511 /* AMD_CG_SUPPORT_GFX_CGCG */
8512 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8513 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8514 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8515
8516 /* AMD_CG_SUPPORT_GFX_CGLS */
8517 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8518 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8519
8520 /* AMD_CG_SUPPORT_GFX_RLC_LS */
8521 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8522 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8523 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8524
8525 /* AMD_CG_SUPPORT_GFX_CP_LS */
8526 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8527 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8528 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8529
8530 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8531 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8532 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8533 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8534
8535 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8536 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8537 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8538 }
8539
gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)8540 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8541 {
8542 /* gfx10 is 32bit rptr*/
8543 return *(uint32_t *)ring->rptr_cpu_addr;
8544 }
8545
gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)8546 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8547 {
8548 struct amdgpu_device *adev = ring->adev;
8549 u64 wptr;
8550
8551 /* XXX check if swapping is necessary on BE */
8552 if (ring->use_doorbell) {
8553 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8554 } else {
8555 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8556 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8557 }
8558
8559 return wptr;
8560 }
8561
gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)8562 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8563 {
8564 struct amdgpu_device *adev = ring->adev;
8565
8566 if (ring->use_doorbell) {
8567 /* XXX check if swapping is necessary on BE */
8568 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8569 ring->wptr);
8570 WDOORBELL64(ring->doorbell_index, ring->wptr);
8571 } else {
8572 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8573 lower_32_bits(ring->wptr));
8574 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8575 upper_32_bits(ring->wptr));
8576 }
8577 }
8578
gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring * ring)8579 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8580 {
8581 /* gfx10 hardware is 32bit rptr */
8582 return *(uint32_t *)ring->rptr_cpu_addr;
8583 }
8584
gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring * ring)8585 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8586 {
8587 u64 wptr;
8588
8589 /* XXX check if swapping is necessary on BE */
8590 if (ring->use_doorbell)
8591 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8592 else
8593 BUG();
8594 return wptr;
8595 }
8596
gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring * ring)8597 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8598 {
8599 struct amdgpu_device *adev = ring->adev;
8600
8601 if (ring->use_doorbell) {
8602 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8603 ring->wptr);
8604 WDOORBELL64(ring->doorbell_index, ring->wptr);
8605 } else {
8606 BUG(); /* only DOORBELL method supported on gfx10 now */
8607 }
8608 }
8609
gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)8610 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8611 {
8612 struct amdgpu_device *adev = ring->adev;
8613 u32 ref_and_mask, reg_mem_engine;
8614 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8615
8616 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8617 switch (ring->me) {
8618 case 1:
8619 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8620 break;
8621 case 2:
8622 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8623 break;
8624 default:
8625 return;
8626 }
8627 reg_mem_engine = 0;
8628 } else {
8629 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8630 reg_mem_engine = 1; /* pfp */
8631 }
8632
8633 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8634 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8635 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8636 ref_and_mask, ref_and_mask, 0x20);
8637 }
8638
gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8639 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8640 struct amdgpu_job *job,
8641 struct amdgpu_ib *ib,
8642 uint32_t flags)
8643 {
8644 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8645 u32 header, control = 0;
8646
8647 if (ib->flags & AMDGPU_IB_FLAG_CE)
8648 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8649 else
8650 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8651
8652 control |= ib->length_dw | (vmid << 24);
8653
8654 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8655 control |= INDIRECT_BUFFER_PRE_ENB(1);
8656
8657 if (flags & AMDGPU_IB_PREEMPTED)
8658 control |= INDIRECT_BUFFER_PRE_RESUME(1);
8659
8660 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8661 gfx_v10_0_ring_emit_de_meta(ring,
8662 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8663 }
8664
8665 amdgpu_ring_write(ring, header);
8666 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8667 amdgpu_ring_write(ring,
8668 #ifdef __BIG_ENDIAN
8669 (2 << 0) |
8670 #endif
8671 lower_32_bits(ib->gpu_addr));
8672 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8673 amdgpu_ring_write(ring, control);
8674 }
8675
gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8676 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8677 struct amdgpu_job *job,
8678 struct amdgpu_ib *ib,
8679 uint32_t flags)
8680 {
8681 unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8682 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8683
8684 /* Currently, there is a high possibility to get wave ID mismatch
8685 * between ME and GDS, leading to a hw deadlock, because ME generates
8686 * different wave IDs than the GDS expects. This situation happens
8687 * randomly when at least 5 compute pipes use GDS ordered append.
8688 * The wave IDs generated by ME are also wrong after suspend/resume.
8689 * Those are probably bugs somewhere else in the kernel driver.
8690 *
8691 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8692 * GDS to 0 for this ring (me/pipe).
8693 */
8694 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8695 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8696 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8697 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8698 }
8699
8700 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8701 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8702 amdgpu_ring_write(ring,
8703 #ifdef __BIG_ENDIAN
8704 (2 << 0) |
8705 #endif
8706 lower_32_bits(ib->gpu_addr));
8707 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8708 amdgpu_ring_write(ring, control);
8709 }
8710
gfx_v10_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8711 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8712 u64 seq, unsigned int flags)
8713 {
8714 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8715 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8716
8717 /* RELEASE_MEM - flush caches, send int */
8718 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8719 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8720 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8721 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8722 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8723 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8724 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8725 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8726 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8727 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8728
8729 /*
8730 * the address should be Qword aligned if 64bit write, Dword
8731 * aligned if only send 32bit data low (discard data high)
8732 */
8733 if (write64bit)
8734 BUG_ON(addr & 0x7);
8735 else
8736 BUG_ON(addr & 0x3);
8737 amdgpu_ring_write(ring, lower_32_bits(addr));
8738 amdgpu_ring_write(ring, upper_32_bits(addr));
8739 amdgpu_ring_write(ring, lower_32_bits(seq));
8740 amdgpu_ring_write(ring, upper_32_bits(seq));
8741 amdgpu_ring_write(ring, 0);
8742 }
8743
gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)8744 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8745 {
8746 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8747 uint32_t seq = ring->fence_drv.sync_seq;
8748 uint64_t addr = ring->fence_drv.gpu_addr;
8749
8750 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8751 upper_32_bits(addr), seq, 0xffffffff, 4);
8752 }
8753
gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)8754 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8755 uint16_t pasid, uint32_t flush_type,
8756 bool all_hub, uint8_t dst_sel)
8757 {
8758 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8759 amdgpu_ring_write(ring,
8760 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8761 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8762 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8763 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8764 }
8765
gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)8766 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8767 unsigned int vmid, uint64_t pd_addr)
8768 {
8769 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8770
8771 /* compute doesn't have PFP */
8772 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8773 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8774 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8775 amdgpu_ring_write(ring, 0x0);
8776 }
8777 }
8778
gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8779 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8780 u64 seq, unsigned int flags)
8781 {
8782 struct amdgpu_device *adev = ring->adev;
8783
8784 /* we only allocate 32bit for each seq wb address */
8785 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8786
8787 /* write fence seq to the "addr" */
8788 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8789 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8790 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8791 amdgpu_ring_write(ring, lower_32_bits(addr));
8792 amdgpu_ring_write(ring, upper_32_bits(addr));
8793 amdgpu_ring_write(ring, lower_32_bits(seq));
8794
8795 if (flags & AMDGPU_FENCE_FLAG_INT) {
8796 /* set register to trigger INT */
8797 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8798 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8799 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8800 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8801 amdgpu_ring_write(ring, 0);
8802 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8803 }
8804 }
8805
gfx_v10_0_ring_emit_sb(struct amdgpu_ring * ring)8806 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8807 {
8808 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8809 amdgpu_ring_write(ring, 0);
8810 }
8811
gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)8812 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8813 uint32_t flags)
8814 {
8815 uint32_t dw2 = 0;
8816
8817 if (ring->adev->gfx.mcbp)
8818 gfx_v10_0_ring_emit_ce_meta(ring,
8819 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8820
8821 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8822 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8823 /* set load_global_config & load_global_uconfig */
8824 dw2 |= 0x8001;
8825 /* set load_cs_sh_regs */
8826 dw2 |= 0x01000000;
8827 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8828 dw2 |= 0x10002;
8829
8830 /* set load_ce_ram if preamble presented */
8831 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8832 dw2 |= 0x10000000;
8833 } else {
8834 /* still load_ce_ram if this is the first time preamble presented
8835 * although there is no context switch happens.
8836 */
8837 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8838 dw2 |= 0x10000000;
8839 }
8840
8841 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8842 amdgpu_ring_write(ring, dw2);
8843 amdgpu_ring_write(ring, 0);
8844 }
8845
gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)8846 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8847 uint64_t addr)
8848 {
8849 unsigned int ret;
8850
8851 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8852 amdgpu_ring_write(ring, lower_32_bits(addr));
8853 amdgpu_ring_write(ring, upper_32_bits(addr));
8854 /* discard following DWs if *cond_exec_gpu_addr==0 */
8855 amdgpu_ring_write(ring, 0);
8856 ret = ring->wptr & ring->buf_mask;
8857 /* patch dummy value later */
8858 amdgpu_ring_write(ring, 0);
8859
8860 return ret;
8861 }
8862
gfx_v10_0_ring_preempt_ib(struct amdgpu_ring * ring)8863 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8864 {
8865 int i, r = 0;
8866 struct amdgpu_device *adev = ring->adev;
8867 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8868 struct amdgpu_ring *kiq_ring = &kiq->ring;
8869 unsigned long flags;
8870
8871 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8872 return -EINVAL;
8873
8874 spin_lock_irqsave(&kiq->ring_lock, flags);
8875
8876 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8877 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8878 return -ENOMEM;
8879 }
8880
8881 /* assert preemption condition */
8882 amdgpu_ring_set_preempt_cond_exec(ring, false);
8883
8884 /* assert IB preemption, emit the trailing fence */
8885 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8886 ring->trail_fence_gpu_addr,
8887 ++ring->trail_seq);
8888 amdgpu_ring_commit(kiq_ring);
8889
8890 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8891
8892 /* poll the trailing fence */
8893 for (i = 0; i < adev->usec_timeout; i++) {
8894 if (ring->trail_seq ==
8895 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8896 break;
8897 udelay(1);
8898 }
8899
8900 if (i >= adev->usec_timeout) {
8901 r = -EINVAL;
8902 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8903 }
8904
8905 /* deassert preemption condition */
8906 amdgpu_ring_set_preempt_cond_exec(ring, true);
8907 return r;
8908 }
8909
gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring * ring,bool resume)8910 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8911 {
8912 struct amdgpu_device *adev = ring->adev;
8913 struct v10_ce_ib_state ce_payload = {0};
8914 uint64_t offset, ce_payload_gpu_addr;
8915 void *ce_payload_cpu_addr;
8916 int cnt;
8917
8918 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8919
8920 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8921 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8922 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8923
8924 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8925 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8926 WRITE_DATA_DST_SEL(8) |
8927 WR_CONFIRM) |
8928 WRITE_DATA_CACHE_POLICY(0));
8929 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8930 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8931
8932 if (resume)
8933 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8934 sizeof(ce_payload) >> 2);
8935 else
8936 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8937 sizeof(ce_payload) >> 2);
8938 }
8939
gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring * ring,bool resume)8940 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8941 {
8942 struct amdgpu_device *adev = ring->adev;
8943 struct v10_de_ib_state de_payload = {0};
8944 uint64_t offset, gds_addr, de_payload_gpu_addr;
8945 void *de_payload_cpu_addr;
8946 int cnt;
8947
8948 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8949 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8950 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8951
8952 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8953 AMDGPU_CSA_SIZE - adev->gds.gds_size,
8954 PAGE_SIZE);
8955
8956 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8957 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8958
8959 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8960 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8961 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8962 WRITE_DATA_DST_SEL(8) |
8963 WR_CONFIRM) |
8964 WRITE_DATA_CACHE_POLICY(0));
8965 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8966 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8967
8968 if (resume)
8969 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8970 sizeof(de_payload) >> 2);
8971 else
8972 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8973 sizeof(de_payload) >> 2);
8974 }
8975
gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)8976 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8977 bool secure)
8978 {
8979 uint32_t v = secure ? FRAME_TMZ : 0;
8980
8981 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8982 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8983 }
8984
gfx_v10_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)8985 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8986 uint32_t reg_val_offs)
8987 {
8988 struct amdgpu_device *adev = ring->adev;
8989
8990 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8991 amdgpu_ring_write(ring, 0 | /* src: register*/
8992 (5 << 8) | /* dst: memory */
8993 (1 << 20)); /* write confirm */
8994 amdgpu_ring_write(ring, reg);
8995 amdgpu_ring_write(ring, 0);
8996 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8997 reg_val_offs * 4));
8998 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8999 reg_val_offs * 4));
9000 }
9001
gfx_v10_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)9002 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
9003 uint32_t val)
9004 {
9005 uint32_t cmd = 0;
9006
9007 switch (ring->funcs->type) {
9008 case AMDGPU_RING_TYPE_GFX:
9009 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
9010 break;
9011 case AMDGPU_RING_TYPE_KIQ:
9012 cmd = (1 << 16); /* no inc addr */
9013 break;
9014 default:
9015 cmd = WR_CONFIRM;
9016 break;
9017 }
9018 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9019 amdgpu_ring_write(ring, cmd);
9020 amdgpu_ring_write(ring, reg);
9021 amdgpu_ring_write(ring, 0);
9022 amdgpu_ring_write(ring, val);
9023 }
9024
gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)9025 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9026 uint32_t val, uint32_t mask)
9027 {
9028 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9029 }
9030
gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)9031 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9032 uint32_t reg0, uint32_t reg1,
9033 uint32_t ref, uint32_t mask)
9034 {
9035 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9036 struct amdgpu_device *adev = ring->adev;
9037 bool fw_version_ok = false;
9038
9039 fw_version_ok = adev->gfx.cp_fw_write_wait;
9040
9041 if (fw_version_ok)
9042 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9043 ref, mask, 0x20);
9044 else
9045 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9046 ref, mask);
9047 }
9048
gfx_v10_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned int vmid)9049 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9050 unsigned int vmid)
9051 {
9052 struct amdgpu_device *adev = ring->adev;
9053 uint32_t value = 0;
9054
9055 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9056 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9057 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9058 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9059 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9060 WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9061 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9062 }
9063
9064 static void
gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)9065 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9066 uint32_t me, uint32_t pipe,
9067 enum amdgpu_interrupt_state state)
9068 {
9069 uint32_t cp_int_cntl, cp_int_cntl_reg;
9070
9071 if (!me) {
9072 switch (pipe) {
9073 case 0:
9074 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9075 break;
9076 case 1:
9077 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9078 break;
9079 default:
9080 DRM_DEBUG("invalid pipe %d\n", pipe);
9081 return;
9082 }
9083 } else {
9084 DRM_DEBUG("invalid me %d\n", me);
9085 return;
9086 }
9087
9088 switch (state) {
9089 case AMDGPU_IRQ_STATE_DISABLE:
9090 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9091 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9092 TIME_STAMP_INT_ENABLE, 0);
9093 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9094 break;
9095 case AMDGPU_IRQ_STATE_ENABLE:
9096 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9097 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9098 TIME_STAMP_INT_ENABLE, 1);
9099 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9100 break;
9101 default:
9102 break;
9103 }
9104 }
9105
gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)9106 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9107 int me, int pipe,
9108 enum amdgpu_interrupt_state state)
9109 {
9110 u32 mec_int_cntl, mec_int_cntl_reg;
9111
9112 /*
9113 * amdgpu controls only the first MEC. That's why this function only
9114 * handles the setting of interrupts for this specific MEC. All other
9115 * pipes' interrupts are set by amdkfd.
9116 */
9117
9118 if (me == 1) {
9119 switch (pipe) {
9120 case 0:
9121 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9122 break;
9123 case 1:
9124 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9125 break;
9126 case 2:
9127 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9128 break;
9129 case 3:
9130 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9131 break;
9132 default:
9133 DRM_DEBUG("invalid pipe %d\n", pipe);
9134 return;
9135 }
9136 } else {
9137 DRM_DEBUG("invalid me %d\n", me);
9138 return;
9139 }
9140
9141 switch (state) {
9142 case AMDGPU_IRQ_STATE_DISABLE:
9143 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9144 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9145 TIME_STAMP_INT_ENABLE, 0);
9146 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9147 break;
9148 case AMDGPU_IRQ_STATE_ENABLE:
9149 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9150 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9151 TIME_STAMP_INT_ENABLE, 1);
9152 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9153 break;
9154 default:
9155 break;
9156 }
9157 }
9158
gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)9159 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9160 struct amdgpu_irq_src *src,
9161 unsigned int type,
9162 enum amdgpu_interrupt_state state)
9163 {
9164 switch (type) {
9165 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9166 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9167 break;
9168 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9169 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9170 break;
9171 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9172 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9173 break;
9174 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9175 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9176 break;
9177 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9178 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9179 break;
9180 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9181 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9182 break;
9183 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9184 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9185 break;
9186 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9187 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9188 break;
9189 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9190 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9191 break;
9192 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9193 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9194 break;
9195 default:
9196 break;
9197 }
9198 return 0;
9199 }
9200
gfx_v10_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9201 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9202 struct amdgpu_irq_src *source,
9203 struct amdgpu_iv_entry *entry)
9204 {
9205 int i;
9206 u8 me_id, pipe_id, queue_id;
9207 struct amdgpu_ring *ring;
9208
9209 DRM_DEBUG("IH: CP EOP\n");
9210
9211 me_id = (entry->ring_id & 0x0c) >> 2;
9212 pipe_id = (entry->ring_id & 0x03) >> 0;
9213 queue_id = (entry->ring_id & 0x70) >> 4;
9214
9215 switch (me_id) {
9216 case 0:
9217 if (pipe_id == 0)
9218 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9219 else
9220 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9221 break;
9222 case 1:
9223 case 2:
9224 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9225 ring = &adev->gfx.compute_ring[i];
9226 /* Per-queue interrupt is supported for MEC starting from VI.
9227 * The interrupt can only be enabled/disabled per pipe instead
9228 * of per queue.
9229 */
9230 if ((ring->me == me_id) &&
9231 (ring->pipe == pipe_id) &&
9232 (ring->queue == queue_id))
9233 amdgpu_fence_process(ring);
9234 }
9235 break;
9236 }
9237
9238 return 0;
9239 }
9240
gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)9241 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9242 struct amdgpu_irq_src *source,
9243 unsigned int type,
9244 enum amdgpu_interrupt_state state)
9245 {
9246 u32 cp_int_cntl_reg, cp_int_cntl;
9247 int i, j;
9248
9249 switch (state) {
9250 case AMDGPU_IRQ_STATE_DISABLE:
9251 case AMDGPU_IRQ_STATE_ENABLE:
9252 for (i = 0; i < adev->gfx.me.num_me; i++) {
9253 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9254 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9255
9256 if (cp_int_cntl_reg) {
9257 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9258 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9259 PRIV_REG_INT_ENABLE,
9260 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9261 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9262 }
9263 }
9264 }
9265 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9266 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9267 /* MECs start at 1 */
9268 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9269
9270 if (cp_int_cntl_reg) {
9271 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9272 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9273 PRIV_REG_INT_ENABLE,
9274 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9275 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9276 }
9277 }
9278 }
9279 break;
9280 default:
9281 break;
9282 }
9283
9284 return 0;
9285 }
9286
gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)9287 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
9288 struct amdgpu_irq_src *source,
9289 unsigned type,
9290 enum amdgpu_interrupt_state state)
9291 {
9292 u32 cp_int_cntl_reg, cp_int_cntl;
9293 int i, j;
9294
9295 switch (state) {
9296 case AMDGPU_IRQ_STATE_DISABLE:
9297 case AMDGPU_IRQ_STATE_ENABLE:
9298 for (i = 0; i < adev->gfx.me.num_me; i++) {
9299 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9300 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9301
9302 if (cp_int_cntl_reg) {
9303 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9304 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9305 OPCODE_ERROR_INT_ENABLE,
9306 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9307 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9308 }
9309 }
9310 }
9311 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9312 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9313 /* MECs start at 1 */
9314 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9315
9316 if (cp_int_cntl_reg) {
9317 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9318 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9319 OPCODE_ERROR_INT_ENABLE,
9320 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9321 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9322 }
9323 }
9324 }
9325 break;
9326 default:
9327 break;
9328 }
9329 return 0;
9330 }
9331
gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)9332 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9333 struct amdgpu_irq_src *source,
9334 unsigned int type,
9335 enum amdgpu_interrupt_state state)
9336 {
9337 u32 cp_int_cntl_reg, cp_int_cntl;
9338 int i, j;
9339
9340 switch (state) {
9341 case AMDGPU_IRQ_STATE_DISABLE:
9342 case AMDGPU_IRQ_STATE_ENABLE:
9343 for (i = 0; i < adev->gfx.me.num_me; i++) {
9344 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9345 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9346
9347 if (cp_int_cntl_reg) {
9348 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9349 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9350 PRIV_INSTR_INT_ENABLE,
9351 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9352 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9353 }
9354 }
9355 }
9356 break;
9357 default:
9358 break;
9359 }
9360
9361 return 0;
9362 }
9363
gfx_v10_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)9364 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9365 struct amdgpu_iv_entry *entry)
9366 {
9367 u8 me_id, pipe_id, queue_id;
9368 struct amdgpu_ring *ring;
9369 int i;
9370
9371 me_id = (entry->ring_id & 0x0c) >> 2;
9372 pipe_id = (entry->ring_id & 0x03) >> 0;
9373 queue_id = (entry->ring_id & 0x70) >> 4;
9374
9375 switch (me_id) {
9376 case 0:
9377 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9378 ring = &adev->gfx.gfx_ring[i];
9379 if (ring->me == me_id && ring->pipe == pipe_id &&
9380 ring->queue == queue_id)
9381 drm_sched_fault(&ring->sched);
9382 }
9383 break;
9384 case 1:
9385 case 2:
9386 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9387 ring = &adev->gfx.compute_ring[i];
9388 if (ring->me == me_id && ring->pipe == pipe_id &&
9389 ring->queue == queue_id)
9390 drm_sched_fault(&ring->sched);
9391 }
9392 break;
9393 default:
9394 BUG();
9395 }
9396 }
9397
gfx_v10_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9398 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9399 struct amdgpu_irq_src *source,
9400 struct amdgpu_iv_entry *entry)
9401 {
9402 DRM_ERROR("Illegal register access in command stream\n");
9403 gfx_v10_0_handle_priv_fault(adev, entry);
9404 return 0;
9405 }
9406
gfx_v10_0_bad_op_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9407 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
9408 struct amdgpu_irq_src *source,
9409 struct amdgpu_iv_entry *entry)
9410 {
9411 DRM_ERROR("Illegal opcode in command stream \n");
9412 gfx_v10_0_handle_priv_fault(adev, entry);
9413 return 0;
9414 }
9415
gfx_v10_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9416 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9417 struct amdgpu_irq_src *source,
9418 struct amdgpu_iv_entry *entry)
9419 {
9420 DRM_ERROR("Illegal instruction in command stream\n");
9421 gfx_v10_0_handle_priv_fault(adev, entry);
9422 return 0;
9423 }
9424
gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)9425 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9426 struct amdgpu_irq_src *src,
9427 unsigned int type,
9428 enum amdgpu_interrupt_state state)
9429 {
9430 uint32_t tmp, target;
9431 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9432
9433 if (ring->me == 1)
9434 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9435 else
9436 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9437 target += ring->pipe;
9438
9439 switch (type) {
9440 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9441 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9442 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9443 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9444 GENERIC2_INT_ENABLE, 0);
9445 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9446
9447 tmp = RREG32_SOC15_IP(GC, target);
9448 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9449 GENERIC2_INT_ENABLE, 0);
9450 WREG32_SOC15_IP(GC, target, tmp);
9451 } else {
9452 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9453 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9454 GENERIC2_INT_ENABLE, 1);
9455 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9456
9457 tmp = RREG32_SOC15_IP(GC, target);
9458 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9459 GENERIC2_INT_ENABLE, 1);
9460 WREG32_SOC15_IP(GC, target, tmp);
9461 }
9462 break;
9463 default:
9464 BUG(); /* kiq only support GENERIC2_INT now */
9465 break;
9466 }
9467 return 0;
9468 }
9469
gfx_v10_0_kiq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9470 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9471 struct amdgpu_irq_src *source,
9472 struct amdgpu_iv_entry *entry)
9473 {
9474 u8 me_id, pipe_id, queue_id;
9475 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9476
9477 me_id = (entry->ring_id & 0x0c) >> 2;
9478 pipe_id = (entry->ring_id & 0x03) >> 0;
9479 queue_id = (entry->ring_id & 0x70) >> 4;
9480 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9481 me_id, pipe_id, queue_id);
9482
9483 amdgpu_fence_process(ring);
9484 return 0;
9485 }
9486
gfx_v10_0_emit_mem_sync(struct amdgpu_ring * ring)9487 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9488 {
9489 const unsigned int gcr_cntl =
9490 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9491 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9492 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9493 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9494 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9495 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9496 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9497 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9498
9499 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9500 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9501 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9502 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9503 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9504 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9505 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9506 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9507 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9508 }
9509
gfx_v10_ring_insert_nop(struct amdgpu_ring * ring,uint32_t num_nop)9510 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
9511 {
9512 /* Header itself is a NOP packet */
9513 if (num_nop == 1) {
9514 amdgpu_ring_write(ring, ring->funcs->nop);
9515 return;
9516 }
9517
9518 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
9519 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
9520
9521 /* Header is at index 0, followed by num_nops - 1 NOP packet's */
9522 amdgpu_ring_insert_nop(ring, num_nop - 1);
9523 }
9524
gfx_v10_0_reset_kgq(struct amdgpu_ring * ring,unsigned int vmid)9525 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
9526 {
9527 struct amdgpu_device *adev = ring->adev;
9528 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9529 struct amdgpu_ring *kiq_ring = &kiq->ring;
9530 unsigned long flags;
9531 u32 tmp;
9532 u64 addr;
9533 int r;
9534
9535 if (amdgpu_sriov_vf(adev))
9536 return -EINVAL;
9537
9538 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9539 return -EINVAL;
9540
9541 spin_lock_irqsave(&kiq->ring_lock, flags);
9542
9543 if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
9544 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9545 return -ENOMEM;
9546 }
9547
9548 addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +
9549 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);
9550 tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
9551 if (ring->pipe == 0)
9552 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
9553 else
9554 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
9555
9556 gfx_v10_0_ring_emit_wreg(kiq_ring,
9557 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
9558 gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,
9559 lower_32_bits(addr), upper_32_bits(addr),
9560 0, 1, 0x20);
9561 gfx_v10_0_ring_emit_reg_wait(kiq_ring,
9562 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
9563 kiq->pmf->kiq_map_queues(kiq_ring, ring);
9564 amdgpu_ring_commit(kiq_ring);
9565
9566 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9567
9568 r = amdgpu_ring_test_ring(kiq_ring);
9569 if (r)
9570 return r;
9571
9572 r = gfx_v10_0_kgq_init_queue(ring, true);
9573 if (r) {
9574 DRM_ERROR("fail to init kgq\n");
9575 return r;
9576 }
9577
9578 return amdgpu_ring_test_ring(ring);
9579 }
9580
gfx_v10_0_reset_kcq(struct amdgpu_ring * ring,unsigned int vmid)9581 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
9582 unsigned int vmid)
9583 {
9584 struct amdgpu_device *adev = ring->adev;
9585 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9586 struct amdgpu_ring *kiq_ring = &kiq->ring;
9587 unsigned long flags;
9588 int i, r;
9589
9590 if (amdgpu_sriov_vf(adev))
9591 return -EINVAL;
9592
9593 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9594 return -EINVAL;
9595
9596 spin_lock_irqsave(&kiq->ring_lock, flags);
9597
9598 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
9599 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9600 return -ENOMEM;
9601 }
9602
9603 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
9604 0, 0);
9605 amdgpu_ring_commit(kiq_ring);
9606 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9607
9608 r = amdgpu_ring_test_ring(kiq_ring);
9609 if (r)
9610 return r;
9611
9612 /* make sure dequeue is complete*/
9613 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9614 mutex_lock(&adev->srbm_mutex);
9615 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
9616 for (i = 0; i < adev->usec_timeout; i++) {
9617 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
9618 break;
9619 udelay(1);
9620 }
9621 if (i >= adev->usec_timeout)
9622 r = -ETIMEDOUT;
9623 nv_grbm_select(adev, 0, 0, 0, 0);
9624 mutex_unlock(&adev->srbm_mutex);
9625 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9626 if (r) {
9627 dev_err(adev->dev, "fail to wait on hqd deactivate\n");
9628 return r;
9629 }
9630
9631 r = gfx_v10_0_kcq_init_queue(ring, true);
9632 if (r) {
9633 dev_err(adev->dev, "fail to init kcq\n");
9634 return r;
9635 }
9636
9637 spin_lock_irqsave(&kiq->ring_lock, flags);
9638 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
9639 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9640 return -ENOMEM;
9641 }
9642 kiq->pmf->kiq_map_queues(kiq_ring, ring);
9643 amdgpu_ring_commit(kiq_ring);
9644 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9645
9646 r = amdgpu_ring_test_ring(kiq_ring);
9647 if (r)
9648 return r;
9649
9650 return amdgpu_ring_test_ring(ring);
9651 }
9652
gfx_v10_ip_print(struct amdgpu_ip_block * ip_block,struct drm_printer * p)9653 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
9654 {
9655 struct amdgpu_device *adev = ip_block->adev;
9656 uint32_t i, j, k, reg, index = 0;
9657 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9658
9659 if (!adev->gfx.ip_dump_core)
9660 return;
9661
9662 for (i = 0; i < reg_count; i++)
9663 drm_printf(p, "%-50s \t 0x%08x\n",
9664 gc_reg_list_10_1[i].reg_name,
9665 adev->gfx.ip_dump_core[i]);
9666
9667 /* print compute queue registers for all instances */
9668 if (!adev->gfx.ip_dump_compute_queues)
9669 return;
9670
9671 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9672 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
9673 adev->gfx.mec.num_mec,
9674 adev->gfx.mec.num_pipe_per_mec,
9675 adev->gfx.mec.num_queue_per_pipe);
9676
9677 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9678 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9679 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9680 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
9681 for (reg = 0; reg < reg_count; reg++) {
9682 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
9683 drm_printf(p, "%-50s \t 0x%08x\n",
9684 "mmCP_MEC_ME2_HEADER_DUMP",
9685 adev->gfx.ip_dump_compute_queues[index + reg]);
9686 else
9687 drm_printf(p, "%-50s \t 0x%08x\n",
9688 gc_cp_reg_list_10[reg].reg_name,
9689 adev->gfx.ip_dump_compute_queues[index + reg]);
9690 }
9691 index += reg_count;
9692 }
9693 }
9694 }
9695
9696 /* print gfx queue registers for all instances */
9697 if (!adev->gfx.ip_dump_gfx_queues)
9698 return;
9699
9700 index = 0;
9701 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9702 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
9703 adev->gfx.me.num_me,
9704 adev->gfx.me.num_pipe_per_me,
9705 adev->gfx.me.num_queue_per_pipe);
9706
9707 for (i = 0; i < adev->gfx.me.num_me; i++) {
9708 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9709 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9710 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
9711 for (reg = 0; reg < reg_count; reg++) {
9712 drm_printf(p, "%-50s \t 0x%08x\n",
9713 gc_gfx_queue_reg_list_10[reg].reg_name,
9714 adev->gfx.ip_dump_gfx_queues[index + reg]);
9715 }
9716 index += reg_count;
9717 }
9718 }
9719 }
9720 }
9721
gfx_v10_ip_dump(struct amdgpu_ip_block * ip_block)9722 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
9723 {
9724 struct amdgpu_device *adev = ip_block->adev;
9725 uint32_t i, j, k, reg, index = 0;
9726 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9727
9728 if (!adev->gfx.ip_dump_core)
9729 return;
9730
9731 amdgpu_gfx_off_ctrl(adev, false);
9732 for (i = 0; i < reg_count; i++)
9733 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9734 amdgpu_gfx_off_ctrl(adev, true);
9735
9736 /* dump compute queue registers for all instances */
9737 if (!adev->gfx.ip_dump_compute_queues)
9738 return;
9739
9740 reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9741 amdgpu_gfx_off_ctrl(adev, false);
9742 mutex_lock(&adev->srbm_mutex);
9743 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9744 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9745 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9746 /* ME0 is for GFX so start from 1 for CP */
9747 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
9748
9749 for (reg = 0; reg < reg_count; reg++) {
9750 if (i && gc_cp_reg_list_10[reg].reg_offset == mmCP_MEC_ME1_HEADER_DUMP)
9751 adev->gfx.ip_dump_compute_queues[index + reg] =
9752 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));
9753 else
9754 adev->gfx.ip_dump_compute_queues[index + reg] =
9755 RREG32(SOC15_REG_ENTRY_OFFSET(
9756 gc_cp_reg_list_10[reg]));
9757 }
9758 index += reg_count;
9759 }
9760 }
9761 }
9762 nv_grbm_select(adev, 0, 0, 0, 0);
9763 mutex_unlock(&adev->srbm_mutex);
9764 amdgpu_gfx_off_ctrl(adev, true);
9765
9766 /* dump gfx queue registers for all instances */
9767 if (!adev->gfx.ip_dump_gfx_queues)
9768 return;
9769
9770 index = 0;
9771 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9772 amdgpu_gfx_off_ctrl(adev, false);
9773 mutex_lock(&adev->srbm_mutex);
9774 for (i = 0; i < adev->gfx.me.num_me; i++) {
9775 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9776 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9777 nv_grbm_select(adev, i, j, k, 0);
9778
9779 for (reg = 0; reg < reg_count; reg++) {
9780 adev->gfx.ip_dump_gfx_queues[index + reg] =
9781 RREG32(SOC15_REG_ENTRY_OFFSET(
9782 gc_gfx_queue_reg_list_10[reg]));
9783 }
9784 index += reg_count;
9785 }
9786 }
9787 }
9788 nv_grbm_select(adev, 0, 0, 0, 0);
9789 mutex_unlock(&adev->srbm_mutex);
9790 amdgpu_gfx_off_ctrl(adev, true);
9791 }
9792
gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring * ring)9793 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
9794 {
9795 /* Emit the cleaner shader */
9796 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
9797 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
9798 }
9799
gfx_v10_0_ring_begin_use(struct amdgpu_ring * ring)9800 static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring)
9801 {
9802 amdgpu_gfx_profile_ring_begin_use(ring);
9803
9804 amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
9805 }
9806
gfx_v10_0_ring_end_use(struct amdgpu_ring * ring)9807 static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring)
9808 {
9809 amdgpu_gfx_profile_ring_end_use(ring);
9810
9811 amdgpu_gfx_enforce_isolation_ring_end_use(ring);
9812 }
9813
9814 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9815 .name = "gfx_v10_0",
9816 .early_init = gfx_v10_0_early_init,
9817 .late_init = gfx_v10_0_late_init,
9818 .sw_init = gfx_v10_0_sw_init,
9819 .sw_fini = gfx_v10_0_sw_fini,
9820 .hw_init = gfx_v10_0_hw_init,
9821 .hw_fini = gfx_v10_0_hw_fini,
9822 .suspend = gfx_v10_0_suspend,
9823 .resume = gfx_v10_0_resume,
9824 .is_idle = gfx_v10_0_is_idle,
9825 .wait_for_idle = gfx_v10_0_wait_for_idle,
9826 .soft_reset = gfx_v10_0_soft_reset,
9827 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9828 .set_powergating_state = gfx_v10_0_set_powergating_state,
9829 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9830 .dump_ip_state = gfx_v10_ip_dump,
9831 .print_ip_state = gfx_v10_ip_print,
9832 };
9833
9834 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9835 .type = AMDGPU_RING_TYPE_GFX,
9836 .align_mask = 0xff,
9837 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9838 .support_64bit_ptrs = true,
9839 .secure_submission_supported = true,
9840 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9841 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9842 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9843 .emit_frame_size = /* totally 242 maximum if 16 IBs */
9844 5 + /* COND_EXEC */
9845 7 + /* PIPELINE_SYNC */
9846 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9847 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9848 4 + /* VM_FLUSH */
9849 8 + /* FENCE for VM_FLUSH */
9850 20 + /* GDS switch */
9851 4 + /* double SWITCH_BUFFER,
9852 * the first COND_EXEC jump to the place
9853 * just prior to this double SWITCH_BUFFER
9854 */
9855 5 + /* COND_EXEC */
9856 7 + /* HDP_flush */
9857 4 + /* VGT_flush */
9858 14 + /* CE_META */
9859 31 + /* DE_META */
9860 3 + /* CNTX_CTRL */
9861 5 + /* HDP_INVL */
9862 8 + 8 + /* FENCE x2 */
9863 2 + /* SWITCH_BUFFER */
9864 8 + /* gfx_v10_0_emit_mem_sync */
9865 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9866 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9867 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9868 .emit_fence = gfx_v10_0_ring_emit_fence,
9869 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9870 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9871 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9872 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9873 .test_ring = gfx_v10_0_ring_test_ring,
9874 .test_ib = gfx_v10_0_ring_test_ib,
9875 .insert_nop = gfx_v10_ring_insert_nop,
9876 .pad_ib = amdgpu_ring_generic_pad_ib,
9877 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9878 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9879 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9880 .preempt_ib = gfx_v10_0_ring_preempt_ib,
9881 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9882 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9883 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9884 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9885 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9886 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9887 .reset = gfx_v10_0_reset_kgq,
9888 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9889 .begin_use = gfx_v10_0_ring_begin_use,
9890 .end_use = gfx_v10_0_ring_end_use,
9891 };
9892
9893 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9894 .type = AMDGPU_RING_TYPE_COMPUTE,
9895 .align_mask = 0xff,
9896 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9897 .support_64bit_ptrs = true,
9898 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9899 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9900 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9901 .emit_frame_size =
9902 20 + /* gfx_v10_0_ring_emit_gds_switch */
9903 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9904 5 + /* hdp invalidate */
9905 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9906 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9907 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9908 2 + /* gfx_v10_0_ring_emit_vm_flush */
9909 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9910 8 + /* gfx_v10_0_emit_mem_sync */
9911 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9912 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9913 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9914 .emit_fence = gfx_v10_0_ring_emit_fence,
9915 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9916 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9917 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9918 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9919 .test_ring = gfx_v10_0_ring_test_ring,
9920 .test_ib = gfx_v10_0_ring_test_ib,
9921 .insert_nop = gfx_v10_ring_insert_nop,
9922 .pad_ib = amdgpu_ring_generic_pad_ib,
9923 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9924 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9925 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9926 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9927 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9928 .reset = gfx_v10_0_reset_kcq,
9929 .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9930 .begin_use = gfx_v10_0_ring_begin_use,
9931 .end_use = gfx_v10_0_ring_end_use,
9932 };
9933
9934 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9935 .type = AMDGPU_RING_TYPE_KIQ,
9936 .align_mask = 0xff,
9937 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9938 .support_64bit_ptrs = true,
9939 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9940 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9941 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9942 .emit_frame_size =
9943 20 + /* gfx_v10_0_ring_emit_gds_switch */
9944 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9945 5 + /*hdp invalidate */
9946 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9947 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9948 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9949 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9950 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9951 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9952 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9953 .test_ring = gfx_v10_0_ring_test_ring,
9954 .test_ib = gfx_v10_0_ring_test_ib,
9955 .insert_nop = amdgpu_ring_insert_nop,
9956 .pad_ib = amdgpu_ring_generic_pad_ib,
9957 .emit_rreg = gfx_v10_0_ring_emit_rreg,
9958 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9959 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9960 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9961 };
9962
gfx_v10_0_set_ring_funcs(struct amdgpu_device * adev)9963 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9964 {
9965 int i;
9966
9967 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9968
9969 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9970 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9971
9972 for (i = 0; i < adev->gfx.num_compute_rings; i++)
9973 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9974 }
9975
9976 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9977 .set = gfx_v10_0_set_eop_interrupt_state,
9978 .process = gfx_v10_0_eop_irq,
9979 };
9980
9981 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9982 .set = gfx_v10_0_set_priv_reg_fault_state,
9983 .process = gfx_v10_0_priv_reg_irq,
9984 };
9985
9986 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
9987 .set = gfx_v10_0_set_bad_op_fault_state,
9988 .process = gfx_v10_0_bad_op_irq,
9989 };
9990
9991 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9992 .set = gfx_v10_0_set_priv_inst_fault_state,
9993 .process = gfx_v10_0_priv_inst_irq,
9994 };
9995
9996 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9997 .set = gfx_v10_0_kiq_set_interrupt_state,
9998 .process = gfx_v10_0_kiq_irq,
9999 };
10000
gfx_v10_0_set_irq_funcs(struct amdgpu_device * adev)10001 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
10002 {
10003 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
10004 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
10005
10006 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
10007 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
10008
10009 adev->gfx.priv_reg_irq.num_types = 1;
10010 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
10011
10012 adev->gfx.bad_op_irq.num_types = 1;
10013 adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
10014
10015 adev->gfx.priv_inst_irq.num_types = 1;
10016 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
10017 }
10018
gfx_v10_0_set_rlc_funcs(struct amdgpu_device * adev)10019 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
10020 {
10021 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
10022 case IP_VERSION(10, 1, 10):
10023 case IP_VERSION(10, 1, 1):
10024 case IP_VERSION(10, 1, 3):
10025 case IP_VERSION(10, 1, 4):
10026 case IP_VERSION(10, 3, 2):
10027 case IP_VERSION(10, 3, 1):
10028 case IP_VERSION(10, 3, 4):
10029 case IP_VERSION(10, 3, 5):
10030 case IP_VERSION(10, 3, 6):
10031 case IP_VERSION(10, 3, 3):
10032 case IP_VERSION(10, 3, 7):
10033 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
10034 break;
10035 case IP_VERSION(10, 1, 2):
10036 case IP_VERSION(10, 3, 0):
10037 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
10038 break;
10039 default:
10040 break;
10041 }
10042 }
10043
gfx_v10_0_set_gds_init(struct amdgpu_device * adev)10044 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
10045 {
10046 unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
10047 adev->gfx.config.max_sh_per_se *
10048 adev->gfx.config.max_shader_engines;
10049
10050 adev->gds.gds_size = 0x10000;
10051 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
10052 adev->gds.gws_size = 64;
10053 adev->gds.oa_size = 16;
10054 }
10055
gfx_v10_0_set_mqd_funcs(struct amdgpu_device * adev)10056 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
10057 {
10058 /* set gfx eng mqd */
10059 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
10060 sizeof(struct v10_gfx_mqd);
10061 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
10062 gfx_v10_0_gfx_mqd_init;
10063 /* set compute eng mqd */
10064 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
10065 sizeof(struct v10_compute_mqd);
10066 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
10067 gfx_v10_0_compute_mqd_init;
10068 }
10069
gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)10070 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
10071 u32 bitmap)
10072 {
10073 u32 data;
10074
10075 if (!bitmap)
10076 return;
10077
10078 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10079 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10080
10081 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
10082 }
10083
gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)10084 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
10085 {
10086 u32 disabled_mask =
10087 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
10088 u32 efuse_setting = 0;
10089 u32 vbios_setting = 0;
10090
10091 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
10092 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10093 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10094
10095 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
10096 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10097 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10098
10099 disabled_mask |= efuse_setting | vbios_setting;
10100
10101 return (~disabled_mask);
10102 }
10103
gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)10104 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
10105 {
10106 u32 wgp_idx, wgp_active_bitmap;
10107 u32 cu_bitmap_per_wgp, cu_active_bitmap;
10108
10109 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
10110 cu_active_bitmap = 0;
10111
10112 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
10113 /* if there is one WGP enabled, it means 2 CUs will be enabled */
10114 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
10115 if (wgp_active_bitmap & (1 << wgp_idx))
10116 cu_active_bitmap |= cu_bitmap_per_wgp;
10117 }
10118
10119 return cu_active_bitmap;
10120 }
10121
gfx_v10_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)10122 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
10123 struct amdgpu_cu_info *cu_info)
10124 {
10125 int i, j, k, counter, active_cu_number = 0;
10126 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
10127 unsigned int disable_masks[4 * 2];
10128
10129 if (!adev || !cu_info)
10130 return -EINVAL;
10131
10132 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
10133
10134 mutex_lock(&adev->grbm_idx_mutex);
10135 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
10136 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
10137 bitmap = i * adev->gfx.config.max_sh_per_se + j;
10138 if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
10139 IP_VERSION(10, 3, 0)) ||
10140 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10141 IP_VERSION(10, 3, 3)) ||
10142 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10143 IP_VERSION(10, 3, 6)) ||
10144 (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10145 IP_VERSION(10, 3, 7))) &&
10146 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
10147 continue;
10148 mask = 1;
10149 ao_bitmap = 0;
10150 counter = 0;
10151 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
10152 if (i < 4 && j < 2)
10153 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
10154 adev, disable_masks[i * 2 + j]);
10155 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
10156 cu_info->bitmap[0][i][j] = bitmap;
10157
10158 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
10159 if (bitmap & mask) {
10160 if (counter < adev->gfx.config.max_cu_per_sh)
10161 ao_bitmap |= mask;
10162 counter++;
10163 }
10164 mask <<= 1;
10165 }
10166 active_cu_number += counter;
10167 if (i < 2 && j < 2)
10168 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
10169 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
10170 }
10171 }
10172 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
10173 mutex_unlock(&adev->grbm_idx_mutex);
10174
10175 cu_info->number = active_cu_number;
10176 cu_info->ao_cu_mask = ao_cu_mask;
10177 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
10178
10179 return 0;
10180 }
10181
gfx_v10_3_get_disabled_sa(struct amdgpu_device * adev)10182 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
10183 {
10184 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
10185
10186 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
10187 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10188 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10189
10190 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
10191 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10192 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10193
10194 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
10195 adev->gfx.config.max_shader_engines);
10196 disabled_sa = efuse_setting | vbios_setting;
10197 disabled_sa &= max_sa_mask;
10198
10199 return disabled_sa;
10200 }
10201
gfx_v10_3_program_pbb_mode(struct amdgpu_device * adev)10202 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
10203 {
10204 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
10205 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
10206
10207 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
10208
10209 max_sa_per_se = adev->gfx.config.max_sh_per_se;
10210 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
10211 max_shader_engines = adev->gfx.config.max_shader_engines;
10212
10213 for (se_index = 0; max_shader_engines > se_index; se_index++) {
10214 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
10215 disabled_sa_per_se &= max_sa_per_se_mask;
10216 if (disabled_sa_per_se == max_sa_per_se_mask) {
10217 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
10218 break;
10219 }
10220 }
10221 }
10222
gfx_v10_3_set_power_brake_sequence(struct amdgpu_device * adev)10223 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
10224 {
10225 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
10226 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
10227 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
10228 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
10229
10230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
10231 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
10232 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
10233 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
10234 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
10235 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
10236
10237 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
10238 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
10239 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
10240 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
10241
10242 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
10243
10244 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
10245 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
10246 }
10247
10248 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
10249 .type = AMD_IP_BLOCK_TYPE_GFX,
10250 .major = 10,
10251 .minor = 0,
10252 .rev = 0,
10253 .funcs = &gfx_v10_0_ip_funcs,
10254 };
10255