1 /*-
2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2014 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Semihalf
7 * under sponsorship of the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/proc.h>
36 #include <sys/pcpu.h>
37 #include <sys/sbuf.h>
38 #include <sys/smp.h>
39 #include <sys/sysctl.h>
40 #include <sys/sysent.h>
41 #include <sys/systm.h>
42
43 #include <machine/atomic.h>
44 #include <machine/cpu.h>
45 #include <machine/cpu_feat.h>
46 #include <machine/cpufunc.h>
47 #include <machine/elf.h>
48 #include <machine/md_var.h>
49 #include <machine/undefined.h>
50
51 static MALLOC_DEFINE(M_IDENTCPU, "CPU ID", "arm64 CPU identification memory");
52
53 struct cpu_desc;
54 #ifdef INVARIANTS
55 static bool hwcaps_set = false;
56 #endif
57
58 static void print_cpu_midr(struct sbuf *sb, u_int cpu);
59 static void print_cpu_features(u_int cpu, struct cpu_desc *desc,
60 struct cpu_desc *prev_desc);
61 static void print_cpu_caches(struct sbuf *sb, struct cpu_desc *desc);
62 #ifdef COMPAT_FREEBSD32
63 static u_long parse_cpu_features_hwcap32(void);
64 #endif
65
66 const char machine[] = "arm64";
67
68 #ifdef SCTL_MASK32
69 extern int adaptive_machine_arch;
70 #endif
71
72 static SYSCTL_NODE(_machdep, OID_AUTO, cache, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
73 "Cache management tuning");
74
75 static int allow_dic = 1;
76 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_dic, CTLFLAG_RDTUN, &allow_dic, 0,
77 "Allow optimizations based on the DIC cache bit");
78
79 static int allow_idc = 1;
80 SYSCTL_INT(_machdep_cache, OID_AUTO, allow_idc, CTLFLAG_RDTUN, &allow_idc, 0,
81 "Allow optimizations based on the IDC cache bit");
82
83 static bool emulate_ctr = false;
84
85 static void check_cpu_regs(u_int cpu, struct cpu_desc *desc,
86 struct cpu_desc *prev_desc);
87 static uint64_t update_special_reg_field(uint64_t user_reg, u_int type,
88 uint64_t value, u_int width, u_int shift, bool sign);
89
90 /*
91 * The default implementation of I-cache sync assumes we have an
92 * aliasing cache until we know otherwise.
93 */
94 void (*arm64_icache_sync_range)(void *, vm_size_t) =
95 &arm64_aliasing_icache_sync_range;
96
97 static int
sysctl_hw_machine(SYSCTL_HANDLER_ARGS)98 sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
99 {
100 #ifdef SCTL_MASK32
101 static const char machine32[] = "arm";
102 #endif
103 int error;
104
105 #ifdef SCTL_MASK32
106 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
107 error = SYSCTL_OUT(req, machine32, sizeof(machine32));
108 else
109 #endif
110 error = SYSCTL_OUT(req, machine, sizeof(machine));
111 return (error);
112 }
113
114 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
115 CTLFLAG_CAPRD | CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A",
116 "Machine class");
117
118 static char cpu_model[64];
119 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_CAPRD,
120 cpu_model, sizeof(cpu_model), "Machine model");
121
122 #define MAX_CACHES 8 /* Maximum number of caches supported
123 architecturally. */
124 /*
125 * Per-CPU affinity as provided in MPIDR_EL1
126 * Indexed by CPU number in logical order selected by the system.
127 * Relevant fields can be extracted using CPU_AFFn macros,
128 * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system.
129 *
130 * Fields used by us:
131 * Aff1 - Cluster number
132 * Aff0 - CPU number in Aff1 cluster
133 */
134 uint64_t __cpu_affinity[MAXCPU];
135 static u_int cpu_aff_levels;
136
137 struct cpu_desc {
138 uint64_t mpidr;
139 uint64_t id_aa64afr0;
140 uint64_t id_aa64afr1;
141 uint64_t id_aa64dfr0;
142 uint64_t id_aa64dfr1;
143 uint64_t id_aa64isar0;
144 uint64_t id_aa64isar1;
145 uint64_t id_aa64isar2;
146 uint64_t id_aa64mmfr0;
147 uint64_t id_aa64mmfr1;
148 uint64_t id_aa64mmfr2;
149 uint64_t id_aa64mmfr3;
150 uint64_t id_aa64mmfr4;
151 uint64_t id_aa64pfr0;
152 uint64_t id_aa64pfr1;
153 uint64_t id_aa64pfr2;
154 uint64_t id_aa64zfr0;
155 uint64_t ctr;
156 #ifdef COMPAT_FREEBSD32
157 uint64_t id_isar5;
158 uint64_t mvfr0;
159 uint64_t mvfr1;
160 #endif
161 uint64_t clidr;
162 uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */
163 bool have_sve;
164 };
165
166 static struct cpu_desc cpu_desc0;
167 static struct cpu_desc *cpu_desc;
168 static struct cpu_desc kern_cpu_desc;
169 static struct cpu_desc user_cpu_desc;
170 static struct cpu_desc l_user_cpu_desc;
171
172 static struct cpu_desc *
get_cpu_desc(u_int cpu)173 get_cpu_desc(u_int cpu)
174 {
175 /* The cpu_desc for CPU 0 is used before the allocator is ready. */
176 if (cpu == 0)
177 return (&cpu_desc0);
178
179 MPASS(cpu_desc != NULL);
180 return (&cpu_desc[cpu - 1]);
181 }
182
183 struct cpu_parts {
184 u_int part_id;
185 const char *part_name;
186 };
187 #define CPU_PART_NONE { 0, NULL }
188
189 struct cpu_implementers {
190 u_int impl_id;
191 const char *impl_name;
192 /*
193 * Part number is implementation defined
194 * so each vendor will have its own set of values and names.
195 */
196 const struct cpu_parts *cpu_parts;
197 };
198 #define CPU_IMPLEMENTER_NONE { 0, NULL, NULL }
199
200 /*
201 * Per-implementer table of (PartNum, CPU Name) pairs.
202 */
203 /* ARM Ltd. */
204 static const struct cpu_parts cpu_parts_arm[] = {
205 { CPU_PART_AEM_V8, "AEMv8" },
206 { CPU_PART_FOUNDATION, "Foundation-Model" },
207 { CPU_PART_CORTEX_A34, "Cortex-A34" },
208 { CPU_PART_CORTEX_A35, "Cortex-A35" },
209 { CPU_PART_CORTEX_A53, "Cortex-A53" },
210 { CPU_PART_CORTEX_A55, "Cortex-A55" },
211 { CPU_PART_CORTEX_A57, "Cortex-A57" },
212 { CPU_PART_CORTEX_A65, "Cortex-A65" },
213 { CPU_PART_CORTEX_A65AE, "Cortex-A65AE" },
214 { CPU_PART_CORTEX_A72, "Cortex-A72" },
215 { CPU_PART_CORTEX_A73, "Cortex-A73" },
216 { CPU_PART_CORTEX_A75, "Cortex-A75" },
217 { CPU_PART_CORTEX_A76, "Cortex-A76" },
218 { CPU_PART_CORTEX_A76AE, "Cortex-A76AE" },
219 { CPU_PART_CORTEX_A77, "Cortex-A77" },
220 { CPU_PART_CORTEX_A78, "Cortex-A78" },
221 { CPU_PART_CORTEX_A78AE, "Cortex-A78AE" },
222 { CPU_PART_CORTEX_A78C, "Cortex-A78C" },
223 { CPU_PART_CORTEX_A510, "Cortex-A510" },
224 { CPU_PART_CORTEX_A520, "Cortex-A520" },
225 { CPU_PART_CORTEX_A710, "Cortex-A710" },
226 { CPU_PART_CORTEX_A715, "Cortex-A715" },
227 { CPU_PART_CORTEX_A720, "Cortex-A720" },
228 { CPU_PART_CORTEX_A725, "Cortex-A725" },
229 { CPU_PART_CORTEX_X925, "Cortex-A925" },
230 { CPU_PART_CORTEX_X1, "Cortex-X1" },
231 { CPU_PART_CORTEX_X1C, "Cortex-X1C" },
232 { CPU_PART_CORTEX_X2, "Cortex-X2" },
233 { CPU_PART_CORTEX_X3, "Cortex-X3" },
234 { CPU_PART_CORTEX_X4, "Cortex-X4" },
235 { CPU_PART_NEOVERSE_E1, "Neoverse-E1" },
236 { CPU_PART_NEOVERSE_N1, "Neoverse-N1" },
237 { CPU_PART_NEOVERSE_N2, "Neoverse-N2" },
238 { CPU_PART_NEOVERSE_N3, "Neoverse-N3" },
239 { CPU_PART_NEOVERSE_V1, "Neoverse-V1" },
240 { CPU_PART_NEOVERSE_V2, "Neoverse-V2" },
241 { CPU_PART_NEOVERSE_V3, "Neoverse-V3" },
242 { CPU_PART_NEOVERSE_V3AE, "Neoverse-V3AE" },
243 CPU_PART_NONE,
244 };
245
246 /* Cavium */
247 static const struct cpu_parts cpu_parts_cavium[] = {
248 { CPU_PART_THUNDERX, "ThunderX" },
249 { CPU_PART_THUNDERX2, "ThunderX2" },
250 CPU_PART_NONE,
251 };
252
253 /* APM (now Ampere) */
254 static const struct cpu_parts cpu_parts_apm[] = {
255 { CPU_PART_EMAG8180, "eMAG 8180" },
256 CPU_PART_NONE,
257 };
258
259 /* Ampere */
260 static const struct cpu_parts cpu_parts_ampere[] = {
261 { CPU_PART_AMPERE1, "AmpereOne AC03" },
262 { CPU_PART_AMPERE1A, "AmpereOne AC04" },
263 CPU_PART_NONE,
264 };
265
266 /* Microsoft */
267 static const struct cpu_parts cpu_parts_microsoft[] = {
268 { CPU_PART_AZURE_COBALT_100, "Azure Cobalt 100" },
269 CPU_PART_NONE,
270 };
271
272 /* Qualcomm */
273 static const struct cpu_parts cpu_parts_qcom[] = {
274 { CPU_PART_KRYO400_GOLD, "Kryo 400 Gold" },
275 { CPU_PART_KRYO400_SILVER, "Kryo 400 Silver" },
276 CPU_PART_NONE,
277 };
278
279 /* Apple */
280 static const struct cpu_parts cpu_parts_apple[] = {
281 { CPU_PART_M1_ICESTORM, "M1 Icestorm" },
282 { CPU_PART_M1_FIRESTORM, "M1 Firestorm" },
283 { CPU_PART_M1_ICESTORM_PRO, "M1 Pro Icestorm" },
284 { CPU_PART_M1_FIRESTORM_PRO, "M1 Pro Firestorm" },
285 { CPU_PART_M1_ICESTORM_MAX, "M1 Max Icestorm" },
286 { CPU_PART_M1_FIRESTORM_MAX, "M1 Max Firestorm" },
287 { CPU_PART_M2_BLIZZARD, "M2 Blizzard" },
288 { CPU_PART_M2_AVALANCHE, "M2 Avalanche" },
289 { CPU_PART_M2_BLIZZARD_PRO, "M2 Pro Blizzard" },
290 { CPU_PART_M2_AVALANCHE_PRO, "M2 Pro Avalanche" },
291 { CPU_PART_M2_BLIZZARD_MAX, "M2 Max Blizzard" },
292 { CPU_PART_M2_AVALANCHE_MAX, "M2 Max Avalanche" },
293 CPU_PART_NONE,
294 };
295
296 /* Unknown */
297 static const struct cpu_parts cpu_parts_none[] = {
298 CPU_PART_NONE,
299 };
300
301 /*
302 * Implementers table.
303 */
304 const struct cpu_implementers cpu_implementers[] = {
305 { CPU_IMPL_AMPERE, "Ampere", cpu_parts_ampere },
306 { CPU_IMPL_APPLE, "Apple", cpu_parts_apple },
307 { CPU_IMPL_APM, "APM", cpu_parts_apm },
308 { CPU_IMPL_ARM, "ARM", cpu_parts_arm },
309 { CPU_IMPL_BROADCOM, "Broadcom", cpu_parts_none },
310 { CPU_IMPL_CAVIUM, "Cavium", cpu_parts_cavium },
311 { CPU_IMPL_DEC, "DEC", cpu_parts_none },
312 { CPU_IMPL_FREESCALE, "Freescale", cpu_parts_none },
313 { CPU_IMPL_FUJITSU, "Fujitsu", cpu_parts_none },
314 { CPU_IMPL_HISILICON, "HiSilicon", cpu_parts_none },
315 { CPU_IMPL_INFINEON, "IFX", cpu_parts_none },
316 { CPU_IMPL_INTEL, "Intel", cpu_parts_none },
317 { CPU_IMPL_MARVELL, "Marvell", cpu_parts_none },
318 { CPU_IMPL_MICROSOFT, "Microsoft", cpu_parts_microsoft },
319 { CPU_IMPL_NVIDIA, "NVIDIA", cpu_parts_none },
320 { CPU_IMPL_QUALCOMM, "Qualcomm", cpu_parts_qcom },
321 CPU_IMPLEMENTER_NONE,
322 };
323
324 #define MRS_TYPE_MASK 0xf
325 #define MRS_INVALID 0
326 #define MRS_EXACT 1
327 #define MRS_EXACT_IF_DIFFERENT 2
328 #define MRS_LOWER 3
329 #define MRS_HIGHER_OR_ZERO 4
330 #define MRS_HIGHER 5
331 #define MRS_SAFE_SHIFT 4
332 #define MRS_SAFE_MASK (0xfu << MRS_SAFE_SHIFT)
333 #define MRS_SAFE(x) (((x) << MRS_SAFE_SHIFT) & MRS_SAFE_MASK)
334 #define MRS_SAFE_VAL(x) (((x) & MRS_SAFE_MASK) >> MRS_SAFE_SHIFT)
335 #define MRS_FREEBSD (1u << 8)
336 #define MRS_LINUX (1u << 9)
337 #define MRS_USERSPACE (MRS_FREEBSD | MRS_LINUX)
338
339 struct mrs_field_value {
340 uint64_t value;
341 const char *desc;
342 };
343
344 #define MRS_FIELD_VALUE(_value, _desc) \
345 { \
346 .value = (_value), \
347 .desc = (_desc), \
348 }
349
350 #define MRS_FIELD_VALUE_NONE_IMPL(_reg, _field, _none, _impl) \
351 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _none, ""), \
352 MRS_FIELD_VALUE(_reg ## _ ## _field ## _ ## _impl, #_field)
353
354 #define MRS_FIELD_VALUE_COUNT(_reg, _field, _desc) \
355 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, "1 " _desc), \
356 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "2 " _desc "s"), \
357 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "3 " _desc "s"), \
358 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "4 " _desc "s"), \
359 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "5 " _desc "s"), \
360 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "6 " _desc "s"), \
361 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "7 " _desc "s"), \
362 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc "s"), \
363 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "9 " _desc "s"), \
364 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "10 "_desc "s"), \
365 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "11 "_desc "s"), \
366 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "12 "_desc "s"), \
367 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "13 "_desc "s"), \
368 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "14 "_desc "s"), \
369 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "15 "_desc "s"), \
370 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "16 "_desc "s")
371
372 /*
373 * Used for printing I/D cache line sizes & CWG/ERG, as 0 is a special case
374 * in some cases the decoded string needs to be passed in.
375 */
376 #define MRS_FIELD_VALUE_CACHE(_reg, _field, _0desc, _desc) \
377 MRS_FIELD_VALUE(0ul << _reg ## _ ## _field ## _SHIFT, _0desc), \
378 MRS_FIELD_VALUE(1ul << _reg ## _ ## _field ## _SHIFT, "8 " _desc), \
379 MRS_FIELD_VALUE(2ul << _reg ## _ ## _field ## _SHIFT, "16 " _desc), \
380 MRS_FIELD_VALUE(3ul << _reg ## _ ## _field ## _SHIFT, "32 " _desc), \
381 MRS_FIELD_VALUE(4ul << _reg ## _ ## _field ## _SHIFT, "64 " _desc), \
382 MRS_FIELD_VALUE(5ul << _reg ## _ ## _field ## _SHIFT, "128 " _desc), \
383 MRS_FIELD_VALUE(6ul << _reg ## _ ## _field ## _SHIFT, "256 " _desc), \
384 MRS_FIELD_VALUE(7ul << _reg ## _ ## _field ## _SHIFT, "512 " _desc), \
385 MRS_FIELD_VALUE(8ul << _reg ## _ ## _field ## _SHIFT, "1k " _desc), \
386 MRS_FIELD_VALUE(9ul << _reg ## _ ## _field ## _SHIFT, "2k " _desc), \
387 MRS_FIELD_VALUE(10ul<< _reg ## _ ## _field ## _SHIFT, "4k " _desc), \
388 MRS_FIELD_VALUE(11ul<< _reg ## _ ## _field ## _SHIFT, "8k " _desc), \
389 MRS_FIELD_VALUE(12ul<< _reg ## _ ## _field ## _SHIFT, "16k " _desc), \
390 MRS_FIELD_VALUE(13ul<< _reg ## _ ## _field ## _SHIFT, "32k " _desc), \
391 MRS_FIELD_VALUE(14ul<< _reg ## _ ## _field ## _SHIFT, "64k " _desc), \
392 MRS_FIELD_VALUE(15ul<< _reg ## _ ## _field ## _SHIFT, "128k "_desc)
393
394 #define MRS_FIELD_VALUE_END { .desc = NULL }
395
396 struct mrs_field_hwcap {
397 uint64_t min;
398 u_long hwcap_val;
399 u_int hwcap_id;
400 };
401
402 #define MRS_HWCAP(_hwcap_id, _val, _min) \
403 { \
404 .hwcap_id = (_hwcap_id), \
405 .hwcap_val = (_val), \
406 .min = (_min), \
407 }
408
409 #define MRS_HWCAP_END { .hwcap_id = 0 }
410
411 struct mrs_field {
412 const char *name;
413 const struct mrs_field_value *values;
414 const struct mrs_field_hwcap *hwcaps;
415 uint64_t mask;
416 bool sign;
417 u_int type;
418 u_int width;
419 u_int shift;
420 };
421
422 #define MRS_FIELD_RES1(_width, _shift) \
423 { \
424 .sign = false, \
425 .type = MRS_EXACT | MRS_SAFE((1u << (_width)) - 1) | \
426 MRS_USERSPACE, \
427 .width = (_width), \
428 .shift = (_shift), \
429 }
430
431 #define MRS_FIELD_HWCAP(_register, _name, _sign, _type, _visibility, \
432 _values, _hwcap) \
433 { \
434 .name = #_name, \
435 .sign = (_sign), \
436 .type = ((_type) | (_visibility)), \
437 .width = _register ## _ ## _name ## _WIDTH, \
438 .shift = _register ## _ ## _name ## _SHIFT, \
439 .mask = _register ## _ ## _name ## _MASK, \
440 .values = (_values), \
441 .hwcaps = (_hwcap), \
442 }
443
444 #define MRS_FIELD(_register, _name, _sign, _type, _visibility, _values) \
445 MRS_FIELD_HWCAP(_register, _name, _sign, _type, _visibility, \
446 _values, NULL)
447
448 #define MRS_FIELD_END { .type = MRS_INVALID, }
449
450 /* CTR_EL0 */
451 static const struct mrs_field_value ctr_dic[] = {
452 MRS_FIELD_VALUE_NONE_IMPL(CTR, DIC, NONE, IMPL),
453 MRS_FIELD_VALUE_END,
454 };
455
456 static const struct mrs_field_value ctr_idc[] = {
457 MRS_FIELD_VALUE_NONE_IMPL(CTR, IDC, NONE, IMPL),
458 MRS_FIELD_VALUE_END,
459 };
460
461 static const struct mrs_field_value ctr_cwg[] = {
462 MRS_FIELD_VALUE_CACHE(CTR, CWG, "Unknown CWG",
463 "byte CWG"),
464 MRS_FIELD_VALUE_END,
465 };
466
467 static const struct mrs_field_value ctr_erg[] = {
468 MRS_FIELD_VALUE_CACHE(CTR, ERG, "Unknown ERG",
469 "byte ERG"),
470 MRS_FIELD_VALUE_END,
471 };
472
473 static const struct mrs_field_value ctr_dline[] = {
474 MRS_FIELD_VALUE_CACHE(CTR, DLINE, "4 byte D-cacheline",
475 "byte D-cacheline"),
476 MRS_FIELD_VALUE_END,
477 };
478
479 static const struct mrs_field_value ctr_l1ip[] = {
480 MRS_FIELD_VALUE(CTR_L1IP_VIPT, "VIPT I-cache"),
481 MRS_FIELD_VALUE(CTR_L1IP_PIPT, "PIPT I-cache"),
482 MRS_FIELD_VALUE_END,
483 };
484
485 static const struct mrs_field_value ctr_iline[] = {
486 MRS_FIELD_VALUE_CACHE(CTR, ILINE, "4 byte I-cacheline",
487 "byte I-cacheline"),
488 MRS_FIELD_VALUE_END,
489 };
490
491 static const struct mrs_field ctr_fields[] = {
492 /* Bit 31 is RES1 */
493 MRS_FIELD_RES1(1, 31),
494 MRS_FIELD(CTR, DIC, false, MRS_LOWER, MRS_USERSPACE, ctr_dic),
495 MRS_FIELD(CTR, IDC, false, MRS_LOWER, MRS_USERSPACE, ctr_idc),
496 MRS_FIELD(CTR, CWG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_cwg),
497 MRS_FIELD(CTR, ERG, false, MRS_HIGHER_OR_ZERO, MRS_USERSPACE, ctr_erg),
498 MRS_FIELD(CTR, DLINE, false, MRS_LOWER, MRS_USERSPACE, ctr_dline),
499 /* If the ICache types are different report the safe option */
500 MRS_FIELD(CTR, L1IP, false, MRS_EXACT_IF_DIFFERENT |
501 MRS_SAFE(CTR_L1IP_VIPT >> CTR_L1IP_SHIFT), MRS_USERSPACE,
502 ctr_l1ip),
503 MRS_FIELD(CTR, ILINE, false, MRS_LOWER, MRS_USERSPACE, ctr_iline),
504 MRS_FIELD_END,
505 };
506
507 /* ID_AA64AFR0_EL1 */
508 static const struct mrs_field id_aa64afr0_fields[] = {
509 MRS_FIELD_END,
510 };
511
512
513 /* ID_AA64AFR1_EL1 */
514 static const struct mrs_field id_aa64afr1_fields[] = {
515 MRS_FIELD_END,
516 };
517
518
519 /* ID_AA64DFR0_EL1 */
520 static const struct mrs_field_value id_aa64dfr0_hpmn0[] = {
521 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, HPMN0, CONSTR, DEFINED),
522 MRS_FIELD_VALUE_END,
523 };
524
525 static const struct mrs_field_value id_aa64dfr0_brbe[] = {
526 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, BRBE, NONE, IMPL),
527 MRS_FIELD_VALUE(ID_AA64DFR0_BRBE_EL3, "BRBE EL3"),
528 MRS_FIELD_VALUE_END,
529 };
530
531 static const struct mrs_field_value id_aa64dfr0_mtpmu[] = {
532 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, MTPMU, NONE, IMPL),
533 MRS_FIELD_VALUE(ID_AA64DFR0_MTPMU_NONE_MT_RES0, "MTPMU res0"),
534 MRS_FIELD_VALUE_END,
535 };
536
537 static const struct mrs_field_value id_aa64dfr0_tracebuffer[] = {
538 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, TraceBuffer, NONE, IMPL),
539 MRS_FIELD_VALUE_END,
540 };
541
542 static const struct mrs_field_value id_aa64dfr0_tracefilt[] = {
543 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_NONE, ""),
544 MRS_FIELD_VALUE(ID_AA64DFR0_TraceFilt_8_4, "Trace v8.4"),
545 MRS_FIELD_VALUE_END,
546 };
547
548 static const struct mrs_field_value id_aa64dfr0_doublelock[] = {
549 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_IMPL, "DoubleLock"),
550 MRS_FIELD_VALUE(ID_AA64DFR0_DoubleLock_NONE, ""),
551 MRS_FIELD_VALUE_END,
552 };
553
554 static const struct mrs_field_value id_aa64dfr0_pmsver[] = {
555 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_NONE, ""),
556 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE, "SPE"),
557 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_1, "SPEv1p1"),
558 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_2, "SPEv1p2"),
559 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_3, "SPEv1p3"),
560 MRS_FIELD_VALUE(ID_AA64DFR0_PMSVer_SPE_1_4, "SPEv1p4"),
561 MRS_FIELD_VALUE_END,
562 };
563
564 static const struct mrs_field_value id_aa64dfr0_ctx_cmps[] = {
565 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, CTX_CMPs, "CTX BKPT"),
566 MRS_FIELD_VALUE_END,
567 };
568
569 static const struct mrs_field_value id_aa64dfr0_wrps[] = {
570 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, WRPs, "Watchpoint"),
571 MRS_FIELD_VALUE_END,
572 };
573
574 static const struct mrs_field_value id_aa64dfr0_pmss[] = {
575 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, PMSS, NONE, IMPL),
576 MRS_FIELD_VALUE_END,
577 };
578
579 static const struct mrs_field_value id_aa64dfr0_brps[] = {
580 MRS_FIELD_VALUE_COUNT(ID_AA64DFR0, BRPs, "Breakpoint"),
581 MRS_FIELD_VALUE_END,
582 };
583
584 static const struct mrs_field_value id_aa64dfr0_pmuver[] = {
585 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_NONE, ""),
586 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3, "PMUv3"),
587 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_1, "PMUv3p1"),
588 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_4, "PMUv3p4"),
589 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_5, "PMUv3p5"),
590 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_7, "PMUv3p7"),
591 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_8, "PMUv3p8"),
592 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_3_9, "PMUv3p9"),
593 MRS_FIELD_VALUE(ID_AA64DFR0_PMUVer_IMPL, "IMPL PMU"),
594 MRS_FIELD_VALUE_END,
595 };
596
597 static const struct mrs_field_value id_aa64dfr0_tracever[] = {
598 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_NONE, ""),
599 MRS_FIELD_VALUE(ID_AA64DFR0_TraceVer_IMPL, "Trace"),
600 MRS_FIELD_VALUE_END,
601 };
602
603 static const struct mrs_field_value id_aa64dfr0_debugver[] = {
604 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8, "Debugv8"),
605 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_VHE, "Debugv8_VHE"),
606 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_2, "Debugv8p2"),
607 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_4, "Debugv8p4"),
608 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_8, "Debugv8p8"),
609 MRS_FIELD_VALUE(ID_AA64DFR0_DebugVer_8_9, "Debugv8p9"),
610 MRS_FIELD_VALUE_END,
611 };
612
613 static const struct mrs_field id_aa64dfr0_fields[] = {
614 MRS_FIELD(ID_AA64DFR0, HPMN0, false, MRS_LOWER, 0, id_aa64dfr0_hpmn0),
615 MRS_FIELD(ID_AA64DFR0, BRBE, false, MRS_LOWER, 0, id_aa64dfr0_brbe),
616 MRS_FIELD(ID_AA64DFR0, MTPMU, true, MRS_LOWER, 0, id_aa64dfr0_mtpmu),
617 MRS_FIELD(ID_AA64DFR0, TraceBuffer, false, MRS_LOWER, 0,
618 id_aa64dfr0_tracebuffer),
619 MRS_FIELD(ID_AA64DFR0, TraceFilt, false, MRS_LOWER, 0,
620 id_aa64dfr0_tracefilt),
621 MRS_FIELD(ID_AA64DFR0, DoubleLock, true, MRS_LOWER, 0,
622 id_aa64dfr0_doublelock),
623 MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_LOWER, 0, id_aa64dfr0_pmsver),
624 MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_LOWER, 0,
625 id_aa64dfr0_ctx_cmps),
626 MRS_FIELD(ID_AA64DFR0, WRPs, false, MRS_LOWER, MRS_USERSPACE,
627 id_aa64dfr0_wrps),
628 MRS_FIELD(ID_AA64DFR0, PMSS, false, MRS_LOWER, 0, id_aa64dfr0_pmss),
629 MRS_FIELD(ID_AA64DFR0, BRPs, false, MRS_LOWER, MRS_USERSPACE,
630 id_aa64dfr0_brps),
631 MRS_FIELD(ID_AA64DFR0, PMUVer, true, MRS_LOWER, 0, id_aa64dfr0_pmuver),
632 MRS_FIELD(ID_AA64DFR0, TraceVer, false, MRS_LOWER, 0,
633 id_aa64dfr0_tracever),
634 MRS_FIELD(ID_AA64DFR0, DebugVer, false, MRS_LOWER | MRS_SAFE(0x6), 0,
635 id_aa64dfr0_debugver),
636 MRS_FIELD_END,
637 };
638
639
640 /* ID_AA64DFR1_EL1 */
641 static const struct mrs_field_value id_aa64dfr1_dpfzs[] = {
642 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, DPFZS, NONE, IMPL),
643 MRS_FIELD_VALUE_END,
644 };
645
646 static const struct mrs_field_value id_aa64dfr1_pmicntr[] = {
647 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, PMICNTR, NONE, IMPL),
648 MRS_FIELD_VALUE_END,
649 };
650
651 static const struct mrs_field_value id_aa64dfr1_spmu[] = {
652 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, SPMU, NONE, IMPL),
653 MRS_FIELD_VALUE_END,
654 };
655
656 static const struct mrs_field id_aa64dfr1_fields[] = {
657 MRS_FIELD(ID_AA64DFR1, DPFZS, false, MRS_LOWER, 0, id_aa64dfr1_dpfzs),
658 MRS_FIELD(ID_AA64DFR1, PMICNTR, false, MRS_LOWER, 0, id_aa64dfr1_pmicntr),
659 MRS_FIELD(ID_AA64DFR1, SPMU, false, MRS_LOWER, 0, id_aa64dfr1_spmu),
660 MRS_FIELD_END,
661 };
662
663
664 /* ID_AA64ISAR0_EL1 */
665 static const struct mrs_field_value id_aa64isar0_rndr[] = {
666 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_NONE, ""),
667 MRS_FIELD_VALUE(ID_AA64ISAR0_RNDR_IMPL, "RNG"),
668 MRS_FIELD_VALUE_END,
669 };
670
671 static const struct mrs_field_hwcap id_aa64isar0_rndr_caps[] = {
672 MRS_HWCAP(2, HWCAP2_RNG, ID_AA64ISAR0_RNDR_IMPL),
673 MRS_HWCAP_END
674 };
675
676 static const struct mrs_field_value id_aa64isar0_tlb[] = {
677 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_NONE, ""),
678 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOS, "TLBI-OS"),
679 MRS_FIELD_VALUE(ID_AA64ISAR0_TLB_TLBIOSR, "TLBI-OSR"),
680 MRS_FIELD_VALUE_END,
681 };
682
683 static const struct mrs_field_value id_aa64isar0_ts[] = {
684 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_NONE, ""),
685 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_4, "CondM-8.4"),
686 MRS_FIELD_VALUE(ID_AA64ISAR0_TS_CondM_8_5, "CondM-8.5"),
687 MRS_FIELD_VALUE_END,
688 };
689
690 static const struct mrs_field_hwcap id_aa64isar0_ts_caps[] = {
691 MRS_HWCAP(1, HWCAP_FLAGM, ID_AA64ISAR0_TS_CondM_8_4),
692 MRS_HWCAP(2, HWCAP2_FLAGM2, ID_AA64ISAR0_TS_CondM_8_5),
693 MRS_HWCAP_END
694 };
695
696 static const struct mrs_field_value id_aa64isar0_fhm[] = {
697 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, FHM, NONE, IMPL),
698 MRS_FIELD_VALUE_END,
699 };
700
701 static const struct mrs_field_hwcap id_aa64isar0_fhm_caps[] = {
702 MRS_HWCAP(1, HWCAP_ASIMDFHM, ID_AA64ISAR0_FHM_IMPL),
703 MRS_HWCAP_END
704 };
705
706 static const struct mrs_field_value id_aa64isar0_dp[] = {
707 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, DP, NONE, IMPL),
708 MRS_FIELD_VALUE_END,
709 };
710
711 static const struct mrs_field_hwcap id_aa64isar0_dp_caps[] = {
712 MRS_HWCAP(1, HWCAP_ASIMDDP, ID_AA64ISAR0_DP_IMPL),
713 MRS_HWCAP_END
714 };
715
716 static const struct mrs_field_value id_aa64isar0_sm4[] = {
717 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM4, NONE, IMPL),
718 MRS_FIELD_VALUE_END,
719 };
720
721 static const struct mrs_field_hwcap id_aa64isar0_sm4_caps[] = {
722 MRS_HWCAP(1, HWCAP_SM4, ID_AA64ISAR0_SM4_IMPL),
723 MRS_HWCAP_END
724 };
725
726 static const struct mrs_field_value id_aa64isar0_sm3[] = {
727 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SM3, NONE, IMPL),
728 MRS_FIELD_VALUE_END,
729 };
730
731 static const struct mrs_field_hwcap id_aa64isar0_sm3_caps[] = {
732 MRS_HWCAP(1, HWCAP_SM3, ID_AA64ISAR0_SM3_IMPL),
733 MRS_HWCAP_END
734 };
735
736 static const struct mrs_field_value id_aa64isar0_sha3[] = {
737 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA3, NONE, IMPL),
738 MRS_FIELD_VALUE_END,
739 };
740
741 static const struct mrs_field_hwcap id_aa64isar0_sha3_caps[] = {
742 MRS_HWCAP(1, HWCAP_SHA3, ID_AA64ISAR0_SHA3_IMPL),
743 MRS_HWCAP_END
744 };
745
746 static const struct mrs_field_value id_aa64isar0_rdm[] = {
747 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, RDM, NONE, IMPL),
748 MRS_FIELD_VALUE_END,
749 };
750
751 static const struct mrs_field_hwcap id_aa64isar0_rdm_caps[] = {
752 MRS_HWCAP(1, HWCAP_ASIMDRDM, ID_AA64ISAR0_RDM_IMPL),
753 MRS_HWCAP_END
754 };
755
756 static const struct mrs_field_value id_aa64isar0_tme[] = {
757 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, TME, NONE, IMPL),
758 MRS_FIELD_VALUE_END,
759 };
760
761 static const struct mrs_field_value id_aa64isar0_atomic[] = {
762 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, Atomic, NONE, IMPL),
763 MRS_FIELD_VALUE_END,
764 };
765
766 static const struct mrs_field_hwcap id_aa64isar0_atomic_caps[] = {
767 MRS_HWCAP(1, HWCAP_ATOMICS, ID_AA64ISAR0_Atomic_IMPL),
768 MRS_HWCAP_END
769 };
770
771 static const struct mrs_field_value id_aa64isar0_crc32[] = {
772 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, CRC32, NONE, BASE),
773 MRS_FIELD_VALUE_END,
774 };
775
776 static const struct mrs_field_hwcap id_aa64isar0_crc32_caps[] = {
777 MRS_HWCAP(1, HWCAP_CRC32, ID_AA64ISAR0_CRC32_BASE),
778 MRS_HWCAP_END
779 };
780
781 static const struct mrs_field_value id_aa64isar0_sha2[] = {
782 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA2, NONE, BASE),
783 MRS_FIELD_VALUE(ID_AA64ISAR0_SHA2_512, "SHA2+SHA512"),
784 MRS_FIELD_VALUE_END,
785 };
786
787 static const struct mrs_field_hwcap id_aa64isar0_sha2_caps[] = {
788 MRS_HWCAP(1, HWCAP_SHA2, ID_AA64ISAR0_SHA2_BASE),
789 MRS_HWCAP(1, HWCAP_SHA512, ID_AA64ISAR0_SHA2_512),
790 MRS_HWCAP_END
791 };
792
793 static const struct mrs_field_value id_aa64isar0_sha1[] = {
794 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, SHA1, NONE, BASE),
795 MRS_FIELD_VALUE_END,
796 };
797
798 static const struct mrs_field_hwcap id_aa64isar0_sha1_caps[] = {
799 MRS_HWCAP(1, HWCAP_SHA1, ID_AA64ISAR0_SHA1_BASE),
800 MRS_HWCAP_END
801 };
802
803 static const struct mrs_field_value id_aa64isar0_aes[] = {
804 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE),
805 MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"),
806 MRS_FIELD_VALUE_END,
807 };
808
809 static const struct mrs_field_hwcap id_aa64isar0_aes_caps[] = {
810 MRS_HWCAP(1, HWCAP_AES, ID_AA64ISAR0_AES_BASE),
811 MRS_HWCAP(1, HWCAP_PMULL, ID_AA64ISAR0_AES_PMULL),
812 MRS_HWCAP_END
813 };
814
815 static const struct mrs_field id_aa64isar0_fields[] = {
816 MRS_FIELD_HWCAP(ID_AA64ISAR0, RNDR, false, MRS_LOWER, MRS_USERSPACE,
817 id_aa64isar0_rndr, id_aa64isar0_rndr_caps),
818 MRS_FIELD(ID_AA64ISAR0, TLB, false, MRS_LOWER, 0, id_aa64isar0_tlb),
819 MRS_FIELD_HWCAP(ID_AA64ISAR0, TS, false, MRS_LOWER, MRS_USERSPACE,
820 id_aa64isar0_ts, id_aa64isar0_ts_caps),
821 MRS_FIELD_HWCAP(ID_AA64ISAR0, FHM, false, MRS_LOWER, MRS_USERSPACE,
822 id_aa64isar0_fhm, id_aa64isar0_fhm_caps),
823 MRS_FIELD_HWCAP(ID_AA64ISAR0, DP, false, MRS_LOWER, MRS_USERSPACE,
824 id_aa64isar0_dp, id_aa64isar0_dp_caps),
825 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM4, false, MRS_LOWER, MRS_USERSPACE,
826 id_aa64isar0_sm4, id_aa64isar0_sm4_caps),
827 MRS_FIELD_HWCAP(ID_AA64ISAR0, SM3, false, MRS_LOWER, MRS_USERSPACE,
828 id_aa64isar0_sm3, id_aa64isar0_sm3_caps),
829 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA3, false, MRS_LOWER, MRS_USERSPACE,
830 id_aa64isar0_sha3, id_aa64isar0_sha3_caps),
831 MRS_FIELD_HWCAP(ID_AA64ISAR0, RDM, false, MRS_LOWER, MRS_USERSPACE,
832 id_aa64isar0_rdm, id_aa64isar0_rdm_caps),
833 MRS_FIELD(ID_AA64ISAR0, TME, false, MRS_LOWER, 0, id_aa64isar0_tme),
834 MRS_FIELD_HWCAP(ID_AA64ISAR0, Atomic, false, MRS_LOWER, MRS_USERSPACE,
835 id_aa64isar0_atomic, id_aa64isar0_atomic_caps),
836 MRS_FIELD_HWCAP(ID_AA64ISAR0, CRC32, false, MRS_LOWER, MRS_USERSPACE,
837 id_aa64isar0_crc32, id_aa64isar0_crc32_caps),
838 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA2, false, MRS_LOWER, MRS_USERSPACE,
839 id_aa64isar0_sha2, id_aa64isar0_sha2_caps),
840 MRS_FIELD_HWCAP(ID_AA64ISAR0, SHA1, false, MRS_LOWER, MRS_USERSPACE,
841 id_aa64isar0_sha1, id_aa64isar0_sha1_caps),
842 MRS_FIELD_HWCAP(ID_AA64ISAR0, AES, false, MRS_LOWER, MRS_USERSPACE,
843 id_aa64isar0_aes, id_aa64isar0_aes_caps),
844 MRS_FIELD_END,
845 };
846
847
848 /* ID_AA64ISAR1_EL1 */
849 static const struct mrs_field_value id_aa64isar1_ls64[] = {
850 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, LS64, NONE, IMPL),
851 MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_V, "LS64v"),
852 MRS_FIELD_VALUE(ID_AA64ISAR1_LS64_ACCDATA, "LS64+ACCDATA"),
853 MRS_FIELD_VALUE_END,
854 };
855
856 static const struct mrs_field_value id_aa64isar1_xs[] = {
857 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, XS, NONE, IMPL),
858 MRS_FIELD_VALUE_END,
859 };
860
861 static const struct mrs_field_value id_aa64isar1_i8mm[] = {
862 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, I8MM, NONE, IMPL),
863 MRS_FIELD_VALUE_END,
864 };
865
866 static const struct mrs_field_hwcap id_aa64isar1_i8mm_caps[] = {
867 MRS_HWCAP(2, HWCAP2_I8MM, ID_AA64ISAR1_I8MM_IMPL),
868 MRS_HWCAP_END
869 };
870
871 static const struct mrs_field_value id_aa64isar1_dgh[] = {
872 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, DGH, NONE, IMPL),
873 MRS_FIELD_VALUE_END,
874 };
875
876 static const struct mrs_field_hwcap id_aa64isar1_dgh_caps[] = {
877 MRS_HWCAP(2, HWCAP2_DGH, ID_AA64ISAR1_DGH_IMPL),
878 MRS_HWCAP_END
879 };
880
881 static const struct mrs_field_value id_aa64isar1_bf16[] = {
882 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
883 MRS_FIELD_VALUE(ID_AA64ISAR1_BF16_EBF, "EBF16"),
884 MRS_FIELD_VALUE_END,
885 };
886
887 static const struct mrs_field_hwcap id_aa64isar1_bf16_caps[] = {
888 MRS_HWCAP(2, HWCAP2_BF16, ID_AA64ISAR1_BF16_IMPL),
889 MRS_HWCAP_END
890 };
891
892 static const struct mrs_field_value id_aa64isar1_specres[] = {
893 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_NONE, ""),
894 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_8_5, "PredInv v8.5"),
895 MRS_FIELD_VALUE(ID_AA64ISAR1_SPECRES_8_9, "PredInv v8.9"),
896 MRS_FIELD_VALUE_END,
897 };
898
899 static const struct mrs_field_value id_aa64isar1_sb[] = {
900 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, SB, NONE, IMPL),
901 MRS_FIELD_VALUE_END,
902 };
903
904 static const struct mrs_field_hwcap id_aa64isar1_sb_caps[] = {
905 MRS_HWCAP(1, HWCAP_SB, ID_AA64ISAR1_SB_IMPL),
906 MRS_HWCAP_END
907 };
908
909 static const struct mrs_field_value id_aa64isar1_frintts[] = {
910 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FRINTTS, NONE, IMPL),
911 MRS_FIELD_VALUE_END,
912 };
913
914 static const struct mrs_field_hwcap id_aa64isar1_frintts_caps[] = {
915 MRS_HWCAP(2, HWCAP2_FRINT, ID_AA64ISAR1_FRINTTS_IMPL),
916 MRS_HWCAP_END
917 };
918
919 static const struct mrs_field_value id_aa64isar1_gpi[] = {
920 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPI, NONE, IMPL),
921 MRS_FIELD_VALUE_END,
922 };
923
924 static const struct mrs_field_hwcap id_aa64isar1_gpi_caps[] = {
925 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR1_GPI_IMPL),
926 MRS_HWCAP_END
927 };
928
929 static const struct mrs_field_value id_aa64isar1_gpa[] = {
930 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, GPA, NONE, IMPL),
931 MRS_FIELD_VALUE_END,
932 };
933
934 static const struct mrs_field_hwcap id_aa64isar1_gpa_caps[] = {
935 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR1_GPA_IMPL),
936 MRS_HWCAP_END
937 };
938
939 static const struct mrs_field_value id_aa64isar1_lrcpc[] = {
940 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_NONE, ""),
941 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_3, "RCPC-8.3"),
942 MRS_FIELD_VALUE(ID_AA64ISAR1_LRCPC_RCPC_8_4, "RCPC-8.4"),
943 MRS_FIELD_VALUE_END,
944 };
945
946 static const struct mrs_field_hwcap id_aa64isar1_lrcpc_caps[] = {
947 MRS_HWCAP(1, HWCAP_LRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_3),
948 MRS_HWCAP(1, HWCAP_ILRCPC, ID_AA64ISAR1_LRCPC_RCPC_8_4),
949 MRS_HWCAP_END
950 };
951
952 static const struct mrs_field_value id_aa64isar1_fcma[] = {
953 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, FCMA, NONE, IMPL),
954 MRS_FIELD_VALUE_END,
955 };
956
957 static const struct mrs_field_hwcap id_aa64isar1_fcma_caps[] = {
958 MRS_HWCAP(1, HWCAP_FCMA, ID_AA64ISAR1_FCMA_IMPL),
959 MRS_HWCAP_END
960 };
961
962 static const struct mrs_field_value id_aa64isar1_jscvt[] = {
963 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, JSCVT, NONE, IMPL),
964 MRS_FIELD_VALUE_END,
965 };
966
967 static const struct mrs_field_hwcap id_aa64isar1_jscvt_caps[] = {
968 MRS_HWCAP(1, HWCAP_JSCVT, ID_AA64ISAR1_JSCVT_IMPL),
969 MRS_HWCAP_END
970 };
971
972 static const struct mrs_field_value id_aa64isar1_api[] = {
973 MRS_FIELD_VALUE(ID_AA64ISAR1_API_NONE, ""),
974 MRS_FIELD_VALUE(ID_AA64ISAR1_API_PAC, "API PAC"),
975 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC, "API EPAC"),
976 MRS_FIELD_VALUE(ID_AA64ISAR1_API_EPAC2, "Impl PAuth+EPAC2"),
977 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC, "Impl PAuth+FPAC"),
978 MRS_FIELD_VALUE(ID_AA64ISAR1_API_FPAC_COMBINED,
979 "Impl PAuth+FPAC+Combined"),
980 MRS_FIELD_VALUE_END,
981 };
982
983 static const struct mrs_field_hwcap id_aa64isar1_api_caps[] = {
984 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR1_API_PAC),
985 MRS_HWCAP_END
986 };
987
988 static const struct mrs_field_value id_aa64isar1_apa[] = {
989 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""),
990 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"),
991 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"),
992 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "APA EPAC2"),
993 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "APA FPAC"),
994 MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED,
995 "APA FPAC+Combined"),
996 MRS_FIELD_VALUE_END,
997 };
998
999 static const struct mrs_field_hwcap id_aa64isar1_apa_caps[] = {
1000 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR1_APA_PAC),
1001 MRS_HWCAP_END
1002 };
1003
1004 static const struct mrs_field_value id_aa64isar1_dpb[] = {
1005 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_NONE, ""),
1006 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVAP, "DCPoP"),
1007 MRS_FIELD_VALUE(ID_AA64ISAR1_DPB_DCCVADP, "DCCVADP"),
1008 MRS_FIELD_VALUE_END,
1009 };
1010
1011 static const struct mrs_field_hwcap id_aa64isar1_dpb_caps[] = {
1012 MRS_HWCAP(1, HWCAP_DCPOP, ID_AA64ISAR1_DPB_DCCVAP),
1013 MRS_HWCAP(2, HWCAP2_DCPODP, ID_AA64ISAR1_DPB_DCCVADP),
1014 MRS_HWCAP_END
1015 };
1016
1017 static const struct mrs_field id_aa64isar1_fields[] = {
1018 MRS_FIELD(ID_AA64ISAR1, LS64, false, MRS_LOWER, 0, id_aa64isar1_ls64),
1019 MRS_FIELD(ID_AA64ISAR1, XS, false, MRS_LOWER, 0, id_aa64isar1_xs),
1020 MRS_FIELD_HWCAP(ID_AA64ISAR1, I8MM, false, MRS_LOWER, MRS_USERSPACE,
1021 id_aa64isar1_i8mm, id_aa64isar1_i8mm_caps),
1022 MRS_FIELD_HWCAP(ID_AA64ISAR1, DGH, false, MRS_LOWER, MRS_USERSPACE,
1023 id_aa64isar1_dgh, id_aa64isar1_dgh_caps),
1024 MRS_FIELD_HWCAP(ID_AA64ISAR1, BF16, false, MRS_LOWER, MRS_USERSPACE,
1025 id_aa64isar1_bf16, id_aa64isar1_bf16_caps),
1026 MRS_FIELD(ID_AA64ISAR1, SPECRES, false, MRS_LOWER, 0,
1027 id_aa64isar1_specres),
1028 MRS_FIELD_HWCAP(ID_AA64ISAR1, SB, false, MRS_LOWER, MRS_USERSPACE,
1029 id_aa64isar1_sb, id_aa64isar1_sb_caps),
1030 MRS_FIELD_HWCAP(ID_AA64ISAR1, FRINTTS, false, MRS_LOWER, MRS_USERSPACE,
1031 id_aa64isar1_frintts, id_aa64isar1_frintts_caps),
1032 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPI, false, MRS_LOWER, MRS_USERSPACE,
1033 id_aa64isar1_gpi, id_aa64isar1_gpi_caps),
1034 MRS_FIELD_HWCAP(ID_AA64ISAR1, GPA, false, MRS_LOWER, MRS_USERSPACE,
1035 id_aa64isar1_gpa, id_aa64isar1_gpa_caps),
1036 MRS_FIELD_HWCAP(ID_AA64ISAR1, LRCPC, false, MRS_LOWER, MRS_USERSPACE,
1037 id_aa64isar1_lrcpc, id_aa64isar1_lrcpc_caps),
1038 MRS_FIELD_HWCAP(ID_AA64ISAR1, FCMA, false, MRS_LOWER, MRS_USERSPACE,
1039 id_aa64isar1_fcma, id_aa64isar1_fcma_caps),
1040 MRS_FIELD_HWCAP(ID_AA64ISAR1, JSCVT, false, MRS_LOWER, MRS_USERSPACE,
1041 id_aa64isar1_jscvt, id_aa64isar1_jscvt_caps),
1042 MRS_FIELD_HWCAP(ID_AA64ISAR1, API, false, MRS_LOWER, MRS_USERSPACE,
1043 id_aa64isar1_api, id_aa64isar1_api_caps),
1044 MRS_FIELD_HWCAP(ID_AA64ISAR1, APA, false, MRS_LOWER, MRS_USERSPACE,
1045 id_aa64isar1_apa, id_aa64isar1_apa_caps),
1046 MRS_FIELD_HWCAP(ID_AA64ISAR1, DPB, false, MRS_LOWER, MRS_USERSPACE,
1047 id_aa64isar1_dpb, id_aa64isar1_dpb_caps),
1048 MRS_FIELD_END,
1049 };
1050
1051
1052 /* ID_AA64ISAR2_EL1 */
1053 static const struct mrs_field_value id_aa64isar2_ats1a[] = {
1054 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, ATS1A, NONE, IMPL),
1055 MRS_FIELD_VALUE_END,
1056 };
1057
1058 static const struct mrs_field_value id_aa64isar2_cssc[] = {
1059 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, CSSC, NONE, IMPL),
1060 MRS_FIELD_VALUE_END,
1061 };
1062
1063 static const struct mrs_field_value id_aa64isar2_rprfm[] = {
1064 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRFM, NONE, IMPL),
1065 MRS_FIELD_VALUE_END,
1066 };
1067
1068 static const struct mrs_field_value id_aa64isar2_prfmslc[] = {
1069 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PRFMSLC, NONE, IMPL),
1070 MRS_FIELD_VALUE_END,
1071 };
1072
1073 static const struct mrs_field_value id_aa64isar2_clrbhb[] = {
1074 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, CLRBHB, NONE, IMPL),
1075 MRS_FIELD_VALUE_END,
1076 };
1077
1078 static const struct mrs_field_value id_aa64isar2_pac_frac[] = {
1079 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PAC_frac, NONE, IMPL),
1080 MRS_FIELD_VALUE_END,
1081 };
1082
1083 static const struct mrs_field_value id_aa64isar2_bc[] = {
1084 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, BC, NONE, IMPL),
1085 MRS_FIELD_VALUE_END,
1086 };
1087
1088 static const struct mrs_field_value id_aa64isar2_mops[] = {
1089 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, MOPS, NONE, IMPL),
1090 MRS_FIELD_VALUE_END,
1091 };
1092
1093 static const struct mrs_field_value id_aa64isar2_apa3[] = {
1094 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_NONE, ""),
1095 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_PAC, "APA3 PAC"),
1096 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC, "APA3 EPAC"),
1097 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC2, "APA3 EPAC2"),
1098 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC, "APA3 FPAC"),
1099 MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC_COMBINED,
1100 "APA3 FPAC+Combined"),
1101 MRS_FIELD_VALUE_END,
1102 };
1103
1104 static const struct mrs_field_hwcap id_aa64isar2_apa3_caps[] = {
1105 MRS_HWCAP(1, HWCAP_PACA, ID_AA64ISAR2_APA3_PAC),
1106 MRS_HWCAP_END
1107 };
1108
1109 static const struct mrs_field_value id_aa64isar2_gpa3[] = {
1110 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, GPA3, NONE, IMPL),
1111 MRS_FIELD_VALUE_END,
1112 };
1113
1114 static const struct mrs_field_hwcap id_aa64isar2_gpa3_caps[] = {
1115 MRS_HWCAP(1, HWCAP_PACG, ID_AA64ISAR2_GPA3_IMPL),
1116 MRS_HWCAP_END
1117 };
1118
1119 static const struct mrs_field_value id_aa64isar2_rpres[] = {
1120 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRES, NONE, IMPL),
1121 MRS_FIELD_VALUE_END,
1122 };
1123
1124 static const struct mrs_field_hwcap id_aa64isar2_rpres_caps[] = {
1125 MRS_HWCAP(2, HWCAP2_RPRES, ID_AA64ISAR2_RPRES_IMPL),
1126 MRS_HWCAP_END
1127 };
1128
1129 static const struct mrs_field_value id_aa64isar2_wfxt[] = {
1130 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, WFxT, NONE, IMPL),
1131 MRS_FIELD_VALUE_END,
1132 };
1133
1134 static const struct mrs_field_hwcap id_aa64isar2_wfxt_caps[] = {
1135 MRS_HWCAP(2, HWCAP2_WFXT, ID_AA64ISAR2_WFxT_IMPL),
1136 MRS_HWCAP_END
1137 };
1138
1139 static const struct mrs_field id_aa64isar2_fields[] = {
1140 MRS_FIELD(ID_AA64ISAR2, ATS1A, false, MRS_LOWER, 0, id_aa64isar2_ats1a),
1141 MRS_FIELD(ID_AA64ISAR2, CSSC, false, MRS_LOWER, 0, id_aa64isar2_cssc),
1142 MRS_FIELD(ID_AA64ISAR2, RPRFM, false, MRS_LOWER, 0, id_aa64isar2_rprfm),
1143 MRS_FIELD(ID_AA64ISAR2, PRFMSLC, false, MRS_LOWER, 0, id_aa64isar2_prfmslc),
1144 MRS_FIELD(ID_AA64ISAR2, CLRBHB, false, MRS_LOWER, 0, id_aa64isar2_clrbhb),
1145 MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_LOWER, 0,
1146 id_aa64isar2_pac_frac),
1147 MRS_FIELD(ID_AA64ISAR2, BC, false, MRS_LOWER, 0, id_aa64isar2_bc),
1148 MRS_FIELD(ID_AA64ISAR2, MOPS, false, MRS_LOWER, 0, id_aa64isar2_mops),
1149 MRS_FIELD_HWCAP(ID_AA64ISAR2, APA3, false, MRS_LOWER, MRS_USERSPACE,
1150 id_aa64isar2_apa3, id_aa64isar2_apa3_caps),
1151 MRS_FIELD_HWCAP(ID_AA64ISAR2, GPA3, false, MRS_LOWER, MRS_USERSPACE,
1152 id_aa64isar2_gpa3, id_aa64isar2_gpa3_caps),
1153 MRS_FIELD_HWCAP(ID_AA64ISAR2, RPRES, false, MRS_LOWER, MRS_USERSPACE,
1154 id_aa64isar2_rpres, id_aa64isar2_rpres_caps),
1155 MRS_FIELD_HWCAP(ID_AA64ISAR2, WFxT, false, MRS_LOWER, 0,
1156 id_aa64isar2_wfxt, id_aa64isar2_wfxt_caps),
1157 MRS_FIELD_END,
1158 };
1159
1160
1161 /* ID_AA64MMFR0_EL1 */
1162 static const struct mrs_field_value id_aa64mmfr0_ecv[] = {
1163 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ECV, NONE, IMPL),
1164 MRS_FIELD_VALUE(ID_AA64MMFR0_ECV_POFF, "ECV POFF"),
1165 MRS_FIELD_VALUE_END,
1166 };
1167
1168 static const struct mrs_field_value id_aa64mmfr0_fgt[] = {
1169 MRS_FIELD_VALUE(ID_AA64MMFR0_FGT_NONE, ""),
1170 MRS_FIELD_VALUE(ID_AA64MMFR0_FGT_8_6, "FGT v8.6"),
1171 MRS_FIELD_VALUE(ID_AA64MMFR0_FGT_8_9, "FGT v8.9"),
1172 MRS_FIELD_VALUE_END,
1173 };
1174
1175 static const struct mrs_field_value id_aa64mmfr0_exs[] = {
1176 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
1177 MRS_FIELD_VALUE_END,
1178 };
1179
1180 static const struct mrs_field_value id_aa64mmfr0_tgran4_2[] = {
1181 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_TGran4, ""),
1182 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_NONE, "No S2 TGran4"),
1183 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_IMPL, "S2 TGran4"),
1184 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_2_LPA2, "S2 TGran4+LPA2"),
1185 MRS_FIELD_VALUE_END,
1186 };
1187
1188 static const struct mrs_field_value id_aa64mmfr0_tgran64_2[] = {
1189 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_TGran64, ""),
1190 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_NONE, "No S2 TGran64"),
1191 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran64_2_IMPL, "S2 TGran64"),
1192 MRS_FIELD_VALUE_END,
1193 };
1194
1195 static const struct mrs_field_value id_aa64mmfr0_tgran16_2[] = {
1196 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_TGran16, ""),
1197 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_NONE, "No S2 TGran16"),
1198 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_IMPL, "S2 TGran16"),
1199 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_2_LPA2, "S2 TGran16+LPA2"),
1200 MRS_FIELD_VALUE_END,
1201 };
1202
1203 static const struct mrs_field_value id_aa64mmfr0_tgran4[] = {
1204 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran4, NONE, IMPL),
1205 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran4_LPA2, "TGran4+LPA2"),
1206 MRS_FIELD_VALUE_END,
1207 };
1208
1209 static const struct mrs_field_value id_aa64mmfr0_tgran64[] = {
1210 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran64, NONE, IMPL),
1211 MRS_FIELD_VALUE_END,
1212 };
1213
1214 static const struct mrs_field_value id_aa64mmfr0_tgran16[] = {
1215 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, TGran16, NONE, IMPL),
1216 MRS_FIELD_VALUE(ID_AA64MMFR0_TGran16_LPA2, "TGran16+LPA2"),
1217 MRS_FIELD_VALUE_END,
1218 };
1219
1220 static const struct mrs_field_value id_aa64mmfr0_bigendel0[] = {
1221 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEndEL0, FIXED, MIXED),
1222 MRS_FIELD_VALUE_END,
1223 };
1224
1225 static const struct mrs_field_value id_aa64mmfr0_snsmem[] = {
1226 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, SNSMem, NONE, DISTINCT),
1227 MRS_FIELD_VALUE_END,
1228 };
1229
1230 static const struct mrs_field_value id_aa64mmfr0_bigend[] = {
1231 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, BigEnd, FIXED, MIXED),
1232 MRS_FIELD_VALUE_END,
1233 };
1234
1235 static const struct mrs_field_value id_aa64mmfr0_asidbits[] = {
1236 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_8, "8bit ASID"),
1237 MRS_FIELD_VALUE(ID_AA64MMFR0_ASIDBits_16, "16bit ASID"),
1238 MRS_FIELD_VALUE_END,
1239 };
1240
1241 static const struct mrs_field_value id_aa64mmfr0_parange[] = {
1242 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4G, "4GB PA"),
1243 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_64G, "64GB PA"),
1244 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_1T, "1TB PA"),
1245 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4T, "4TB PA"),
1246 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_16T, "16TB PA"),
1247 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_256T, "256TB PA"),
1248 MRS_FIELD_VALUE(ID_AA64MMFR0_PARange_4P, "4PB PA"),
1249 MRS_FIELD_VALUE_END,
1250 };
1251
1252 static const struct mrs_field id_aa64mmfr0_fields[] = {
1253 MRS_FIELD(ID_AA64MMFR0, ECV, false, MRS_LOWER, 0, id_aa64mmfr0_ecv),
1254 MRS_FIELD(ID_AA64MMFR0, FGT, false, MRS_LOWER, 0, id_aa64mmfr0_fgt),
1255 MRS_FIELD(ID_AA64MMFR0, ExS, false, MRS_LOWER, 0, id_aa64mmfr0_exs),
1256 MRS_FIELD(ID_AA64MMFR0, TGran4_2, false, MRS_LOWER, 0,
1257 id_aa64mmfr0_tgran4_2),
1258 MRS_FIELD(ID_AA64MMFR0, TGran64_2, false, MRS_LOWER, 0,
1259 id_aa64mmfr0_tgran64_2),
1260 MRS_FIELD(ID_AA64MMFR0, TGran16_2, false, MRS_LOWER, 0,
1261 id_aa64mmfr0_tgran16_2),
1262 MRS_FIELD(ID_AA64MMFR0, TGran4, true, MRS_LOWER, 0,
1263 id_aa64mmfr0_tgran4),
1264 MRS_FIELD(ID_AA64MMFR0, TGran64, true, MRS_LOWER, 0,
1265 id_aa64mmfr0_tgran64),
1266 MRS_FIELD(ID_AA64MMFR0, TGran16, false, MRS_LOWER, 0,
1267 id_aa64mmfr0_tgran16),
1268 MRS_FIELD(ID_AA64MMFR0, BigEndEL0, false, MRS_LOWER, 0,
1269 id_aa64mmfr0_bigendel0),
1270 MRS_FIELD(ID_AA64MMFR0, SNSMem, false, MRS_LOWER, 0,
1271 id_aa64mmfr0_snsmem),
1272 MRS_FIELD(ID_AA64MMFR0, BigEnd, false, MRS_LOWER, 0,
1273 id_aa64mmfr0_bigend),
1274 MRS_FIELD(ID_AA64MMFR0, ASIDBits, false, MRS_LOWER, 0,
1275 id_aa64mmfr0_asidbits),
1276 MRS_FIELD(ID_AA64MMFR0, PARange, false, MRS_LOWER, 0,
1277 id_aa64mmfr0_parange),
1278 MRS_FIELD_END,
1279 };
1280
1281
1282 /* ID_AA64MMFR1_EL1 */
1283 static const struct mrs_field_value id_aa64mmfr1_ecbhb[] = {
1284 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, ECBHB, NONE, IMPL),
1285 MRS_FIELD_VALUE_END,
1286 };
1287
1288 static const struct mrs_field_value id_aa64mmfr1_cmovw[] = {
1289 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, CMOVW, NONE, IMPL),
1290 MRS_FIELD_VALUE_END,
1291 };
1292
1293 static const struct mrs_field_value id_aa64mmfr1_tidcp1[] = {
1294 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TIDCP1, NONE, IMPL),
1295 MRS_FIELD_VALUE_END,
1296 };
1297
1298 static const struct mrs_field_value id_aa64mmfr1_ntlbpa[] = {
1299 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, nTLBPA, NONE, IMPL),
1300 MRS_FIELD_VALUE_END,
1301 };
1302
1303 static const struct mrs_field_value id_aa64mmfr1_afp[] = {
1304 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, AFP, NONE, IMPL),
1305 MRS_FIELD_VALUE_END,
1306 };
1307
1308 static const struct mrs_field_hwcap id_aa64mmfr1_afp_caps[] = {
1309 MRS_HWCAP(2, HWCAP2_AFP, ID_AA64MMFR1_AFP_IMPL),
1310 MRS_HWCAP_END
1311 };
1312
1313 static const struct mrs_field_value id_aa64mmfr1_hcx[] = {
1314 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, HCX, NONE, IMPL),
1315 MRS_FIELD_VALUE_END,
1316 };
1317
1318 static const struct mrs_field_value id_aa64mmfr1_ets[] = {
1319 MRS_FIELD_VALUE(ID_AA64MMFR1_ETS_NONE, ""),
1320 MRS_FIELD_VALUE(ID_AA64MMFR1_ETS_NONE2, ""),
1321 MRS_FIELD_VALUE(ID_AA64MMFR1_ETS_IMPL, "ETS2"),
1322 MRS_FIELD_VALUE_END,
1323 };
1324
1325 static const struct mrs_field_value id_aa64mmfr1_twed[] = {
1326 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, TWED, NONE, IMPL),
1327 MRS_FIELD_VALUE_END,
1328 };
1329
1330 static const struct mrs_field_value id_aa64mmfr1_xnx[] = {
1331 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, XNX, NONE, IMPL),
1332 MRS_FIELD_VALUE_END,
1333 };
1334
1335 static const struct mrs_field_value id_aa64mmfr1_specsei[] = {
1336 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, SpecSEI, NONE, IMPL),
1337 MRS_FIELD_VALUE_END,
1338 };
1339
1340 static const struct mrs_field_value id_aa64mmfr1_pan[] = {
1341 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, PAN, NONE, IMPL),
1342 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_ATS1E1, "PAN+ATS1E1"),
1343 MRS_FIELD_VALUE(ID_AA64MMFR1_PAN_EPAN, "EPAN"),
1344 MRS_FIELD_VALUE_END,
1345 };
1346
1347 static const struct mrs_field_value id_aa64mmfr1_lo[] = {
1348 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, LO, NONE, IMPL),
1349 MRS_FIELD_VALUE_END,
1350 };
1351
1352 static const struct mrs_field_value id_aa64mmfr1_hpds[] = {
1353 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_NONE, ""),
1354 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_HPD, "HPD"),
1355 MRS_FIELD_VALUE(ID_AA64MMFR1_HPDS_TTPBHA, "HPD+TTPBHA"),
1356 MRS_FIELD_VALUE_END,
1357 };
1358
1359 static const struct mrs_field_value id_aa64mmfr1_vh[] = {
1360 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR1, VH, NONE, IMPL),
1361 MRS_FIELD_VALUE_END,
1362 };
1363
1364 static const struct mrs_field_value id_aa64mmfr1_vmidbits[] = {
1365 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_8, "8bit VMID"),
1366 MRS_FIELD_VALUE(ID_AA64MMFR1_VMIDBits_16, "16bit VMID"),
1367 MRS_FIELD_VALUE_END,
1368 };
1369
1370 static const struct mrs_field_value id_aa64mmfr1_hafdbs[] = {
1371 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_NONE, ""),
1372 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF, "HAF"),
1373 MRS_FIELD_VALUE(ID_AA64MMFR1_HAFDBS_AF_DBS, "HAF+DS"),
1374 MRS_FIELD_VALUE_END,
1375 };
1376
1377 static const struct mrs_field id_aa64mmfr1_fields[] = {
1378 MRS_FIELD(ID_AA64MMFR1, ECBHB, false, MRS_LOWER, 0, id_aa64mmfr1_ecbhb),
1379 MRS_FIELD(ID_AA64MMFR1, CMOVW, false, MRS_LOWER, 0, id_aa64mmfr1_cmovw),
1380 MRS_FIELD(ID_AA64MMFR1, TIDCP1, false, MRS_LOWER, 0,
1381 id_aa64mmfr1_tidcp1),
1382 MRS_FIELD(ID_AA64MMFR1, nTLBPA, false, MRS_LOWER, 0,
1383 id_aa64mmfr1_ntlbpa),
1384 MRS_FIELD_HWCAP(ID_AA64MMFR1, AFP, false, MRS_LOWER, 0,
1385 id_aa64mmfr1_afp, id_aa64mmfr1_afp_caps),
1386 MRS_FIELD(ID_AA64MMFR1, HCX, false, MRS_LOWER, 0, id_aa64mmfr1_hcx),
1387 MRS_FIELD(ID_AA64MMFR1, ETS, false, MRS_LOWER, 0, id_aa64mmfr1_ets),
1388 MRS_FIELD(ID_AA64MMFR1, TWED, false, MRS_LOWER, 0, id_aa64mmfr1_twed),
1389 MRS_FIELD(ID_AA64MMFR1, XNX, false, MRS_LOWER, 0, id_aa64mmfr1_xnx),
1390 /*
1391 * SpecSEI != 0 indicates the CPU might generate an external abort
1392 * under speculation, while 0 indicates it can't happen. It's safer
1393 * to incorrectly indicate it might happen when it can't rather than
1394 * say it can't happen when it could. As such use the largest value
1395 * found in the system.
1396 */
1397 MRS_FIELD(ID_AA64MMFR1, SpecSEI, false, MRS_HIGHER, 0,
1398 id_aa64mmfr1_specsei),
1399 MRS_FIELD(ID_AA64MMFR1, PAN, false, MRS_LOWER, 0, id_aa64mmfr1_pan),
1400 MRS_FIELD(ID_AA64MMFR1, LO, false, MRS_LOWER, 0, id_aa64mmfr1_lo),
1401 MRS_FIELD(ID_AA64MMFR1, HPDS, false, MRS_LOWER, 0, id_aa64mmfr1_hpds),
1402 MRS_FIELD(ID_AA64MMFR1, VH, false, MRS_LOWER, 0, id_aa64mmfr1_vh),
1403 MRS_FIELD(ID_AA64MMFR1, VMIDBits, false, MRS_LOWER, 0,
1404 id_aa64mmfr1_vmidbits),
1405 MRS_FIELD(ID_AA64MMFR1, HAFDBS, false, MRS_LOWER, 0, id_aa64mmfr1_hafdbs),
1406 MRS_FIELD_END,
1407 };
1408
1409
1410 /* ID_AA64MMFR2_EL1 */
1411 static const struct mrs_field_value id_aa64mmfr2_e0pd[] = {
1412 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, E0PD, NONE, IMPL),
1413 MRS_FIELD_VALUE_END,
1414 };
1415
1416 static const struct mrs_field_value id_aa64mmfr2_evt[] = {
1417 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_NONE, ""),
1418 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_2, "EVT-8.2"),
1419 MRS_FIELD_VALUE(ID_AA64MMFR2_EVT_8_5, "EVT-8.5"),
1420 MRS_FIELD_VALUE_END,
1421 };
1422
1423 static const struct mrs_field_value id_aa64mmfr2_bbm[] = {
1424 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL0, ""),
1425 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL1, "BBM level 1"),
1426 MRS_FIELD_VALUE(ID_AA64MMFR2_BBM_LEVEL2, "BBM level 2"),
1427 MRS_FIELD_VALUE_END,
1428 };
1429
1430 static const struct mrs_field_value id_aa64mmfr2_ttl[] = {
1431 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, TTL, NONE, IMPL),
1432 MRS_FIELD_VALUE_END,
1433 };
1434
1435 static const struct mrs_field_value id_aa64mmfr2_fwb[] = {
1436 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, FWB, NONE, IMPL),
1437 MRS_FIELD_VALUE_END,
1438 };
1439
1440 static const struct mrs_field_value id_aa64mmfr2_ids[] = {
1441 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IDS, NONE, IMPL),
1442 MRS_FIELD_VALUE_END,
1443 };
1444
1445 static const struct mrs_field_value id_aa64mmfr2_at[] = {
1446 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, AT, NONE, IMPL),
1447 MRS_FIELD_VALUE_END,
1448 };
1449
1450 static const struct mrs_field_hwcap id_aa64mmfr2_at_caps[] = {
1451 MRS_HWCAP(1, HWCAP_USCAT, ID_AA64MMFR2_AT_IMPL),
1452 MRS_HWCAP_END
1453 };
1454
1455 static const struct mrs_field_value id_aa64mmfr2_st[] = {
1456 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, ST, NONE, IMPL),
1457 MRS_FIELD_VALUE_END,
1458 };
1459
1460 static const struct mrs_field_value id_aa64mmfr2_nv[] = {
1461 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, NV, NONE, 8_3),
1462 MRS_FIELD_VALUE(ID_AA64MMFR2_NV_8_4, "NV v8.4"),
1463 MRS_FIELD_VALUE_END,
1464 };
1465
1466 static const struct mrs_field_value id_aa64mmfr2_ccidx[] = {
1467 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_32, "32bit CCIDX"),
1468 MRS_FIELD_VALUE(ID_AA64MMFR2_CCIDX_64, "64bit CCIDX"),
1469 MRS_FIELD_VALUE_END,
1470 };
1471
1472 static const struct mrs_field_value id_aa64mmfr2_varange[] = {
1473 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_48, "48bit VA"),
1474 MRS_FIELD_VALUE(ID_AA64MMFR2_VARange_52, "52bit VA"),
1475 MRS_FIELD_VALUE_END,
1476 };
1477
1478 static const struct mrs_field_value id_aa64mmfr2_iesb[] = {
1479 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, IESB, NONE, IMPL),
1480 MRS_FIELD_VALUE_END,
1481 };
1482
1483 static const struct mrs_field_value id_aa64mmfr2_lsm[] = {
1484 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, LSM, NONE, IMPL),
1485 MRS_FIELD_VALUE_END,
1486 };
1487
1488 static const struct mrs_field_value id_aa64mmfr2_uao[] = {
1489 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, UAO, NONE, IMPL),
1490 MRS_FIELD_VALUE_END,
1491 };
1492
1493 static const struct mrs_field_value id_aa64mmfr2_cnp[] = {
1494 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR2, CnP, NONE, IMPL),
1495 MRS_FIELD_VALUE_END,
1496 };
1497
1498 static const struct mrs_field id_aa64mmfr2_fields[] = {
1499 MRS_FIELD(ID_AA64MMFR2, E0PD, false, MRS_LOWER, 0, id_aa64mmfr2_e0pd),
1500 MRS_FIELD(ID_AA64MMFR2, EVT, false, MRS_LOWER, 0, id_aa64mmfr2_evt),
1501 MRS_FIELD(ID_AA64MMFR2, BBM, false, MRS_LOWER, 0, id_aa64mmfr2_bbm),
1502 MRS_FIELD(ID_AA64MMFR2, TTL, false, MRS_LOWER, 0, id_aa64mmfr2_ttl),
1503 MRS_FIELD(ID_AA64MMFR2, FWB, false, MRS_LOWER, 0, id_aa64mmfr2_fwb),
1504 MRS_FIELD(ID_AA64MMFR2, IDS, false, MRS_LOWER, 0, id_aa64mmfr2_ids),
1505 MRS_FIELD_HWCAP(ID_AA64MMFR2, AT, false, MRS_LOWER, MRS_USERSPACE,
1506 id_aa64mmfr2_at, id_aa64mmfr2_at_caps),
1507 MRS_FIELD(ID_AA64MMFR2, ST, false, MRS_LOWER, 0, id_aa64mmfr2_st),
1508 MRS_FIELD(ID_AA64MMFR2, NV, false, MRS_LOWER, 0, id_aa64mmfr2_nv),
1509 MRS_FIELD(ID_AA64MMFR2, CCIDX, false, MRS_LOWER, 0, id_aa64mmfr2_ccidx),
1510 MRS_FIELD(ID_AA64MMFR2, VARange, false, MRS_LOWER, 0,
1511 id_aa64mmfr2_varange),
1512 MRS_FIELD(ID_AA64MMFR2, IESB, false, MRS_LOWER, 0, id_aa64mmfr2_iesb),
1513 MRS_FIELD(ID_AA64MMFR2, LSM, false, MRS_LOWER, 0, id_aa64mmfr2_lsm),
1514 MRS_FIELD(ID_AA64MMFR2, UAO, false, MRS_LOWER, 0, id_aa64mmfr2_uao),
1515 MRS_FIELD(ID_AA64MMFR2, CnP, false, MRS_LOWER, 0, id_aa64mmfr2_cnp),
1516 MRS_FIELD_END,
1517 };
1518
1519
1520 /* ID_AA64MMFR2_EL1 */
1521 static const struct mrs_field_value id_aa64mmfr3_spec_fpacc[] = {
1522 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, Spec_FPACC, NONE, IMPL),
1523 MRS_FIELD_VALUE_END,
1524 };
1525
1526 static const struct mrs_field_value id_aa64mmfr3_aderr[] = {
1527 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, ADERR, NONE, SOME),
1528 MRS_FIELD_VALUE_END,
1529 };
1530
1531 static const struct mrs_field_value id_aa64mmfr3_sderr[] = {
1532 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SDERR, NONE, ALL),
1533 MRS_FIELD_VALUE_END,
1534 };
1535
1536 static const struct mrs_field_value id_aa64mmfr3_anerr[] = {
1537 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, ANERR, NONE, SOME),
1538 MRS_FIELD_VALUE_END,
1539 };
1540
1541 static const struct mrs_field_value id_aa64mmfr3_snerr[] = {
1542 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SNERR, NONE, ALL),
1543 MRS_FIELD_VALUE_END,
1544 };
1545
1546 static const struct mrs_field_value id_aa64mmfr3_mec[] = {
1547 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, MEC, NONE, IMPL),
1548 MRS_FIELD_VALUE_END,
1549 };
1550
1551 static const struct mrs_field_value id_aa64mmfr3_aie[] = {
1552 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, AIE, NONE, IMPL),
1553 MRS_FIELD_VALUE_END,
1554 };
1555
1556 static const struct mrs_field_value id_aa64mmfr3_s2poe[] = {
1557 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S2POE, NONE, IMPL),
1558 MRS_FIELD_VALUE_END,
1559 };
1560
1561 static const struct mrs_field_value id_aa64mmfr3_s1poe[] = {
1562 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S1POE, NONE, IMPL),
1563 MRS_FIELD_VALUE_END,
1564 };
1565
1566 static const struct mrs_field_value id_aa64mmfr3_s2pie[] = {
1567 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S2PIE, NONE, IMPL),
1568 MRS_FIELD_VALUE_END,
1569 };
1570
1571 static const struct mrs_field_value id_aa64mmfr3_s1pie[] = {
1572 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, S1PIE, NONE, IMPL),
1573 MRS_FIELD_VALUE_END,
1574 };
1575
1576 static const struct mrs_field_value id_aa64mmfr3_sctlrx[] = {
1577 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SCTLRX, NONE, IMPL),
1578 MRS_FIELD_VALUE_END,
1579 };
1580
1581 static const struct mrs_field_value id_aa64mmfr3_tcrx[] = {
1582 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, TCRX, NONE, IMPL),
1583 MRS_FIELD_VALUE_END,
1584 };
1585
1586 static const struct mrs_field id_aa64mmfr3_fields[] = {
1587 MRS_FIELD(ID_AA64MMFR3, Spec_FPACC, false, MRS_LOWER, 0,
1588 id_aa64mmfr3_spec_fpacc),
1589 MRS_FIELD(ID_AA64MMFR3, ADERR, false, MRS_LOWER, 0, id_aa64mmfr3_aderr),
1590 MRS_FIELD(ID_AA64MMFR3, SDERR, false, MRS_LOWER, 0, id_aa64mmfr3_sderr),
1591 MRS_FIELD(ID_AA64MMFR3, ANERR, false, MRS_LOWER, 0, id_aa64mmfr3_anerr),
1592 MRS_FIELD(ID_AA64MMFR3, SNERR, false, MRS_LOWER, 0, id_aa64mmfr3_snerr),
1593 MRS_FIELD(ID_AA64MMFR3, MEC, false, MRS_LOWER, 0, id_aa64mmfr3_mec),
1594 MRS_FIELD(ID_AA64MMFR3, AIE, false, MRS_LOWER, 0, id_aa64mmfr3_aie),
1595 MRS_FIELD(ID_AA64MMFR3, S2POE, false, MRS_LOWER, 0, id_aa64mmfr3_s2poe),
1596 MRS_FIELD(ID_AA64MMFR3, S1POE, false, MRS_LOWER, 0, id_aa64mmfr3_s1poe),
1597 MRS_FIELD(ID_AA64MMFR3, S2PIE, false, MRS_LOWER, 0, id_aa64mmfr3_s2pie),
1598 MRS_FIELD(ID_AA64MMFR3, S1PIE, false, MRS_LOWER, 0, id_aa64mmfr3_s1pie),
1599 MRS_FIELD(ID_AA64MMFR3, SCTLRX, false, MRS_LOWER, 0,
1600 id_aa64mmfr3_sctlrx),
1601 MRS_FIELD(ID_AA64MMFR3, TCRX, false, MRS_LOWER, 0, id_aa64mmfr3_tcrx),
1602 MRS_FIELD_END,
1603 };
1604
1605
1606 /* ID_AA64MMFR4_EL1 */
1607 static const struct mrs_field id_aa64mmfr4_fields[] = {
1608 MRS_FIELD_END,
1609 };
1610
1611
1612 /* ID_AA64PFR0_EL1 */
1613 static const struct mrs_field_value id_aa64pfr0_csv3[] = {
1614 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
1615 MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_ISOLATED, "CSV3"),
1616 MRS_FIELD_VALUE_END,
1617 };
1618
1619 static const struct mrs_field_value id_aa64pfr0_csv2[] = {
1620 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_NONE, ""),
1621 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_ISOLATED, "CSV2"),
1622 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_SCXTNUM, "CSV2_2"),
1623 MRS_FIELD_VALUE(ID_AA64PFR0_CSV2_3, "CSV2_3"),
1624 MRS_FIELD_VALUE_END,
1625 };
1626
1627 static const struct mrs_field_value id_aa64pfr0_rme[] = {
1628 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, RME, NONE, IMPL),
1629 MRS_FIELD_VALUE_END,
1630 };
1631
1632 static const struct mrs_field_value id_aa64pfr0_dit[] = {
1633 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_NONE, ""),
1634 MRS_FIELD_VALUE(ID_AA64PFR0_DIT_PSTATE, "PSTATE.DIT"),
1635 MRS_FIELD_VALUE_END,
1636 };
1637
1638 static const struct mrs_field_hwcap id_aa64pfr0_dit_caps[] = {
1639 MRS_HWCAP(1, HWCAP_DIT, ID_AA64PFR0_DIT_PSTATE),
1640 MRS_HWCAP_END
1641 };
1642
1643 static const struct mrs_field_value id_aa64pfr0_amu[] = {
1644 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_NONE, ""),
1645 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1, "AMUv1"),
1646 MRS_FIELD_VALUE(ID_AA64PFR0_AMU_V1_1, "AMUv1p1"),
1647 MRS_FIELD_VALUE_END,
1648 };
1649
1650 static const struct mrs_field_value id_aa64pfr0_mpam[] = {
1651 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, MPAM, NONE, IMPL),
1652 MRS_FIELD_VALUE_END,
1653 };
1654
1655 static const struct mrs_field_value id_aa64pfr0_sel2[] = {
1656 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SEL2, NONE, IMPL),
1657 MRS_FIELD_VALUE_END,
1658 };
1659
1660 static const struct mrs_field_value id_aa64pfr0_sve[] = {
1661 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, SVE, NONE, IMPL),
1662 MRS_FIELD_VALUE_END,
1663 };
1664
1665 static const struct mrs_field_hwcap id_aa64pfr0_sve_caps[] = {
1666 MRS_HWCAP(1, HWCAP_SVE, ID_AA64PFR0_SVE_IMPL),
1667 MRS_HWCAP_END
1668 };
1669
1670 static const struct mrs_field_value id_aa64pfr0_ras[] = {
1671 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_NONE, ""),
1672 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_IMPL, "RAS"),
1673 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_4, "RAS v8.4"),
1674 MRS_FIELD_VALUE(ID_AA64PFR0_RAS_8_9, "RAS v8.9"),
1675 MRS_FIELD_VALUE_END,
1676 };
1677
1678 static const struct mrs_field_value id_aa64pfr0_gic[] = {
1679 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN),
1680 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""),
1681 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"),
1682 MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"),
1683 MRS_FIELD_VALUE_END,
1684 };
1685
1686 static const struct mrs_field_value id_aa64pfr0_advsimd[] = {
1687 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, AdvSIMD, NONE, IMPL),
1688 MRS_FIELD_VALUE(ID_AA64PFR0_AdvSIMD_HP, "AdvSIMD+HP"),
1689 MRS_FIELD_VALUE_END,
1690 };
1691
1692 static const struct mrs_field_hwcap id_aa64pfr0_advsimd_caps[] = {
1693 MRS_HWCAP(1, HWCAP_ASIMD, ID_AA64PFR0_AdvSIMD_IMPL),
1694 MRS_HWCAP(1, HWCAP_ASIMDHP, ID_AA64PFR0_AdvSIMD_HP),
1695 MRS_HWCAP_END
1696 };
1697
1698 static const struct mrs_field_value id_aa64pfr0_fp[] = {
1699 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, FP, NONE, IMPL),
1700 MRS_FIELD_VALUE(ID_AA64PFR0_FP_HP, "FP+HP"),
1701 MRS_FIELD_VALUE_END,
1702 };
1703
1704 static const struct mrs_field_hwcap id_aa64pfr0_fp_caps[] = {
1705 MRS_HWCAP(1, HWCAP_FP, ID_AA64PFR0_FP_IMPL),
1706 MRS_HWCAP(1, HWCAP_FPHP, ID_AA64PFR0_FP_HP),
1707 MRS_HWCAP_END
1708 };
1709
1710 static const struct mrs_field_value id_aa64pfr0_el3[] = {
1711 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL3, NONE, 64),
1712 MRS_FIELD_VALUE(ID_AA64PFR0_EL3_64_32, "EL3 32"),
1713 MRS_FIELD_VALUE_END,
1714 };
1715
1716 static const struct mrs_field_value id_aa64pfr0_el2[] = {
1717 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, EL2, NONE, 64),
1718 MRS_FIELD_VALUE(ID_AA64PFR0_EL2_64_32, "EL2 32"),
1719 MRS_FIELD_VALUE_END,
1720 };
1721
1722 static const struct mrs_field_value id_aa64pfr0_el1[] = {
1723 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64, "EL1"),
1724 MRS_FIELD_VALUE(ID_AA64PFR0_EL1_64_32, "EL1 32"),
1725 MRS_FIELD_VALUE_END,
1726 };
1727
1728 static const struct mrs_field_value id_aa64pfr0_el0[] = {
1729 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64, "EL0"),
1730 MRS_FIELD_VALUE(ID_AA64PFR0_EL0_64_32, "EL0 32"),
1731 MRS_FIELD_VALUE_END,
1732 };
1733
1734 static const struct mrs_field id_aa64pfr0_fields[] = {
1735 MRS_FIELD(ID_AA64PFR0, CSV3, false, MRS_LOWER, 0, id_aa64pfr0_csv3),
1736 MRS_FIELD(ID_AA64PFR0, CSV2, false, MRS_LOWER, 0, id_aa64pfr0_csv2),
1737 MRS_FIELD(ID_AA64PFR0, RME, false, MRS_LOWER, 0, id_aa64pfr0_rme),
1738 MRS_FIELD_HWCAP(ID_AA64PFR0, DIT, false, MRS_LOWER, MRS_USERSPACE,
1739 id_aa64pfr0_dit, id_aa64pfr0_dit_caps),
1740 MRS_FIELD(ID_AA64PFR0, AMU, false, MRS_LOWER, 0, id_aa64pfr0_amu),
1741 MRS_FIELD(ID_AA64PFR0, MPAM, false, MRS_LOWER, 0, id_aa64pfr0_mpam),
1742 MRS_FIELD(ID_AA64PFR0, SEL2, false, MRS_LOWER, 0, id_aa64pfr0_sel2),
1743 MRS_FIELD_HWCAP(ID_AA64PFR0, SVE, false, MRS_LOWER,
1744 MRS_FREEBSD, id_aa64pfr0_sve, id_aa64pfr0_sve_caps),
1745 MRS_FIELD(ID_AA64PFR0, RAS, false, MRS_LOWER, 0, id_aa64pfr0_ras),
1746 MRS_FIELD(ID_AA64PFR0, GIC, false, MRS_LOWER, 0, id_aa64pfr0_gic),
1747 MRS_FIELD_HWCAP(ID_AA64PFR0, AdvSIMD, true, MRS_LOWER, MRS_USERSPACE,
1748 id_aa64pfr0_advsimd, id_aa64pfr0_advsimd_caps),
1749 MRS_FIELD_HWCAP(ID_AA64PFR0, FP, true, MRS_LOWER, MRS_USERSPACE,
1750 id_aa64pfr0_fp, id_aa64pfr0_fp_caps),
1751 MRS_FIELD(ID_AA64PFR0, EL3, false, MRS_LOWER, 0, id_aa64pfr0_el3),
1752 MRS_FIELD(ID_AA64PFR0, EL2, false, MRS_LOWER, 0, id_aa64pfr0_el2),
1753 MRS_FIELD(ID_AA64PFR0, EL1, false, MRS_LOWER, MRS_USERSPACE,
1754 id_aa64pfr0_el1),
1755 MRS_FIELD(ID_AA64PFR0, EL0, false, MRS_LOWER, MRS_USERSPACE,
1756 id_aa64pfr0_el0),
1757 MRS_FIELD_END,
1758 };
1759
1760
1761 /* ID_AA64PFR1_EL1 */
1762 static const struct mrs_field_value id_aa64pfr1_pfar[] = {
1763 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, PFAR, NONE, IMPL),
1764 MRS_FIELD_VALUE_END,
1765 };
1766
1767 static const struct mrs_field_value id_aa64pfr1_df2[] = {
1768 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, DF2, NONE, IMPL),
1769 MRS_FIELD_VALUE_END,
1770 };
1771
1772 static const struct mrs_field_value id_aa64pfr1_mtex[] = {
1773 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, MTEX, NONE, IMPL),
1774 MRS_FIELD_VALUE_END,
1775 };
1776
1777 static const struct mrs_field_value id_aa64pfr1_the[] = {
1778 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, THE, NONE, IMPL),
1779 MRS_FIELD_VALUE_END,
1780 };
1781
1782 static const struct mrs_field_value id_aa64pfr1_mtefrac[] = {
1783 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, MTE_frac, NONE, IMPL),
1784 MRS_FIELD_VALUE_END,
1785 };
1786
1787 static const struct mrs_field_value id_aa64pfr1_nmi[] = {
1788 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, NMI, NONE, IMPL),
1789 MRS_FIELD_VALUE_END,
1790 };
1791
1792 static const struct mrs_field_value id_aa64pfr1_csv2_frac[] = {
1793 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p0, ""),
1794 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p1, "CSV2 p1"),
1795 MRS_FIELD_VALUE(ID_AA64PFR1_CSV2_frac_p2, "CSV2 p2"),
1796 MRS_FIELD_VALUE_END,
1797 };
1798
1799 static const struct mrs_field_value id_aa64pfr1_rndr_trap[] = {
1800 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, RNDR_trap, NONE, IMPL),
1801 MRS_FIELD_VALUE_END,
1802 };
1803
1804 static const struct mrs_field_value id_aa64pfr1_sme[] = {
1805 MRS_FIELD_VALUE(ID_AA64PFR1_SME_NONE, ""),
1806 MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME, "SME"),
1807 MRS_FIELD_VALUE(ID_AA64PFR1_SME_SME2, "SME2"),
1808 MRS_FIELD_VALUE_END,
1809 };
1810
1811 static const struct mrs_field_value id_aa64pfr1_mpam_frac[] = {
1812 MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p0, ""),
1813 MRS_FIELD_VALUE(ID_AA64PFR1_MPAM_frac_p1, "MPAM p1"),
1814 MRS_FIELD_VALUE_END,
1815 };
1816
1817 static const struct mrs_field_value id_aa64pfr1_ras_frac[] = {
1818 MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p0, ""),
1819 MRS_FIELD_VALUE(ID_AA64PFR1_RAS_frac_p1, "RAS p1"),
1820 MRS_FIELD_VALUE_END,
1821 };
1822
1823 static const struct mrs_field_value id_aa64pfr1_mte[] = {
1824 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_NONE, ""),
1825 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE, "MTE"),
1826 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE2, "MTE2"),
1827 MRS_FIELD_VALUE(ID_AA64PFR1_MTE_MTE3, "MTE3"),
1828 MRS_FIELD_VALUE_END,
1829 };
1830
1831 static const struct mrs_field_value id_aa64pfr1_ssbs[] = {
1832 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_NONE, ""),
1833 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE, "PSTATE.SSBS"),
1834 MRS_FIELD_VALUE(ID_AA64PFR1_SSBS_PSTATE_MSR, "PSTATE.SSBS MSR"),
1835 MRS_FIELD_VALUE_END,
1836 };
1837
1838 static const struct mrs_field_hwcap id_aa64pfr1_ssbs_caps[] = {
1839 MRS_HWCAP(1, HWCAP_SSBS, ID_AA64PFR1_SSBS_PSTATE),
1840 MRS_HWCAP_END
1841 };
1842
1843 static const struct mrs_field_value id_aa64pfr1_bt[] = {
1844 MRS_FIELD_VALUE(ID_AA64PFR1_BT_NONE, ""),
1845 MRS_FIELD_VALUE(ID_AA64PFR1_BT_IMPL, "BTI"),
1846 MRS_FIELD_VALUE_END,
1847 };
1848
1849 static const struct mrs_field_hwcap id_aa64pfr1_bt_caps[] = {
1850 MRS_HWCAP(2, HWCAP2_BTI, ID_AA64PFR1_BT_IMPL),
1851 MRS_HWCAP_END
1852 };
1853
1854 static const struct mrs_field id_aa64pfr1_fields[] = {
1855 MRS_FIELD(ID_AA64PFR1, PFAR, false, MRS_LOWER, 0, id_aa64pfr1_pfar),
1856 MRS_FIELD(ID_AA64PFR1, DF2, false, MRS_LOWER, 0, id_aa64pfr1_df2),
1857 MRS_FIELD(ID_AA64PFR1, MTEX, false, MRS_LOWER, 0, id_aa64pfr1_mtex),
1858 MRS_FIELD(ID_AA64PFR1, THE, false, MRS_LOWER, 0, id_aa64pfr1_the),
1859 MRS_FIELD(ID_AA64PFR1, MTE_frac, true, MRS_LOWER, 0,
1860 id_aa64pfr1_mtefrac),
1861 MRS_FIELD(ID_AA64PFR1, NMI, false, MRS_LOWER, 0, id_aa64pfr1_nmi),
1862 MRS_FIELD(ID_AA64PFR1, CSV2_frac, false, MRS_LOWER, 0,
1863 id_aa64pfr1_csv2_frac),
1864 MRS_FIELD(ID_AA64PFR1, RNDR_trap, false, MRS_LOWER, 0,
1865 id_aa64pfr1_rndr_trap),
1866 MRS_FIELD(ID_AA64PFR1, SME, false, MRS_LOWER, 0, id_aa64pfr1_sme),
1867 MRS_FIELD(ID_AA64PFR1, MPAM_frac, false, MRS_LOWER, 0,
1868 id_aa64pfr1_mpam_frac),
1869 MRS_FIELD(ID_AA64PFR1, RAS_frac, false, MRS_LOWER, 0,
1870 id_aa64pfr1_ras_frac),
1871 MRS_FIELD(ID_AA64PFR1, MTE, false, MRS_LOWER, 0, id_aa64pfr1_mte),
1872 MRS_FIELD_HWCAP(ID_AA64PFR1, SSBS, false, MRS_LOWER, MRS_USERSPACE,
1873 id_aa64pfr1_ssbs, id_aa64pfr1_ssbs_caps),
1874 MRS_FIELD_HWCAP(ID_AA64PFR1, BT, false, MRS_LOWER,
1875 MRS_FREEBSD, id_aa64pfr1_bt, id_aa64pfr1_bt_caps),
1876 MRS_FIELD_END,
1877 };
1878
1879
1880 /* ID_AA64PFR2_EL1 */
1881 static const struct mrs_field id_aa64pfr2_fields[] = {
1882 MRS_FIELD_END,
1883 };
1884
1885
1886 /* ID_AA64ZFR0_EL1 */
1887 static const struct mrs_field_value id_aa64zfr0_f64mm[] = {
1888 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F64MM, NONE, IMPL),
1889 MRS_FIELD_VALUE_END,
1890 };
1891
1892 static const struct mrs_field_hwcap id_aa64zfr0_f64mm_caps[] = {
1893 MRS_HWCAP(2, HWCAP2_SVEF64MM, ID_AA64ZFR0_F64MM_IMPL),
1894 MRS_HWCAP_END,
1895 };
1896
1897 static const struct mrs_field_value id_aa64zfr0_f32mm[] = {
1898 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, F32MM, NONE, IMPL),
1899 MRS_FIELD_VALUE_END,
1900 };
1901
1902 static const struct mrs_field_hwcap id_aa64zfr0_f32mm_caps[] = {
1903 MRS_HWCAP(2, HWCAP2_SVEF32MM, ID_AA64ZFR0_F32MM_IMPL),
1904 MRS_HWCAP_END,
1905 };
1906
1907 static const struct mrs_field_value id_aa64zfr0_i8mm[] = {
1908 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, I8MM, NONE, IMPL),
1909 MRS_FIELD_VALUE_END,
1910 };
1911
1912 static const struct mrs_field_hwcap id_aa64zfr0_i8mm_caps[] = {
1913 MRS_HWCAP(2, HWCAP2_SVEI8MM, ID_AA64ZFR0_I8MM_IMPL),
1914 MRS_HWCAP_END,
1915 };
1916
1917 static const struct mrs_field_value id_aa64zfr0_sm4[] = {
1918 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SM4, NONE, IMPL),
1919 MRS_FIELD_VALUE_END,
1920 };
1921
1922 static const struct mrs_field_hwcap id_aa64zfr0_sm4_caps[] = {
1923 MRS_HWCAP(2, HWCAP2_SVESM4, ID_AA64ZFR0_SM4_IMPL),
1924 MRS_HWCAP_END,
1925 };
1926
1927 static const struct mrs_field_value id_aa64zfr0_sha3[] = {
1928 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, SHA3, NONE, IMPL),
1929 MRS_FIELD_VALUE_END,
1930 };
1931
1932 static const struct mrs_field_hwcap id_aa64zfr0_sha3_caps[] = {
1933 MRS_HWCAP(2, HWCAP2_SVESHA3, ID_AA64ZFR0_SHA3_IMPL),
1934 MRS_HWCAP_END,
1935 };
1936
1937 static const struct mrs_field_value id_aa64zfr0_bf16[] = {
1938 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BF16, NONE, BASE),
1939 MRS_FIELD_VALUE(ID_AA64ZFR0_BF16_EBF, "BF16+EBF"),
1940 MRS_FIELD_VALUE_END,
1941 };
1942
1943 static const struct mrs_field_hwcap id_aa64zfr0_bf16_caps[] = {
1944 MRS_HWCAP(2, HWCAP2_SVEBF16, ID_AA64ZFR0_BF16_BASE),
1945 MRS_HWCAP(2, HWCAP2_SVE_EBF16, ID_AA64ZFR0_BF16_EBF),
1946 MRS_HWCAP_END,
1947 };
1948
1949 static const struct mrs_field_value id_aa64zfr0_bitperm[] = {
1950 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BitPerm, NONE, IMPL),
1951 MRS_FIELD_VALUE_END,
1952 };
1953
1954 static const struct mrs_field_hwcap id_aa64zfr0_bitperm_caps[] = {
1955 MRS_HWCAP(2, HWCAP2_SVEBITPERM, ID_AA64ZFR0_BitPerm_IMPL),
1956 MRS_HWCAP_END,
1957 };
1958
1959 static const struct mrs_field_value id_aa64zfr0_aes[] = {
1960 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, AES, NONE, BASE),
1961 MRS_FIELD_VALUE(ID_AA64ZFR0_AES_PMULL, "AES+PMULL"),
1962 MRS_FIELD_VALUE_END,
1963 };
1964
1965 static const struct mrs_field_hwcap id_aa64zfr0_aes_caps[] = {
1966 MRS_HWCAP(2, HWCAP2_SVEAES, ID_AA64ZFR0_AES_BASE),
1967 MRS_HWCAP(2, HWCAP2_SVEPMULL, ID_AA64ZFR0_AES_PMULL),
1968 MRS_HWCAP_END,
1969 };
1970
1971 static const struct mrs_field_value id_aa64zfr0_svever[] = {
1972 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE1, "SVE1"),
1973 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2, "SVE2"),
1974 MRS_FIELD_VALUE(ID_AA64ZFR0_SVEver_SVE2P1, "SVE2P1"),
1975 MRS_FIELD_VALUE_END,
1976 };
1977
1978 static const struct mrs_field_hwcap id_aa64zfr0_svever_caps[] = {
1979 MRS_HWCAP(2, HWCAP2_SVE2, ID_AA64ZFR0_SVEver_SVE2),
1980 MRS_HWCAP(2, HWCAP2_SVE2P1, ID_AA64ZFR0_SVEver_SVE2P1),
1981 MRS_HWCAP_END,
1982 };
1983
1984 static const struct mrs_field id_aa64zfr0_fields[] = {
1985 MRS_FIELD_HWCAP(ID_AA64ZFR0, F64MM, false, MRS_LOWER, MRS_USERSPACE,
1986 id_aa64zfr0_f64mm, id_aa64zfr0_f64mm_caps),
1987 MRS_FIELD_HWCAP(ID_AA64ZFR0, F32MM, false, MRS_LOWER, MRS_USERSPACE,
1988 id_aa64zfr0_f32mm, id_aa64zfr0_f32mm_caps),
1989 MRS_FIELD_HWCAP(ID_AA64ZFR0, I8MM, false, MRS_LOWER, MRS_USERSPACE,
1990 id_aa64zfr0_i8mm, id_aa64zfr0_i8mm_caps),
1991 MRS_FIELD_HWCAP(ID_AA64ZFR0, SM4, false, MRS_LOWER, MRS_USERSPACE,
1992 id_aa64zfr0_sm4, id_aa64zfr0_sm4_caps),
1993 MRS_FIELD_HWCAP(ID_AA64ZFR0, SHA3, false, MRS_LOWER, MRS_USERSPACE,
1994 id_aa64zfr0_sha3, id_aa64zfr0_sha3_caps),
1995 MRS_FIELD_HWCAP(ID_AA64ZFR0, BF16, false, MRS_LOWER, MRS_USERSPACE,
1996 id_aa64zfr0_bf16, id_aa64zfr0_bf16_caps),
1997 MRS_FIELD_HWCAP(ID_AA64ZFR0, BitPerm, false, MRS_LOWER, MRS_USERSPACE,
1998 id_aa64zfr0_bitperm, id_aa64zfr0_bitperm_caps),
1999 MRS_FIELD_HWCAP(ID_AA64ZFR0, AES, false, MRS_LOWER, MRS_USERSPACE,
2000 id_aa64zfr0_aes, id_aa64zfr0_aes_caps),
2001 MRS_FIELD_HWCAP(ID_AA64ZFR0, SVEver, false, MRS_LOWER, MRS_USERSPACE,
2002 id_aa64zfr0_svever, id_aa64zfr0_svever_caps),
2003 MRS_FIELD_END,
2004 };
2005
2006
2007 #ifdef COMPAT_FREEBSD32
2008 /* ID_ISAR5_EL1 */
2009 static const struct mrs_field_value id_isar5_vcma[] = {
2010 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, VCMA, NONE, IMPL),
2011 MRS_FIELD_VALUE_END,
2012 };
2013
2014 static const struct mrs_field_value id_isar5_rdm[] = {
2015 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, RDM, NONE, IMPL),
2016 MRS_FIELD_VALUE_END,
2017 };
2018
2019 static const struct mrs_field_value id_isar5_crc32[] = {
2020 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, CRC32, NONE, IMPL),
2021 MRS_FIELD_VALUE_END,
2022 };
2023
2024 static const struct mrs_field_hwcap id_isar5_crc32_caps[] = {
2025 MRS_HWCAP(2, HWCAP32_2_CRC32, ID_ISAR5_CRC32_IMPL),
2026 MRS_HWCAP_END
2027 };
2028
2029 static const struct mrs_field_value id_isar5_sha2[] = {
2030 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA2, NONE, IMPL),
2031 MRS_FIELD_VALUE_END,
2032 };
2033
2034 static const struct mrs_field_hwcap id_isar5_sha2_caps[] = {
2035 MRS_HWCAP(2, HWCAP32_2_SHA2, ID_ISAR5_SHA2_IMPL),
2036 MRS_HWCAP_END
2037 };
2038
2039 static const struct mrs_field_value id_isar5_sha1[] = {
2040 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA1, NONE, IMPL),
2041 MRS_FIELD_VALUE_END,
2042 };
2043
2044 static const struct mrs_field_hwcap id_isar5_sha1_caps[] = {
2045 MRS_HWCAP(2, HWCAP32_2_SHA1, ID_ISAR5_SHA1_IMPL),
2046 MRS_HWCAP_END
2047 };
2048
2049 static const struct mrs_field_value id_isar5_aes[] = {
2050 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, AES, NONE, BASE),
2051 MRS_FIELD_VALUE(ID_ISAR5_AES_VMULL, "AES+VMULL"),
2052 MRS_FIELD_VALUE_END,
2053 };
2054
2055 static const struct mrs_field_hwcap id_isar5_aes_caps[] = {
2056 MRS_HWCAP(2, HWCAP32_2_AES, ID_ISAR5_AES_BASE),
2057 MRS_HWCAP(2, HWCAP32_2_PMULL, ID_ISAR5_AES_VMULL),
2058 MRS_HWCAP_END
2059 };
2060
2061 static const struct mrs_field_value id_isar5_sevl[] = {
2062 MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SEVL, NOP, IMPL),
2063 MRS_FIELD_VALUE_END,
2064 };
2065
2066 static const struct mrs_field id_isar5_fields[] = {
2067 MRS_FIELD(ID_ISAR5, VCMA, false, MRS_LOWER,MRS_USERSPACE,
2068 id_isar5_vcma),
2069 MRS_FIELD(ID_ISAR5, RDM, false, MRS_LOWER, MRS_USERSPACE, id_isar5_rdm),
2070 MRS_FIELD_HWCAP(ID_ISAR5, CRC32, false, MRS_LOWER, MRS_USERSPACE,
2071 id_isar5_crc32, id_isar5_crc32_caps),
2072 MRS_FIELD_HWCAP(ID_ISAR5, SHA2, false, MRS_LOWER, MRS_USERSPACE,
2073 id_isar5_sha2, id_isar5_sha2_caps),
2074 MRS_FIELD_HWCAP(ID_ISAR5, SHA1, false, MRS_LOWER, MRS_USERSPACE,
2075 id_isar5_sha1, id_isar5_sha1_caps),
2076 MRS_FIELD_HWCAP(ID_ISAR5, AES, false, MRS_LOWER, MRS_USERSPACE,
2077 id_isar5_aes, id_isar5_aes_caps),
2078 MRS_FIELD(ID_ISAR5, SEVL, false, MRS_LOWER, MRS_USERSPACE,
2079 id_isar5_sevl),
2080 MRS_FIELD_END,
2081 };
2082
2083 /* MVFR0 */
2084 static const struct mrs_field_value mvfr0_fpround[] = {
2085 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPRound, NONE, IMPL),
2086 MRS_FIELD_VALUE_END,
2087 };
2088
2089 static const struct mrs_field_value mvfr0_fpsqrt[] = {
2090 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPSqrt, NONE, IMPL),
2091 MRS_FIELD_VALUE_END,
2092 };
2093
2094 static const struct mrs_field_value mvfr0_fpdivide[] = {
2095 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPDivide, NONE, IMPL),
2096 MRS_FIELD_VALUE_END,
2097 };
2098
2099 static const struct mrs_field_value mvfr0_fptrap[] = {
2100 MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPTrap, NONE, IMPL),
2101 MRS_FIELD_VALUE_END,
2102 };
2103
2104 static const struct mrs_field_value mvfr0_fpdp[] = {
2105 MRS_FIELD_VALUE(MVFR0_FPDP_NONE, ""),
2106 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v2, "DP VFPv2"),
2107 MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v3_v4, "DP VFPv3+v4"),
2108 MRS_FIELD_VALUE_END,
2109 };
2110
2111 static const struct mrs_field_hwcap mvfr0_fpdp_caps[] = {
2112 MRS_HWCAP(1, HWCAP32_VFP, MVFR0_FPDP_VFP_v2),
2113 MRS_HWCAP(1, HWCAP32_VFPv3, MVFR0_FPDP_VFP_v3_v4),
2114 MRS_HWCAP_END
2115 };
2116
2117 static const struct mrs_field_value mvfr0_fpsp[] = {
2118 MRS_FIELD_VALUE(MVFR0_FPSP_NONE, ""),
2119 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v2, "SP VFPv2"),
2120 MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v3_v4, "SP VFPv3+v4"),
2121 MRS_FIELD_VALUE_END,
2122 };
2123
2124 static const struct mrs_field_value mvfr0_simdreg[] = {
2125 MRS_FIELD_VALUE(MVFR0_SIMDReg_NONE, ""),
2126 MRS_FIELD_VALUE(MVFR0_SIMDReg_FP, "FP 16x64"),
2127 MRS_FIELD_VALUE(MVFR0_SIMDReg_AdvSIMD, "AdvSIMD"),
2128 MRS_FIELD_VALUE_END,
2129 };
2130
2131 static const struct mrs_field mvfr0_fields[] = {
2132 MRS_FIELD(MVFR0, FPRound, false, MRS_LOWER, MRS_USERSPACE,
2133 mvfr0_fpround),
2134 MRS_FIELD(MVFR0, FPSqrt, false, MRS_LOWER, MRS_USERSPACE,
2135 mvfr0_fpsqrt),
2136 MRS_FIELD(MVFR0, FPDivide, false, MRS_LOWER, MRS_USERSPACE,
2137 mvfr0_fpdivide),
2138 MRS_FIELD(MVFR0, FPTrap, false, MRS_LOWER, MRS_USERSPACE,
2139 mvfr0_fptrap),
2140 MRS_FIELD_HWCAP(MVFR0, FPDP, false, MRS_LOWER, MRS_USERSPACE,
2141 mvfr0_fpdp, mvfr0_fpdp_caps),
2142 MRS_FIELD(MVFR0, FPSP, false, MRS_LOWER, MRS_USERSPACE, mvfr0_fpsp),
2143 MRS_FIELD(MVFR0, SIMDReg, false, MRS_LOWER, MRS_USERSPACE,
2144 mvfr0_simdreg),
2145 MRS_FIELD_END,
2146 };
2147
2148 /* MVFR1 */
2149 static const struct mrs_field_value mvfr1_simdfmac[] = {
2150 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDFMAC, NONE, IMPL),
2151 MRS_FIELD_VALUE_END,
2152 };
2153
2154 static const struct mrs_field_hwcap mvfr1_simdfmac_caps[] = {
2155 MRS_HWCAP(1, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL),
2156 MRS_HWCAP_END
2157 };
2158
2159 static const struct mrs_field_value mvfr1_fphp[] = {
2160 MRS_FIELD_VALUE(MVFR1_FPHP_NONE, ""),
2161 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_SP, "FPHP SP Conv"),
2162 MRS_FIELD_VALUE(MVFR1_FPHP_CONV_DP, "FPHP DP Conv"),
2163 MRS_FIELD_VALUE(MVFR1_FPHP_ARITH, "FPHP Arith"),
2164 MRS_FIELD_VALUE_END,
2165 };
2166
2167 static const struct mrs_field_value mvfr1_simdhp[] = {
2168 MRS_FIELD_VALUE(MVFR1_SIMDHP_NONE, ""),
2169 MRS_FIELD_VALUE(MVFR1_SIMDHP_CONV_SP, "SIMDHP SP Conv"),
2170 MRS_FIELD_VALUE(MVFR1_SIMDHP_ARITH, "SIMDHP Arith"),
2171 MRS_FIELD_VALUE_END,
2172 };
2173
2174 static const struct mrs_field_value mvfr1_simdsp[] = {
2175 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDSP, NONE, IMPL),
2176 MRS_FIELD_VALUE_END,
2177 };
2178
2179 static const struct mrs_field_value mvfr1_simdint[] = {
2180 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDInt, NONE, IMPL),
2181 MRS_FIELD_VALUE_END,
2182 };
2183
2184 static const struct mrs_field_value mvfr1_simdls[] = {
2185 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDLS, NONE, IMPL),
2186 MRS_FIELD_VALUE_END,
2187 };
2188
2189 static const struct mrs_field_hwcap mvfr1_simdls_caps[] = {
2190 MRS_HWCAP(1, HWCAP32_VFPv4, MVFR1_SIMDFMAC_IMPL),
2191 MRS_HWCAP_END
2192 };
2193
2194 static const struct mrs_field_value mvfr1_fpdnan[] = {
2195 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPDNaN, NONE, IMPL),
2196 MRS_FIELD_VALUE_END,
2197 };
2198
2199 static const struct mrs_field_value mvfr1_fpftz[] = {
2200 MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPFtZ, NONE, IMPL),
2201 MRS_FIELD_VALUE_END,
2202 };
2203
2204 static const struct mrs_field mvfr1_fields[] = {
2205 MRS_FIELD_HWCAP(MVFR1, SIMDFMAC, false, MRS_LOWER, MRS_USERSPACE,
2206 mvfr1_simdfmac, mvfr1_simdfmac_caps),
2207 MRS_FIELD(MVFR1, FPHP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_fphp),
2208 MRS_FIELD(MVFR1, SIMDHP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_simdhp),
2209 MRS_FIELD(MVFR1, SIMDSP, false, MRS_LOWER, MRS_USERSPACE, mvfr1_simdsp),
2210 MRS_FIELD(MVFR1, SIMDInt, false, MRS_LOWER, MRS_USERSPACE,
2211 mvfr1_simdint),
2212 MRS_FIELD_HWCAP(MVFR1, SIMDLS, false, MRS_LOWER, MRS_USERSPACE,
2213 mvfr1_simdls, mvfr1_simdls_caps),
2214 MRS_FIELD(MVFR1, FPDNaN, false, MRS_LOWER, MRS_USERSPACE,
2215 mvfr1_fpdnan),
2216 MRS_FIELD(MVFR1, FPFtZ, false, MRS_LOWER, MRS_USERSPACE,
2217 mvfr1_fpftz),
2218 MRS_FIELD_END,
2219 };
2220 #endif /* COMPAT_FREEBSD32 */
2221
2222 struct mrs_user_reg {
2223 u_int iss;
2224 bool is64bit;
2225 size_t offset;
2226 const struct mrs_field *fields;
2227 };
2228
2229 #define USER_REG(name, field_name, _is64bit) \
2230 { \
2231 .iss = name##_ISS, \
2232 .offset = __offsetof(struct cpu_desc, field_name), \
2233 .fields = field_name##_fields, \
2234 .is64bit = _is64bit, \
2235 }
2236 static const struct mrs_user_reg user_regs[] = {
2237 USER_REG(ID_AA64AFR0_EL1, id_aa64afr0, true),
2238 USER_REG(ID_AA64AFR1_EL1, id_aa64afr1, true),
2239
2240 USER_REG(ID_AA64DFR0_EL1, id_aa64dfr0, true),
2241 USER_REG(ID_AA64DFR1_EL1, id_aa64dfr1, true),
2242
2243 USER_REG(ID_AA64ISAR0_EL1, id_aa64isar0, true),
2244 USER_REG(ID_AA64ISAR1_EL1, id_aa64isar1, true),
2245 USER_REG(ID_AA64ISAR2_EL1, id_aa64isar2, true),
2246
2247 USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0, true),
2248 USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1, true),
2249 USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2, true),
2250 USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3, true),
2251 USER_REG(ID_AA64MMFR4_EL1, id_aa64mmfr4, true),
2252
2253 USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0, true),
2254 USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1, true),
2255 USER_REG(ID_AA64PFR2_EL1, id_aa64pfr2, true),
2256
2257 USER_REG(ID_AA64ZFR0_EL1, id_aa64zfr0, true),
2258
2259 USER_REG(CTR_EL0, ctr, true),
2260
2261 #ifdef COMPAT_FREEBSD32
2262 USER_REG(ID_ISAR5_EL1, id_isar5, false),
2263
2264 USER_REG(MVFR0_EL1, mvfr0, false),
2265 USER_REG(MVFR1_EL1, mvfr1, false),
2266 #endif /* COMPAT_FREEBSD32 */
2267 };
2268
2269 #define CPU_DESC_FIELD(desc, idx) \
2270 *(uint64_t *)((char *)&(desc) + user_regs[(idx)].offset)
2271
2272 static bool
user_ctr_has_neoverse_n1_1542419(uint32_t midr,uint64_t ctr)2273 user_ctr_has_neoverse_n1_1542419(uint32_t midr, uint64_t ctr)
2274 {
2275 /*
2276 * Neoverse-N1 erratum 1542419
2277 * Present in r3p0 - r4p0
2278 * Fixed in r4p1
2279 */
2280 return (midr_check_var_part_range(midr, CPU_IMPL_ARM,
2281 CPU_PART_NEOVERSE_N1, 3, 0, 4, 0) && CTR_DIC_VAL(ctr) != 0);
2282 }
2283
2284 static cpu_feat_en
user_ctr_check(const struct cpu_feat * feat __unused,u_int midr)2285 user_ctr_check(const struct cpu_feat *feat __unused, u_int midr)
2286 {
2287 if (emulate_ctr)
2288 return (FEAT_DEFAULT_ENABLE);
2289
2290 if (user_ctr_has_neoverse_n1_1542419(midr, READ_SPECIALREG(ctr_el0)))
2291 return (FEAT_DEFAULT_ENABLE);
2292
2293 return (FEAT_ALWAYS_DISABLE);
2294 }
2295
2296 static bool
user_ctr_has_errata(const struct cpu_feat * feat __unused,u_int midr,u_int ** errata_list,u_int * errata_count)2297 user_ctr_has_errata(const struct cpu_feat *feat __unused, u_int midr,
2298 u_int **errata_list, u_int *errata_count)
2299 {
2300 if (user_ctr_has_neoverse_n1_1542419(midr, READ_SPECIALREG(ctr_el0))) {
2301 static u_int errata_id = 1542419;
2302
2303 *errata_list = &errata_id;
2304 *errata_count = 1;
2305 return (true);
2306 }
2307
2308 return (false);
2309 }
2310
2311 static bool
user_ctr_enable(const struct cpu_feat * feat __unused,cpu_feat_errata errata_status,u_int * errata_list,u_int errata_count)2312 user_ctr_enable(const struct cpu_feat *feat __unused,
2313 cpu_feat_errata errata_status, u_int *errata_list, u_int errata_count)
2314 {
2315 MPASS(emulate_ctr || errata_status != ERRATA_NONE);
2316
2317 /*
2318 * The Errata Management Firmware Interface may incorrectly mark
2319 * this as firmware mitigated. We should ignore that as there is
2320 * a kernel component to the mitigation.
2321 */
2322 if (errata_status != ERRATA_NONE && PCPU_GET(cpuid) == 0 &&
2323 cpu_feat_has_erratum(errata_list, errata_count, 1542419)) {
2324 /* Clear fields we will change */
2325 user_cpu_desc.ctr &= ~(CTR_DIC_MASK | CTR_ILINE_WIDTH);
2326
2327 /*
2328 * Set DIC to none so userspace will execute an 'ic ivau'
2329 * instruction that can be trapped by EL3.
2330 */
2331 user_cpu_desc.ctr |= CTR_DIC_NONE;
2332 /*
2333 * Set the i-cache line size to be page size to reduce the
2334 * number of times userspace needs to execute the 'ic ivau'
2335 * instruction. The ctr_el0.IminLine is log2 the number of
2336 * 4-byte words the instruction covers. As PAGE_SHIFT is log2
2337 * of the number of bytes in a page we need to subtract 2.
2338 */
2339 user_cpu_desc.ctr |= (PAGE_SHIFT - 2) << CTR_ILINE_SHIFT;
2340
2341 l_user_cpu_desc.ctr = user_cpu_desc.ctr;
2342 }
2343
2344 WRITE_SPECIALREG(sctlr_el1,
2345 READ_SPECIALREG(sctlr_el1) & ~SCTLR_UCT);
2346 isb();
2347
2348 return (true);
2349 }
2350
2351 CPU_FEAT(trap_ctr, "Trap CTR_EL0",
2352 user_ctr_check, user_ctr_has_errata, user_ctr_enable,
2353 CPU_FEAT_AFTER_DEV | CPU_FEAT_PER_CPU);
2354
2355 static bool
user_ctr_handler(uint64_t esr,struct trapframe * frame)2356 user_ctr_handler(uint64_t esr, struct trapframe *frame)
2357 {
2358 uint64_t value;
2359 int reg;
2360
2361 if (ESR_ELx_EXCEPTION(esr) != EXCP_MSR)
2362 return (false);
2363
2364 /* Only support reading from ctr_el0 */
2365 if ((esr & ISS_MSR_DIR) == 0)
2366 return (false);
2367
2368 /* Check if this is the ctr_el0 register */
2369 if ((esr & ISS_MSR_REG_MASK) != CTR_EL0_ISS)
2370 return (false);
2371
2372 if (SV_CURPROC_ABI() == SV_ABI_FREEBSD)
2373 value = user_cpu_desc.ctr;
2374 else
2375 value = l_user_cpu_desc.ctr;
2376 /*
2377 * We will handle this instruction, move to the next so we
2378 * don't trap here again.
2379 */
2380 frame->tf_elr += INSN_SIZE;
2381
2382 reg = ISS_MSR_Rt(esr);
2383 /* If reg is 31 then write to xzr, i.e. do nothing */
2384 if (reg == 31)
2385 return (true);
2386
2387 if (reg < nitems(frame->tf_x))
2388 frame->tf_x[reg] = value;
2389 else if (reg == 30)
2390 frame->tf_lr = value;
2391
2392 return (true);
2393 }
2394
2395 static bool
user_idreg_handler(uint64_t esr,struct trapframe * frame)2396 user_idreg_handler(uint64_t esr, struct trapframe *frame)
2397 {
2398 uint64_t value;
2399 int reg;
2400
2401 if (ESR_ELx_EXCEPTION(esr) != EXCP_MSR)
2402 return (false);
2403
2404 /* Only support reading from ID registers */
2405 if ((esr & ISS_MSR_DIR) == 0)
2406 return (false);
2407
2408 /*
2409 * This only handles the ID register space and a few registers that
2410 * are safe to pass through to userspace.
2411 *
2412 * These registers are all in the space op0 == 3, op1 == 0,
2413 * CRn == 0. We support the following CRm:
2414 * - CRm == 0: midr_el1, mpidr_el1, and revidr_el1.
2415 * - CRm in {4-7}: sanitized ID registers.
2416 *
2417 * Registers in the ID register space (CRm in {4-7}) are all
2418 * read-only and have either defined fields, or are read as
2419 * zero (RAZ). For these we return 0 for any unknown register.
2420 */
2421 if (ISS_MSR_OP0(esr) != 3 || ISS_MSR_OP1(esr) != 0 ||
2422 ISS_MSR_CRn(esr) != 0)
2423 return (false);
2424
2425 value = 0;
2426 if (ISS_MSR_CRm(esr) >= 4 && ISS_MSR_CRm(esr) <= 7) {
2427 for (int i = 0; i < nitems(user_regs); i++) {
2428 if (user_regs[i].iss == (esr & ISS_MSR_REG_MASK)) {
2429 if (SV_CURPROC_ABI() == SV_ABI_FREEBSD)
2430 value = CPU_DESC_FIELD(user_cpu_desc, i);
2431 else
2432 value = CPU_DESC_FIELD(l_user_cpu_desc, i);
2433 break;
2434 }
2435 }
2436 } else if (ISS_MSR_CRm(esr) == 0) {
2437 switch (ISS_MSR_OP2(esr)) {
2438 case 0:
2439 value = READ_SPECIALREG(midr_el1);
2440 break;
2441 case 5:
2442 value = READ_SPECIALREG(mpidr_el1);
2443 break;
2444 case 6:
2445 value = READ_SPECIALREG(revidr_el1);
2446 break;
2447 default:
2448 return (false);
2449 }
2450 } else {
2451 return (false);
2452 }
2453
2454 /*
2455 * We will handle this instruction, move to the next so we
2456 * don't trap here again.
2457 */
2458 frame->tf_elr += INSN_SIZE;
2459
2460 reg = ISS_MSR_Rt(esr);
2461 /* If reg is 31 then write to xzr, i.e. do nothing */
2462 if (reg == 31)
2463 return (1);
2464
2465 if (reg < nitems(frame->tf_x))
2466 frame->tf_x[reg] = value;
2467 else if (reg == 30)
2468 frame->tf_lr = value;
2469
2470 return (true);
2471 }
2472
2473 /*
2474 * Compares two field values that may be signed or unsigned.
2475 * Returns:
2476 * < 0 when a is less than b
2477 * = 0 when a equals b
2478 * > 0 when a is greater than b
2479 */
2480 static int
mrs_field_cmp(uint64_t a,uint64_t b,u_int shift,int width,bool sign)2481 mrs_field_cmp(uint64_t a, uint64_t b, u_int shift, int width, bool sign)
2482 {
2483 uint64_t mask;
2484
2485 KASSERT(width > 0 && width < 64, ("%s: Invalid width %d", __func__,
2486 width));
2487
2488 mask = (1ul << width) - 1;
2489 /* Move the field to the lower bits */
2490 a = (a >> shift) & mask;
2491 b = (b >> shift) & mask;
2492
2493 if (sign) {
2494 /*
2495 * The field is signed. Toggle the upper bit so the comparison
2496 * works on unsigned values as this makes positive numbers,
2497 * i.e. those with a 0 bit, larger than negative numbers,
2498 * i.e. those with a 1 bit, in an unsigned comparison.
2499 */
2500 a ^= 1ul << (width - 1);
2501 b ^= 1ul << (width - 1);
2502 }
2503
2504 return (a - b);
2505 }
2506
2507 bool
get_kernel_reg_iss(u_int iss,uint64_t * val)2508 get_kernel_reg_iss(u_int iss, uint64_t *val)
2509 {
2510 int i;
2511
2512 for (i = 0; i < nitems(user_regs); i++) {
2513 if (user_regs[i].iss == iss) {
2514 *val = CPU_DESC_FIELD(kern_cpu_desc, i);
2515 return (true);
2516 }
2517 }
2518
2519 return (false);
2520 }
2521
2522 /*
2523 * Fetch the specified register's value, ensuring that individual field values
2524 * do not exceed those in the mask.
2525 */
2526 bool
get_kernel_reg_iss_masked(u_int iss,uint64_t * valp,uint64_t mask)2527 get_kernel_reg_iss_masked(u_int iss, uint64_t *valp, uint64_t mask)
2528 {
2529 const struct mrs_field *fields;
2530 uint64_t val;
2531
2532 for (int i = 0; i < nitems(user_regs); i++) {
2533 if (user_regs[i].iss == iss) {
2534 val = CPU_DESC_FIELD(kern_cpu_desc, i);
2535 fields = user_regs[i].fields;
2536 for (int j = 0; fields[j].type != 0; j++) {
2537 mask = update_special_reg_field(mask,
2538 fields[j].type, val, fields[j].width,
2539 fields[j].shift, fields[j].sign);
2540 }
2541 *valp = mask;
2542 return (true);
2543 }
2544 }
2545
2546 return (false);
2547 }
2548
2549 bool
get_user_reg_iss(u_int iss,uint64_t * val,bool fbsd)2550 get_user_reg_iss(u_int iss, uint64_t *val, bool fbsd)
2551 {
2552 int i;
2553
2554 for (i = 0; i < nitems(user_regs); i++) {
2555 if (user_regs[i].iss == iss) {
2556 if (fbsd)
2557 *val = CPU_DESC_FIELD(user_cpu_desc, i);
2558 else
2559 *val = CPU_DESC_FIELD(l_user_cpu_desc, i);
2560 return (true);
2561 }
2562 }
2563
2564 return (false);
2565 }
2566
2567 static uint64_t
update_special_reg_field(uint64_t user_reg,u_int type,uint64_t value,u_int width,u_int shift,bool sign)2568 update_special_reg_field(uint64_t user_reg, u_int type, uint64_t value,
2569 u_int width, u_int shift, bool sign)
2570 {
2571 uint64_t cur, mask, new_val;
2572
2573 mask = ((1ul << width) - 1) << shift;
2574 cur = user_reg & mask;
2575 new_val = value & mask;
2576
2577 switch (type & MRS_TYPE_MASK) {
2578 case MRS_EXACT_IF_DIFFERENT:
2579 if (mrs_field_cmp(new_val, cur, shift, width, sign) == 0)
2580 break;
2581 /* FALLTHROUGH */
2582 case MRS_EXACT:
2583 cur = (uint64_t)MRS_SAFE_VAL(type) << shift;
2584 break;
2585 case MRS_LOWER:
2586 if (mrs_field_cmp(new_val, cur, shift, width, sign) < 0)
2587 cur = new_val;
2588 break;
2589 case MRS_HIGHER_OR_ZERO:
2590 if (cur == 0 || new_val == 0) {
2591 cur = 0;
2592 break;
2593 }
2594 /* FALLTHROUGH */
2595 case MRS_HIGHER:
2596 if (mrs_field_cmp(new_val, cur, shift, width, sign) > 0)
2597 cur = new_val;
2598 break;
2599 default:
2600 panic("Invalid field type: %d", type);
2601 }
2602
2603 user_reg &= ~mask;
2604 user_reg |= cur;
2605
2606 return (user_reg);
2607 }
2608
2609 static void
clear_set_special_reg_idx(int idx,uint64_t clear,uint64_t set)2610 clear_set_special_reg_idx(int idx, uint64_t clear, uint64_t set)
2611 {
2612 const struct mrs_field *fields;
2613 uint64_t k_old, k_new;
2614 uint64_t f_old, f_new;
2615 uint64_t l_old, l_new;
2616
2617 MPASS(idx < nitems(user_regs));
2618
2619 k_old = CPU_DESC_FIELD(kern_cpu_desc, idx);
2620 k_new = (k_old & ~clear) | set;
2621
2622 f_old = CPU_DESC_FIELD(user_cpu_desc, idx);
2623 f_new = (f_old & ~clear) | set;
2624
2625 l_old = CPU_DESC_FIELD(l_user_cpu_desc, idx);
2626 l_new = (l_old & ~clear) | set;
2627
2628 fields = user_regs[idx].fields;
2629 for (int j = 0; fields[j].type != 0; j++) {
2630 u_int type;
2631
2632 /* Update the FreeBSD userspace ID register view */
2633 type = ((fields[j].type & MRS_FREEBSD) != 0) ?
2634 fields[j].type :
2635 (MRS_EXACT | (fields[j].type & MRS_SAFE_MASK));
2636 f_new = update_special_reg_field(f_new,
2637 type, f_old, fields[j].width, fields[j].shift,
2638 fields[j].sign);
2639
2640 /* Update the Linux userspace ID register view */
2641 type = ((fields[j].type & MRS_LINUX) != 0) ?
2642 fields[j].type :
2643 (MRS_EXACT | (fields[j].type & MRS_SAFE_MASK));
2644 l_new = update_special_reg_field(l_new,
2645 type, l_old, fields[j].width, fields[j].shift,
2646 fields[j].sign);
2647
2648 /* Update the kernel ID register view */
2649 k_new = update_special_reg_field(k_new,
2650 fields[j].type, k_old, fields[j].width,
2651 fields[j].shift, fields[j].sign);
2652 }
2653
2654 CPU_DESC_FIELD(kern_cpu_desc, idx) = k_new;
2655 CPU_DESC_FIELD(user_cpu_desc, idx) = f_new;
2656 CPU_DESC_FIELD(l_user_cpu_desc, idx) = l_new;
2657 }
2658
2659 void
update_special_regs(u_int cpu)2660 update_special_regs(u_int cpu)
2661 {
2662 struct cpu_desc *desc;
2663 uint64_t value;
2664 int i;
2665
2666 if (cpu == 0) {
2667 /* Create a user visible cpu description with safe values */
2668 memset(&user_cpu_desc, 0, sizeof(user_cpu_desc));
2669 /* Safe values for these registers */
2670 user_cpu_desc.id_aa64pfr0 = ID_AA64PFR0_AdvSIMD_NONE |
2671 ID_AA64PFR0_FP_NONE | ID_AA64PFR0_EL1_64 |
2672 ID_AA64PFR0_EL0_64;
2673 user_cpu_desc.id_aa64dfr0 = ID_AA64DFR0_DebugVer_8;
2674 /* Create the Linux user visible cpu description */
2675 memcpy(&l_user_cpu_desc, &user_cpu_desc, sizeof(user_cpu_desc));
2676 }
2677
2678 desc = get_cpu_desc(cpu);
2679 for (i = 0; i < nitems(user_regs); i++) {
2680 value = CPU_DESC_FIELD(*desc, i);
2681 if (cpu == 0) {
2682 CPU_DESC_FIELD(kern_cpu_desc, i) = value;
2683 CPU_DESC_FIELD(user_cpu_desc, i) = value;
2684 CPU_DESC_FIELD(l_user_cpu_desc, i) = value;
2685 }
2686
2687 clear_set_special_reg_idx(i, UINT64_MAX, value);
2688 }
2689 }
2690
2691 /*
2692 * Updates a special register in all views. This creates a copy of the
2693 * register then clears it and sets new bits. It will then compare this
2694 * with the old version as if it was the ID register for a new CPU.
2695 *
2696 * It is intended to let code that disables features, e.g. due to errata,
2697 * to clear the user visible field.
2698 *
2699 * This needs to be called before the HWCAPs are set. If called from a CPU
2700 * feature handler this safe to call from CPU_FEAT_EARLY_BOOT. It also needs
2701 * to be before link_elf_late_ireloc is called. As this is called after the
2702 * HWCAPs are set the check for these is enough.
2703 */
2704 void
update_special_reg_iss(u_int iss,uint64_t clear,uint64_t set)2705 update_special_reg_iss(u_int iss, uint64_t clear, uint64_t set)
2706 {
2707 MPASS(hwcaps_set == false);
2708 /* There is no locking here, so we only support changing this on CPU0 */
2709 /* TODO: Add said locking */
2710 MPASS(PCPU_GET(cpuid) == 0);
2711
2712 for (int i = 0; i < nitems(user_regs); i++) {
2713 if (user_regs[i].iss != iss)
2714 continue;
2715
2716 clear_set_special_reg_idx(i, clear, set);
2717 return;
2718 }
2719 }
2720
2721 void
cpu_desc_init(void)2722 cpu_desc_init(void)
2723 {
2724 if (mp_ncpus == 1)
2725 return;
2726
2727 /*
2728 * Allocate memory for the non-boot CPUs to store their registers.
2729 * As this is indexed by CPU ID we need to allocate space for CPUs
2730 * 1 to mp_maxid. Because of this mp_maxid is already the correct
2731 * number of elements.
2732 */
2733 cpu_desc = mallocarray(mp_maxid, sizeof(*cpu_desc), M_IDENTCPU,
2734 M_ZERO | M_WAITOK);
2735 }
2736
2737 /* HWCAP */
2738 bool __read_frequently lse_supported = false;
2739
2740 bool __read_frequently icache_aliasing = false;
2741 bool __read_frequently icache_vmid = false;
2742
2743 int64_t dcache_line_size; /* The minimum D cache line size */
2744 int64_t icache_line_size; /* The minimum I cache line size */
2745 int64_t idcache_line_size; /* The minimum cache line size */
2746
2747 /*
2748 * Find the values to export to userspace as AT_HWCAP and AT_HWCAP2.
2749 */
2750 static void
parse_cpu_features(bool is64bit,struct cpu_desc * cpu_desc,u_long * hwcap,u_long * hwcap2)2751 parse_cpu_features(bool is64bit, struct cpu_desc *cpu_desc, u_long *hwcap,
2752 u_long *hwcap2)
2753 {
2754 const struct mrs_field_hwcap *hwcaps;
2755 const struct mrs_field *fields;
2756 uint64_t min, reg;
2757 u_long *cur_hwcap;
2758 int i, j, k;
2759
2760 for (i = 0; i < nitems(user_regs); i++) {
2761 if (user_regs[i].is64bit != is64bit)
2762 continue;
2763
2764 reg = CPU_DESC_FIELD(*cpu_desc, i);
2765 fields = user_regs[i].fields;
2766 for (j = 0; fields[j].type != 0; j++) {
2767 hwcaps = fields[j].hwcaps;
2768 if (hwcaps == NULL)
2769 continue;
2770
2771 for (k = 0; hwcaps[k].hwcap_id != 0; k++) {
2772 KASSERT(hwcaps[k].hwcap_id == 1 ||
2773 hwcaps[k].hwcap_id == 2,
2774 ("%s: Invalid HWCAP ID %d", __func__,
2775 hwcaps[k].hwcap_id));
2776
2777 cur_hwcap = hwcaps[k].hwcap_id == 1 ?
2778 hwcap : hwcap2;
2779 min = hwcaps[k].min;
2780
2781 /*
2782 * If the field is greater than the minimum
2783 * value we can set the hwcap;
2784 */
2785 if (mrs_field_cmp(reg, min, fields[j].shift,
2786 4, fields[j].sign) >= 0) {
2787 *cur_hwcap |= hwcaps[k].hwcap_val;
2788 }
2789 }
2790 }
2791 }
2792 }
2793
2794 static void
identify_cpu_sysinit(void * dummy __unused)2795 identify_cpu_sysinit(void *dummy __unused)
2796 {
2797 struct cpu_desc *desc, *prev_desc;
2798 int cpu;
2799 bool dic, idc;
2800
2801 dic = (allow_dic != 0);
2802 idc = (allow_idc != 0);
2803
2804 prev_desc = NULL;
2805 CPU_FOREACH(cpu) {
2806 desc = get_cpu_desc(cpu);
2807 if (cpu != 0) {
2808 check_cpu_regs(cpu, desc, prev_desc);
2809 update_special_regs(cpu);
2810 }
2811
2812 if (CTR_DIC_VAL(desc->ctr) == 0)
2813 dic = false;
2814 if (CTR_IDC_VAL(desc->ctr) == 0)
2815 idc = false;
2816 prev_desc = desc;
2817 }
2818
2819 #ifdef INVARIANTS
2820 /* Check we dont update the special registers after this point */
2821 hwcaps_set = true;
2822 #endif
2823
2824 /* Find the values to export to userspace as AT_HWCAP and AT_HWCAP2 */
2825 parse_cpu_features(true, &user_cpu_desc, &elf_hwcap, &elf_hwcap2);
2826 parse_cpu_features(true, &l_user_cpu_desc, &linux_elf_hwcap,
2827 &linux_elf_hwcap2);
2828 #ifdef COMPAT_FREEBSD32
2829 parse_cpu_features(false, &user_cpu_desc, &elf32_hwcap, &elf32_hwcap2);
2830 #endif
2831
2832 /* We export the CPUID registers */
2833 elf_hwcap |= HWCAP_CPUID;
2834 linux_elf_hwcap |= HWCAP_CPUID;
2835
2836 #ifdef COMPAT_FREEBSD32
2837 /* Set the default caps and any that need to check multiple fields */
2838 elf32_hwcap |= parse_cpu_features_hwcap32();
2839 #endif
2840
2841 if (dic && idc) {
2842 arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range;
2843 if (bootverbose)
2844 printf("Enabling DIC & IDC ICache sync\n");
2845 } else if (idc) {
2846 arm64_icache_sync_range = &arm64_idc_aliasing_icache_sync_range;
2847 if (bootverbose)
2848 printf("Enabling IDC ICache sync\n");
2849 }
2850
2851 if ((elf_hwcap & HWCAP_ATOMICS) != 0) {
2852 lse_supported = true;
2853 if (bootverbose)
2854 printf("Enabling LSE atomics in the kernel\n");
2855 }
2856 #ifdef LSE_ATOMICS
2857 if (!lse_supported)
2858 panic("CPU does not support LSE atomic instructions");
2859 #endif
2860
2861 install_sys_handler(user_ctr_handler);
2862 install_sys_handler(user_idreg_handler);
2863 }
2864 /*
2865 * This needs to be after the APs have stareted as they may have errata that
2866 * means we need to mask out ID registers & that could affect hwcaps, etc.
2867 */
2868 SYSINIT(identify_cpu, SI_SUB_CONFIGURE, SI_ORDER_ANY, identify_cpu_sysinit,
2869 NULL);
2870
2871 static void
cpu_features_sysinit(void * dummy __unused)2872 cpu_features_sysinit(void *dummy __unused)
2873 {
2874 struct sbuf sb;
2875 struct cpu_desc *desc, *prev_desc;
2876 u_int cpu;
2877
2878 prev_desc = NULL;
2879 CPU_FOREACH(cpu) {
2880 desc = get_cpu_desc(cpu);
2881 print_cpu_features(cpu, desc, prev_desc);
2882 prev_desc = desc;
2883 }
2884
2885 /* Fill in cpu_model for the hw.model sysctl */
2886 sbuf_new(&sb, cpu_model, sizeof(cpu_model), SBUF_FIXEDLEN);
2887 print_cpu_midr(&sb, 0);
2888
2889 sbuf_finish(&sb);
2890 sbuf_delete(&sb);
2891
2892 free(cpu_desc, M_IDENTCPU);
2893 }
2894 /* Log features before APs are released and start printing to the dmesg. */
2895 SYSINIT(cpu_features, SI_SUB_SMP - 1, SI_ORDER_ANY, cpu_features_sysinit, NULL);
2896
2897 static void
tcr_set_e0pd1(void * arg __unused)2898 tcr_set_e0pd1(void *arg __unused)
2899 {
2900 uint64_t tcr;
2901
2902 tcr = READ_SPECIALREG(tcr_el1);
2903 tcr |= TCR_E0PD1;
2904 WRITE_SPECIALREG(tcr_el1, tcr);
2905 isb();
2906 }
2907
2908 /* Enable support for more recent architecture features */
2909 static void
cpu_feat_support(void * arg __unused)2910 cpu_feat_support(void *arg __unused)
2911 {
2912 /*
2913 * If FEAT_E0PD is supported use it to cause faults without a page
2914 * table walk if userspace tries to access kernel memory.
2915 */
2916 if (ID_AA64MMFR2_E0PD_VAL(kern_cpu_desc.id_aa64mmfr2) !=
2917 ID_AA64MMFR2_E0PD_NONE)
2918 smp_rendezvous(NULL, tcr_set_e0pd1, NULL, NULL);
2919 }
2920 SYSINIT(cpu_feat_support, SI_SUB_SMP, SI_ORDER_ANY, cpu_feat_support, NULL);
2921
2922 #ifdef COMPAT_FREEBSD32
2923 static u_long
parse_cpu_features_hwcap32(void)2924 parse_cpu_features_hwcap32(void)
2925 {
2926 u_long hwcap = HWCAP32_DEFAULT;
2927
2928 if ((MVFR1_SIMDLS_VAL(user_cpu_desc.mvfr1) >=
2929 MVFR1_SIMDLS_IMPL) &&
2930 (MVFR1_SIMDInt_VAL(user_cpu_desc.mvfr1) >=
2931 MVFR1_SIMDInt_IMPL) &&
2932 (MVFR1_SIMDSP_VAL(user_cpu_desc.mvfr1) >=
2933 MVFR1_SIMDSP_IMPL))
2934 hwcap |= HWCAP32_NEON;
2935
2936 return (hwcap);
2937 }
2938 #endif /* COMPAT_FREEBSD32 */
2939
2940 static void
print_register(struct sbuf * sb,const char * reg_name,uint64_t reg,void (* print_fields)(struct sbuf *,uint64_t,const void *),const void * arg)2941 print_register(struct sbuf *sb, const char *reg_name, uint64_t reg,
2942 void (*print_fields)(struct sbuf *, uint64_t, const void *),
2943 const void *arg)
2944 {
2945
2946 sbuf_printf(sb, "%29s = <", reg_name);
2947
2948 print_fields(sb, reg, arg);
2949
2950 sbuf_finish(sb);
2951 printf("%s>\n", sbuf_data(sb));
2952 sbuf_clear(sb);
2953 }
2954
2955 static void
print_id_fields(struct sbuf * sb,uint64_t reg,const void * arg)2956 print_id_fields(struct sbuf *sb, uint64_t reg, const void *arg)
2957 {
2958 const struct mrs_field *fields = arg;
2959 const struct mrs_field_value *fv;
2960 int field, i, j, printed;
2961
2962 #define SEP_STR ((printed++) == 0) ? "" : ","
2963 printed = 0;
2964 for (i = 0; fields[i].type != 0; i++) {
2965 fv = fields[i].values;
2966
2967 if (fv == NULL)
2968 goto next;
2969
2970 field = (reg & fields[i].mask) >> fields[i].shift;
2971 for (j = 0; fv[j].desc != NULL; j++) {
2972 if ((fv[j].value >> fields[i].shift) != field)
2973 continue;
2974
2975 if (fv[j].desc[0] != '\0')
2976 sbuf_printf(sb, "%s%s", SEP_STR, fv[j].desc);
2977 break;
2978 }
2979 if (fv[j].desc == NULL)
2980 sbuf_printf(sb, "%sUnknown %s(%x)", SEP_STR,
2981 fields[i].name, field);
2982
2983 next:
2984 reg &= ~(((1ul << fields[i].width) - 1) << fields[i].shift);
2985 }
2986
2987 if (reg != 0)
2988 sbuf_printf(sb, "%s%#lx", SEP_STR, reg);
2989 #undef SEP_STR
2990 }
2991
2992 static void
print_id_register(struct sbuf * sb,const char * reg_name,uint64_t reg,const struct mrs_field * fields)2993 print_id_register(struct sbuf *sb, const char *reg_name, uint64_t reg,
2994 const struct mrs_field *fields)
2995 {
2996
2997 print_register(sb, reg_name, reg, print_id_fields, fields);
2998 }
2999
3000 static void
print_cpu_midr(struct sbuf * sb,u_int cpu)3001 print_cpu_midr(struct sbuf *sb, u_int cpu)
3002 {
3003 const struct cpu_parts *cpu_partsp;
3004 const char *cpu_impl_name;
3005 const char *cpu_part_name;
3006 u_int midr;
3007 u_int impl_id;
3008 u_int part_id;
3009
3010 midr = pcpu_find(cpu)->pc_midr;
3011
3012 cpu_impl_name = NULL;
3013 cpu_partsp = NULL;
3014 impl_id = CPU_IMPL(midr);
3015 for (int i = 0; cpu_implementers[i].impl_name != NULL; i++) {
3016 if (impl_id == cpu_implementers[i].impl_id) {
3017 cpu_impl_name = cpu_implementers[i].impl_name;
3018 cpu_partsp = cpu_implementers[i].cpu_parts;
3019 break;
3020 }
3021 }
3022 /* Unknown implementer, so unknown part */
3023 if (cpu_impl_name == NULL) {
3024 sbuf_printf(sb, "Unknown Implementer (midr: %08x)", midr);
3025 return;
3026 }
3027
3028 KASSERT(cpu_partsp != NULL, ("%s: No parts table for implementer %s",
3029 __func__, cpu_impl_name));
3030
3031 cpu_part_name = NULL;
3032 part_id = CPU_PART(midr);
3033 for (int i = 0; cpu_partsp[i].part_name != NULL; i++) {
3034 if (part_id == cpu_partsp[i].part_id) {
3035 cpu_part_name = cpu_partsp[i].part_name;
3036 break;
3037 }
3038 }
3039 /* Known Implementer, Unknown part */
3040 if (cpu_part_name == NULL) {
3041 sbuf_printf(sb, "%s Unknown CPU r%dp%d (midr: %08x)",
3042 cpu_impl_name, CPU_VAR(midr), CPU_REV(midr), midr);
3043 return;
3044 }
3045
3046 sbuf_printf(sb, "%s %s r%dp%d", cpu_impl_name,
3047 cpu_part_name, CPU_VAR(midr), CPU_REV(midr));
3048 }
3049
3050 static void
print_cpu_cache(struct cpu_desc * desc,struct sbuf * sb,uint64_t ccs,bool icache,bool unified)3051 print_cpu_cache(struct cpu_desc *desc, struct sbuf *sb, uint64_t ccs,
3052 bool icache, bool unified)
3053 {
3054 size_t cache_size;
3055 size_t line_size;
3056
3057 /* LineSize is Log2(S) - 4. */
3058 line_size = 1 << ((ccs & CCSIDR_LineSize_MASK) + 4);
3059 /*
3060 * Calculate cache size (sets * ways * line size). There are different
3061 * formats depending on the FEAT_CCIDX bit in ID_AA64MMFR2 feature
3062 * register.
3063 */
3064 if ((desc->id_aa64mmfr2 & ID_AA64MMFR2_CCIDX_64))
3065 cache_size = (CCSIDR_NSETS_64(ccs) + 1) *
3066 (CCSIDR_ASSOC_64(ccs) + 1);
3067 else
3068 cache_size = (CCSIDR_NSETS(ccs) + 1) * (CCSIDR_ASSOC(ccs) + 1);
3069
3070 cache_size *= line_size;
3071 sbuf_printf(sb, "%zuKB (%s)", cache_size / 1024,
3072 icache ? "instruction" : unified ? "unified" : "data");
3073 }
3074
3075 static void
print_cpu_caches(struct sbuf * sb,struct cpu_desc * desc)3076 print_cpu_caches(struct sbuf *sb, struct cpu_desc *desc)
3077 {
3078 /* Print out each cache combination */
3079 uint64_t clidr;
3080 int i = 1;
3081 clidr = desc->clidr;
3082
3083 for (i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
3084 int j = 0;
3085 int ctype_m = (clidr & CLIDR_CTYPE_MASK);
3086
3087 sbuf_printf(sb, " L%d cache: ", i + 1);
3088 if ((clidr & CLIDR_CTYPE_IO)) {
3089 print_cpu_cache(desc, sb, desc->ccsidr[i][j++], true,
3090 false);
3091 /* If there's more, add to the line. */
3092 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0)
3093 sbuf_printf(sb, ", ");
3094 }
3095 if ((ctype_m & ~CLIDR_CTYPE_IO) != 0) {
3096 print_cpu_cache(desc, sb, desc->ccsidr[i][j], false,
3097 (clidr & CLIDR_CTYPE_UNIFIED));
3098 }
3099 sbuf_printf(sb, "\n");
3100
3101 }
3102 sbuf_finish(sb);
3103 printf("%s", sbuf_data(sb));
3104 }
3105
3106 static void
print_cpu_features(u_int cpu,struct cpu_desc * desc,struct cpu_desc * prev_desc)3107 print_cpu_features(u_int cpu, struct cpu_desc *desc,
3108 struct cpu_desc *prev_desc)
3109 {
3110 struct sbuf *sb;
3111
3112 sb = sbuf_new_auto();
3113 sbuf_printf(sb, "CPU%3u: ", cpu);
3114 print_cpu_midr(sb, cpu);
3115
3116 sbuf_cat(sb, " affinity:");
3117 switch(cpu_aff_levels) {
3118 default:
3119 case 4:
3120 sbuf_printf(sb, " %2d", CPU_AFF3(desc->mpidr));
3121 /* FALLTHROUGH */
3122 case 3:
3123 sbuf_printf(sb, " %2d", CPU_AFF2(desc->mpidr));
3124 /* FALLTHROUGH */
3125 case 2:
3126 sbuf_printf(sb, " %2d", CPU_AFF1(desc->mpidr));
3127 /* FALLTHROUGH */
3128 case 1:
3129 case 0: /* On UP this will be zero */
3130 sbuf_printf(sb, " %2d", CPU_AFF0(desc->mpidr));
3131 break;
3132 }
3133 sbuf_finish(sb);
3134 printf("%s\n", sbuf_data(sb));
3135 sbuf_clear(sb);
3136
3137 /*
3138 * There is a hardware errata where, if one CPU is performing a TLB
3139 * invalidation while another is performing a store-exclusive the
3140 * store-exclusive may return the wrong status. A workaround seems
3141 * to be to use an IPI to invalidate on each CPU, however given the
3142 * limited number of affected units (pass 1.1 is the evaluation
3143 * hardware revision), and the lack of information from Cavium
3144 * this has not been implemented.
3145 *
3146 * At the time of writing this the only information is from:
3147 * https://lkml.org/lkml/2016/8/4/722
3148 */
3149 /*
3150 * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also
3151 * triggers on pass 2.0+.
3152 */
3153 if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 &&
3154 CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1)
3155 printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known "
3156 "hardware bugs that may cause the incorrect operation of "
3157 "atomic operations.\n");
3158
3159 #define SHOULD_PRINT_REG(_reg) \
3160 (prev_desc == NULL || desc->_reg != prev_desc->_reg)
3161
3162 /* Cache Type Register */
3163 if (SHOULD_PRINT_REG(ctr))
3164 print_id_register(sb, "Cache Type", desc->ctr, ctr_fields);
3165
3166 /* AArch64 Instruction Set Attribute Register 0 */
3167 if (SHOULD_PRINT_REG(id_aa64isar0))
3168 print_id_register(sb, "Instruction Set Attributes 0",
3169 desc->id_aa64isar0, id_aa64isar0_fields);
3170
3171 /* AArch64 Instruction Set Attribute Register 1 */
3172 if (SHOULD_PRINT_REG(id_aa64isar1))
3173 print_id_register(sb, "Instruction Set Attributes 1",
3174 desc->id_aa64isar1, id_aa64isar1_fields);
3175
3176 /* AArch64 Instruction Set Attribute Register 2 */
3177 if (SHOULD_PRINT_REG(id_aa64isar2))
3178 print_id_register(sb, "Instruction Set Attributes 2",
3179 desc->id_aa64isar2, id_aa64isar2_fields);
3180
3181 /* AArch64 Processor Feature Register 0 */
3182 if (SHOULD_PRINT_REG(id_aa64pfr0))
3183 print_id_register(sb, "Processor Features 0",
3184 desc->id_aa64pfr0, id_aa64pfr0_fields);
3185
3186 /* AArch64 Processor Feature Register 1 */
3187 if (SHOULD_PRINT_REG(id_aa64pfr1))
3188 print_id_register(sb, "Processor Features 1",
3189 desc->id_aa64pfr1, id_aa64pfr1_fields);
3190
3191 /* AArch64 Processor Feature Register 2 */
3192 if (SHOULD_PRINT_REG(id_aa64pfr2))
3193 print_id_register(sb, "Processor Features 2",
3194 desc->id_aa64pfr2, id_aa64pfr2_fields);
3195
3196 /* AArch64 Memory Model Feature Register 0 */
3197 if (SHOULD_PRINT_REG(id_aa64mmfr0))
3198 print_id_register(sb, "Memory Model Features 0",
3199 desc->id_aa64mmfr0, id_aa64mmfr0_fields);
3200
3201 /* AArch64 Memory Model Feature Register 1 */
3202 if (SHOULD_PRINT_REG(id_aa64mmfr1))
3203 print_id_register(sb, "Memory Model Features 1",
3204 desc->id_aa64mmfr1, id_aa64mmfr1_fields);
3205
3206 /* AArch64 Memory Model Feature Register 2 */
3207 if (SHOULD_PRINT_REG(id_aa64mmfr2))
3208 print_id_register(sb, "Memory Model Features 2",
3209 desc->id_aa64mmfr2, id_aa64mmfr2_fields);
3210
3211 /* AArch64 Memory Model Feature Register 3 */
3212 if (SHOULD_PRINT_REG(id_aa64mmfr3))
3213 print_id_register(sb, "Memory Model Features 3",
3214 desc->id_aa64mmfr3, id_aa64mmfr3_fields);
3215
3216 /* AArch64 Memory Model Feature Register 4 */
3217 if (SHOULD_PRINT_REG(id_aa64mmfr4))
3218 print_id_register(sb, "Memory Model Features 4",
3219 desc->id_aa64mmfr4, id_aa64mmfr4_fields);
3220
3221 /* AArch64 Debug Feature Register 0 */
3222 if (SHOULD_PRINT_REG(id_aa64dfr0))
3223 print_id_register(sb, "Debug Features 0",
3224 desc->id_aa64dfr0, id_aa64dfr0_fields);
3225
3226 /* AArch64 Memory Model Feature Register 1 */
3227 if (SHOULD_PRINT_REG(id_aa64dfr1))
3228 print_id_register(sb, "Debug Features 1",
3229 desc->id_aa64dfr1, id_aa64dfr1_fields);
3230
3231 /* AArch64 Auxiliary Feature Register 0 */
3232 if (SHOULD_PRINT_REG(id_aa64afr0))
3233 print_id_register(sb, "Auxiliary Features 0",
3234 desc->id_aa64afr0, id_aa64afr0_fields);
3235
3236 /* AArch64 Auxiliary Feature Register 1 */
3237 if (SHOULD_PRINT_REG(id_aa64afr1))
3238 print_id_register(sb, "Auxiliary Features 1",
3239 desc->id_aa64afr1, id_aa64afr1_fields);
3240
3241 /* AArch64 SVE Feature Register 0 */
3242 if (desc->have_sve) {
3243 if (SHOULD_PRINT_REG(id_aa64zfr0) ||
3244 !prev_desc->have_sve) {
3245 print_id_register(sb, "SVE Features 0",
3246 desc->id_aa64zfr0, id_aa64zfr0_fields);
3247 }
3248 }
3249
3250 #ifdef COMPAT_FREEBSD32
3251 /* AArch32 Instruction Set Attribute Register 5 */
3252 if (SHOULD_PRINT_REG(id_isar5))
3253 print_id_register(sb, "AArch32 Instruction Set Attributes 5",
3254 desc->id_isar5, id_isar5_fields);
3255
3256 /* AArch32 Media and VFP Feature Register 0 */
3257 if (SHOULD_PRINT_REG(mvfr0))
3258 print_id_register(sb, "AArch32 Media and VFP Features 0",
3259 desc->mvfr0, mvfr0_fields);
3260
3261 /* AArch32 Media and VFP Feature Register 1 */
3262 if (SHOULD_PRINT_REG(mvfr1))
3263 print_id_register(sb, "AArch32 Media and VFP Features 1",
3264 desc->mvfr1, mvfr1_fields);
3265 #endif
3266 if (bootverbose)
3267 print_cpu_caches(sb, desc);
3268
3269 sbuf_delete(sb);
3270 sb = NULL;
3271 #undef SHOULD_PRINT_REG
3272 #undef SEP_STR
3273 }
3274
3275 void
identify_cache(uint64_t ctr)3276 identify_cache(uint64_t ctr)
3277 {
3278
3279 /* Identify the L1 cache type */
3280 switch (CTR_L1IP_VAL(ctr)) {
3281 case CTR_L1IP_PIPT:
3282 break;
3283 default:
3284 case CTR_L1IP_VIPT:
3285 icache_aliasing = true;
3286 break;
3287 }
3288
3289 if (dcache_line_size == 0) {
3290 KASSERT(icache_line_size == 0, ("%s: i-cacheline size set: %ld",
3291 __func__, icache_line_size));
3292
3293 /* Get the D cache line size */
3294 dcache_line_size = CTR_DLINE_SIZE(ctr);
3295 /* And the same for the I cache */
3296 icache_line_size = CTR_ILINE_SIZE(ctr);
3297
3298 idcache_line_size = MIN(dcache_line_size, icache_line_size);
3299 }
3300
3301 if (dcache_line_size != CTR_DLINE_SIZE(ctr)) {
3302 printf("WARNING: D-cacheline size mismatch %ld != %d\n",
3303 dcache_line_size, CTR_DLINE_SIZE(ctr));
3304 }
3305
3306 if (icache_line_size != CTR_ILINE_SIZE(ctr)) {
3307 printf("WARNING: I-cacheline size mismatch %ld != %d\n",
3308 icache_line_size, CTR_ILINE_SIZE(ctr));
3309 }
3310 }
3311
3312 void
identify_cpu(u_int cpu)3313 identify_cpu(u_int cpu)
3314 {
3315 struct cpu_desc *desc;
3316 uint64_t clidr;
3317
3318 desc = get_cpu_desc(cpu);
3319 /* Save affinity for current CPU */
3320 desc->mpidr = get_mpidr();
3321 CPU_AFFINITY(cpu) = desc->mpidr & CPU_AFF_MASK;
3322
3323 desc->ctr = READ_SPECIALREG(ctr_el0);
3324 desc->id_aa64dfr0 = READ_SPECIALREG(ID_AA64DFR0_EL1_REG);
3325 desc->id_aa64dfr1 = READ_SPECIALREG(ID_AA64DFR1_EL1_REG);
3326 desc->id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1_REG);
3327 desc->id_aa64isar1 = READ_SPECIALREG(ID_AA64ISAR1_EL1_REG);
3328 desc->id_aa64isar2 = READ_SPECIALREG(ID_AA64ISAR2_EL1_REG);
3329 desc->id_aa64mmfr0 = READ_SPECIALREG(ID_AA64MMFR0_EL1_REG);
3330 desc->id_aa64mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1_REG);
3331 desc->id_aa64mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1_REG);
3332 desc->id_aa64mmfr3 = READ_SPECIALREG(ID_AA64MMFR3_EL1_REG);
3333 desc->id_aa64mmfr4 = READ_SPECIALREG(ID_AA64MMFR4_EL1_REG);
3334 desc->id_aa64pfr0 = READ_SPECIALREG(ID_AA64PFR0_EL1_REG);
3335 desc->id_aa64pfr1 = READ_SPECIALREG(ID_AA64PFR1_EL1_REG);
3336 desc->id_aa64pfr2 = READ_SPECIALREG(ID_AA64PFR2_EL1_REG);
3337
3338 /*
3339 * ID_AA64ZFR0_EL1 is only valid when at least one of:
3340 * - ID_AA64PFR0_EL1.SVE is non-zero
3341 * - ID_AA64PFR1_EL1.SME is non-zero
3342 * In other cases it is zero, but still safe to read
3343 */
3344 desc->have_sve =
3345 (ID_AA64PFR0_SVE_VAL(desc->id_aa64pfr0) != 0);
3346 desc->id_aa64zfr0 = READ_SPECIALREG(ID_AA64ZFR0_EL1_REG);
3347
3348 desc->clidr = READ_SPECIALREG(clidr_el1);
3349
3350 clidr = desc->clidr;
3351
3352 for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) {
3353 int j = 0;
3354 if ((clidr & CLIDR_CTYPE_IO)) {
3355 WRITE_SPECIALREG(csselr_el1,
3356 CSSELR_Level(i) | CSSELR_InD);
3357 desc->ccsidr[i][j++] =
3358 READ_SPECIALREG(ccsidr_el1);
3359 }
3360 if ((clidr & ~CLIDR_CTYPE_IO) == 0)
3361 continue;
3362 WRITE_SPECIALREG(csselr_el1, CSSELR_Level(i));
3363 desc->ccsidr[i][j] = READ_SPECIALREG(ccsidr_el1);
3364 }
3365
3366 #ifdef COMPAT_FREEBSD32
3367 /* Only read aarch32 SRs if EL0-32 is available */
3368 if (ID_AA64PFR0_EL0_VAL(desc->id_aa64pfr0) == ID_AA64PFR0_EL0_64_32) {
3369 desc->id_isar5 = READ_SPECIALREG(id_isar5_el1);
3370 desc->mvfr0 = READ_SPECIALREG(mvfr0_el1);
3371 desc->mvfr1 = READ_SPECIALREG(mvfr1_el1);
3372 }
3373 #endif
3374 }
3375
3376 static void
check_cpu_regs(u_int cpu,struct cpu_desc * desc,struct cpu_desc * prev_desc)3377 check_cpu_regs(u_int cpu, struct cpu_desc *desc, struct cpu_desc *prev_desc)
3378 {
3379 switch (cpu_aff_levels) {
3380 case 0:
3381 if (CPU_AFF0(desc->mpidr) != CPU_AFF0(prev_desc->mpidr))
3382 cpu_aff_levels = 1;
3383 /* FALLTHROUGH */
3384 case 1:
3385 if (CPU_AFF1(desc->mpidr) != CPU_AFF1(prev_desc->mpidr))
3386 cpu_aff_levels = 2;
3387 /* FALLTHROUGH */
3388 case 2:
3389 if (CPU_AFF2(desc->mpidr) != CPU_AFF2(prev_desc->mpidr))
3390 cpu_aff_levels = 3;
3391 /* FALLTHROUGH */
3392 case 3:
3393 if (CPU_AFF3(desc->mpidr) != CPU_AFF3(prev_desc->mpidr))
3394 cpu_aff_levels = 4;
3395 break;
3396 }
3397
3398 if (desc->ctr != prev_desc->ctr) {
3399 /*
3400 * If the cache is different on different cores we should
3401 * emulate for userspace to provide a uniform value
3402 */
3403 emulate_ctr = true;
3404
3405 /*
3406 * If the cache type register is different we may
3407 * have a different l1 cache type.
3408 */
3409 identify_cache(desc->ctr);
3410 }
3411 }
3412